58218 lines
4.2 MiB
58218 lines
4.2 MiB
; --------------------------------------------------------------------------------
|
|
; @Title: STM32F3x On-Chip Peripherals
|
|
; @Props: Released
|
|
; @Author: BIC, KBR, WYS, AJK, TRJ, KMB
|
|
; @Changelog: 2012-10-17
|
|
; 2015-04-15 MKK
|
|
; 2017-03-30 TRJ
|
|
; 2018-04-12 KMB
|
|
; @Manufacturer: STM - ST Microelectronics N.V.
|
|
; @Doc: DB-STM32F38x-DM00063949.pdf (Rev 1, 2012-09)
|
|
; DB-STM32F313-DM00063977.pdf (Rev 1, 2012-09)
|
|
; DS-STM32F37x-DM00046749.pdf (Rev 2, 2012-09)
|
|
; DS-STM32F30x-DM00058181.pdf (Rev 3, 2012-09)
|
|
; RM-STM32F30x-F313-DM00043574.pdf (Rev 1, 2012-09)
|
|
; RM-STM32F37x-38x-DM00041563.pdf (Rev 1, 2012-09)
|
|
; RM-STM32F3xx-F4xx-dm00046982.pdf (Rev 3, 2012-09)
|
|
; RM_DM00094350.pdf (Rev. 2,2014-09)
|
|
; RM_DM00094349.pdf (Rev. 3,2014-09)
|
|
; RM_DM00043574.pdf (Rev. 4,2014-08)
|
|
; RM_DM00093941.pdf (Rev. 1,2014-06)
|
|
; RM_DM00041563.pdf (Rev. 3,2014-05)
|
|
; DS_DM00093332.pdf (Rev. 3, 2014-12)
|
|
; DS_DM00115350.pdf (Rev. 3, 2014-12)
|
|
; DS_DM00093333.pdf (Rev. 3, 2014-12)
|
|
; DS_DM00094064.pdf (Rev. 2, 2014-04)
|
|
; DS_DM00092070.pdf (Rev. 1, 2014-04)
|
|
; DS_DM00058181.pdf (Rev. 8, 2014-04)
|
|
; DS_DM00116561.pdf (Rev. 1, 2014-05)
|
|
; DS_DM00100431.pdf (Rev. 1, 2014-04)
|
|
; DS_DM00097745.pdf (Rev. 1, 2014-04)
|
|
; DS_DM00101621.pdf (Rev. 3, 2015-06)
|
|
; en.DM00043574.pdf (Rev. 7, 2016-05)
|
|
; en.DM00093941.pdf (Rev. 3, 2017-09)
|
|
; @Core: Cortex-M4F
|
|
; @Chip: STM32F302RD, STM32F302RE, STM32F302VD, STM32F302VE,
|
|
; STM32F302ZD, STM32F302ZE, STM32F303RD, STM32F303RE,
|
|
; STM32F303VD, STM32F303VE, STM32F303ZD, STM32F303ZE,
|
|
; STM32F398VE;
|
|
; @Copyright: (C) 1989-2018 Lauterbach GmbH, licensed for use with TRACE32(R) only
|
|
; --------------------------------------------------------------------------------
|
|
; $Id: perstm32f3x.per 17736 2024-04-08 09:26:07Z kwisniewski $
|
|
|
|
; Known problems:
|
|
; Module Register Description
|
|
; GPIO PORTG and PORTH No pin description for STM32F398VE
|
|
; COMP COMP3_CSR Register only in (STM32F302xB/C/D/E and STM32F302x6/8) and (Only in STM32F303xB/C and STM32F358xC)
|
|
; COMP COMP4INMSEL[3:0] To many value's
|
|
; CAN CAN_TDTxR Unknown access for "TGT" bit
|
|
; --------------------------------------------------------------------------------
|
|
tree.close "Core Registers (Cortex-M4F)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
|
|
bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
|
|
bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
|
|
bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
|
|
group.long 0x10++0x0B
|
|
line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
|
|
rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
|
|
bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
|
|
line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
|
|
line.long 0x08 "SYST_CVR,SysTick Current Value Register"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
|
|
bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
|
|
bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
|
|
bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD04++0x23
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
|
|
textline " "
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
|
|
bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
|
|
hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
|
|
bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
|
|
line.long 0x04 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
|
|
rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
|
|
bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
|
|
textline " "
|
|
bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
|
|
bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
|
|
bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
|
|
line.long 0x0C "SCR,System Control Register"
|
|
bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
line.long 0x10 "CCR,Configuration Control Register"
|
|
bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
|
|
bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
|
|
bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
|
|
line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
|
|
textline " "
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
|
|
line.long 0x18 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
|
|
textline " "
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
|
|
line.long 0x1C "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
|
|
textline " "
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
|
|
line.long 0x20 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
|
|
bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
|
|
textline " "
|
|
bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
|
|
bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
|
|
bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
|
|
bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
|
|
bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
|
|
bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
|
|
group.byte 0xD28++0x1
|
|
line.byte 0x00 "MMFSR,MemManage Status Register"
|
|
bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
|
|
bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
|
|
line.byte 0x01 "BFSR,Bus Fault Status Register"
|
|
bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
|
|
bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
|
|
bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
|
|
group.word 0xD2A++0x1
|
|
line.word 0x00 "USAFAULT,Usage Fault Status Register"
|
|
bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
|
|
bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
|
|
bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
|
|
bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
|
|
bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
|
|
group.long 0xD2C++0x07
|
|
line.long 0x00 "HFSR,Hard Fault Status Register"
|
|
bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
|
|
bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
|
|
line.long 0x04 "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
|
|
bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
|
|
bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
|
|
bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
|
|
group.long 0xD34++0x0B
|
|
line.long 0x00 "MMFAR,MemManage Fault Address Register"
|
|
line.long 0x04 "BFAR,BusFault Address Register"
|
|
line.long 0x08 "AFSR,Auxiliary Fault Status Register"
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
|
|
bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
|
|
wgroup.long 0xF00++0x03
|
|
line.long 0x00 "STIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
|
|
width 10.
|
|
tree "Feature Registers"
|
|
rgroup.long 0xD40++0x0B
|
|
line.long 0x00 "ID_PFR0,Processor Feature Register 0"
|
|
bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
|
|
line.long 0x04 "ID_PFR1,Processor Feature Register 1"
|
|
bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
|
|
line.long 0x08 "ID_DFR0,Debug Feature Register 0"
|
|
bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
|
|
hgroup.long 0xD4C++0x03
|
|
hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
|
|
rgroup.long 0xD50++0x03
|
|
line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
|
|
bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
|
|
bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
|
|
bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
|
|
bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
|
|
hgroup.long 0xD54++0x03
|
|
hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
|
|
rgroup.long 0xD58++0x03
|
|
line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
|
|
bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
|
|
rgroup.long 0xD60++0x13
|
|
line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
|
|
bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
|
|
bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
|
|
bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
|
|
bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
|
|
bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
|
|
line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
|
|
bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
|
|
bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
|
|
bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
|
|
line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
|
|
bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
|
|
bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
|
|
bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
|
|
bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
|
|
bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
|
|
textline " "
|
|
bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
|
|
line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
|
|
bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
|
|
bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
config 16. 8.
|
|
tree "EFM (Embedded Flash memory)"
|
|
base ad:0x40022000
|
|
width 15.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FLASH_ACR,Flash access control register"
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||cpuis("STM32F334*")||cpuis("STM32F303?D")||cpuis("STM32F302?D")||cpuis("STM32F303?E")||cpuis("STM32F302?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 5. " PRFTBS ,Prefetch buffer status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRFTBE ,Prefetch buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " HLFCYA ,Flash half cycle access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " LATENCY ,Latency" "Zero wait state,One wait state,Two wait states,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 5. " PRFTBS ,Prefetch buffer status" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PRFTBE ,Prefetch buffer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--2. " LATENCY ,Latency" "Zero wait state,One wait state,Two wait states,?..."
|
|
endif
|
|
wgroup.long 0x04++0x07
|
|
line.long 0x00 "FLASH_KEYR,FPEC key register"
|
|
line.long 0x04 "FLASH_OPTKEYR,Flash OPTKEY register"
|
|
group.long 0x0C++0x07
|
|
line.long 0x00 "FLASH_SR,Flash status register"
|
|
eventfld.long 0x00 5. " EOP ,End of operation" "Not asserted,Asserted"
|
|
eventfld.long 0x00 4. " WRPRTERR ,Write protection error" "No error,Error"
|
|
eventfld.long 0x00 2. " PGERR ,Programming error" "No error,Error"
|
|
bitfld.long 0x00 0. " BSY ,Busy" "Not busy,Busy"
|
|
line.long 0x04 "FLASH_CR,Flash control register"
|
|
bitfld.long 0x04 13. " OBL_LAUNCH ,Force option byte loading" "Not active,Active"
|
|
bitfld.long 0x04 12. " EOPIE ,End of operation interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " ERRIE ,Error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " OPTWRE ,Option bytes write enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 7. " LOCK ,Lock" "Not locked,Locked"
|
|
bitfld.long 0x04 6. " STRT ,Triggers an ERASE operation" "No,Yes"
|
|
bitfld.long 0x04 5. " OPTER ,Option byte erase" "Not erased,Erased"
|
|
bitfld.long 0x04 4. " OPTPG ,Option byte programming" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x04 2. " MER ,Mass erase" "Not erased,Erased"
|
|
bitfld.long 0x04 1. " PER ,Page Erase" "Not erased,Erased"
|
|
bitfld.long 0x04 0. " PG ,Flash programming" "No,Yes"
|
|
if (((per.l(ad:0x40022000+0x0C))&0x01)==0x01)
|
|
hgroup.long 0x14++0x03
|
|
hide.long 0x00 "FLASH_AR,Flash address register"
|
|
else
|
|
wgroup.long 0x14++0x03
|
|
line.long 0x00 "FLASH_AR,Flash address register"
|
|
endif
|
|
rgroup.long 0x1C++0x07
|
|
line.long 0x00 "FLASH_OBR,Option byte register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " DATA1 ,Data 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. " DATA0 ,Data 0"
|
|
textline " "
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")
|
|
bitfld.long 0x00 15. " SDADC12_VDD_MONITOR ,SDADC12_VDD_MONITOR" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")
|
|
bitfld.long 0x00 13. " VDDA_MONITOR ,VDDA_MONITOR" "Low,High"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 14. " SRAM_PE ,SRAM_PE" "Low,High"
|
|
bitfld.long 0x00 13. " VDDA_MONITOR ,VDDA_MONITOR" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " NBOOT1 ,NBOOT1" "Low,High"
|
|
bitfld.long 0x00 10. " NRST_STDBY ,NRST_STDBY" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " NRST_STOP ,NRST_STOP" "Low,High"
|
|
bitfld.long 0x00 8. " WDG_SW ,WDG_SW" "Low,High"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||cpuis("STM32F334*")||(cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||cpuis("STM32F303?D")||cpuis("STM32F302?D")||cpuis("STM32F303?E")||cpuis("STM32F302?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 1.--2. " RDPRT ,Read protection level status" "Level 0,Level 1,,Level 2"
|
|
textline " "
|
|
elif cpuis("STM32F37*")
|
|
bitfld.long 0x00 2. " LEVEL2_PROT ,Level 2 Read protection Status" "Not active,Active"
|
|
bitfld.long 0x00 1. " LEVEL1_PROT ,Level 1 Read protection Status" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " OPTERR ,Option byte error" "No error,Error"
|
|
line.long 0x04 "FLASH_WRPR,Write protection register"
|
|
width 0xB
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40023000
|
|
width 10.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "CRC_DR, Data Register"
|
|
line.long 0x04 "CRC_IDR, Independent Data Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " IDR ,General-purpose 8-bit data register bits"
|
|
line.long 0x08 "CRC_CR, Control Register"
|
|
bitfld.long 0x08 7. " REV_OUT ,Reverse output data" "Not affected,Reversed"
|
|
bitfld.long 0x08 5.--6. " REV_IN ,Reverse input data" "Not affected,By byte,By half-word,By word"
|
|
textline " "
|
|
sif ((cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||cpuis("STM32F048?6")||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098?C")||cpuis("STM32F071*")||cpuis("STM32F072*")||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383VC")||(cpu()=="STM32F378CC")||cpuis("STM32F301*8")||cpuis("STM32F301*6")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE"))
|
|
bitfld.long 0x08 3.--4. " POLYSIZE ,Polynomial size" "32 bit,16-bit,8-bit,7-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0. " RESET , Reset CRC bit" "No reset,Reset"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CRC_INIT,Initial CRC Value"
|
|
sif ((cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||cpuis("STM32F048?6")||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098?C")||cpuis("STM32F071*")||cpuis("STM32F072*")||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")||cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE"))
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CRC_POL,CRC Polynomial"
|
|
elif cpuis("STM32F038E6")||cpuis("STM32F058T8")||cpuis("STM32F051T8")||cpuis("STM32F031E6")
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CRC_POL,CRC Polynomial"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "PWR (Power Control Register)"
|
|
base ad:0x40007000
|
|
width 9.
|
|
group.long 0x00++0x7
|
|
line.long 0x00 "PWR_CR,Power Control Register"
|
|
sif ((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC"))
|
|
bitfld.long 0x00 11. " ENSD3 ,Enable SDADC3" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ENSD2 ,Enable SDADC2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ENSD1 ,Enable SDADC1" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DBP ,Disable backup domain write protection" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 5.--7. " PLS ,PVD level selection" "Threshold 0,Threshold 1,Threshold 2,Threshold 3,Threshold 4,Threshold 5,Threshold 6,Threshold 7"
|
|
bitfld.long 0x00 4. " PVDE ,Power voltage detector enable" "Disabled,Enabled"
|
|
textline " "
|
|
eventfld.long 0x00 3. " CSBF ,Clear standby flag" "No effect,Cleared"
|
|
eventfld.long 0x00 2. " CWUF ,Clear wake-up flag" "No effect,Cleared"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PDDS ,Power down deep-sleep" "Stop,Standby"
|
|
bitfld.long 0x00 0. " LPDS ,Low-power deep-sleep" "Normal,Low-power"
|
|
textline " "
|
|
elif (cpu()=="STM32F030C6"||cpu()=="STM32F030C8"||cpu()=="STM32F030F4"||cpu()=="STM32F030K6"||cpu()=="STM32F030R8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")
|
|
bitfld.long 0x00 8. " DBP ,Disable RTC domain write protection" "No,Yes"
|
|
eventfld.long 0x00 3. " CSBF ,Clear standby flag" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CWUF ,Clear wake-up flag" "No effect,Cleared"
|
|
bitfld.long 0x00 1. " PDDS ,Power down deep-sleep" "Stop,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPDS ,Low-power deep-sleep" "Normal,Low-power"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8. " DBP ,Disable backup domain write protection" "No,Yes"
|
|
bitfld.long 0x00 5.--7. " PLS ,PVD level selection" "2.2V,2.3V,2.4V,2.5V,2.6V,2.7V,2.8V,2.9V"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PVDE ,Power voltage detector enable" "Disabled,Enabled"
|
|
eventfld.long 0x00 3. " CSBF ,Clear Standby flag" "No effect,Clear"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CWUF ,Clear wake-up flag" "No effect,Clear"
|
|
bitfld.long 0x00 1. " PDDS ,Power down deep-sleep" "Stop,Standby"
|
|
textline " "
|
|
bitfld.long 0x00 0. " LPDS ,Low-power deep-sleep" "Normal,Low-power"
|
|
endif
|
|
line.long 0x04 "PWR_CSR,Power Control/Status Register"
|
|
sif ((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC"))
|
|
bitfld.long 0x04 9. " EWUP3 ,Enable WKUP3 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" "VDD<PVD threshold,VDD>PVD threshold"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "No standby,Standby"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wake-up Flag" "No wake-up,Wake-up"
|
|
textline " "
|
|
elif cpuis("STM32F070CB")||cpuis("STM32F030RC")||cpuis("STM32F030CC")||cpuis("STM32F070RB")
|
|
bitfld.long 0x04 14. " EWUP7 ,Enable WKUP7 pin" "general purpose I/O,wakeup from Standby"
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP6 pin" "general purpose I/O,wakeup from Standby"
|
|
bitfld.long 0x04 12. " EWUP5 ,Enable WKUP5 pin" "general purpose I/O,wakeup from Standby"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP4 pin" "general purpose I/O,wakeup from Standby"
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "general purpose I/O,wakeup from Standby"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "general purpose I/O,wakeup from Standby"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "No wakeup,Wakeup"
|
|
textline " "
|
|
elif cpuis("STM32F070C6")||cpuis("STM32F070F6")
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "general purpose I/O,wakeup from Standby"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "general purpose I/O,wakeup from Standby"
|
|
bitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " WUF ,Wakeup flag" "No wakeup,Wakeup"
|
|
textline " "
|
|
elif cpuis("STM32F301*6")||cpuis("STM32F301*8")
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x04 10. " EWUP3 ,Enable WKUP3 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F302*")||cpuis("STM32F303*")||cpuis("STM32F051?4")||cpuis("STM32F051?6")||(cpuis("STM32F051?8")&&!cpuis("STM32F051T8"))
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif ((cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC"))
|
|
bitfld.long 0x04 10. " EWUP3 ,Enable WKUP3 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("STM32F07*")||cpuis("STM32F091V*"))||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")
|
|
bitfld.long 0x04 15. " EWUP8 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 14. " EWUP7 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 12. " EWUP5 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " EWUP3 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpu()=="STM32F030C6"||cpu()=="STM32F030C8"||cpu()=="STM32F030F4"||cpu()=="STM32F030K6"||cpu()=="STM32F030R8")
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "No standby,Standby"
|
|
rbitfld.long 0x04 0. " WUF ,Wake-up Flag" "No wake-up,Wake-up"
|
|
textline " "
|
|
elif cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||cpuis("STM32F302**")||cpuis("STM32F303**")||cpuis("STM32F031?4)||cpuis("STM32F031?6)||cpuis("STM32F042?4")||cpuis("STM32F042?6")||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" "VDD<PVD threshold,VDD>PVD threshold"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "No standby,Standby"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wake-up Flag" "No wake-up,Wake-up"
|
|
textline " "
|
|
elif ((cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373VC")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373V8")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F373VB")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")&&(cpu()!="STM32F383VC"))
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" "VDD<PVD threshold,VDD>PVD threshold"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "No standby,Standby"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wake-up Flag" "No wake-up,Wake-up"
|
|
textline " "
|
|
elif (cpuis("STM32F038C6")||cpuis("STM32F058C8")||cpuis("STM32F058R8"))
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("STM32F038F6")||cpuis("STM32F038G6")||cpuis("STM32F038K6"))
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP1 pin" "Disabled,Enabled"
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis(("STM32F048C6")||cpuis("STM32F091R*")||cpuis("STM32F091C*")||cpuis("STM32F098CC"))
|
|
bitfld.long 0x04 14. " EWUP7 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
textline " "
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif (cpuis("STM32F048G6")||cpuis("STM32F048T6"))
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F098RC")
|
|
bitfld.long 0x04 14. " EWUP7 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 13. " EWUP6 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 12. " EWUP5 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " EWUP4 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " EWUP2 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
bitfld.long 0x04 8. " EWUP1 ,Enable WKUP2 pin" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x04 3. " VREFINTRDYF , VREFINT ready" "Not ready,Ready"
|
|
rbitfld.long 0x04 2. " PVDO ,PVD output" ">PVD,<PVD"
|
|
textline " "
|
|
rbitfld.long 0x04 1. " SBF ,Standby flag" "Disabled,Enabled"
|
|
rbitfld.long 0x04 0. " WUF ,Wakeup flag" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F318*8")
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40021000
|
|
width 14.
|
|
group.long 0x00++0x33
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " HSERDY ,High Speed External clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,High Speed External clock enable" "Off,On"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,High Speed Internal clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,High Speed Internal clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " HSIRDY ,High Speed Internal clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,High Speed Internal clock enable" "Off,On"
|
|
line.long 0x04 "RCC_CFGR,Clock configuration register"
|
|
bitfld.long 0x04 31. " PLLNODIV ,Do not divide PLL to MCO" "PLL/2,Not divided"
|
|
bitfld.long 0x04 28.--30. " MCOPRE ,Microcontroller Clock Output Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128,..."
|
|
bitfld.long 0x04 24.--26. " MCO ,Microcontroller Clock Output" "Disabled,,LSI,LSE,SYSCLK,HSI,HSE,PLL"
|
|
textline " "
|
|
bitfld.long 0x04 18.--21. " PLLMUL ,PLL multiplication factor" "x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x16"
|
|
bitfld.long 0x04 17. " PLLXTPRE ,HSE divider for PLL input clock" "Not divided,/2"
|
|
bitfld.long 0x04 16. " PLLSRC ,PLL entry clock source (input clock)" "HSI/2,HSE/PREDIV"
|
|
textline " "
|
|
bitfld.long 0x04 11.--13. " PPRE2 ,APB high-speed prescaler (APB2)" "-,-,-,-,/2,/2,/8,/16"
|
|
bitfld.long 0x04 8.--10. " PPRE1 ,APB Low-speed prescaler (APB1)" "-,-,-,-,/2,/2,/8,/16"
|
|
bitfld.long 0x04 4.--7. " HPRE ,HLCK prescaler" "-,-,-,-,-,-,-,-,/2,/4,/8,/16,/64,/128,/256,/512"
|
|
rbitfld.long 0x04 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,Not applicable"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,Not allowed"
|
|
line.long 0x08 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x08 23. " CSSC ,Clock Security System Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " PLLRDYC ,PLL Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 19. " HSERDYC ,HSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " HSIRDYC ,HSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " LSERDYC ,LSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " LSIRDYC ,LSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x08 7. " CSSF ,Clock Security System Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 4. " PLLRDYF ,PLL Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 3. " HSERDYF ,HSE Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 2. " HSIRDYF ,HSI Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 1. " LSERDYF ,LSE Ready Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 0. " LSIRDYF ,LSI Ready Interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x0C "RCC_APB2RSTR,APB2 Peripheral Reset Register"
|
|
bitfld.long 0x0C 18. " TIM17RST ,TIM17 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 17. " TIM16RST ,TIM16 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 16. " TIM15RST ,TIM15 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 14. " USART1RST ,USART1 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 11. " TIM1RST ,USART1 Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 0. " SYSCFGRST ,Comparators And Operational Amplifiers Reset" "No effect,Reset"
|
|
line.long 0x10 "RCC_APB1RSTR,APB1 Peripheral reset register"
|
|
bitfld.long 0x10 30. " I2C3RST ,I2C3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 29. " DAC1RST , DAC1 interface clock enable" "No effect,Reset"
|
|
bitfld.long 0x10 28. " PWRRST , Power interface clock enable" "No effect,Reset"
|
|
bitfld.long 0x10 22. " I2C2RST ,I2C2 clock enable" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C1 clock enable" "No effect,Reset"
|
|
bitfld.long 0x10 18. " USART3RST ,USART3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 17. " USART2RST ,USART2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 15. " SPI3RST ,SPI 3 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 14. " SPI2EN ,SPI2 clock enable" "No effect,Reset"
|
|
bitfld.long 0x10 11. " SPI2EN ,SPI2 clock enable" "No effect,Reset"
|
|
bitfld.long 0x10 4. " TIM6RST ,Timer 6 reset" "No effect,Reset"
|
|
bitfld.long 0x10 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
line.long 0x14 "RCC_AHBENR,AHB Peripheral Clock enable register"
|
|
bitfld.long 0x14 28. " ADC1EN ,ADC1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " TSCEN ,Touch sensing controller clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " IOPFEN ,I/O port F clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DMA1EN ,DMA 1 clock enable" "Disabled,Enabled"
|
|
line.long 0x18 "RCC_APB2ENR,APB2 Peripheral Clock enable register"
|
|
bitfld.long 0x18 18. " TIM17EN ,TIM17 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " TIM16EN ,TIM16 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 16. " TIM15EN ,TIM15 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 11. " TIM1EN ,TIM1 Timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " SYSCFGEN ,SYSCFG clock enable" "Disabled,Enabled"
|
|
line.long 0x1C "RCC_APB1ENR,APB1 Peripheral Clock enable register"
|
|
bitfld.long 0x1C 30. " I2C3EN ,I2C3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " DAC1EN ,DAC 1 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 18. " USART3EN ,USART3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " USART2EN ,USART2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " SPI3EN ,SPI 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 4. " TIM6EN ,Timer 6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
line.long 0x20 "RCC_BDCR,Backup domain control register"
|
|
bitfld.long 0x20 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x20 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x20 3.--4. " LSEDRV ,LSE oscillator drive capability in Xtal mode" "Lower,Medium low,Medium high,Higher"
|
|
textline " "
|
|
bitfld.long 0x20 2. " LSEBYP ,Low Speed External oscillator Bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x20 1. " LSERDY ,Low Speed External oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x20 0. " LSEON ,Low Speed External oscillator enable" "Off,On"
|
|
line.long 0x24 "RCC_CSR,Control/status register"
|
|
rbitfld.long 0x24 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x24 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x24 29. " IWDGRSTF ,Independent Watchdog reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x24 28. " SFTRSTF ,Software Reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x24 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x24 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x24 25. " OBLRSTF ,Option byte loader reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x24 24. " RMVF ,Remove reset flag" "No effect,Reset"
|
|
textline " "
|
|
rbitfld.long 0x24 1. " LSIRDY ,Internal Low Speed oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x24 0. " LSION ,Internal Low Speed oscillator enable" "Off,On"
|
|
line.long 0x28 "RCC_AHBRSTR,AHB peripheral reset register"
|
|
bitfld.long 0x28 28. " ADC1PRST ,ADC1 reset" "No effect,Reset"
|
|
bitfld.long 0x28 24. " TSCRST ,Touch sensing controller reset" "No effect,Reset"
|
|
bitfld.long 0x28 22. " IOPFRST ,I/O port F reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x28 20. " IOPDRST ,I/O port D reset" "No effect,Reset"
|
|
bitfld.long 0x28 19. " IOPCRST ,I/O port C reset" "No effect,Reset"
|
|
bitfld.long 0x28 18. " IOPBRST ,I/O port B reset" "No effect,Reset"
|
|
bitfld.long 0x28 17. " IOPARST ,I/O port A reset" "No effect,Reset"
|
|
line.long 0x2C "RCC_CFGR2,Clock configuration register 2"
|
|
bitfld.long 0x2C 4.--8. " ADC1PRES ,ADC1 prescaler" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,/1,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,/256,/256,/256,/256"
|
|
bitfld.long 0x2C 0.--3. " PREDIV[3:0] ,PREDIV division factor" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
line.long 0x30 "RCC_CFGR3,Clock configuration register 3"
|
|
bitfld.long 0x30 18.--19. " USART3SW[1:0] ,USART3 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x30 16.--17. " USART2SW[1:0] ,USART2 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x30 13. " TIM17SW ,Timer17 clock source selection" "PCLK2 clock,PLL vco output"
|
|
bitfld.long 0x30 11. " TIM16SW ,Timer16 clock source selection" "PCLK2 clock,PLL vco output"
|
|
textline " "
|
|
bitfld.long 0x30 10. " TIM15SW ,Timer15 clock source selection" "PCLK2 clock,PLL vco output"
|
|
bitfld.long 0x30 8. " TIM1SW ,Timer 1 clock source selection" "PCLK2,PLL"
|
|
sif CPUIS("STM32F318*8")
|
|
bitfld.long 0x30 6. " I2C3SW ,I2C3 clock source selection" "HSI,SYSCLK"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x30 5. " I2C2SW ,I2C2 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x30 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x30 0.--1. " USART1SW[1:0] ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
width 0xB
|
|
tree.end
|
|
elif cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40021000
|
|
width 14.
|
|
if (((per.l(ad:0x40021000))&0x10000)==0x10000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
rbitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " HSERDY ,High Speed External clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,High Speed External clock enable" "Off,On"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,High Speed Internal clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,High Speed Internal clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " HSIRDY ,High Speed Internal clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,High Speed Internal clock enable" "Off,On"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " HSERDY ,High Speed External clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,High Speed External clock enable" "Off,On"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,High Speed Internal clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,High Speed Internal clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " HSIRDY ,High Speed Internal clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,High Speed Internal clock enable" "Off,On"
|
|
endif
|
|
if (((per.l(ad:0x40021000))&0x1000000)==0x1000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RCC_CFGR,Clock configuration register"
|
|
sif cpuis("STM32F302*6")||cpuis("STM32F302*8")
|
|
bitfld.long 0x00 31. " PLLNODIV ,Do not divide PLL to MCO" "PLL/2,Not divided"
|
|
bitfld.long 0x00 29.--30. " MCOPRE ,Microcontroller Clock Output Prescaler" "/1-/2,/4-/8,/16-/32,/64-/128"
|
|
textline " "
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 31. " PLLNODIV ,Do not divide PLL to MCO" "PLL/2,Not divided"
|
|
bitfld.long 0x00 28.--30. " MCOPRE ,Microcontroller Clock Output Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
rbitfld.long 0x00 28. " MCOF ,Microcontroller Clock Output Flag" "Reset,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--26. " MCO ,Microcontroller Clock Output" "Disabled,,LSI,LSE,SYSCLK,HSI,HSE,PLL"
|
|
bitfld.long 0x00 23. " I2SSRC ,I2S external clock source selection" "System clock,External clock"
|
|
textline " "
|
|
bitfld.long 0x00 22. " USBPRES ,USB prescaler" "PLL/1.5,Not divided"
|
|
rbitfld.long 0x00 18.--21. " PLLMUL ,PLL multiplication factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
rbitfld.long 0x00 17. " PLLXTPRE ,HSE divider for PLL input clock" "Not divided,/2"
|
|
textline " "
|
|
sif cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
rbitfld.long 0x00 15.--16. " PLLSRC ,PLL entry clock source (input clock)" "HSI/2,HS1,HSE,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 16. " PLLSRC ,PLL entry clock source (input clock)" "HSI/2,HSE/PREDIV"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11.--13. " PPRE2 ,APB high-speed prescaler (APB2)" "-,-,-,-,HCLK/2,HCLK/2,HCLK/8,HCLK/16"
|
|
bitfld.long 0x00 8.--10. " PPRE1 ,APB Low-speed prescaler (APB1)" "-,-,-,-,HCLK/2,HCLK/2,HCLK/8,HCLK/16"
|
|
bitfld.long 0x00 4.--7. " HPRE ,HLCK prescaler" "-,-,-,-,-,-,-,-,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,?..."
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RCC_CFGR,Clock configuration register"
|
|
sif cpuis("STM32F302*6")||cpuis("STM32F302*8")
|
|
bitfld.long 0x00 31. " PLLNODIV ,Do not divide PLL to MCO" "PLL/2,Not divided"
|
|
bitfld.long 0x00 29.--30. " MCOPRE ,Microcontroller Clock Output Prescaler" "/1-/2,/4-/8,/16-/32,/64-/128"
|
|
textline " "
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 31. " PLLNODIV ,Do not divide PLL to MCO" "PLL/2,Not divided"
|
|
bitfld.long 0x00 28.--30. " MCOPRE ,Microcontroller Clock Output Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
rbitfld.long 0x00 28. " MCOF ,Microcontroller Clock Output Flag" "Reset,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--26. " MCO ,Microcontroller Clock Output" "Disabled,,LSI,LSE,SYSCLK,HSI,HSE,PLL"
|
|
bitfld.long 0x00 23. " I2SSRC ,I2S external clock source selection" "System clock,External clock"
|
|
textline " "
|
|
bitfld.long 0x00 22. " USBPRES ,USB prescaler" "PLL/1.5,Not divided"
|
|
bitfld.long 0x00 18.--21. " PLLMUL ,PLL multiplication factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
bitfld.long 0x00 17. " PLLXTPRE ,HSE divider for PLL input clock" "Not divided,/2"
|
|
textline " "
|
|
sif cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x00 15.--16. " PLLSRC ,PLL entry clock source (input clock)" "HSI/2,HS1,HSE,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16. " PLLSRC ,PLL entry clock source (input clock)" "HSI/2,HSE/PREDIV"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11.--13. " PPRE2 ,APB high-speed prescaler (APB2)" "-,-,-,-,HCLK/2,HCLK/2,HCLK/8,HCLK/16"
|
|
bitfld.long 0x00 8.--10. " PPRE1 ,APB Low-speed prescaler (APB1)" "-,-,-,-,HCLK/2,HCLK/2,HCLK/8,HCLK/16"
|
|
bitfld.long 0x00 4.--7. " HPRE ,HLCK prescaler" "-,-,-,-,-,-,-,-,SYSCLK/2,SYSCLK/4,SYSCLK/8,SYSCLK/16,SYSCLK/64,SYSCLK/128,SYSCLK/256,SYSCLK/512"
|
|
textline " "
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,?..."
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,?..."
|
|
endif
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x00 23. " CSSC ,Clock Security System Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " PLLRDYC ,PLL Ready Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " HSERDYC ,HSE Ready Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " HSIRDYC ,HSI Ready Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " LSERDYC ,LSE Ready Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " LSIRDYC ,LSI Ready Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " CSSF ,Clock Security System Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " PLLRDYF ,PLL Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 3. " HSERDYF ,HSE Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 2. " HSIRDYF ,HSI Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 1. " LSERDYF ,LSE Ready Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " LSIRDYF ,LSI Ready Interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x04 "RCC_APB2RSTR,APB2 Peripheral Reset Register"
|
|
bitfld.long 0x04 18. " TIM17RST ,TIM17 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x04 17. " TIM16RST ,TIM16 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x04 16. " TIM15RST ,TIM15 Timer Reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x04 15. " SPI4RST ,SPI4 Reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 14. " USART1RST ,USART1 Reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x04 12. " SPI1RST ,SPI1 Reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11. " TIM1RST ,TIM1 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x04 0. " SYSCFGRST ,Comparators And Operational Amplifiers Reset" "No effect,Reset"
|
|
line.long 0x08 "RCC_APB1RSTR,APB1 Peripheral reset register"
|
|
bitfld.long 0x08 30. " I2C3RST ,I2C3 reset" "No effect,Reset"
|
|
bitfld.long 0x08 29. " DAC1RST , DAC1 interface reset" "No effect,Reset"
|
|
bitfld.long 0x08 28. " PWRRST , Power interface reset" "No effect,Reset"
|
|
bitfld.long 0x08 25. " CANRST ,CAN reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x08 23. " USBRST ,USB reset" "No effect,Reset"
|
|
bitfld.long 0x08 22. " I2C2RST ,I2C2 reset" "No effect,Reset"
|
|
bitfld.long 0x08 21. " I2C1RST ,I2C1 reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x08 20. " UART5RST ,UART5 reset" "No effect,Reset"
|
|
bitfld.long 0x08 19. " UART4RST ,UART4 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 18. " USART3RST ,USART3 reset" "No effect,Reset"
|
|
bitfld.long 0x08 17. " USART2RST ,USART2 reset" "No effect,Reset"
|
|
bitfld.long 0x08 15. " SPI3RST ,SPI 3 reset" "No effect,Reset"
|
|
bitfld.long 0x08 14. " SPI2RST ,SPI2 reset" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 11. " WWDGRST ,Window watchdog reset" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TIM6RST ,Timer 6 reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
bitfld.long 0x08 2. " TIM4RST ,TIM4 timer reset" "No effect,Reset"
|
|
bitfld.long 0x08 1. " TIM3RST ,TIM3 timer reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
line.long 0x0C "RCC_AHBENR,AHB Peripheral Clock enable register"
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
bitfld.long 0x0C 28. " ADC12EN ,ADC1 and ADC2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x0C 28. " ADC1EN ,ADC1 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 24. " TSCEN ,Touch sensing controller clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x0C 23. " IOPGEN ,I/O port G clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 22. " IOPREN ,I/O port F clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
bitfld.long 0x0C 21. " IOPEEN ,I/O port E clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 20. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x0C 16. " IOPHEN ,I/O port H clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x0C 5. " FMCEN ,FMC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
bitfld.long 0x0C 1. " DMA2EN ,DMA 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 0. " DMA1EN ,DMA 1 clock enable" "Disabled,Enabled"
|
|
line.long 0x10 "RCC_APB2ENR,APB2 Peripheral Clock enable register"
|
|
bitfld.long 0x10 18. " TIM17EN ,TIM17 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " TIM16EN ,TIM16 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " TIM15EN ,TIM15 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x10 15. " SPI4EN ,SPI4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F302?E")&&!cpuis("STM32F302?D")
|
|
bitfld.long 0x10 12. " SPI1EN , SPI1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 11. " TIM1EN ,TIM1 Timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " SYSCFGEN ,SYSCFG clock enable" "Disabled,Enabled"
|
|
line.long 0x14 "RCC_APB1ENR,APB1 Peripheral Clock enable register"
|
|
sif cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x14 30. " I2C3EN ,I2C3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 29. " DAC1EN ,DAC 1 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 25. " CANEN ,CAN clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 23. " USBEN ,USB clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 22. " I2C2EN ,I2C2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x14 20. " UART5EN ,USART5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 19. " UART4EN ,USART4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 18. " USART3EN ,USART3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " USART2EN ,USART2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 15. " SPI3EN ,SPI 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " TIM6EN ,Timer 6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x14 2. " TIM4EN ,Timer 4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
bitfld.long 0x14 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40021000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RCC_BDCR,RTC domain control register"
|
|
bitfld.long 0x00 16. " BDRST ,RTC domain software reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x00 3.--4. " LSEDRV ,LSE oscillator drive capability in Xtal mode" "Lower,Medium low,Medium high,Higher"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " LSEBYP ,Low Speed External oscillator Bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 1. " LSERDY ,Low Speed External oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " LSEON ,Low Speed External oscillator enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RCC_BDCR,RTC domain control register"
|
|
bitfld.long 0x00 16. " BDRST ,RTC domain software reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x00 3.--4. " LSEDRV ,LSE oscillator drive capability in Xtal mode" "Lower,Medium low,Medium high,Higher"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LSEBYP ,Low Speed External oscillator Bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 1. " LSERDY ,Low Speed External oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " LSEON ,Low Speed External oscillator enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x24++0x0F
|
|
line.long 0x00 "RCC_CSR,Control/status register"
|
|
rbitfld.long 0x00 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 29. " IWDGRSTF ,Independent Watchdog reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 28. " SFTRSTF ,Software Reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 25. " OBLRSTF ,Option byte loader reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 24. " RMVF ,Remove reset flag" "No effect,Reset"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " V18PWRRSTF ,Reset flag of the 1.8 V domain" "Not occurred,Reset"
|
|
rbitfld.long 0x00 1. " LSIRDY ,Internal Low Speed oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " LSION ,Internal Low Speed oscillator enable" "Off,On"
|
|
line.long 0x04 "RCC_AHBRSTR,AHB peripheral reset register"
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x04 28. " ADC1PRST ,ADC1 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 24. " TSCRST ,Touch sensing controller reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x04 23. " IOPGRST ,I/O port G reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 22. " IOPFRST ,I/O port F reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F302?B")||cpuis("STM32F302?C")
|
|
bitfld.long 0x04 21. " IOPERST ,I/O port E reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 20. " IOPDRST ,I/O port D reset" "No effect,Reset"
|
|
bitfld.long 0x04 19. " IOPCRST ,I/O port C reset" "No effect,Reset"
|
|
bitfld.long 0x04 18. " IOPBRST ,I/O port B reset" "No effect,Reset"
|
|
bitfld.long 0x04 17. " IOPARST ,I/O port A reset" "No effect,Reset"
|
|
sif cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
textline " "
|
|
bitfld.long 0x04 16. " IOPHRST , I/O port H reset" "No effect,Reset"
|
|
bitfld.long 0x04 5. " FMCRST , FMC reset" "No effect,Reset"
|
|
endif
|
|
if (((per.l(ad:0x40021000))&0x1000000)==0x1000000)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RCC_CFGR2,Clock configuration register 2"
|
|
sif !cpuis("STM32F302?E")&&!cpuis("STM32F302?D")
|
|
bitfld.long 0x00 4.--8. " ADC1PRES ,ADC1 prescaler" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,/1,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,/256,/256,/256,/256"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 0.--3. " PREDIV ,PREDIV division factor" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RCC_CFGR2,Clock configuration register 2"
|
|
sif !cpuis("STM32F302?E")&&!cpuis("STM32F302?D")
|
|
bitfld.long 0x00 4.--8. " ADC1PRES ,ADC1 prescaler" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,/1,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,/256,/256,/256,/256"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0.--3. " PREDIV ,PREDIV division factor" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
sif cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
if (((per.l(ad:0x40021000))&0x1000000)==0x1000000)&&((((per.l(ad:0x40021000+0x04))&0x3800)<=0x2000)||(((per.l(ad:0x40021000+0x04))&0xF0)<=0x80))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCC_CFGR3,Clock configuration register 3"
|
|
bitfld.long 0x00 25. " TIM34SW ,Timer34 clock source selection" "PCLK2,PLL"
|
|
bitfld.long 0x00 24. " TIM2SW ,Timer2 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " USART3SW ,USART3 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 16.--17. " USART2SW ,USART2 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TIM17SW ,Timer17 clock source selection" "PCLK2,PLL"
|
|
bitfld.long 0x00 11. " TIM16SW ,Timer16 clock source selection" "PCLK2,PLL"
|
|
bitfld.long 0x00 10. " TIM15SW ,Timer15 clock source selection" "PCLK2,PLL"
|
|
bitfld.long 0x00 9. " TIM8SW ,Timer 8 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIM1SW ,Timer 1 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I2C2SW ,I2C2 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 0.--1. " USART1SW ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCC_CFGR3,Clock configuration register 3"
|
|
rbitfld.long 0x00 25. " TIM34SW ,Timer34 clock source selection" "PCLK2,PLL"
|
|
rbitfld.long 0x00 24. " TIM2SW ,Timer2 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " USART3SW ,USART3 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 16.--17. " USART2SW ,USART2 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " TIM17SW ,Timer17 clock source selection" "PCLK2,PLL"
|
|
rbitfld.long 0x00 11. " TIM16SW ,Timer16 clock source selection" "PCLK2,PLL"
|
|
rbitfld.long 0x00 10. " TIM15SW ,Timer15 clock source selection" "PCLK2,PLL"
|
|
rbitfld.long 0x00 9. " TIM8SW ,Timer 8 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " TIM1SW ,Timer 1 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
bitfld.long 0x00 5. " I2C2SW ,I2C2 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 0.--1. " USART1SW ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40021000))&0x1000000)==0x1000000)&&((((per.l(ad:0x40021000+0x04))&0x3800)<=0x2000)||(((per.l(ad:0x40021000+0x04))&0xF0)<=0x80))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCC_CFGR3,Clock configuration register 3"
|
|
bitfld.long 0x00 22.--23. " USART5SW ,USART5 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 20.--21. " USART4SW ,USART4 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 18.--19. " USART3SW ,USART3 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 16.--17. " USART2SW ,USART2 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TIM17SW ,Timer17 clock source selection" "PCLK2 clock,PLL vco output"
|
|
bitfld.long 0x00 11. " TIM16SW ,Timer16 clock source selection" "PCLK2 clock,PLL vco output"
|
|
bitfld.long 0x00 10. " TIM15SW ,Timer15 clock source selection" "PCLK2 clock,PLL vco output"
|
|
bitfld.long 0x00 8. " TIM1SW ,Timer 1 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CECSW ,HDMI CEC clock source selection" "HSI,LSE"
|
|
bitfld.long 0x00 5. " I2C2SW ,I2C2 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 0.--1. " USART1SW ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCC_CFGR3,Clock configuration register 3"
|
|
bitfld.long 0x00 22.--23. " USART5SW ,USART5 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 20.--21. " USART4SW ,USART4 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 18.--19. " USART3SW ,USART3 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 16.--17. " USART2SW ,USART2 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " TIM17SW ,Timer17 clock source selection" "PCLK2 clock,PLL vco output"
|
|
rbitfld.long 0x00 11. " TIM16SW ,Timer16 clock source selection" "PCLK2 clock,PLL vco output"
|
|
rbitfld.long 0x00 10. " TIM15SW ,Timer15 clock source selection" "PCLK2 clock,PLL vco output"
|
|
rbitfld.long 0x00 8. " TIM1SW ,Timer 1 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
bitfld.long 0x00 6. " CECSW ,HDMI CEC clock source selection" "HSI,LSE"
|
|
bitfld.long 0x00 5. " I2C2SW ,I2C2 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 0.--1. " USART1SW ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
elif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40021000
|
|
width 16.
|
|
if (((per.l(ad:0x40021000))&0x10000)==0x10000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
rbitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " HSERDY ,High Speed External clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,High Speed External clock enable" "Off,On"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,High Speed Internal clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,High Speed Internal clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " HSIRDY ,High Speed Internal clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,High Speed Internal clock enable" "Off,On"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " HSERDY ,High Speed External clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,High Speed External clock enable" "Off,On"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,High Speed Internal clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,High Speed Internal clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " HSIRDY ,High Speed Internal clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,High Speed Internal clock enable" "Off,On"
|
|
endif
|
|
if (((per.l(ad:0x40021000))&0x1000000)==0x1000000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RCC_CFGR,Clock configuration register"
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 31. " PLLNODIV ,Do not divide PLL to MCO" "PLL/2,Not divided"
|
|
bitfld.long 0x00 28.--30. " MCOPRE ,Microcontroller Clock Output Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
textline " "
|
|
elif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F328*8")
|
|
bitfld.long 0x00 31. " PLLNODIV ,Do not divide PLL to MCO" "PLL/2,Not divided"
|
|
bitfld.long 0x00 29.--30. " MCOPRE ,Microcontroller Clock Output Prescaler" "/1-/2,/4-/8,/16-/32,/64-/128"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
rbitfld.long 0x00 28. " MCOF ,Microcontroller Clock Output Flag" "Reset,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--26. " MCO ,Microcontroller Clock Output" "Disabled,,LSI,LSE,SYSCLK,HSI,HSE,PLL"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 23. " I2SSRC ,I2S external clock source selection" "System clock,External clock"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.long 0x00 22. " USBPRE ,USB prescaler" "PLL/1.5,Not divided"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 18.--21. " PLLMUL ,PLL multiplication factor" "x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x16"
|
|
rbitfld.long 0x00 17. " PLLXTPRE ,HSE divider for PLL input clock" "Not divided,/2"
|
|
textline " "
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
rbitfld.long 0x00 15.--16. " PLLSRC ,PLL entry clock source (input clock)" "HSI/2,HS1/PREDIV1,HSE/PREDIV1,?..."
|
|
textline " "
|
|
else
|
|
rbitfld.long 0x00 16. " PLLSRC ,PLL entry clock source (input clock)" "HSI/2,HSE/PREDIV"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11.--13. " PPRE2 ,APB high-speed prescaler (APB2)" "-,-,-,-,/2,/2,/8,/16"
|
|
bitfld.long 0x00 8.--10. " PPRE1 ,APB Low-speed prescaler (APB1)" "-,-,-,-,/2,/2,/8,/16"
|
|
bitfld.long 0x00 4.--7. " HPRE ,HLCK prescaler" "-,-,-,-,-,-,-,-,/2,/4,/8,/16,/64,/128,/256,/512"
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,Not applicable"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,Not allowed"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RCC_CFGR,Clock configuration register"
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 31. " PLLNODIV ,Do not divide PLL to MCO" "PLL/2,Not divided"
|
|
bitfld.long 0x00 28.--30. " MCOPRE ,Microcontroller Clock Output Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
textline " "
|
|
elif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F328*8")
|
|
bitfld.long 0x00 31. " PLLNODIV ,Do not divide PLL to MCO" "PLL/2,Not divided"
|
|
bitfld.long 0x00 29.--30. " MCOPRE ,Microcontroller Clock Output Prescaler" "/1-/2,/4-/8,/16-/32,/64-/128"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
rbitfld.long 0x00 28. " MCOF ,Microcontroller Clock Output Flag" "Reset,Set"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--26. " MCO ,Microcontroller Clock Output" "Disabled,,LSI,LSE,SYSCLK,HSI,HSE,PLL"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 23. " I2SSRC ,I2S external clock source selection" "System clock,External clock"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.long 0x00 22. " USBPRE ,USB prescaler" "PLL/1.5,Not divided"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--21. " PLLMUL ,PLL multiplication factor" "x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x16"
|
|
bitfld.long 0x00 17. " PLLXTPRE ,HSE divider for PLL input clock" "Not divided,/2"
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 15.--16. " PLLSRC ,PLL entry clock source (input clock)" "HSI/2,HS1/PREDIV1,HSE/PREDIV1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 16. " PLLSRC ,PLL entry clock source (input clock)" "HSI/2,HSE/PREDIV"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 11.--13. " PPRE2 ,APB high-speed prescaler (APB2)" "-,-,-,-,/2,/2,/8,/16"
|
|
bitfld.long 0x00 8.--10. " PPRE1 ,APB Low-speed prescaler (APB1)" "-,-,-,-,/2,/2,/8,/16"
|
|
bitfld.long 0x00 4.--7. " HPRE ,HLCK prescaler" "-,-,-,-,-,-,-,-,/2,/4,/8,/16,/64,/128,/256,/512"
|
|
rbitfld.long 0x00 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,Not applicable"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,Not allowed"
|
|
endif
|
|
group.long 0x08++0x17
|
|
line.long 0x00 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x00 23. " CSSC ,Clock Security System Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " PLLRDYC ,PLL Ready Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 19. " HSERDYC ,HSE Ready Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " HSIRDYC ,HSI Ready Interrupt Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " LSERDYC ,LSE Ready Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " LSIRDYC ,LSI Ready Interrupt Clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 7. " CSSF ,Clock Security System Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " PLLRDYF ,PLL Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 3. " HSERDYF ,HSE Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 2. " HSIRDYF ,HSI Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x00 1. " LSERDYF ,LSE Ready Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " LSIRDYF ,LSI Ready Interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x04 "RCC_APB2RSTR,APB2 Peripheral Reset Register"
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
bitfld.long 0x04 20. " TIM20RST ,TIM20 Timer Reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 18. " TIM17RST ,TIM17 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x04 17. " TIM16RST ,TIM16 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x04 16. " TIM15RST ,TIM15 Timer Reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
bitfld.long 0x04 15. " SPI4RST ,SPI4 Reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 14. " USART1RST ,USART1 Reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
bitfld.long 0x04 13. " TIM8RST ,TIM8 timer Reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 12. " SPI1RST ,SPI1 Reset" "No effect,Reset"
|
|
bitfld.long 0x04 11. " TIM1RST ,TIM1 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x04 0. " SYSCFGRST ,Comparators And Operational Amplifiers Reset" "No effect,Reset"
|
|
line.long 0x08 "RCC_APB1RSTR,APB1 Peripheral reset register"
|
|
sif cpuis("STM32F303?B")||cpuis("STM32F303?C")||cpuis("STM32F358?C")
|
|
bitfld.long 0x08 30. " I2C3RST ,I2C3 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 29. " DAC1RST , DAC1 interface clock reset" "No effect,Reset"
|
|
bitfld.long 0x08 28. " PWRRST , Power interface clock reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F328*8")
|
|
bitfld.long 0x08 26. " DAC2RST ,DAC 2 interface reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 25. " CANRST ,CAN interface reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?E")||cpuis("STM32F303?D")
|
|
bitfld.long 0x08 23. " USBRST ,USB interface reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F303?C")||cpuis("STM32F303?B")||cpuis("STM32F358?C")||cpuis("STM32F398VE")
|
|
bitfld.long 0x08 22. " I2C2RST ,I2C2 clock reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 21. " I2C1RST ,I2C1 clock reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
bitfld.long 0x08 20. " UART5RST ,USART5 reset" "No effect,Reset"
|
|
bitfld.long 0x08 19. " UART4RST ,USART4 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 18. " USART3RST ,USART3 reset" "No effect,Reset"
|
|
bitfld.long 0x08 17. " USART2RST ,USART2 reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
bitfld.long 0x08 15. " SPI3RST ,SPI 3 reset" "No effect,Reset"
|
|
bitfld.long 0x08 14. " SPI2RST ,SPI2 clock reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 11. " SPI2RST ,SPI2 clock enable" "No effect,Reset"
|
|
bitfld.long 0x08 5. " TIM7RST ,Timer 7 reset" "No effect,Reset"
|
|
bitfld.long 0x08 4. " TIM6RST ,Timer 6 reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F303?B")||cpuis("STM32F303?C")||cpuis("STM32F358?C")
|
|
bitfld.long 0x08 2. " TIM4RST ,Timer 4 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
bitfld.long 0x08 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
line.long 0x0C "RCC_AHBENR,AHB Peripheral Clock enable register"
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
bitfld.long 0x0C 29. " ADC34EN ,ADC3 and ADC4 reset" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 28. " ADC12EN ,ADC1 ADC2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " TSCEN ,Touch sensing controller clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")
|
|
bitfld.long 0x0C 23. " IOPGEN ,I/O port G clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 22. " IOPREN ,I/O port F clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x0C 21. " IOPEEN ,I/O port E clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 20. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 19. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 17. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")
|
|
bitfld.long 0x0C 16. " IOPHEN ,I/O port H clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")
|
|
bitfld.long 0x0C 5. " FMCEN ,FMC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x0C 1. " DMA2EN ,DMA 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 0. " DMA1EN ,DMA 1 clock enable" "Disabled,Enabled"
|
|
line.long 0x10 "RCC_APB2ENR,APB2 Peripheral Clock enable register"
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
bitfld.long 0x10 20. " TIM120EN ,TIM20 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 18. " TIM17EN ,TIM17 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " TIM16EN ,TIM16 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " TIM15EN ,TIM15 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
bitfld.long 0x10 15. " SPI4EN ,SPI4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
bitfld.long 0x10 13. " TIM8EN ,TIM8 Timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 12. " SPI1EN , SPI1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 11. " TIM1EN ,TIM1 Timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " SYSCFGEN ,SYSCFG clock enable" "Disabled,Enabled"
|
|
line.long 0x14 "RCC_APB1ENR,APB1 Peripheral Clock enable register"
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")
|
|
bitfld.long 0x14 30. " I2C3EN , I2C3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 29. " DAC1EN ,DAC 1 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F328*8")
|
|
bitfld.long 0x14 26. " DAC2EN ,DAC2 interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 25. " CANEN ,CAN interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x14 23. " USBEN ,USB interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x14 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x14 20. " UART5EN ,USART5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 19. " UART4EN ,USART4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 18. " USART3EN ,USART3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " USART2EN ,USART2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x14 15. " SPI3EN ,SPI 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 5. " TIM7EN ,Timer 7 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " TIM6EN ,Timer 6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x14 2. " TIM4EN ,Timer 4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40021000+0x20))&0x01)==0x01)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RCC_BDCR,Backup domain control register"
|
|
bitfld.long 0x00 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x00 3.--4. " LSEDRV ,LSE oscillator drive capability in Xtal mode" "Lower,Medium low,Medium high,Higher"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " LSEBYP ,Low Speed External oscillator Bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 1. " LSERDY ,Low Speed External oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " LSEON ,Low Speed External oscillator enable" "Off,On"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RCC_BDCR,Backup domain control register"
|
|
bitfld.long 0x00 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x00 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x00 3.--4. " LSEDRV ,LSE oscillator drive capability in Xtal mode" "Lower,Medium low,Medium high,Higher"
|
|
textline " "
|
|
bitfld.long 0x00 2. " LSEBYP ,Low Speed External oscillator Bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x00 1. " LSERDY ,Low Speed External oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " LSEON ,Low Speed External oscillator enable" "Off,On"
|
|
endif
|
|
group.long 0x24++0x07
|
|
line.long 0x00 "RCC_CSR,Control/status register"
|
|
rbitfld.long 0x00 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 29. " IWDGRSTF ,Independent Watchdog reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 28. " SFTRSTF ,Software Reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 25. " OBLRSTF ,Option byte loader reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 24. " RMVF ,Remove reset flag" "No effect,Reset"
|
|
textline " "
|
|
sif !cpuis("STM32F3*8")
|
|
rbitfld.long 0x00 23. " V18PWRRSTF ,Reset flag of the 1.8 V domain" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 1. " LSIRDY ,Internal Low Speed oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " LSION ,Internal Low Speed oscillator enable" "Off,On"
|
|
line.long 0x04 "RCC_AHBRSTR,AHB peripheral reset register"
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x04 29. " ADC34PRES ,ADC3 and ADC4 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 28. " ADC12PRST ,ADC1 ADC2 reset" "No effect,Reset"
|
|
bitfld.long 0x04 24. " TSCRST ,Touch sensing controller reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")
|
|
bitfld.long 0x04 23. " IOPGRST ,I/O port G reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 22. " IOPFRST ,I/O port F reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x04 21. " OPERST ,I/O port E reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 20. " IOPDRST ,I/O port D reset" "No effect,Reset"
|
|
bitfld.long 0x04 19. " IOPCRST ,I/O port C reset" "No effect,Reset"
|
|
bitfld.long 0x04 18. " IOPBRST ,I/O port B reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 17. " IOPARST ,I/O port A reset" "No effect,Reset"
|
|
textline " "
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")
|
|
bitfld.long 0x04 16. " IOPHRST , I/O port H reset" "No effect,Reset"
|
|
bitfld.long 0x04 5. " FMCRST , FMC reset" "No effect,Reset"
|
|
endif
|
|
if (((per.l(ad:0x40021000))&0x1000000)==0x1000000)
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RCC_CFGR2,Clock configuration register 2"
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 9.--13. " ADC34PRES ,ADC34 prescaler" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,/1,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,/256,/256,/256,/256"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--8. " ADC12PRES ,ADC1 prescaler" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,/1,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,/256,/256,/256,/256"
|
|
rbitfld.long 0x00 0.--3. " PREDIV ,PREDIV division factor" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
else
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "RCC_CFGR2,Clock configuration register 2"
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 9.--13. " ADC34PRES ,ADC34 prescaler" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,/1,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,/256,/256,/256,/256"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--8. " ADC12PRES ,ADC1 prescaler" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,/1,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,/256,/256,/256,/256"
|
|
bitfld.long 0x00 0.--3. " PREDIV ,PREDIV division factor" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
endif
|
|
sif cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40021000))&0x1000000)==0x1000000)&&((((per.l(ad:0x40021000+0x04))&0x3800)<=0x2000)||(((per.l(ad:0x40021000+0x04))&0xF0)<=0x80))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCC_CFGR3,Clock configuration register 3"
|
|
bitfld.long 0x00 25. " TIM34SW ,Timer34 clock source selection" "PCLK2,PLL"
|
|
bitfld.long 0x00 24. " TIM2SW ,Timer2 clock source selection" "PCLK2,PLL"
|
|
bitfld.long 0x00 22.--23. " USART5SW ,USART5 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 20.--21. " USART4SW ,USART4 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " USART3SW ,USART3 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 16.--17. " USART2SW ,USART2 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
sif !cpuis("STM32F398VE")
|
|
bitfld.long 0x00 15. " TIM20SW ,Timer20 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " TIM17SW ,Timer17 clock source selection" "PCLK2,PLL"
|
|
bitfld.long 0x00 11. " TIM16SW ,Timer16 clock source selection" "PCLK2,PLL"
|
|
bitfld.long 0x00 10. " TIM15SW ,Timer15 clock source selection" "PCLK2,PLL"
|
|
bitfld.long 0x00 9. " TIM8SW ,Timer 8 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIM1SW ,Timer 1 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
sif !cpuis("STM32F398VE")
|
|
bitfld.long 0x00 6. " I2C3SW ,I2C3 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " I2C2SW ,I2C2 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 0.--1. " USART1SW ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCC_CFGR3,Clock configuration register 3"
|
|
rbitfld.long 0x00 25. " TIM34SW ,Timer34 clock source selection" "PCLK2,PLL"
|
|
rbitfld.long 0x00 24. " TIM2SW ,Timer2 clock source selection" "PCLK2,PLL"
|
|
bitfld.long 0x00 22.--23. " USART5SW ,USART5 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 20.--21. " USART4SW ,USART4 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
sif !cpuis("STM32F398VE")
|
|
rbitfld.long 0x00 15. " TIM20SW ,Timer20 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 13. " TIM17SW ,Timer17 clock source selection" "PCLK2,PLL"
|
|
rbitfld.long 0x00 11. " TIM16SW ,Timer16 clock source selection" "PCLK2,PLL"
|
|
rbitfld.long 0x00 10. " TIM15SW ,Timer15 clock source selection" "PCLK2,PLL"
|
|
rbitfld.long 0x00 9. " TIM8SW ,Timer 8 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " TIM1SW ,Timer 1 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
sif !cpuis("STM32F398VE")
|
|
bitfld.long 0x00 6. " I2C3SW ,I2C3 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 5. " I2C2SW ,I2C2 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 0.--1. " USART1SW ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40021000))&0x1000000)==0x1000000)&&((((per.l(ad:0x40021000+0x04))&0x3800)<=0x2000)||(((per.l(ad:0x40021000+0x04))&0xF0)<=0x80))
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCC_CFGR3,Clock configuration register 3"
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 22.--23. " USART5SW ,USART5 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 20.--21. " USART4SW ,USART4 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " USART3SW ,USART3 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 16.--17. " USART2SW ,USART2 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 9. " TIM8SW ,Timer 8 clock source selection" "PCLK2,PLL"
|
|
bitfld.long 0x00 8. " TIM1SW ,Timer 1 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 5. " I2C2SW ,I2C2 clock source selection" "HSI,SYSCLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 0.--1. " USART1SW ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
endif
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "RCC_CFGR3,Clock configuration register 3"
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 22.--23. " USART5SW ,USART5 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 20.--21. " USART4SW ,USART4 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " USART3SW ,USART3 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x00 16.--17. " USART2SW ,USART2 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
rbitfld.long 0x00 9. " TIM8SW ,Timer 8 clock source selection" "PCLK2,PLL"
|
|
rbitfld.long 0x00 8. " TIM1SW ,Timer 1 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 5. " I2C2SW ,I2C2 clock source selection" "HSI,SYSCLK"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x00 0.--1. " USART1SW ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
endif
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC")
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40021000
|
|
width 14.
|
|
group.long 0x00++0x33
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " HSERDY ,High Speed External clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,High Speed External clock enable" "Off,On"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,High Speed Internal clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,High Speed Internal clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " HSIRDY ,High Speed Internal clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,High Speed Internal clock enable" "Off,On"
|
|
line.long 0x04 "RCC_CFGR,Clock configuration register"
|
|
bitfld.long 0x04 27.--31. " SDPRE ,SDADC prescaler" "/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/4,/6,/8,/10,/12,/14,/16,/20,/24,/28,/32,/36,/40,/44,/48"
|
|
bitfld.long 0x04 24.--26. " MCO ,Microcontroller Clock Output" "Disabled,,LSI,LSE,SYSCLK,HSI,HSE,PLL"
|
|
bitfld.long 0x04 22. " USBPRE ,USB prescaler" "PLL/1.5,Not divided"
|
|
bitfld.long 0x04 18.--21. " PLLMUL ,PLL multiplication factor" "x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x16"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PLLXTPRE ,HSE divider for PLL input clock" "Not divided,/2"
|
|
bitfld.long 0x04 16. " PLLSRC ,PLL entry clock source (input clock)" "HSI/2,HSE/PREDIV"
|
|
bitfld.long 0x04 14.--15. " ADCPRE ,ADC prescaler" "PCLK/2,PCLK/4,PCLK/6,PCLK/8"
|
|
bitfld.long 0x04 11.--13. " PPRE2 ,APB high-speed prescaler (APB2)" "-,-,-,-,/2,/2,/8,/16"
|
|
bitfld.long 0x04 8.--10. " PPRE1 ,APB Low-speed prescaler (APB1)" "-,-,-,-,/2,/2,/8,/16"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " HPRE ,HLCK prescaler" "-,-,-,-,-,-,-,-,/2,/4,/8,/16,/64,/128,/256,/512"
|
|
rbitfld.long 0x04 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,Not applicable"
|
|
bitfld.long 0x04 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,Not allowed"
|
|
line.long 0x08 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x08 23. " CSSC ,Clock Security System Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " PLLRDYC ,PLL Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 19. " HSERDYC ,HSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " HSIRDYC ,HSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " LSERDYC ,LSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " LSIRDYC ,LSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x08 7. " CSSF ,Clock Security System Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 4. " PLLRDYF ,PLL Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 3. " HSERDYF ,HSE Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 2. " HSIRDYF ,HSI Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 1. " LSERDYF ,LSE Ready Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 0. " LSIRDYF ,LSI Ready Interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x0C "RCC_APB2RSTR,APB2 Peripheral Reset Register"
|
|
bitfld.long 0x0C 26. " SDAD3RST ,SDADC3 (Sigma delta ADC 3) Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 25. " SDAD3RST ,SDADC2 (Sigma delta ADC 2) Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 24. " SDAD3RST ,SDADC1 (Sigma delta ADC 1) Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 19. " TIM19RST ,TIM19 Timer Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 18. " TIM17RST ,TIM17 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 17. " TIM16RST ,TIM16 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 16. " TIM15RST ,TIM15 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 14. " USART1RST ,USART1 Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 12. " SPI1RST ,SPI1 Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 9. " ADCRST ,ADC interface reset" "No effect,Reset"
|
|
bitfld.long 0x0C 0. " SYSCFGRST ,Comparators And Operational Amplifiers Reset" "No effect,Reset"
|
|
line.long 0x10 "RCC_APB1RSTR,APB1 Peripheral reset register"
|
|
bitfld.long 0x10 30. " CECRST ,HDMI CEC reset" "No effect,Reset"
|
|
bitfld.long 0x10 29. " DAC1RST , DAC1 interface clock reset" "No effect,Reset"
|
|
bitfld.long 0x10 28. " PWRRST , Power interface clock reset" "No effect,Reset"
|
|
bitfld.long 0x10 26. " DAC2RST ,DAC 2 interface reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 25. " CANRST ,CAN interface reset" "No effect,Reset"
|
|
bitfld.long 0x10 23. " USBRST ,USB interface reset" "No effect,Reset"
|
|
bitfld.long 0x10 22. " I2C2RST ,I2C 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C1 clock reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 18. " USART3RST ,USART3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 17. " USART2RST ,USART2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 15. " SPI3RST ,SPI 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 11. " WWDGRST ,Window watchdog reset" "No effect,Reset"
|
|
bitfld.long 0x10 9. " TIM18EN ,TIM18 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 8. " TIM14EN ,TIM14 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 7. " TIM13EN ,TIM13 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 6. " TIM12EN ,TIM12 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " TIM7RST ,Timer 7 reset" "No effect,Reset"
|
|
bitfld.long 0x10 4. " TIM6RST ,Timer 6 reset" "No effect,Reset"
|
|
bitfld.long 0x10 3. " TIM5RST ,Timer 5 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 2. " TIM4RST ,Timer 4 reset" "No effect,Reset"
|
|
bitfld.long 0x10 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
line.long 0x14 "RCC_AHBENR,AHB Peripheral Clock enable register"
|
|
bitfld.long 0x14 24. " TSCEN ,Touch sensing controller clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " IOPREN ,I/O port F clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 21. " IOPEEN ,I/O port E clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " DMA2EN ,DMA 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DMA1EN ,DMA 1 clock enable" "Disabled,Enabled"
|
|
line.long 0x18 "RCC_APB2ENR,APB2 Peripheral Clock enable register"
|
|
bitfld.long 0x18 26. " SDADC3 ,SDADC3 (Sigma Delta ADC 3) clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 25. " SDADC2 ,SDADC2 (Sigma Delta ADC 2) clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 24. " SDADC1 ,SDADC1 (Sigma Delta ADC 1) clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 19. " TIM19EN ,TIM19 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 18. " TIM17EN ,TIM17 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " TIM16EN ,TIM16 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 16. " TIM15EN ,TIM15 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 12. " SPI1EN , SPI1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 9. " ADCEN ,ADC interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " SYSCFGEN ,SYSCFG clock enable" "Disabled,Enabled"
|
|
line.long 0x1C "RCC_APB1ENR,APB1 Peripheral Clock enable register"
|
|
bitfld.long 0x1C 30. " CECEN ,HDMI CEC interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 29. " DAC1EN ,DAC 1 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 26. " DAC2EN ,DAC2 interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 25. " CANEN ,CAN interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 23. " USBEN ,USB interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 18. " USART3EN ,USART3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " USART2EN ,USART2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 15. " SPI3EN ,SPI 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 14. " SPI2EN ,SPI2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 9. " TIM18EN ,TIM18 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 8. " TIM14EN ,Timer 14 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 7. " TIM13EN ,Timer 13 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " TIM12EN ,Timer 12 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 5. " TIM7EN ,Timer 7 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 4. " TIM6EN ,Timer 6 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 3. " TIM5EN ,Timer 5 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 2. " TIM4EN ,Timer 4 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
line.long 0x20 "RCC_BDCR,Backup domain control register"
|
|
bitfld.long 0x20 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x20 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x20 3.--4. " LSEDRV ,LSE oscillator drive capability in Xtal mode" "Lower,Medium low,Medium high,Higher"
|
|
textline " "
|
|
bitfld.long 0x20 2. " LSEBYP ,Low Speed External oscillator Bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x20 1. " LSERDY ,Low Speed External oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x20 0. " LSEON ,Low Speed External oscillator enable" "Off,On"
|
|
line.long 0x24 "RCC_CSR,Control/status register"
|
|
bitfld.long 0x24 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 29. " IWDGRSTF ,Independent Watchdog reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 28. " SFTRSTF ,Software Reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 25. " OBLRSTF ,Option byte loader reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 24. " RMVF ,Remove reset flag" "Not activated,Reset"
|
|
textline " "
|
|
rbitfld.long 0x24 1. " LSIRDY ,Internal Low Speed oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x24 0. " LSION ,Internal Low Speed oscillator enable" "Off,On"
|
|
line.long 0x28 "RCC_AHBRSTR,AHB peripheral reset register"
|
|
bitfld.long 0x28 24. " TSCRST ,Touch sensing controller reset" "No effect,Reset"
|
|
bitfld.long 0x28 22. " IOPFRST ,I/O port F reset" "No effect,Reset"
|
|
bitfld.long 0x28 21. " IOPERST ,I/O port E reset" "No effect,Reset"
|
|
bitfld.long 0x28 20. " IOPDRST ,I/O port D reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x28 19. " IOPCRST ,I/O port C reset" "No effect,Reset"
|
|
bitfld.long 0x28 18. " IOPBRST ,I/O port B reset" "No effect,Reset"
|
|
bitfld.long 0x28 17. " IOPARST ,I/O port A reset" "No effect,Reset"
|
|
line.long 0x2C "RCC_CFGR2,Clock configuration register 2"
|
|
bitfld.long 0x2C 0.--3. " PREDIV[3:0] ,PREDIV division factor" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
line.long 0x30 "RCC_CFGR3,Clock configuration register 3"
|
|
bitfld.long 0x30 18.--19. " USART3SW[1:0] ,USART3 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x30 16.--17. " USART2SW[1:0] ,USART2 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x30 6. " CECSW ,HDMI CEC clock source selection" "HSI,LSE"
|
|
bitfld.long 0x30 5. " I2C2SW ,I2C2 clock source selection" "HSI,SYSCLK"
|
|
textline " "
|
|
bitfld.long 0x30 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x30 0.--1. " USART1SW[1:0] ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
width 0xB
|
|
tree.end
|
|
elif cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40021000
|
|
width 14.
|
|
group.long 0x00++0x33
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
rbitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
rbitfld.long 0x00 17. " HSERDY ,High Speed External clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,High Speed External clock enable" "Off,On"
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,High Speed Internal clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,High Speed Internal clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " HSIRDY ,High Speed Internal clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,High Speed Internal clock enable" "Off,On"
|
|
line.long 0x04 "RCC_CFGR,Clock configuration register"
|
|
bitfld.long 0x04 31. " PLLNODIV ,Do not divide PLL to MCO" "PLL/2,Not divided"
|
|
bitfld.long 0x04 28.--30. " MCOPRE ,Microcontroller Clock Output Prescaler" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x04 24.--26. " MCO ,Microcontroller Clock Output" "Disabled,,LSI,LSE,SYSCLK,HSI,HSE,PLL"
|
|
textline " "
|
|
bitfld.long 0x04 18.--21. " PLLMUL ,PLL multiplication factor" "x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x16"
|
|
bitfld.long 0x04 17. " PLLXTPRE ,HSE divider for PLL input clock" "Not divided,/2"
|
|
bitfld.long 0x04 16. " PLLSRC ,PLL entry clock source (input clock)" "HSI/2,HSE/PREDIV"
|
|
textline " "
|
|
bitfld.long 0x04 11.--13. " PPRE2 ,APB high-speed prescaler (APB2)" "-,-,-,-,/2,/2,/8,/16"
|
|
bitfld.long 0x04 8.--10. " PPRE1 ,APB Low-speed prescaler (APB1)" "-,-,-,-,/2,/2,/8,/16"
|
|
bitfld.long 0x04 4.--7. " HPRE ,HLCK prescaler" "-,-,-,-,-,-,-,-,/2,/4,/8,/16,/64,/128,/256,/512"
|
|
rbitfld.long 0x04 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,Not applicable"
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,Not allowed"
|
|
line.long 0x08 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x08 23. " CSSC ,Clock Security System Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " PLLRDYC ,PLL Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 19. " HSERDYC ,HSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " HSIRDYC ,HSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " LSERDYC ,LSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " LSIRDYC ,LSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
rbitfld.long 0x08 7. " CSSF ,Clock Security System Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 4. " PLLRDYF ,PLL Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 3. " HSERDYF ,HSE Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 2. " HSIRDYF ,HSI Ready Interrupt flag" "No interrupt,Interrupt"
|
|
rbitfld.long 0x08 1. " LSERDYF ,LSE Ready Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.long 0x08 0. " LSIRDYF ,LSI Ready Interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x0C "RCC_APB2RSTR,APB2 Peripheral Reset Register"
|
|
bitfld.long 0x0C 29. " HRTIM1RST ,High Resolution Timer1 reset" "No effect,Reset"
|
|
bitfld.long 0x0C 18. " TIM17RST ,TIM17 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 17. " TIM16RST ,TIM16 Timer Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 16. " TIM15RST ,TIM15 Timer Reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " USART1RST ,USART1 Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 12. " SPI1RST ,SPI1 Reset" "No effect,Reset"
|
|
bitfld.long 0x0C 11. " TIM1RST ,TIM1 timer reset" "No effect,Reset"
|
|
bitfld.long 0x0C 0. " SYSCFGRST ,Comparators And Operational Amplifiers Reset" "No effect,Reset"
|
|
line.long 0x10 "RCC_APB1RSTR,APB1 Peripheral reset register"
|
|
bitfld.long 0x10 29. " DAC1RST , DAC1 interface clock reset" "No effect,Reset"
|
|
bitfld.long 0x10 28. " PWRRST , Power interface clock reset" "No effect,Reset"
|
|
bitfld.long 0x10 26. " DAC2RST ,DAC 2 interface reset" "No effect,Reset"
|
|
bitfld.long 0x10 25. " CANRST ,CAN interface reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C1 clock reset" "No effect,Reset"
|
|
bitfld.long 0x10 18. " USART3RST ,USART3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 17. " USART2RST ,USART2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 11. " SPI2RST ,SPI2 clock enable" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 5. " TIM7RST ,Timer 7 reset" "No effect,Reset"
|
|
bitfld.long 0x10 4. " TIM6RST ,Timer 6 reset" "No effect,Reset"
|
|
bitfld.long 0x10 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
line.long 0x14 "RCC_AHBENR,AHB Peripheral Clock enable register"
|
|
bitfld.long 0x14 28. " ADC12EN ,ADC1 ADC2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 24. " TSCEN ,Touch sensing controller clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " IOPREN ,I/O port F clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 20. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 19. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 18. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " DMA2EN ,DMA 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " DMA1EN ,DMA 1 clock enable" "Disabled,Enabled"
|
|
line.long 0x18 "RCC_APB2ENR,APB2 Peripheral Clock enable register"
|
|
bitfld.long 0x18 29. " HRTIMER1EN , High Resolution Timer 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 18. " TIM17EN ,TIM17 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " TIM16EN ,TIM16 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 16. " TIM15EN ,TIM15 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 12. " SPI1EN , SPI1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 11. " TIM1EN ,TIM1 Timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 0. " SYSCFGEN ,SYSCFG clock enable" "Disabled,Enabled"
|
|
line.long 0x1C "RCC_APB1ENR,APB1 Peripheral Clock enable register"
|
|
bitfld.long 0x1C 29. " DAC1EN ,DAC 1 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 26. " DAC2EN ,DAC2 interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 25. " CANEN ,CAN interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 18. " USART3EN ,USART3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " USART2EN ,USART2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 5. " TIM7EN ,Timer 7 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 4. " TIM6EN ,Timer 6 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
line.long 0x20 "RCC_BDCR,Backup domain control register"
|
|
bitfld.long 0x20 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x20 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x20 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x20 3.--4. " LSEDRV ,LSE oscillator drive capability in Xtal mode" "Lower,Medium low,Medium high,Higher"
|
|
textline " "
|
|
bitfld.long 0x20 2. " LSEBYP ,Low Speed External oscillator Bypass" "Not bypassed,Bypassed"
|
|
rbitfld.long 0x20 1. " LSERDY ,Low Speed External oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x20 0. " LSEON ,Low Speed External oscillator enable" "Off,On"
|
|
line.long 0x24 "RCC_CSR,Control/status register"
|
|
rbitfld.long 0x24 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x24 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x24 29. " IWDGRSTF ,Independent Watchdog reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x24 28. " SFTRSTF ,Software Reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x24 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x24 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x24 25. " OBLRSTF ,Option byte loader reset flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x24 24. " RMVF ,Remove reset flag" "No effect,Reset"
|
|
textline " "
|
|
rbitfld.long 0x24 1. " LSIRDY ,Internal Low Speed oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x24 0. " LSION ,Internal Low Speed oscillator enable" "Off,On"
|
|
line.long 0x28 "RCC_AHBRSTR,AHB peripheral reset register"
|
|
bitfld.long 0x28 28. " ADC12PRST ,ADC1 ADC2 reset" "No effect,Reset"
|
|
bitfld.long 0x28 24. " TSCRST ,Touch sensing controller reset" "No effect,Reset"
|
|
bitfld.long 0x28 22. " IOPFRST ,I/O port F reset" "No effect,Reset"
|
|
bitfld.long 0x28 20. " IOPDRST ,I/O port D reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x28 19. " IOPCRST ,I/O port C reset" "No effect,Reset"
|
|
bitfld.long 0x28 18. " IOPBRST ,I/O port B reset" "No effect,Reset"
|
|
bitfld.long 0x28 17. " IOPARST ,I/O port A reset" "No effect,Reset"
|
|
line.long 0x2C "RCC_CFGR2,Clock configuration register 2"
|
|
bitfld.long 0x2C 4.--8. " ADC1PRES ,ADC1 prescaler" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,/1,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,/256,/256,/256,/256"
|
|
bitfld.long 0x2C 0.--3. " PREDIV[3:0] ,PREDIV division factor" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
line.long 0x30 "RCC_CFGR3,Clock configuration register 3"
|
|
bitfld.long 0x30 18.--19. " USART3SW[1:0] ,USART3 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x30 16.--17. " USART2SW[1:0] ,USART2 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
bitfld.long 0x30 12. " HRTIM1SW ,High Resolution Timer1 clock source selection" "High,Low"
|
|
bitfld.long 0x30 8. " TIM1SW ,Timer 1 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
bitfld.long 0x30 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x30 0.--1. " USART1SW[1:0] ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
width 0xB
|
|
tree.end
|
|
else
|
|
tree "RCC (Reset and Clock Control)"
|
|
base ad:0x40021000
|
|
width 14.
|
|
group.long 0x00++0x33
|
|
line.long 0x00 "RCC_CR,Clock control register"
|
|
bitfld.long 0x00 25. " PLLRDY ,PLL clock ready flag" "Unlocked,Locked"
|
|
bitfld.long 0x00 24. " PLLON ,PLL enable" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CSSON ,Clock Security System enable" "Off,On"
|
|
bitfld.long 0x00 18. " HSEBYP ,External High Speed clock Bypass" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 17. " HSERDY ,High Speed External clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 16. " HSEON ,High Speed External clock enable" "Off,On"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " HSICAL ,High Speed Internal clock Calibration"
|
|
bitfld.long 0x00 3.--7. " HSITRIM ,High Speed Internal clock trimming" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 1. " HSIRDY ,High Speed Internal clock ready flag" "Not ready,Ready"
|
|
bitfld.long 0x00 0. " HSION ,High Speed Internal clock enable" "Off,On"
|
|
line.long 0x04 "RCC_CFGR,Clock configuration register"
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x04 27.--31. " SDPRE ,SDADC prescaler" "/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/2,/4,/6,/8,/10,/12,/14,/16,/20,/24,/28,/32,/36,/40,/44,/48"
|
|
else
|
|
bitfld.long 0x04 28. " MCOF ,Microcontroller Clock Output Flag" "Low,High"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 24.--26. " MCO ,Microcontroller Clock Output" "No clock,,LSI,LSE,SYSCLK,HSI,HSE,PLL/2"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x04 23. " I2SSRC ,I2S external clock source selection" "System,External"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&cpu()!="STM32F313VC"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC")
|
|
bitfld.long 0x04 22. " USBPRE ,USB prescaler" "/1.5,Not divided"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 18.--21. " PLLMUL ,PLL Multiplication Factor" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,16"
|
|
textline " "
|
|
bitfld.long 0x04 17. " PLLXTPRE ,HSE divider for PLL entry" "HSE,HSE/2"
|
|
bitfld.long 0x04 16. " PLLSRC ,PLL entry clock source" "HSI/2,HSE/PREDIV"
|
|
textline " "
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x04 14.--15. " ADCPRE ,ADC prescaler" "PLCK/2,PLCK/4,PLCK/6,PLCK/8"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 11.--13. " PPRE2 ,APB2 high speed prescaler" "Not divided,Not divided,Not divided,Not divided,/2,/4,/8,/16"
|
|
bitfld.long 0x04 8.--10. " PPRE1 ,APB1 Low speed prescaler" "Not divided,Not divided,Not divided,Not divided,/2,/4,/8,/16"
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " HPRE ,AHB prescaler" "Not divided,Not divided,Not divided,Not divided,Not divided,Not divided,Not divided,Not divided,/2,/4,/8,/16,/64,/128,/256,/512"
|
|
bitfld.long 0x04 2.--3. " SWS ,System clock switch status" "HSI,HSE,PLL,?..."
|
|
textline " "
|
|
bitfld.long 0x04 0.--1. " SW ,System clock switch" "HSI,HSE,PLL,?..."
|
|
line.long 0x08 "RCC_CIR,Clock interrupt register"
|
|
bitfld.long 0x08 23. " CSSC ,Clock Security System Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 20. " PLLRDYC ,PLL Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 19. " HSERDYC ,HSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 18. " HSIRDYC ,HSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 17. " LSERDYC ,LSE Ready Interrupt Clear" "Not cleared,Cleared"
|
|
bitfld.long 0x08 16. " LSIRDYC ,LSI Ready Interrupt Clear" "Not cleared,Cleared"
|
|
textline " "
|
|
bitfld.long 0x08 12. " PLLRDYIE ,PLL Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " HSERDYIE ,HSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " HSIRDYIE ,HSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " LSERDYIE ,LSE Ready Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 8. " LSIRDYIE ,LSI Ready Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " CSSF ,Clock Security System Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 4. " PLLRDYF ,PLL Ready Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 3. " HSERDYF ,HSE Ready Interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 2. " HSIRDYF ,HSI Ready Interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x08 1. " LSERDYF ,LSE Ready Interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " LSIRDYF ,LSI Ready Interrupt flag" "No interrupt,Interrupt"
|
|
line.long 0x0C "RCC_APB2RSTR,APB2 Peripheral reset register"
|
|
sif (cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x0C 26. " SDAD3RST ,SDADC3 (Sigma delta ADC 3) reset" "No effect,Reset"
|
|
bitfld.long 0x0C 25. " SDAD2RST ,SDADC2 (Sigma delta ADC 2) reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x0C 24. " SDAD1RST ,SDADC1 (Sigma delta ADC 1) reset" "No effect,Reset"
|
|
bitfld.long 0x0C 19. " TIM19RST ,TIM19 timer reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 18. " TIM17RST ,TIM17 timer reset" "No effect,Reset"
|
|
bitfld.long 0x0C 17. " TIM16RST ,TIM16 timer reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " TIM15RST ,TIM15 timer reset" "No effect,Reset"
|
|
bitfld.long 0x0C 14. " USART1RST ,USART1 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x0C 13. " TIM8RST ,TIM8 Timer reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 12. " SPI1RST ,SPI 1 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC")
|
|
bitfld.long 0x0C 11. " TIM1RST ,TIM1 Timer reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x0C 9. " ADCRST ,ADC interface reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 0. " SYSCFGCOMPRST ,SYSCFG and COMP reset" "No effect,Reset"
|
|
line.long 0x10 "RCC_APB1RSTR,APB1 Peripheral reset register"
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x10 30. " CECRST ,HDMI CEC reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x10 29. " DAC1RST ,DAC 1 interface reset" "No effect,Reset"
|
|
else
|
|
bitfld.long 0x10 29. " DACRST ,DAC interface reset" "No effect,Reset"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 28. " PWRRST ,Power interface reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x10 29. " DAC2RST ,DAC 2 interface reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 25. " CANRST ,CAN interface reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&cpu()!="STM32F313VC"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC")
|
|
bitfld.long 0x10 23. " USBRST ,USB interface reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 22. " I2C2RST ,I2C 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 21. " I2C1RST ,I2C 1 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x10 20. " UART5RST ,USART5 reset" "No effect,Reset"
|
|
bitfld.long 0x10 19. " UART4RST ,USART4 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 18. " USART3RST ,USART3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 17. " USART2RST ,USART2 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 15. " SPI3RST ,SPI 3 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 14. " SPI2RST ,SPI 2 reset" "No effect,Reset"
|
|
bitfld.long 0x10 11. " WWDGRST ,Window Watchdog reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x10 9. " TIM18RST ,Timer 18 reset" "No effect,Reset"
|
|
bitfld.long 0x10 8. " TIM14RST ,Timer 14 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 7. " TIM13RST ,Timer 13 reset" "No effect,Reset"
|
|
bitfld.long 0x10 6. " TIM12RST ,Timer 12 reset" "No effect,Reset"
|
|
endif
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302VB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F302VC")&&(cpu()!="STM32F302RB")&&(cpu()!="STM32F302RC")
|
|
bitfld.long 0x10 5. " TIM7RST ,Timer 7 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 4. " TIM6RST ,Timer 6 reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x10 3. " TIM5RST ,Timer 5 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 2. " TIM4RST ,Timer 4 reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x10 1. " TIM3RST ,Timer 3 reset" "No effect,Reset"
|
|
bitfld.long 0x10 0. " TIM2RST ,Timer 2 reset" "No effect,Reset"
|
|
line.long 0x14 "RCC_AHBENR,AHB Peripheral Clock enable register"
|
|
sif (cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x14 29. " ADC34EN ,ADC3 and ADC4 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x14 28. " ADC12EN ,ADC1 and ADC2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 24. " TSCEN ,Touch sensing controller clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 22. " IOPFEN ,I/O port F clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB"&&cpu()!="STM32F302CC"&&cpu()!="STM32F302RB"&&cpu()!="STM32F302RC"&&cpu()!="STM32F303CB"&&cpu()!="STM32F303CC"&&cpu()!="STM32F303RB"&&cpu()!="STM32F303RC"&&cpu()!="STM32F313CC"&&cpu()!="STM32F313RC")
|
|
bitfld.long 0x14 21. " IOPEEN ,I/O port E clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F302CB"&&cpu()!="STM32F302CC"&&cpu()!="STM32F303CB"&&cpu()!="STM32F303CC"&&cpu()!="STM32F313CC")
|
|
bitfld.long 0x14 20. " IOPDEN ,I/O port D clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x14 19. " IOPCEN ,I/O port C clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 18. " IOPBEN ,I/O port B clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 17. " IOPAEN ,I/O port A clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 6. " CRCEN ,CRC clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " FLITFEN ,FLITF clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 2. " SRAMEN ,SRAM interface clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 1. " DMA2EN ,DMA 2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 0. " DMA1EN ,DMA 1 clock enable" "Disabled,Enabled"
|
|
line.long 0x18 "RCC_APB2ENR,APB2 Peripheral Clock enable register"
|
|
sif (cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x18 26. " SDADC3 ,SDADC3 (Sigma Delta ADC 3) clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 25. " SDADC2 ,SDADC2 (Sigma Delta ADC 2) clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x18 24. " SDADC1 ,SDADC1 (Sigma Delta ADC 1) clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x18 19. " TIM19EN ,TIM17 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 18. " TIM17EN ,TIM17 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 17. " TIM16EN ,TIM16 timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x18 16. " TIM15EN ,TIM15 timer clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x18 14. " USART1EN ,USART1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC")
|
|
bitfld.long 0x18 13. " TIM8EN ,TIM8 Timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 12. " SPI1EN ,SPI 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x18 11. " TIM1EN ,TIM1 Timer clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x18 9. " ADC1EN ,ADC interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x18 0. " SYSCFGEN ,SYSCFG clock enable" "Disabled,Enabled"
|
|
line.long 0x1C "RCC_APB1ENR,APB1 Peripheral Clock enable register"
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x1C 30. " CECEN ,HDMI CEC interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x1C 29. " DAC1EN ,DAC 1 interface clock enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x1C 29. " DACEN ,DAC interface clock enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x1C 28. " PWREN ,Power interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x1C 29. " DAC2EN ,DAC 2 interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 25. " CANEN ,CAN interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&cpu()!="STM32F313VC"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC")
|
|
bitfld.long 0x1C 23. " USBEN ,USB interface clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 22. " I2C2EN ,I2C 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 21. " I2C1EN ,I2C 1 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x1C 20. " UART5EN ,USART5 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 19. " UART4EN ,USART4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 18. " USART3EN ,USART3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 17. " USART2EN ,USART2 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " SPI3EN ,SPI 3 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 14. " SPI2EN ,SPI 2 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 11. " WWDGEN ,Window Watchdog clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x1C 9. " TIM18EN ,Timer 18 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 8. " TIM14EN ,Timer 14 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 7. " TIM13EN ,Timer 13 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 6. " TIM12EN ,Timer 12 clock enable" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302VB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F302VC")&&(cpu()!="STM32F302RB")&&(cpu()!="STM32F302RC")
|
|
bitfld.long 0x1C 5. " TIM7EN ,Timer 7 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 4. " TIM6EN ,Timer 6 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x1C 3. " TIM5EN ,Timer 5 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x1C 2. " TIM4EN ,Timer 4 clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x1C 1. " TIM3EN ,Timer 3 clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x1C 0. " TIM2EN ,Timer 2 clock enable" "Disabled,Enabled"
|
|
line.long 0x20 "RCC_BDCR,Backup domain control register"
|
|
bitfld.long 0x20 16. " BDRST ,Backup domain software reset" "No reset,Reset"
|
|
bitfld.long 0x20 15. " RTCEN ,RTC clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x20 8.--9. " RTCSEL ,RTC clock source selection" "No clock,LSE,LSI,HSE"
|
|
bitfld.long 0x20 3.--4. " LSEDRV ,LSE oscillator drive capability in Xtal mode" "Lower,Medium low,Medium high,Higher"
|
|
textline " "
|
|
bitfld.long 0x20 2. " LSEBYP ,Low Speed External oscillator Bypass" "Not bypassed,Bypassed"
|
|
bitfld.long 0x20 1. " LSERDY ,Low Speed External oscillator Ready" "Not ready,Ready"
|
|
textline " "
|
|
bitfld.long 0x20 0. " LSEON ,Low Speed External oscillator enable" "Off,On"
|
|
line.long 0x24 "RCC_CSR,Control/status register"
|
|
bitfld.long 0x24 31. " LPWRRSTF ,Low-Power reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 30. " WWDGRSTF ,Window watchdog reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 29. " IWDGRSTF ,Independent Watchdog reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 28. " SFTRSTF ,Software Reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 27. " PORRSTF ,POR/PDR reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 26. " PINRSTF ,PIN reset flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x24 25. " OBLRSTF ,Option byte loader reset flag" "Not occurred,Occurred"
|
|
bitfld.long 0x24 24. " RMVF ,Remove reset flag" "Not activated,Reset"
|
|
textline " "
|
|
bitfld.long 0x24 1. " LSIRDY ,Internal Low Speed oscillator Ready" "Not ready,Ready"
|
|
bitfld.long 0x24 0. " LSION ,Internal Low Speed oscillator enable" "Off,On"
|
|
line.long 0x28 "RCC_AHBRSTR,AHB peripheral reset register"
|
|
sif (cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x28 29. " ADC34PRES ,ADC3 and ADC4 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x28 28. " ADC12PRES ,ADC1 and ADC2 reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 24. " TSCRST ,Touch sensing controller reset" "No effect,Reset"
|
|
bitfld.long 0x28 22. " IOPFRST ,I/O port F reset" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB"&&cpu()!="STM32F302CC"&&cpu()!="STM32F302RB"&&cpu()!="STM32F302RC"&&cpu()!="STM32F303CB"&&cpu()!="STM32F303CC"&&cpu()!="STM32F303RB"&&cpu()!="STM32F303RC"&&cpu()!="STM32F313CC"&&cpu()!="STM32F313RC")
|
|
bitfld.long 0x28 21. " IOPERST ,I/O port E reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F302CB"&&cpu()!="STM32F302CC"&&cpu()!="STM32F303CB"&&cpu()!="STM32F303CC"&&cpu()!="STM32F313CC")
|
|
bitfld.long 0x28 20. " IOPDRST ,I/O port D reset" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x28 19. " IOPCRST ,I/O port C reset" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x28 18. " IOPBRST ,I/O port B reset" "No effect,Reset"
|
|
bitfld.long 0x28 17. " IOPARST ,I/O port A reset" "No effect,Reset"
|
|
line.long 0x2C "RCC_CFGR2,Clock configuration register 2"
|
|
sif (cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x2C 9.--13. " ADC34PRES ,ADC34 prescaler" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,/1,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,/256,/256,/256,/256"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x2C 4.--8. " ADC12PRES ,ADC12 prescaler" "Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,Disabled,/1,/2,/4,/6,/8,/10,/12,/16,/32,/64,/128,/256,/256,/256,/256,/256"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x2C 0.--3. " PREDIV[3:0] ,PREDIV division factor" "Not divided,/2,/3,/4,/5,/6,/7,/8,/9,/10,/11,/12,/13,/14,/15,/16"
|
|
line.long 0x30 "RCC_CFGR3,Clock configuration register 3"
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x30 22.--23. " USART5SW[1:0] ,USART5 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x30 20.--21. " USART4SW[1:0] ,USART4 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 18.--19. " USART3SW[1:0] ,USART3 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
bitfld.long 0x30 16.--17. " USART2SW[1:0] ,USART2 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC")
|
|
sif (cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC")
|
|
bitfld.long 0x30 9. " TIM8SW ,Timer 8 clock source selection" "PCLK2,PLL"
|
|
endif
|
|
bitfld.long 0x30 8. " TIM1SW ,Timer 1 clock source selection" "PCLK2,PLL"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x30 6. " CECSW ,HDMI CEC clock source selection" "HSI,LSE"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x30 5. " I2C2SW ,I2C2 clock source selection" "HSI,SYSCLK"
|
|
textline " "
|
|
bitfld.long 0x30 4. " I2C1SW ,I2C1 clock source selection" "HSI,SYSCLK"
|
|
bitfld.long 0x30 0.--1. " USART1SW[1:0] ,USART1 clock source selection" "PCLK,SYSCLK,LSE,HSI"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
tree "FSMC (Flexible static memory controller)"
|
|
base ad:0xA0000400
|
|
width 12.
|
|
tree "NOR/PSRAM Controller Registers"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "FSMC_BCR1,SRAM/NOR-Flash Chip-select Control Register 1"
|
|
bitfld.long 0x00 20. " CCLKEN , Continuous Clock Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Not taken,Taken"
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Low,High"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
if (((per.l((ad:0xA0000400+0x0)))&0x4000)==0x4000)
|
|
group.long (0x0+0x4)++0x03
|
|
line.long 0x00 "FSMC_BTR1,SRAM/NOR-Flash chip-select timing register 1"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
else
|
|
group.long (0x0+0x4)++0x03
|
|
line.long 0x00 "FSMC_BTR1,SRAM/NOR-Flash chip-select timing register 1"
|
|
rbitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long (0x0+0x104)++0x3
|
|
line.long 0x00 "FSMC_BWTR1,SRAM/NOR-Flash Write Timing Register 1"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FSMC_BCR2,SRAM/NOR-Flash Chip-select Control Register 2"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Not taken,Taken"
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Low,High"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
if (((per.l((ad:0xA0000400+0x8)))&0x4000)==0x4000)
|
|
group.long (0x8+0x4)++0x03
|
|
line.long 0x00 "FSMC_BTR2,SRAM/NOR-Flash chip-select timing register 2"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
else
|
|
group.long (0x8+0x4)++0x03
|
|
line.long 0x00 "FSMC_BTR2,SRAM/NOR-Flash chip-select timing register 2"
|
|
rbitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long (0x8+0x104)++0x3
|
|
line.long 0x00 "FSMC_BWTR2,SRAM/NOR-Flash Write Timing Register 2"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FSMC_BCR3,SRAM/NOR-Flash Chip-select Control Register 3"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Not taken,Taken"
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Low,High"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
if (((per.l((ad:0xA0000400+0x10)))&0x4000)==0x4000)
|
|
group.long (0x10+0x4)++0x03
|
|
line.long 0x00 "FSMC_BTR3,SRAM/NOR-Flash chip-select timing register 3"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
else
|
|
group.long (0x10+0x4)++0x03
|
|
line.long 0x00 "FSMC_BTR3,SRAM/NOR-Flash chip-select timing register 3"
|
|
rbitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long (0x10+0x104)++0x3
|
|
line.long 0x00 "FSMC_BWTR3,SRAM/NOR-Flash Write Timing Register 3"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FSMC_BCR4,SRAM/NOR-Flash Chip-select Control Register 4"
|
|
bitfld.long 0x00 19. " CBURSTRW ,Write burst enable" "Asynchronous,Synchronous"
|
|
bitfld.long 0x00 15. " ASYNCWAIT ,Wait signal during asynchronous transfers" "Not taken,Taken"
|
|
bitfld.long 0x00 14. " EXTMOD ,Extended mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " WAITEN ,Wait enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WREN ,Write enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " WAITCFG ,Wait timing configuration" "One clock cycle,During wait state"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WRAPMOD ,Wrapped burst mode support" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " WAITPOL ,Wait signal polarity bit" "Low,High"
|
|
bitfld.long 0x00 8. " BURSTEN ,Burst enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " FACCEN ,Flash access enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4.--5. " MWID ,Memory databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 2.--3. " MTYP ,Memory type" "SRAM,PSRAM,NOR,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " MUXEN ,Address/data multiplexing enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MBKEN ,Memory bank enable bit" "Disabled,Enabled"
|
|
if (((per.l((ad:0xA0000400+0x18)))&0x4000)==0x4000)
|
|
group.long (0x18+0x4)++0x03
|
|
line.long 0x00 "FSMC_BTR4,SRAM/NOR-Flash chip-select timing register 4"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
else
|
|
group.long (0x18+0x4)++0x03
|
|
line.long 0x00 "FSMC_BTR4,SRAM/NOR-Flash chip-select timing register 4"
|
|
rbitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 24.--27. " DATLAT ,Data latency" "2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17"
|
|
bitfld.long 0x00 20.--23. " CLKDIV ,Clock divide ratio" ",HCLK*2,HCLK*3,,,,,,,,,,,,,HCLK*16"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
endif
|
|
group.long (0x18+0x104)++0x3
|
|
line.long 0x00 "FSMC_BWTR4,SRAM/NOR-Flash Write Timing Register 4"
|
|
bitfld.long 0x00 28.--29. " ACCMOD ,Access mode" "A,B,C,D"
|
|
bitfld.long 0x00 16.--19. " BUSTURN ,Bus turnaround phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " DATAST ,Data-phase duration"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " ADDHLD ,Address-hold phase duration" ",HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
bitfld.long 0x00 0.--3. " ADDSET ,Address setup phase duration" "HCLK*0,HCLK*1,HCLK*2,HCLK*3,HCLK*4,HCLK*5,HCLK*6,HCLK*7,HCLK*8,HCLK*9,HCLK*10,HCLK*11,HCLK*12,HCLK*13,HCLK*14,HCLK*15"
|
|
tree.end
|
|
tree "NAND Flash/PC Card Controller Registers"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "FSMC_PCR2,PC Card/NAND Flash Control Registers 2"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBKEN ,PC Card/NAND Flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
group.long (0x60+0x4)++0x03
|
|
line.long 0x00 "FSMC_SR2,FIFO Status and Interrupt Register 2"
|
|
rbitfld.long 0x00 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
group.long (0x60+0x8)++0x03
|
|
line.long 0x00 "FSMC_PMEM2,Common Memory Space Timing Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MEMHIZ2 ,Common memory 2 data bus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MEMHOLD2 ,Common memory 2 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MEMWAIT2 ,Common memory 2 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MEMSET2 ,Common memory 2 setup time"
|
|
group.long (0x60+0xC)++0x03
|
|
line.long 0x00 "FSMC_PATT2,Attribute Memory Space Timing Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTHIZ2 ,Attribute memory 2 databus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTHOLD2 ,Attribute memory 2 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTWAIT2 ,Attribute memory 2 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTSET2 ,Attribute memory 2 setup time"
|
|
if (((per.l((ad:0xA0000400+0x60)))&0xe0000)==0x00)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000400+0x60)))&0xe0000)==0x20000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000400+0x60)))&0xe0000)==0x40000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--25. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000400+0x60)))&0xe0000)==0x60000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--27. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000400+0x60)))&0xe0000)==0x80000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
hexmask.long 0x00 0.--29. 1. " ECC2 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000400+0x60)))&0xe0000)==0xa0000)
|
|
rgroup.long (0x60+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
else
|
|
hgroup.long (0x60+0x14)++0x3
|
|
hide.long 0x00 "FSMC_ECCR2,ECC Result Register 2"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "FSMC_PCR3,PC Card/NAND Flash Control Registers 3"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBKEN ,PC Card/NAND Flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
group.long (0x80+0x4)++0x03
|
|
line.long 0x00 "FSMC_SR3,FIFO Status and Interrupt Register 3"
|
|
rbitfld.long 0x00 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
group.long (0x80+0x8)++0x03
|
|
line.long 0x00 "FSMC_PMEM3,Common Memory Space Timing Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MEMHIZ3 ,Common memory 3 data bus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MEMHOLD3 ,Common memory 3 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MEMWAIT3 ,Common memory 3 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MEMSET3 ,Common memory 3 setup time"
|
|
group.long (0x80+0xC)++0x03
|
|
line.long 0x00 "FSMC_PATT3,Attribute Memory Space Timing Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTHIZ3 ,Attribute memory 3 databus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTHOLD3 ,Attribute memory 3 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTWAIT3 ,Attribute memory 3 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTSET3 ,Attribute memory 3 setup time"
|
|
if (((per.l((ad:0xA0000400+0x80)))&0xe0000)==0x00)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long.tbyte 0x00 0.--21. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000400+0x80)))&0xe0000)==0x20000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000400+0x80)))&0xe0000)==0x40000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--25. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000400+0x80)))&0xe0000)==0x60000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--27. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000400+0x80)))&0xe0000)==0x80000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
hexmask.long 0x00 0.--29. 1. " ECC3 ,Value computed by the ECC computation logic"
|
|
elif (((per.l((ad:0xA0000400+0x80)))&0xe0000)==0xa0000)
|
|
rgroup.long (0x80+0x14)++0x3
|
|
line.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
else
|
|
hgroup.long (0x80+0x14)++0x3
|
|
hide.long 0x00 "FSMC_ECCR3,ECC Result Register 3"
|
|
endif
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "FSMC_PCR4,PC Card/NAND Flash Control Registers 4"
|
|
bitfld.long 0x00 17.--19. " ECCPS ,ECC page size" "256 bytes,512 bytes,1024 bytes,2048 bytes,4096 bytes,8192 bytes,?..."
|
|
bitfld.long 0x00 13.--16. " TAR ,ALE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
textline " "
|
|
bitfld.long 0x00 9.--12. " TCLR ,CLE to RE delay" "1 HCLK,2 HCLK,3 HCLK,4 HCLK,5 HCLK,6 HCLK,7 HCLK,8 HCLK,9 HCLK,10 HCLK,11 HCLK,12 HCLK,13 HCLK,14 HCLK,15 HCLK,16 HCLK"
|
|
bitfld.long 0x00 6. " ECCEN ,ECC computation logic enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " PWID ,Databus width" "8 bits,16 bits,?..."
|
|
bitfld.long 0x00 3. " PTYP ,Memory type" "PC Card/CompactFlash/CF+/PCMCIA,NAND Flash"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PBKEN ,PC Card/NAND Flash memory bank enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PWAITEN ,Wait feature enable bit" "Disabled,Enabled"
|
|
group.long (0xA0+0x4)++0x03
|
|
line.long 0x00 "FSMC_SR4,FIFO Status and Interrupt Register 4"
|
|
rbitfld.long 0x00 6. " FEMPT ,FIFO empty" "Not empty,Empty"
|
|
bitfld.long 0x00 5. " IFEN ,Interrupt falling edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ILEN ,Interrupt high-level detection enable bit" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IREN ,Interrupt rising edge detection enable bit" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IFS ,Interrupt falling edge status" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " ILS ,Interrupt high-level status" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IRS ,Interrupt rising edge status" "Not occurred,Occurred"
|
|
group.long (0xA0+0x8)++0x03
|
|
line.long 0x00 "FSMC_PMEM4,Common Memory Space Timing Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " MEMHIZ4 ,Common memory 4 data bus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " MEMHOLD4 ,Common memory 4 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " MEMWAIT4 ,Common memory 4 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " MEMSET4 ,Common memory 4 setup time"
|
|
group.long (0xA0+0xC)++0x03
|
|
line.long 0x00 "FSMC_PATT4,Attribute Memory Space Timing Register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTHIZ4 ,Attribute memory 4 databus HiZ time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTHOLD4 ,Attribute memory 4 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTWAIT4 ,Attribute memory 4 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTSET4 ,Attribute memory 4 setup time"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "FMC_PIO4,I/O space timing register 4"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IOHIZ4 , I/O 4 data bus Hi-Z time"
|
|
hexmask.long.byte 0x00 16.--23. 1. " IOHOLD4 ,I/O 4 hold time"
|
|
textline " "
|
|
hexmask.long.byte 0x00 8.--15. 1. " IOWAIT4 ,I/O 4 wait time"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IOSET4 ,I/O 4 setup time"
|
|
tree.end
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F318*8")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||cpuis("STM32F334*")||cpuis("STM32F378*")
|
|
tree.open "GPIO (General-Purpose I/O)"
|
|
tree "GPIO A"
|
|
base ad:0x48000000
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOA_ODR,GPIO Port A output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port A output data" "Low,High"
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit 3 " "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit 0" "Not locked,Locked"
|
|
textline ""
|
|
width 15.
|
|
sif CPUIS("STM32F358*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,TIM3_CH2,TSC_G2_IO4,TIM8_CH1N,SPI_MOSI,TIM1_CH1N,,COMP2_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,TIM3_CH1,TSC_G2IO3,TIM8_BKIN,SPI1_MISO,TIM1_BKIN,,COMP1_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" ",TIM2_CH1_ETR,,TSC_G2_IO2,,SPI_SCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" ",,TIM3_CH2,TSC_G2_IO1,,SPI1_NSS,SPI3_NSS/I2S3_W3,USART2_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,,TSC_G1_IO4,,,S,USART2_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" ",TIM2_CH3,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" "RTC_REFIN,TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS,,TIM15_CH1N,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" ",TIM2_CH1_ETR,,TSC_G1_IO1,,,,USART2_CTS,COMP1_OUT,TIM8_BKIN,TIM8_ETR,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1_ETR,TIM8_CH1,3,I2C1_SCL,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_RX,,TIM1_BKIN,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" "SWCLK-JTCK,,,TSC_G4_IO4,I2C1_SDA,TIM8_CH2,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" "SWDIO-JTMS,TIM16_CH1N,,TSC_G4_IO3,,IR_OUT,,USART3_CTS,,,TIM4_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,,TIM1_CH2N,USART1_RTS,COMP2_OUT,CAN_TX,TIM4_CH2,TIM1_ETR,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,,,,,TIM1_CH1N,USART1_CTS,COMP1_OUT,CAN_RX,TIM4_CH1,TIM4_CH4,TIM1_BKIN2,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,I2C2_SDA,,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,TIM8_BKIN,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" ",,,TSC_G4_IO1,I2C2_SCL,I2S3_MCK,TIM1_CH2,USART1_TX,COMP5_OUT,TIM15_BKIN,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "MCO,,,,I2C2_SMBA,I2S2_MCK,TIM1_CH1,USART1_CK,COMP3_OUT,,TIM4_ETR,,,,,EVENTOUT"
|
|
elif CPUIS("STM32F301*6")||CPUIS("STM32F301*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,,TSC_G2_IO4,,,TIM1_CH1N,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,,TSC_G2_IO3,,,TIM1_BKIN,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TSC_G2_IO2,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" ",,,TSC_G2_IO1,,,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,,TSC_G1_IO4,,,,USART2_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" ",TIM2_CH2,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" "RTC_REFIN,TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS_DE,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" ",EIM2_CH1/TIM2_ETR,,TSC_G1_IO1,,,,USART2_CTS,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,TSC_SYNC,I2C1_SCL,,SPI3_NSS/I2S3_WS,USART2_RX,,TIM1_BKIN,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" "SWDAT-JTCK,,,TSC_G4_IO4,I2C1_SDA,,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" "SWDAT-JMTS,TIM16_CH1,,TSC_G4_IO3,,IR-OUT,,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,I2SCKIN,TIM1_CH2N,USART1_RTS_DE,COMP2_OUT,,,TIM1_ETR,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,,,,SPI2_MOSI/I2S2_SD,TIM1_CH1N,USART1_CTS,,,,TIM1_CH4,TIM1_BKIN2,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,I2C2_SDA,SPI2_MISO/I2S2_extSD,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" ",,I2C3_SMBAL,TSC_G4_IO1,I2C2_SCL,I2S3_MCK,TIM1_CH2,USART1_TX,,,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "MCO,,,I2C3_SCL,I2C2_SMBAL,I2S2_MCK,TIM1_CH1,USART1_CK,,,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F318*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,,TSC_G2_IO4,,,TIM1_CH1N,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,,TSC_G2_IO3,,,TIM1_BKIN,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TSC_G2_IO2,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" ",,,TSC_G2_IO1,,,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,,TSC_G1_IO4,,,,USART2_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" ",TIM2_CH2,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" "RTC_REFIN,TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS_DE,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" ",EIM2_CH1/TIM2_ETR,,TSC_G1_IO1,,,,USART2_CTS,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,TSC_SYNC,I2C1_SCL,,SPI3_NSS/I2S3_WS,USART2_RX,,TIM1_BKIN,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" "SWDAT-JTCK,,,TSC_G4_IO4,I2C1_SDA,,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" "SWDAT-JMTS,TIM16_CH1,,TSC_G4_IO3,,IR-OUT,,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,I2SCKIN,TIM1_CH2N,USART1_RTS_DE,COMP2_OUT,,,TIM1_ETR,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,,,,SPI2_MOSI/I2S2_SD,TIM1_CH1N,USART1_CTS,,,,TIM1_CH4,TIM1_BKIN2,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,I2C2_SDA,SPI2_MISO/I2S2_extSD,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" ",,I2C3_SMBAL,TSC_G4_IO1,I2C2_SCL,I2S3_MCK,TIM1_CH2,USART1_TX,,,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "MCO,,,I2C3_SCL,I2C2_SMBAL,I2S2_MCK,TIM1_CH1,USART1_CK,,,,,,,,EVENTOUT"
|
|
elif CPUIS("STM32F302*6")||CPUIS("STM32F302*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" ",EIM2_CH1/TIM2_ETR,,TSC_G1_IO1,,,,USART2_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" "RTC_REFIN,TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS_DE,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" ",TIM2_CH2,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" ",TIM2_CH4,,TSC_G1_IO4,,,,USART2_RX,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" ",,,TSC_G2_IO1,,,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" ",TIM2_CH1/TIM2_ETR,,TSC_G2_IO2,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" ",TIM16_CH1,,TSC_G2_IO3,,,TIM1_BKIN,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" ",TIM17_CH1,,TSC_G2_IO4,,,TIM1_CH1N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "MCO,,,I2C3_SCL,I2C2_SMBAL,I2S2_MCK,TIM1_CH1,USART1_CK,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" ",,I2C3_SMBAL,TSC_G4_IO1,I2C2_SCL,I2S3_MCK,TIM1_CH2,USART1_TX,,,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" ",TIM17_BKIN,,TSC_G4_IO2,I2C2_SDA,SPI2_MISO/I2S2_extSD,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",,,,,SPI2_MOSI/I2S2_SD,TIM1_CH1N,USART1_CTS,,CAN_RX,,TIM1_CH4,TIM1_BKIN2,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",TIM16_CH1,,,,I2SCKIN,TIM1_CH2N,USART1_RTS_DE,COMP2_OUT,CAN_TX,,TIM1_ETR,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" "SWDAT-JMTS,TIM16_CH1,,TSC_G4_IO3,,IR-OUT,,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" "SWDAT-JTCK,,,TSC_G4_IO4,I2C1_SDA,,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "JTDI,TIM2_CH1/TIM2_ETR,,TSC_SYNC,I2C1_SCL,,SPI3_NSS/I2S3_WS,USART2_RX,,TIM1_BKIN,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,TIM3_CH2,TSC_G2_IO4,,SPI1_MOSI,TIM1_CH1N,,COMP2_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,TIM3_CH1,TSC_G2_IO3,,SPI1_MISO,TIM1_BKIN,,COMP1_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" ",TIM2_CH1_ETR,,TSC_G2_IO2,,SPI1_SCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" ",,TIM3_CH2,TSC_G2_IO1,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,,TSC_G1_IO4,,,,USART2_RX,,TIM15_CH2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" ",TIM2_CH3,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" "RTC_REFIN,TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS,,TIM15_CH1N,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" ",TIM2_CH1_ETR,,TSC_G1_IO1,,,,USART2_CTS,COMP1_OUT,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1_ETR,,,I2C1_SCL,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_RX,,TIM1_BKIN,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" "SWDAT-JTCK,,,TSC_G4_IO4,I2C1_SDA,,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" "SWDIO-JMTS,TIM16_CH1,,TSC_G4_IO3,,IR-OUT,,USART3_CTS,,,TIM4_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,,TIM1_CH2N,USART1_RTS,COMP2_OUT,CAN_TX,TIM4_CH2,TIM1_ETR,,,USB_DP,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,,,,,TIM1_CH1N,USART1_CTS,COMP1_OUT,CAN_RX,TIM4_CH1,TIM1_CH4,TIM1_BKIN2,,USB_DM,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,I2C2_SDA,,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" ",,,TSC_G4_IO1,I2C2_SCL,I2S3_MCK,TIM1_CH2,USART1_TX,,TIM15_BKIN,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "MCO,,,,I2C2_SMBA,I2S2_MCK,TIM1_CH1,USART1_CK,,,TIM4_ETR,,,,,EVENTOUT"
|
|
elif cpuis("STM32F303*6")||cpuis("STM32F303*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,TIM3_CH2,TSC_G2_IO4,,SPI_MOSI,TIM1_CH1N,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,TIM3_CH1,TSC_G2_IO3,,SPI1_MISO,TIM1_BKIN,,,,,,,OPAMP2_DIG,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TSC_G2_IO2,,SPI_SCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" ",,TIM3_CH2,TSC_G2_IO1,,SPI1_NSS,,USART2_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,,TSC_G1_IO4,,,,USART2_RX,,TIM15_CH2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" ",TIM2_CH2,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" ",TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS,,TIM15_CH1N,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" ",EIM2_CH1/TIM2_ETR,,TSC_G1_IO1,,,,USART2_CTS,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,TSC_SYNC,I2C1_SCL,SPI1_NSS,,USART2_RX,,TIM1_BKIN,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" "SWDAT-JTCK,,,TSC_G4_IO4,I2C1_SDA,,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" "SWDAT-JMTS,TIM16_CH1,,TSC_G4_IO3,,IR-OUT,,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,,TIM1_CH2N,USART1_RTS,COMP2_OUT,CAN_TX,,TIM1_ETR,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,,,,,TIM1_CH1N,USART1_CTS,,CAN_RX,,TIM1_CH4,TIM1_BKIN2,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,,,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" ",,,TSC_G4_IO1,,,TIM1_CH2,USART1_TX,,TIM15_BKIN,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "MCO,,,,,,TIM1_CH1,USART1_CK,,,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F303*B")||cpuis("STM32F303*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,TIM3_CH2,TSC_G2_IO4,TIM8_CH1N,SPI1_MOSI,TIM1_CH1N,,COMP2_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,TIM3_CH1,TSC_G2_IO3,TIM8_BKIN,SPI1_MISO,TIM1_BKIN,,COMP1_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" ",TIM2_CH1_ETR,,TSC_G2_IO2,,SPI1_SCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" ",,TIM3_CH2,TSC_G2_IO1,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,,TSC_G1_IO4,,,,USART2_RX,,TIM15_CH2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" ",TIM2_CH3,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" "RTC_REFIN,TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS,,TIM15_CH1N,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" ",TIM2_CH1_ETR,,TSC_G1_IO1,,,,USART2_CTS,COMP1_OUT,TIM8_BKIN,TIM8_ETR,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1_ETR,TIM8_CH1,,I2C1_SCL,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_RX,,TIM1_BKIN,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" "SWDAT-JTCK,,,TSC_G4_IO4,I2C1_SDA,TIM8_CH2,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" "SWDIO-JMTS,TIM16_CH1,,TSC_G4_IO3,,IR-OUT,,USART3_CTS,,,TIM4_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,,TIM1_CH2N,USART1_RTS,COMP2_OUT,CAN_TX,TIM4_CH2,TIM1_ETR,,,USB_DP,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,,,,,TIM1_CH1N,USART1_CTS,COMP1_OUT,CAN_RX,TIM4_CH1,TIM1_CH4,TIM1_BKIN2,,USB_DM,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,I2C2_SDA,,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,TIM8_BKIN,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" ",,,TSC_G4_IO1,I2C2_SCL,I2S3_MCK,TIM1_CH2,USART1_TX,COMP5_OUT,TIM15_BKIN,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "MCO,,,,I2C2_SMBA,I2S2_MCK,TIM1_CH1,USART1_CK,COMP3_OUT,,TIM4_ETR,,,,,EVENTOUT"
|
|
elif cpuis("STM32F328*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,TIM3_CH2,TSC_G2_IO4,,SPI_MOSI,TIM1_CH1N,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,TIM3_CH1,TSC_G2_IO3,,SPI1_MISO,TIM1_BKIN,,,,,,,OPAMP2_DIG,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TSC_G2_IO2,,SPI_SCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" ",,TIM3_CH2,TSC_G2_IO1,,SPI1_NSS,,USART2_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,,TSC_G1_IO4,,,,USART2_RX,,TIM15_CH2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" ",TIM2_CH2,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" ",TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS,,TIM15_CH1N,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" ",EIM2_CH1/TIM2_ETR,,TSC_G1_IO1,,,,USART2_CTS,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,TSC_SYNC,I2C1_SCL,SPI1_NSS,,USART2_RX,,TIM1_BKIN,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" "SWDAT-JTCK,,,TSC_G4_IO4,I2C1_SDA,,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" "SWDAT-JMTS,TIM16_CH1,,TSC_G4_IO3,,IR-OUT,,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,,TIM1_CH2N,USART1_RTS,COMP2_OUT,CAN_TX,,TIM1_ETR,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,,,,,TIM1_CH1N,USART1_CTS,,CAN_RX,,TIM1_CH4,TIM1_BKIN2,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,,,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" ",,,TSC_G4_IO1,,,TIM1_CH2,USART1_TX,,TIM15_BKIN,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "MCO,,,,,,TIM1_CH1,USART1_CK,,,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F378*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,TIM3_CH2,TSC_G2_IO4,,SPI1_MOSI/I2S1_SD,,,COMP2_OUT,TIM14_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,TIM3_CH1,TSC_G2_IO3,,SPI1_MISO/I2S1_MCK,,,COMP1_OUT,TIM13_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" ",TIM2_CH1_ETR,,TSC_G2_IO2,,SPI1_SCK/I2S1_CK,,CEC,,TIM14_CH1,TIM12_CH2,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" ",,TIM3_CH2,TSC_G2_IO1,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,TIM12_CH1,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TSC_G1_IO4,,,SPI3_MOSI/I2S3_SD,USART2_RX,,TIM15_CH2,,TIM19_CH4,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TSC_G1_IO3,,,SPI3_SCK/S2S3_CK,USART2_TX,COMP2_OUT,TIM15_CH1,,TIM19_CH2,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" "RTC_REFIN,TIM2_CH2,TIM5_CH2,TSC_G1_IO2,,,SPI3_SCK/I2S3,USART2_RTS,,TIM15_CH1N,,TIM19_CH2,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" ",TIM2_CH1_ETR,TIM5_CH1_ETR,TSC_G1_IO1,,,,USART2_CTS,COMP1_OUT,,,TIM19_CH1,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1_ETR,,TSC_SYNC,I2C1_SCL,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,,,TIM12_CH2,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" "SWDAT-JTCK,,,TSC_G4_IO4,I2C1_SDA,,,,,,TIM12_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" "SWDIO-JMTS,TIM16_CH1,TIM5_CH4,TSC_G4_IO3,,IR-OUT,SPI_MISO/I2S1_MCK,USART3_CTS,,,TIM4_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,TIM5_CH3,,,,SPI1_SCK/I2S1_CK,USART1_RTS,COMP2_OUT,CAN_TX,TIM4_CH2,TIM1_ETR,,,USB_DP,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,TIM5_CH2,,,SPI2_NSS/I2S2_WS,SPI1_NSS/I2S1_WS,USART1_CTS,COMP1_OUT,CAN_RX,TIM4_CH1,TIM1_CH4,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,I2C2_SDA,SPI2_MOSI/I2S2_SD,,USART1_RX,,TIM14_CH1,TIM2_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" ",,TIM13_CH1,TSC_G4_IO1,I2C2_SDA,SPI2_MISO/I2S2_MCK,,USART1_TX,,TIM15_BKIN,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "MCO,,TIM5_CH1_ETR,,I2C2_SMBA,SPI2_SCK/I2S2_CK,,USART1_CK,,,TIM4_ETR,,,,,EVENTOUT"
|
|
elif cpuis("STM32F334*6")||cpuis("STM32F334*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,TIM3_CH2,TSC_G2_IO4,,SPI_MOSI,TIM1_CH1N,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,TIM3_CH1,TSC_G2_IO3,,SPI1_MISO,TIM1_BKIN,,,,,,,OPAMP2_DIG,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TSC_G2_IO2,,SPI_SCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" ",,TIM3_CH2,TSC_G2_IO1,,SPI1_NSS,,USART2_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,,TSC_G1_IO4,,,,USART2_RX,,TIM15_CH2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" ",TIM2_CH2,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" ",TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS,,TIM15_CH1N,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" ",EIM2_CH1/TIM2_ETR,,TSC_G1_IO1,,,,USART2_CTS,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,TSC_SYNC,I2C1_SCL,SPI1_NSS,,USART2_RX,,TIM1_BKIN,,,,HRTIM1_FLT2,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" "SWDAT-JTCK,,,TSC_G4_IO4,I2C1_SDA,,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" "SWDAT-JMTS,TIM16_CH1,,TSC_G4_IO3,,IR-OUT,,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,,TIM1_CH2N,USART1_RTS,COMP2_OUT,CAN_TX,,TIM1_ETR,,HRTIM1_FLT1,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,,,,,TIM1_CH1N,USART1_CTS,,CAN_RX,,TIM1_CH4,TIM1_BKIN2,HRTIM1_CHB2,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,,,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,,,HRTIM1_CHB1,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" ",,,TSC_G4_IO1,,,TIM1_CH2,USART1_TX,,TIM15_BKIN,TIM2_CH3,,,HRTIM1_CHA2,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "MCO,,,,,,TIM1_CH1,USART1_CK,,,,,,HRTIM1_CHA1,,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
endif
|
|
width 0xB
|
|
width 15.
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
width 0xB
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOB_ODR,GPIO Port B output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port B output data" "Low,High"
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port B lock bit 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port B lock bit 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port B lock bit 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port B lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port B lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port B lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port B lock bit 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit 3 " "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port B lock bit 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit 0" "Not locked,Locked"
|
|
textline ""
|
|
width 15.
|
|
sif CPUIS("STM32F358*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,TIM4_CH2,TSC_G5_IO4,I2C1_SDA,TIM8_BKIN,,USART1_RX,,,TIM3_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,TIM4_CH1,TSC_G5_IO3,I2C1_SCL,TIM8_CH1,TIM8_ETR,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,TIM3_CH2,TIM8_CH3N,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,USART2_CK,,,TIM17_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" "NJTRST,TIM16_CH1,TIM3_CH1,TSC_G5_IO2,TIM8_CH2N,SPI_MISO,SPI3_MISO/I2S3ext_SD,USART2_RX,,,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,TIM4_ETR,TSC_G5_IO1,TIM8_CH1N,SPI_SCK,SPI3_SCK/I2S3_CK,USART2_TX,,,TIM3_ETR,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" ",,TIM3_CH4,TSC_G3_IO3,TIM8_CH3N,,TIM1_CH3N,,COMP4_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" ",,TIM3_CH3,TSC_G3_IO2,TIM8_CH2N,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO4,,SPI2_MISO/I2S2ext_SD,TIM1_CH2N,USART3_RTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B pin 13" ",,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,TIM1_CH1N,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B pin 12" ",,,TSC_G6_IO2,I2C2_SMBAL,SPI2_NSS/I2S2_WS,TIM1_BKIN,USART3_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B pin 11" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,TIM4_CH4,,I2C1_SDA,,IR-OUT,,COMP2_OUT,CAN_TX,TIM8_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,TIM4_CH3,TSC_SYNC,I2C1_SCL,,,,COMP1_OUT,CAN_RX,TIM8_CH2,,TIM1_BKIN,,,EVENTOUT"
|
|
elif CPUIS("STM32F301*6")||CPUIS("STM32F301*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,,TSC_G5_IO4,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,,TSC_G5_IO3,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,,,I2C1_SMBAI,,SPI3_MOSI/I2S3ext_SD,USART2_CK,I2C3_SDA,,TIM17_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" ",TIM16_CH1,,TSC_G5_IO2,,,SPI3_MISO/I2S3_SD,USART2_RX,,,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,,TSC_G5_IO1,,,SPI3_SCK/I2S3_CK,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B pin 2" ",,,TSC_G3_IO4,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" ",,,TSC_G3_IO3,,,TIM1_CH3N,,COMP4_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" ",,,TSC_G3_IO2,,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO4,,SPI2_MISO/I2S2ext_SD,TIM1_CH2N,USART3_RTS_DE,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B pin 13" ",,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,TIM1_CH1N,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B pin 12" ",,,TSC_G6_IO2,I2C2_SMBAL,SPI2_NSS/I2S2_WS,TIM1_BKIN,USART3_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B pin 11" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,,,I2C1_SDA,,IR-OUT,USART3_TX,COMP2_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,,TSC_SYNC,I2C1_SCL,,,USART3_RX,,,,,TIM1_BKIN,,,EVENTOUT"
|
|
elif cpuis("STM32F318*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,,TSC_G5_IO4,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,,TSC_G5_IO3,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,,,I2C1_SMBAI,,SPI3_MOSI/I2S3ext_SD,USART2_CK,I2C3_SDA,,TIM17_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" ",TIM16_CH1,,TSC_G5_IO2,,,SPI3_MISO/I2S3_SD,USART2_RX,,,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,,TSC_G5_IO1,,,SPI3_SCK/I2S3_CK,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" ",,,TSC_G3_IO3,,,TIM1_CH3N,,COMP4_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" ",,,TSC_G3_IO2,,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO4,,SPI2_MISO/I2S2ext_SD,TIM1_CH2N,USART3_RTS_DE,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B pin 13" ",,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,TIM1_CH1N,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B pin 12" ",,,TSC_G6_IO2,I2C2_SMBAL,SPI2_NSS/I2S2_WS,TIM1_BKIN,USART3_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B pin 11" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,,,I2C1_SDA,,IR-OUT,USART3_TX,COMP2_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,,TSC_SYNC,I2C1_SCL,,,USART3_RX,,,,,TIM1_BKIN,,,EVENTOUT"
|
|
elif CPUIS("STM32F302*6")||CPUIS("STM32F302*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" ",,,TSC_G3_IO2,,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" ",,,TSC_G3_IO3,,,TIM1_CH3N,,COMP4_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" ",,,TSC_G3_IO4,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" "JTDO-TRACESWO,TIM2_CH2,,TSC_G5_IO1,,,SPI3_SCK/I2S3_CK,USART2_TX,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" ",TIM16_CH1,,TSC_G5_IO2,,,SPI3_MISO/I2S3_SD,USART2_RX,,,TIM17_BKIN,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B pin 2" ",TIM16_BKIN,,,I2C1_SMBAI,,SPI3_MOSI/I2S3ext_SD,USART2_CK,I2C3_SDA,,TIM17_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" ",TIM16_CH1N,,TSC_G5_IO3,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" ",TIM17_CH1N,,TSC_G5_IO4,I2C1_SDA,,,USART1_RX,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" ",TIM16_CH1,,TSC_SYNC,I2C1_SCL,,,USART3_RX,,CAN_RX,,,TIM1_BKIN,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" ",TIM17_CH1,,,I2C1_SDA,,IR-OUT,USART3_TX,COMP2_OUT,CAN_TX,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B pin 13" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B pin 12" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B pin 11" ",,,TSC_G6_IO2,I2C2_SMBAL,SPI2_NSS/I2S2_WS,TIM1_BKIN,USART3_CK,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" ",,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,TIM1_CH1N,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" ",TIM15_CH1,,TSC_G6_IO4,,SPI2_MISO/I2S2ext_SD,TIM1_CH2N,USART3_RTS_DE,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" "RTC_REFIN,TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT"
|
|
elif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,TIM4_CH2,TSC_G5_IO4,I2C1_SDA,,,USART1_RX,,,TIM3_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,TIM4_CH1,TSC_G5_IO3,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,USART2_CK,,,TIM17_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" "NJTRST,TIM16_CH1,TIM3_CH1,TSC_G5_IO2,,SPI_MISO,SPI3_MISO/I2S3ext_SD,USART2_RX,,,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,TIM4_ETR,TSC_G5_IO1,,SPI_SCK,SPI3_SCK/I2S3_CK,USART2_TX,,,TIM3_ETR,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B pin 2" ",,,TSC_G3_IO4,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" ",,TIM3_CH4,TSC_G3_IO3,,,TIM1_CH3N,,COMP4_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" ",,TIM3_CH3,TSC_G3_IO2,,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO4,,SPI2_MISO/I2S2ext_SD,TIM1_CH2N,USART3_RTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B pin 13" ",,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,TIM1_CH1N,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B pin 12" ",,,TSC_G6_IO2,I2C2_SMBAL,SPI2_NSS/I2S2_WS,TIM1_BKIN,USART3_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B pin 11" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,TIM4_CH4,,I2C1_SDA,,IR-OUT,,COMP2_OUT,CAN_TX,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,TIM4_CH3,TSC_SYNC,I2C1_SCL,,,,COMP1_OUT,CAN_RX,,,TIM1_BKIN,,,EVENTOUT"
|
|
elif cpuis("STM32F303*6")||cpuis("STM32F303*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,,TSC_G5_IO4,I2C1_SDA,,,USART1_RX,,,TIM3_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,,TSC_G5_IO3,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,TIM3_CH2,,I2C1_SMBA,,SPI3_MOSI,,I2C3_SDA,,TIM17_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" "NJTRST,TIM16_CH1,TIM3_CH2,TSC_G5_IO2,,SPI1_MISO,,USART2_RX,,,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,,TSC_G5_IO1,,SPI1_SCK,,USART2_TX,,,TIM3_ETR,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B pin 2" ",,,TSC_G3_IO4,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" ",,TIM3_CH4,TSC_G3_IO3,,,TIM1_CH3N,,COMP4_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" ",,TIM3_CH3,TSC_G3_IO2,,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" ",TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO4,,,TIM1_CH2N,USART3_RTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B pin 13" ",,,TSC_G6_IO3,,,TIM1_CH1N,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B pin 12" ",,,TSC_G6_IO2,I2C2_SMBAL,,TIM1_BKIN,USART3_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B pin 11" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,,,I2C1_SDA,,IR-OUT,USART3_TX,COMP2_OUT,CAN_TX,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,,TSC_SYNC,I2C1_SCL,,,USART3_RX,,CAN_RX,,,TIM1_BKIN,,,EVENTOUT"
|
|
elif cpuis("STM32F303*B")||cpuis("STM32F303*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,TIM4_CH2,TSC_G5_IO4,I2C1_SDA,TIM8_BKIN,,USART1_RX,,,TIM3_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,TIM4_CH1,TSC_G5_IO3,I2C1_SCL,TIM8_CH1,TIM8_ETR,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,TIM3_CH2,TIM8_CH3N,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,USART2_CK,,,TIM17_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" "NJTRST,TIM16_CH1,TIM3_CH1,TSC_G5_IO2,TIM8_CH2N,SPI_MISO,SPI3_MISO/I2S3ext_SD,USART2_RX,,,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,TIM4_ETR,TSC_G5_IO1,TIM8_CH1N,SPI_SCK,SPI3_SCK/I2S3_CK,USART2_TX,,,TIM3_ETR,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B pin 2" ",,,TSC_G3_IO4,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" ",,TIM3_CH4,TSC_G3_IO3,TIM8_CH3N,,TIM1_CH3N,,COMP4_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" ",,TIM3_CH3,TSC_G3_IO2,TIM8_CH2N,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO4,,SPI2_MISO/I2S2ext_SD,TIM1_CH2N,USART3_RTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B pin 13" ",,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,TIM1_CH1N,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B pin 12" ",,,TSC_G6_IO2,I2C2_SMBAL,SPI2_NSS/I2S2_WS,TIM1_BKIN,USART3_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B pin 11" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,TIM4_CH4,,I2C1_SDA,,IR-OUT,,COMP2_OUT,CAN_TX,TIM8_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,TIM4_CH3,TSC_SYNC,I2C1_SCL,,,,COMP1_OUT,CAN_RX,TIM8_CH2,,TIM1_BKIN,,,EVENTOUT"
|
|
elif cpuis("STM32F328*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,,TSC_G5_IO4,I2C1_SDA,,,USART1_RX,,,TIM3_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,,TSC_G5_IO3,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,TIM3_CH2,,I2C1_SMBA,,SPI3_MOSI,,I2C3_SDA,,TIM17_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" "NJTRST,TIM16_CH1,TIM3_CH2,TSC_G5_IO2,,SPI1_MISO,,USART2_RX,,,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,,TSC_G5_IO1,,SPI1_SCK,,USART2_TX,,,TIM3_ETR,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B pin 2" ",,,TSC_G3_IO4,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" ",,TIM3_CH4,TSC_G3_IO3,,,TIM1_CH3N,,COMP4_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" ",,TIM3_CH3,TSC_G3_IO2,,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" ",TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO4,,,TIM1_CH2N,USART3_RTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B pin 13" ",,,TSC_G6_IO3,,,TIM1_CH1N,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B pin 12" ",,,TSC_G6_IO2,I2C2_SMBAL,,TIM1_BKIN,USART3_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B pin 11" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,,,I2C1_SDA,,IR-OUT,USART3_TX,COMP2_OUT,CAN_TX,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,,TSC_SYNC,I2C1_SCL,,,USART3_RX,,CAN_RX,,,TIM1_BKIN,,,EVENTOUT"
|
|
elif cpuis("STM32F378*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,TIM4_CH2,TSC_G5_IO4,I2C1_SDA,,,USART1_RX,,TIM15_CH2,TIM3_CH4,TIM19_CH2,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,TIM4_CH1,TSC_G5_IO3,I2C1_SCL,,,USART1_TX,,TIM15_CH1,TIM3_CH3,TIM19_CH1,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,TIM3_CH2,,I2C1_SMBA,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,USART2_CK,,,TIM17_CH1,TIM19_ETR,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" "NJTRST,TIM16_CH1,TIM3_CH1,TSC_G5_IO2,,SPI_MISO/I2S1_MCK,SPI3_MISO/I2S3_MCK,USART2_RX,,TIM15_CH1N,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,TIM4_ETR,TSC_G5_IO1,,SPI_SCK/I2S1_MCK,SPI3_SCK/I2S3_CK,USART2_TX,,TIM13_CH1,TIM3_ETR,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" ",,TIM3_CH4,TSC_G3_IO4,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" ",,TIM3_CH3,TSC_G3_IO3,,SPI_MOSI/I2S1_SD,,,,,TIM3_CH2,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM15_CH2,TIM15_CH1N,TSC_G6_IO2,,SPI2_MOSI/I2S2_SD,,,,TIM12_CH2,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO1,,SPI2_MISO/I2S2_MCK,,USART3_RTS,,TIM12_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,SPI2_SCK/I2S2_CK,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,TIM4_CH4,,I2C1_SDA,SPI2_NSS/I2S2_WS,IR-OUT,USART3_RX,COMP2_OUT,CAN_TX,,TIM19_CH4,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,TIM4_CH3,TSC_SYNC,I2C1_SCL,SPI2_SCK/I2S2_CK,CEC,USART3_TX,COMP1_OUT,CAN_RX,,TIM19_CH3,,,,EVENTOUT"
|
|
elif cpuis("STM32F334*6")||cpuis("STM32F334*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,,TSC_G5_IO4,I2C1_SDA,,,USART1_RX,,,TIM3_CH4,,,HRTIM1_EEV3,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,,TSC_G5_IO3,I2C1_SCL,,,USART1_TX,,,,,HRTIM1_SCIN,HRTIM1_EEV4,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,TIM3_CH2,,I2C1_SMBA,,SPI3_MOSI,,I2C3_SDA,,TIM17_CH1,,,HRTIM1_EEV6,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" "NJTRST,TIM16_CH1,TIM3_CH2,TSC_G5_IO2,,SPI1_MISO,,USART2_RX,,,TIM17_BKIN,,,HRTIM1_EEV7,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,,TSC_G5_IO1,,SPI1_SCK,,USART2_TX,,,TIM3_ETR,,HRTIM1_SCOUT,HRTIM1_EEV9,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B pin 2" ",,,TSC_G3_IO4,,,,,,,,,,HRTIM1_SCIN,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" ",,TIM3_CH4,TSC_G3_IO3,,,TIM1_CH3N,,COMP4_OUT,,,,,HRTIM1_SCOUT,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" ",,TIM3_CH3,TSC_G3_IO2,,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" ",TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,,,,,,,,,HRTIM1_CHD2,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO4,,,TIM1_CH2N,USART3_RTS,,,,,,HRTIM1_CHD1,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B pin 13" ",,,TSC_G6_IO3,,,TIM1_CH1N,USART3_CTS,,,,,,HRTIM1_CHC2,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B pin 12" ",,,TSC_G6_IO2,I2C2_SMBAL,,TIM1_BKIN,USART3_CK,,,,,,HRTIM1_CHC1,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B pin 11" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,HRTIM1_FLT4,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,HRTIM1_FLT3,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,,,I2C1_SDA,,IR-OUT,USART3_TX,COMP2_OUT,CAN_TX,,,,HRTIM1_EEV5,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,,TSC_SYNC,I2C1_SCL,,,USART3_RX,,CAN_RX,,,TIM1_BKIN,HRTIM1_EEV8,,EVENTOUT"
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B pin 2" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B pin 13" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B pin 12" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B pin 11" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
endif
|
|
width 0xB
|
|
width 15.
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port B reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port B reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port B reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port B reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port B reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port B reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port B reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port B reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port B reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
width 0xB
|
|
tree.end
|
|
sif !cpuis("STM32F318*8")
|
|
tree "GPIO C"
|
|
base ad:0x48000800
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOC_MODER,GPIO port C mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO port C output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port C output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOC_IDR,GPIO port C input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port C input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOC_ODR,GPIO Port C output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port C output data" "Low,High"
|
|
sif !CPUIS("STM32F302*B")&&!CPUIS("STM32F302*C")&&!CPUIS("STM32F303*B")&&!CPUIS("STM32F303*C")&&!CPUIS("STM32F358*C")
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "GPIOC_LCKR,GPIO port C configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port C lock bit 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port C lock bit 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port C lock bit 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port C lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port C lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port C lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port C lock bit 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port C lock bit 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port C lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Port C lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port C lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port C lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port C lock bit 3 " "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port C lock bit 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port C lock bit 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port C lock bit 0" "Not locked,Locked"
|
|
endif
|
|
textline ""
|
|
width 15.
|
|
sif CPUIS("STM32F358*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C pin 7" ",EVENTOUT,TIM3_CH2,,TIM8_CH2,,I2S3_MCK,TCOMP5_OUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C pin 6" ",EVENTOUT,TIM3_CH1,,TIM8_CH1,,I2S2_MCK,COMP6_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C pin 5" ",EVENTOUT,,TSC_G3_IO1,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C pin 4" ",EVENTOUT,,,,,,USART1_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C pin 3" ",EVENTOUT,,,,,TIM1_BKIN2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C pin 2" ",EVENTOUT,,COMP7_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C pin 1" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C pin 0" ",EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C pin 13" ",,,,TIM1_CH1N,,,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C pin 12" ",EVENTOUT,,,TIM8_CH3N,UART5_TX,SPI3_MOSI/I2S3_SD,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C pin 11" ",EVENTOUT,,,TIM8_CH2N,UART5_RX,SPI3_MISO/I2S3ext_SD,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C pin 10" ",EVENTOUT,,,TIM8_CH1N,UART4_TX,SPI3_SCK/I2S3_CK,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C pin 9" ",EVENTOUT,TIM3_CH4,,TIM8_CH4,I2SCKIN,TIM8_BKIN2,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C pin 8" ",EVENTOUT,TIM3_CH3,,TIM8_CH3,,,COMP3_OUT,?..."
|
|
elif CPUIS("STM32F301*6")||CPUIS("STM32F301*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C pin 7" ",EVENTOUT,,,,,I2S3_MCK,,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C pin 6" ",EVENTOUT,,,,,I2S2_MCK,COMP6_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C pin 5" ",EVENTOUT,TIM15_BKIN,TSC_G3_IO1,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C pin 4" ",EVENTOUT,TIM1_ETR,,,,,USART1_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C pin 3" ",EVENTOUT,TIM1_CH4,TIM1_BKIN2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C pin 2" ",EVENTOUT,TIM1_CH3,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C pin 1" ",EVENTOUT,TIM1_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C pin 0" ",EVENTOUT,TIM1_CH1,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C pin 13" ",,,,TIM1_CH1N,,,,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C pin 12" ",EVENTOUT,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C pin 11" ",EVENTOUT,,,,,SPI3_MISO/I2S3ext_SD,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C pin 10" ",EVENTOUT,,,,,SPI3_SCK/I2S3_CK,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C pin 9" ",EVENTOUT,,I2C3_SDA,,I2SCKIN,,,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C pin 8" ",EVENTOUT,?..."
|
|
elif cpuis("STM32F318*8")
|
|
elif CPUIS("STM32F302*6")||CPUIS("STM32F302*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C pin 7" ",EVENTOUT,TIM1_CH1,,,,,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C pin 6" ",EVENTOUT,TIM1_CH2,,,,,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C pin 5" ",EVENTOUT,TIM1_CH3,,,,,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C pin 4" ",EVENTOUT,TIM1_CH4,,,,TIM1_BKIN2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C pin 3" ",EVENTOUT,TIM1_ETR,,,,,USART1_TX,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C pin 2" ",EVENTOUT,TIM15_BKIN,TSC_G3_IO1,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C pin 1" ",EVENTOUT,,,,,I2S2_MCK,COMP6_OUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C pin 0" ",EVENTOUT,,,,,I2S3_MCK,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C pin 8" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C pin 9" ",EVENTOUT,,I2C3_SDA,,I2SCKIN,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C pin 10" ",EVENTOUT,,,,,SPI3_SCK/I2S3_CK,USART3_TX,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C pin 11" ",EVENTOUT,,,,,SPI3_MISO/I2S3ext_SD,USART3_RX,?..."
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C pin 12" ",EVENTOUT,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C pin 13" ",,,,TIM1_CH1N,?..."
|
|
elif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C pin 7" ",EVENTOUT,TIM3_CH2,,,,I2S3_MCK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C pin 6" ",EVENTOUT,TIM3_CH1,,,,I2S2_MCK,COMP6_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C pin 5" ",EVENTOUT,,TSC_G3_IO1,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C pin 4" ",EVENTOUT,,,,,,USART1_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C pin 3" ",EVENTOUT,,,,,TIM1_BKIN2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C pin 2" ",EVENTOUT,,COMP7_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C pin 1" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C pin 0" ",EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C pin 13" ",,,,TIM1_CH1N,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C pin 12" ",EVENTOUT,,,,UART5_TX,SPI3_MOSI/I2S3_SD,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C pin 11" ",EVENTOUT,,,,UART5_RX,SPI3_MISO/I2S3ext_SD,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C pin 10" ",EVENTOUT,,,,UART4_TX,SPI3_SCK/I2S3_CK,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C pin 9" ",EVENTOUT,TIM3_CH4,,,I2SCKIN,,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C pin 8" ",EVENTOUT,TIM3_CH3,,,,,?..."
|
|
elif cpuis("STM32F303*6")||cpuis("STM32F303*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C pin 7" ",EVENTOUT,TIM3_CH2,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C pin 6" ",EVENTOUT,TIM3_CH1,,,,,COMP6_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C pin 5" ",EVENTOUT,TIM15_BKIN,TSC_G3_IO1,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C pin 4" ",EVENTOUT,TIM1_ETR,,,,,USART1_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C pin 3" ",EVENTOUT,TIM1_CH4,,,,TIM1_BKIN2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C pin 2" ",EVENTOUT,TIM1_CH3,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C pin 1" ",EVENTOUT,TIM1_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C pin 0" ",EVENTOUT,TIM1_CH1,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C pin 13" ",,,,TIM1_CH1N,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C pin 12" ",EVENTOUT,,,,,,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C pin 11" ",EVENTOUT,,,,,,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C pin 10" ",EVENTOUT,,,,,,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C pin 9" ",EVENTOUT,TIM3_CH4,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C pin 8" ",EVENTOUT,TIM3_CH3,?..."
|
|
elif cpuis("STM32F303*B")||cpuis("STM32F303*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C pin 7" ",EVENTOUT,TIM3_CH2,,TIM8_CH2,,I2S3_MCK,TCOMP5_OUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C pin 6" ",EVENTOUT,TIM3_CH1,,TIM8_CH1,,I2S2_MCK,COMP6_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C pin 5" ",EVENTOUT,,TSC_G3_IO1,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C pin 4" ",EVENTOUT,,,,,,USART1_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C pin 3" ",EVENTOUT,,,,,TIM1_BKIN2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C pin 2" ",EVENTOUT,,COMP7_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C pin 1" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C pin 0" ",EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C pin 13" ",,,,TIM1_CH1N,,,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C pin 12" ",EVENTOUT,,,TIM8_CH3N,UART5_TX,SPI3_MOSI/I2S3_SD,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C pin 11" ",EVENTOUT,,,TIM8_CH2N,UART5_RX,SPI3_MISO/I2S3ext_SD,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C pin 10" ",EVENTOUT,,,TIM8_CH1N,UART4_TX,SPI3_SCK/I2S3_CK,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C pin 9" ",EVENTOUT,TIM3_CH4,,TIM8_CH4,I2SCKIN,TIM8_BKIN2,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C pin 8" ",EVENTOUT,TIM3_CH3,,TIM8_CH3,,,COMP3_OUT,?..."
|
|
elif cpuis("STM32F328*8")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port C pin 13" ",,,,TIM1_CH1N,?..."
|
|
elif cpuis("STM32F378*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C pin 7" ",EVENTOUT,TIM3_CH2,,,SPI1_SCK/I2S1_MCK,,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C pin 6" ",EVENTOUT,TIM3_CH1,,,SPI1_NSS/I2S1_WS,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C pin 5" ",EVENTOUT,,TSC_G3_IO2,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C pin 4" ",EVENTOUT,TIM13_CH1,TSC_G3_IO1,,,,USART1_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C pin 3" ",EVENTOUT,TIM5_CH4,,,SPI2_MISO/I2S2_SD,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C pin 2" ",EVENTOUT,TIM5_CH3,,,SPI2_MISO/I2S2_MCK,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C pin 1" ",EVENTOUT,TIM5_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C pin 0" ",EVENTOUT,TIM5_CH1_ETR,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C pin 13" ",,,,TIM1_CH1N,,,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C pin 12" ",EVENTOUT,,,,,SPI3_MOSI/I2S3_SD,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C pin 11" ",EVENTOUT,,,,,SPI3_MISO/I2S3ext_SD,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C pin 10" ",EVENTOUT,,,,,SPI3_SCK/I2S3_CK,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C pin 9" ",EVENTOUT,TIM3_CH4,,,SPI1_MOSI/I2S1_SD,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C pin 8" ",EVENTOUT,TIM3_CH3,,,SPI1_MISO/I2S1_MCK,?..."
|
|
elif cpuis("STM32F334*6")||cpuis("STM32F334*8")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C pin 7" ",EVENTOUT,TIM3_CH2,HRTIM1_FLT5,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C pin 6" ",EVENTOUT,TIM3_CH1,HRTIM1_EEV10,,,,COMP6_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C pin 5" ",EVENTOUT,TIM15_BKIN,TSC_G3_IO1,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C pin 4" ",EVENTOUT,TIM1_ETR,,,,,USART1_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C pin 3" ",EVENTOUT,TIM1_CH4,,,,TIM1_BKIN2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C pin 2" ",EVENTOUT,TIM1_CH3,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C pin 0" ",EVENTOUT,TIM1_CH1,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C pin 13" ",,,,TIM1_CH1N,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C pin 12" ",EVENTOUT,,HRTIM1_EEV1,,,,USART3_CK,?..."
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C pin 11" ",EVENTOUT,,HRTIM1_EEV1,,,,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C pin 10" ",EVENTOUT,,,,,,USART3_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C pin 9" ",EVENTOUT,TIM3_CH4,HRTIM1_CHE2,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C pin 8" ",EVENTOUT,TIM3_CH3,HRTIM1_CHE1,?..."
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C pin 7" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C pin 6" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C pin 5" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C pin 4" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C pin 3" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C pin 2" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C pin 1" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C pin 0" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port C pin 15" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port C pin 14" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C pin 13" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C pin 12" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C pin 11" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C pin 10" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C pin 9" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C pin 8" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
endif
|
|
width 0xB
|
|
width 15.
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port C reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port C reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port C reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port C reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port C reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port C reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port C reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port C reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port C reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port C reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port C reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port C reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port C reset bit 0" "No effect,Reset"
|
|
width 0xB
|
|
tree.end
|
|
tree "GPIO D"
|
|
base ad:0x48000C00
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port D output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOD_ODR,GPIO Port D output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port D output data" "Low,High"
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "GPIOD_LCKR,GPIO port D configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port D lock bit 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port D lock bit 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port D lock bit 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port D lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port D lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port D lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port D lock bit 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port D lock bit 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port D lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Port D lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port D lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port D lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port D lock bit 3 " "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port D lock bit 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port D lock bit 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port D lock bit 0" "Not locked,Locked"
|
|
textline ""
|
|
width 15.
|
|
sif CPUIS("STM32F358*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D pin 7" ",EVENTOUT,TIM2_CH3,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D pin 6" ",EVENTOUT,TIM2_CH4,,,,,USART2_RX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D pin 5" ",EVENTOUT,,,,,,USATR2_TX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D pin 4" ",EVENTOUT,TIM2_CH2,,,,,USART_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D pin 3" ",EVENTOUT,TIM2_CH1_ETR,,,UART5_RX,,USART2_CTS,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,,TIM8_BKIN,USART5_RX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D pin 1" ",EVENTOUT,,,TIM8_CH4,,TIM8_BKIN2,CAN_TX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D pin 0" ",EVENTOUT,,,,,,CAN_RX,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D pin 15" ",EVENTOUT,TIM4_CH4,TSC_G8_IO4,,,SPI2_NSS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D pin 14" ",EVENTOUT,TIM4_CH3,TSC_G8_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D pin 13" ",EVENTOUT,TIM4_CH2,TSC_G8_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D pin 12" ",EVENTOUT,TIM4_CH1,TSC_G8_IO1,,,,USART3_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D pin 11" ",EVENTOUT,,,,,,USART3_CTS,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D pin 10" ",EVENTOUT,,,,,,USART3_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D pin 9" ",EVENTOUT,,,,,,USART3_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D pin 8" ",EVENTOUT,,,,,,USART3_TX,?..."
|
|
elif CPUIS("STM32F301*6")||CPUIS("STM32F301*8")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,?..."
|
|
elif cpuis("STM32F318*8")
|
|
elif CPUIS("STM32F302*6")||CPUIS("STM32F302*8")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,?..."
|
|
elif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D pin 7" ",EVENTOUT,TIM2_CH3,,,,,USART2_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D pin 6" ",EVENTOUT,TIM2_CH4,,,,,USART2_RX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D pin 5" ",EVENTOUT,,,,,,USATR2_TX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D pin 4" ",EVENTOUT,TIM2_CH2,,,,,USART_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D pin 3" ",EVENTOUT,TIM2_CH1_ETR,,,UART5_RX,,USART2_CTS,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,,,USART5_RX,,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D pin 1" ",EVENTOUT,,,,,,CAN_TX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D pin 0" ",EVENTOUT,,,,,,CAN_RX,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D pin 15" ",EVENTOUT,TIM4_CH4,TSC_G8_IO4,,,SPI2_NSS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D pin 14" ",EVENTOUT,TIM4_CH3,TSC_G8_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D pin 13" ",EVENTOUT,TIM4_CH2,TSC_G8_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D pin 12" ",EVENTOUT,TIM4_CH1,TSC_G8_IO1,,,,USART3_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D pin 11" ",EVENTOUT,,,,,,USART3_CTS,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D pin 10" ",EVENTOUT,,,,,,USART3_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D pin 9" ",EVENTOUT,,,,,,USART3_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D pin 8" ",EVENTOUT,,,,,,USART3_TX,?..."
|
|
elif cpuis("STM32F303*6")||cpuis("STM32F303*8")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,?..."
|
|
elif cpuis("STM32F303*B")||cpuis("STM32F303*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D pin 7" ",EVENTOUT,TIM2_CH3,,,,,USART2_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D pin 6" ",EVENTOUT,TIM2_CH4,,,,,USART2_RX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D pin 5" ",EVENTOUT,,,,,,USATR2_TX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D pin 4" ",EVENTOUT,TIM2_CH2,,,,,USART_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D pin 3" ",EVENTOUT,TIM2_CH1_ETR,,,UART5_RX,,USART2_CTS,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,,TIM8_BKIN,USART5_RX,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D pin 1" ",EVENTOUT,,,TIM8_CH4,,TIM8_BKIN2,CAN_TX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D pin 0" ",EVENTOUT,,,,,,CAN_RX,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D pin 15" ",EVENTOUT,TIM4_CH4,TSC_G8_IO4,,,SPI2_NSS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D pin 14" ",EVENTOUT,TIM4_CH3,TSC_G8_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D pin 13" ",EVENTOUT,TIM4_CH2,TSC_G8_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D pin 12" ",EVENTOUT,TIM4_CH1,TSC_G8_IO1,,,,USART3_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D pin 11" ",EVENTOUT,,,,,,USART3_CTS,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D pin 10" ",EVENTOUT,,,,,,USART3_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D pin 9" ",EVENTOUT,,,,,,USART3_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D pin 8" ",EVENTOUT,,,,,,USART3_TX,?..."
|
|
elif cpuis("STM32F328*8")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,?..."
|
|
elif cpuis("STM32F378*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D pin 7" ",EVENTOUT,,,,SPI2_SCK/I2S2_CK,,USART2_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D pin 6" ",EVENTOUT,,,,SPI_NSS/I2S2_WS,,USART2_RX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D pin 5" ",EVENTOUT,,,,,,USATR2_TX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D pin 4" ",EVENTOUT,,,,SPI_MOSI/I2S2_CD,,USART2_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D pin 3" ",EVENTOUT,,,,SPI_MISO/I2S2_MCK,,USART2_CTS,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D pin 1" ",EVENTOUT,TIM19_ETR,,,,,CAN_TX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D pin 0" ",EVENTOUT,TIM19_CH4,,,,,CAN_RX,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D pin 15" ",EVENTOUT,TIM4_CH4,TSC_G8_IO4,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D pin 14" ",EVENTOUT,TIM4_CH3,TSC_G8_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D pin 13" ",EVENTOUT,TIM4_CH2,TSC_G8_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D pin 12" ",EVENTOUT,TIM4_CH1,TSC_G8_IO1,,,,USART3_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D pin 11" ",EVENTOUT,,,,,,USART3_CTS,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D pin 10" ",EVENTOUT,,,,,,USART3_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D pin 9" ",EVENTOUT,,TSC_G6_IO4,,,,USART3_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D pin 8" ",EVENTOUT,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,,USART3_TX,?..."
|
|
elif cpuis("STM32F334*6")||cpuis("STM32F334*8")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,?..."
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D pin 7" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D pin 6" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D pin 5" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D pin 4" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D pin 3" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D pin 1" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D pin 0" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D pin 15" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D pin 14" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D pin 13" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D pin 12" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D pin 11" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D pin 10" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D pin 9" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D pin 8" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
endif
|
|
width 0xB
|
|
width 15.
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port D reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port D reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port D reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port D reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port D reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port D reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port D reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port D reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port D reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port D reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port D reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port D reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port D reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port D reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port D reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port D reset bit 0" "No effect,Reset"
|
|
width 0xB
|
|
tree.end
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&!cpuis("STM32F318*8")&&!cpuis("STM32F302*6")&&!cpuis("STM32F302*8")&&!cpuis("STM32F303*6")&&!cpuis("STM32F303*8")&&!cpuis("STM32F328*8")&&!cpuis("STM32F334?4")&&!cpuis("STM32F334?6")&&!cpuis("STM32F334?8")
|
|
tree "GPIO E"
|
|
base ad:0x48001000
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOE_MODER,GPIO port E mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOE_OTYPER,GPIO port E mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOE_OSPEEDR,GPIO port E output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port E output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOE_PUPDR,GPIO port E pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOE_IDR,GPIO port E input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port E input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOE_ODR,GPIO Port E output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port E output data" "Low,High"
|
|
sif !CPUIS("STM32F302*B")&&!CPUIS("STM32F302*C")&&!CPUIS("STM32F302*6")&&!CPUIS("STM32F302*8")&&!CPUIS("STM32F303*B")&&!CPUIS("STM32F303*C")&&!CPUIS("STM32F303*6")&&!CPUIS("STM32F303*8")&&!CPUIS("STM32F328*8")&&!CPUIS("STM32F358*C")
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "GPIOE_LCKR,GPIO port E configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port E lock bit 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port E lock bit 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port E lock bit 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port E lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port E lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port E lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port E lock bit 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port E lock bit 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port E lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Port E lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port E lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port E lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port E lock bit 3 " "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port E lock bit 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port E lock bit 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port E lock bit 0" "Not locked,Locked"
|
|
endif
|
|
textline ""
|
|
width 15.
|
|
sif CPUIS("STM32F358*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E pin 7" ",EVENTOUT,TIM1_ETR,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E pin 6" "TRACED3,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E pin 5" "TRACED2,EVENTOUT,TIM3_CH4,TSC_G7_IO4,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E pin 4" "TRACED1,EVENTOUT,TIM3_CH3,TSC_G7_IO3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E pin 3" "TRACED0,EVENTOUT,TIM3_CH2,TSC_G7_IO2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E pin 2" "TRACECK,EVENTOUT,TIM3_CH1,TSC_G7_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E pin 1" ",EVENTOUT,,,TIM17_CH1,,USART1_RX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E pin 0" ",EVENTOUT,TIM4_ETR,,TIM16_CH1,,USART1_TX,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E pin 15" ",EVENTOUT,TIM1_BKIN,,,USART3_RX,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E pin 14" ",EVENTOUT,TIM1_CH4,,TIM1_BKIN2,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E pin 13" ",EVENTOUT,TIM1_CH3,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E pin 12" ",EVENTOUT,TIM1_CH3N,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E pin 11" ",EVENTOUT,TIM1_CH2,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E pin 10" ",EVENTOUT,TIM1_CH2N,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E pin 9" ",EVENTOUT,TIM1_CH1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E pin 8" ",EVENTOUT,TIM1_CH1N,?..."
|
|
elif CPUIS("STM32F301*6")||CPUIS("STM32F301*8")
|
|
elif cpuis("STM32F318*8")
|
|
elif CPUIS("STM32F302*6")||CPUIS("STM32F302*8")
|
|
elif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E pin 7" ",EVENTOUT,TIM1_ETR,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E pin 6" "TRACED3,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E pin 5" "TRACED2,EVENTOUT,TIM3_CH4,TSC_G7_IO4,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E pin 4" "TRACED1,EVENTOUT,TIM3_CH3,TSC_G7_IO3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E pin 3" "TRACED0,EVENTOUT,TIM3_CH2,TSC_G7_IO2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E pin 2" "TRACECK,EVENTOUT,TIM3_CH1,TSC_G7_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E pin 1" ",EVENTOUT,,,TIM17_CH1,,USART1_RX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E pin 0" ",EVENTOUT,TIM4_ETR,,TIM16_CH1,,USART1_TX,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E pin 15" ",EVENTOUT,TIM1_BKIN,,,USART3_RX,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E pin 14" ",EVENTOUT,TIM1_CH4,,TIM1_BKIN2,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E pin 13" ",EVENTOUT,TIM1_CH3,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E pin 12" ",EVENTOUT,TIM1_CH3N,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E pin 11" ",EVENTOUT,TIM1_CH2,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E pin 10" ",EVENTOUT,TIM1_CH2N,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E pin 9" ",EVENTOUT,TIM1_CH1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E pin 8" ",EVENTOUT,TIM1_CH1N,?..."
|
|
elif cpuis("STM32F303*6")||cpuis("STM32F303*8")
|
|
elif cpuis("STM32F303*B")||cpuis("STM32F303*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E pin 7" ",EVENTOUT,TIM1_ETR,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E pin 6" "TRACED3,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E pin 5" "TRACED2,EVENTOUT,TIM3_CH4,TSC_G7_IO4,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E pin 4" "TRACED1,EVENTOUT,TIM3_CH3,TSC_G7_IO3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E pin 3" "TRACED0,EVENTOUT,TIM3_CH2,TSC_G7_IO2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E pin 2" "TRACECK,EVENTOUT,TIM3_CH1,TSC_G7_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E pin 1" ",EVENTOUT,,,TIM17_CH1,,USART1_RX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E pin 0" ",EVENTOUT,TIM4_ETR,,TIM16_CH1,,USART1_TX,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E pin 15" ",EVENTOUT,TIM1_BKIN,,,USART3_RX,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E pin 14" ",EVENTOUT,TIM1_CH4,,TIM1_BKIN2,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E pin 13" ",EVENTOUT,TIM1_CH3,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E pin 12" ",EVENTOUT,TIM1_CH3N,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E pin 11" ",EVENTOUT,TIM1_CH2,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E pin 10" ",EVENTOUT,TIM1_CH2N,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E pin 9" ",EVENTOUT,TIM1_CH1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E pin 8" ",EVENTOUT,TIM1_CH1N,?..."
|
|
elif cpuis("STM32F328*8")
|
|
elif cpuis("STM32F378*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E pin 7" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E pin 6" "TRACED3,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E pin 5" "TRACED2,EVENTOUT,,TSC_G7_IO4,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E pin 4" "TRACED1,EVENTOUT,,TSC_G7_IO3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E pin 3" "TRACED0,EVENTOUT,,TSC_G7_IO2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E pin 2" "TRACECK,EVENTOUT,,TSC_G7_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E pin 1" ",EVENTOUT,,,TIM17_CH1,,USART1_RX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E pin 0" ",EVENTOUT,TIM4_ETR,,TIM16_CH1,,USART1_TX,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E pin 15" ",EVENTOUT,,,,USART3_RX,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E pin 14" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E pin 13" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E pin 12" ",EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E pin 11" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E pin 10" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E pin 9" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E pin 8" ",EVENTOUT,?..."
|
|
elif cpuis("STM32F334*6")||cpuis("STM32F334*8")
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E pin 7" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E pin 6" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E pin 5" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E pin 4" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E pin 3" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E pin 2" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E pin 1" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E pin 0" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E pin 15" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E pin 14" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E pin 13" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E pin 12" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E pin 11" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E pin 10" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E pin 9" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E pin 8" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
endif
|
|
width 0xB
|
|
width 15.
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOE_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port E reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port E reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port E reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port E reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port E reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port E reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port E reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port E reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port E reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port E reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port E reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port E reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port E reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port E reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port E reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port E reset bit 0" "No effect,Reset"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "GPIO F"
|
|
base ad:0x48001400
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F mode register"
|
|
bitfld.long 0x04 15. " OT15 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "Low,Low,Medium,High"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOF_ODR,GPIO Port F output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port F output data" "Low,High"
|
|
sif !CPUIS("STM32F302*B")&&!CPUIS("STM32F302*C")&&!CPUIS("STM32F303*B")&&!CPUIS("STM32F303*C")&&!CPUIS("STM32F358*C")
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port F lock bit 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port F lock bit 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port F lock bit 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port F lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port F lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port F lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port F lock bit 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port F lock bit 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port F lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Port F lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port F lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port F lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port F lock bit 3 " "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port F lock bit 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit 0" "Not locked,Locked"
|
|
endif
|
|
textline ""
|
|
width 15.
|
|
sif CPUIS("STM32F358*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F pin 7" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F pin 6" ",EVENTOUT,TIM4_CH4,,I2S_SCL,,USART3_RTS,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port F pin 4" ",EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F pin 2" ",EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,TIM1_CH3N,,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F pin 10" ",EVENTOUT,,TIM15_CH2,SPI2_SCK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F pin 9" ",EVENTOUT,,TIM15_CH1,SPI2_SCK,?..."
|
|
elif CPUIS("STM32F301*6")||CPUIS("STM32F301*8")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F pin 1" ",,,,I2C2_SDA,SPI2_NSS/I2S2_WS,TIM1_CH3N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F pin 0" ",,,,I2C2_SCL,SPI2_SCK/I2S2_CK,?..."
|
|
elif cpuis("STM32F318*8")
|
|
elif CPUIS("STM32F302*6")||CPUIS("STM32F302*8")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F pin 1" ",,,,I2C2_SDA,SPI2_NSS/I2S2_WS,TIM1_CH3N,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F pin 0" ",,,,I2C2_SCL,SPI2_SCK/I2S2_CK,?..."
|
|
elif cpuis("STM32F302*B")||cpuis("STM32F302*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F pin 6" ",EVENTOUT,TIM4_CH4,,I2S_SCL,,USART3_RTS,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port F pin 4" ",EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F pin 2" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,TIM1_CH3N,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F pin 10" ",EVENTOUT,,TIM15_CH2,SPI2_SCK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F pin 9" ",EVENTOUT,,TIM15_CH1,SPI2_SCK,?..."
|
|
elif cpuis("STM32F303*6")||cpuis("STM32F303*8")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F pin 1" ",,,,,,TIM1_CH3N,?..."
|
|
elif cpuis("STM32F303*B")||cpuis("STM32F303*C")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F pin 7" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F pin 6" ",EVENTOUT,TIM4_CH4,,I2S_SCL,,USART3_RTS,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port F pin 4" ",EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F pin 2" ",EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,,TIM1_CH3N,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F pin 10" ",EVENTOUT,,TIM15_CH2,SPI2_SCK,,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F pin 9" ",EVENTOUT,,TIM15_CH1,,SPI2_SCK,?..."
|
|
elif cpuis("STM32F328*8")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F pin 1" ",,,,,,TIM1_CH3N,?..."
|
|
elif cpuis("STM32F378*")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F pin 7" ",EVENTOUT,,,I2C2_SDA,,,USART2_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F pin 6" ",EVENTOUT,TIM4_CH4,,I2S_SCL,SPI1_MOSI/I2S1_SD,USART3_RTS,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port F pin 4" ",EVENTOUT,COMP1_OUT,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F pin 2" ",EVENTOUT,,I2S2_SMBA,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F pin 1" ",,,,I2C2_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F pin 0" ",,,,I2C2_SDA,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F pin 10" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F pin 9" ",EVENTOUT,TIM14_CH1,?..."
|
|
elif cpuis("STM32F334*6")||cpuis("STM32F334*8")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F pin 1" ",,,,,,TIM1_CH3N,?..."
|
|
else
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F pin 7" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F pin 6" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port F pin 5" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port F pin 4" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port F pin 3" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F pin 2" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F pin 1" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F pin 0" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port F pin 15" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port F pin 14" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port F pin 13" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port F pin 12" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port F pin 11" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port F pin 10" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port F pin 9" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port F pin 8" "AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15"
|
|
endif
|
|
width 0xB
|
|
width 15.
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port F reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port F reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port F reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port F reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port F reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port F reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port F reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port F reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port F reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port F reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port F reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port F reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port F reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
else
|
|
tree.open "GPIO (General-Purpose I/O)"
|
|
tree "GPIO A"
|
|
base ad:0x48000000
|
|
width 22.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOA_MODER,GPIO port A mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif (cpu()!="STM32F372C8"&&cpu()!="STM32F372CB"&&cpu()!="STM32F372CC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373CC"&&cpu()!="STM32F383C8"&&cpu()!="STM32F383CB"&&cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port A configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOA_OTYPER,GPIO port A output type register"
|
|
bitfld.long 0x04 15. " OT15 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 11. " OT11 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif (cpu()!="STM32F372C8"&&cpu()!="STM32F372CB"&&cpu()!="STM32F372CC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373CC"&&cpu()!="STM32F383C8"&&cpu()!="STM32F383CB"&&cpu()!="STM32F383CC")
|
|
bitfld.long 0x04 7. " OT7 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 6. " OT6 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 2. " OT2 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port A output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOA_OSPEEDR,GPIO port A output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
sif (cpu()!="STM32F372C8"&&cpu()!="STM32F372CB"&&cpu()!="STM32F372CC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373CC"&&cpu()!="STM32F383C8"&&cpu()!="STM32F383CB"&&cpu()!="STM32F383CC")
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port A output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOA_PUPDR,GPIO port A pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif (cpu()!="STM32F372C8"&&cpu()!="STM32F372CB"&&cpu()!="STM32F372CC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373CC"&&cpu()!="STM32F383C8"&&cpu()!="STM32F383CB"&&cpu()!="STM32F383CC")
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port A configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOA_IDR,GPIO port A input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " IDR11 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port A input data" "Low,High"
|
|
textline " "
|
|
sif (cpu()!="STM32F372C8"&&cpu()!="STM32F372CB"&&cpu()!="STM32F372CC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373CC"&&cpu()!="STM32F383C8"&&cpu()!="STM32F383CB"&&cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 7. " IDR7 ,Port A input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " IDR6 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 3. " IDR3 ,Port A input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDR2 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port A input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port A input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOA_ODR_SET/CLR,GPIO Port A output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15 ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14 ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13 ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12 ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11 ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10 ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9 ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8 ,Port A output data" "Low,High"
|
|
textline " "
|
|
sif (cpu()!="STM32F372C8"&&cpu()!="STM32F372CB"&&cpu()!="STM32F372CC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373CC"&&cpu()!="STM32F383C8"&&cpu()!="STM32F383CB"&&cpu()!="STM32F383CC")
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7 ,Port A output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6 ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5 ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4 ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3 ,Port A output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2 ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1 ,Port A output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0 ,Port A output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOA_LCKR,GPIO port A configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port A lock bit 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port A lock bit 14" "Not locked,Locked"
|
|
bitfld.long 0x00 13. " LCK13 ,Port A lock bit 13" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port A lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port A lock bit 11" "Not locked,Locked"
|
|
bitfld.long 0x00 10. " LCK10 ,Port A lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port A lock bit 9" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port A lock bit 8" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpu()!="STM32F372C8"&&cpu()!="STM32F372CB"&&cpu()!="STM32F372CC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373CC"&&cpu()!="STM32F383C8"&&cpu()!="STM32F383CB"&&cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 7. " LCK7 ,Port A lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " LCK6 ,Port A lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port A lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port A lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port A lock bit 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port A lock bit 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port A lock bit 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port A lock bit 0" "Not locked,Locked"
|
|
sif ((cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,TIM3_CH2,TSC_G2_IO4,TIM8_CH1N,SPI1_MOSI,TIM1_CH1N,,COMP2_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,TIM3_CH1,TSC_G2_IO3,TIM8_BKIN,SPI1_MISO,TIM1_BKIN,,COMP1_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" ",TIM2_CH1_ETR,,TSC_G2_IO2,,SPI_SCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" ",,TIM3_CH2,TSC_G2_IO1,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,,TSC_G1_IO4,,,,USART2_RX,,TIM15_CH2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" ",TIM2_CH3,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" ",TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS,,TIM15_CH1N,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" ",TIM2_CH1_ETR,,TSC_G1_IO1,,,,USART2_CTS,COMP1_OUT,TIM8_BKIN,TIM8_ETR,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1_ETR,TIM8_CH1,,I2C1_SCL,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_RX,,TIM1_BKIN,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" "SWCLK-JTCK,,,TSC_G4_IO4,I2C1_SDA,TIM8_CH2,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" "SWDAT-JTMS,TIM16_CH1N,,TSC_G4_IO3,,IR_OUT,,USART3_CTS,,,TIM4_CH3,,,,,EVENTOUT"
|
|
textline " "
|
|
sif (cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,,TIM1_CH2N,USART1_RTS,COMP2_OUT,CAN_TX,TIM4_CH2,TIM1_ETR,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,,,,,TIM1_CH1N,USART1_CTS,COMP1_OUT,CAN_RX,TIM4_CH1,TIM1_CH4,TIM1_BKIN2,,,EVENTOUT"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,,TIM1_CH2N,USART1_RTS,COMP2_OUT,CAN_TX,TIM4_CH2,TIM1_ETR,,,USBDP,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,,,,,TIM1_CH1N,USART1_CTS,COMP1_OUT,CAN_RX,TIM4_CH1,TIM1_CH4,TIM1_BKIN2,,USBDM,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,I2C2_SDA,,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,TIM8_BKIN,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" ",,,TSC_G4_IO1,I2C2_SCL,I2S3_MCK,TIM1_CH2,USART1_TX,COMP5_OUT,TIM15_BKIN,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "MCO,,,,I2C2_SMBA,I2S2_MCK,TIM1_CH1,USART1_CK,COMP3_OUT,,TIM4_ETR,,,,,EVENTOUT"
|
|
elif ((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
sif (cpu()!="STM32F372C8"&&cpu()!="STM32F372CB"&&cpu()!="STM32F372CC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373CC"&&cpu()!="STM32F383C8"&&cpu()!="STM32F383CB"&&cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,TIM3_CH2,TSC_G2_IO4,,SPI_MOSI/I2S1_SD,,,COMP2_OUT,TIM14_CH1,,,,,,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,TIM3_CH1,TSC_G2_IO3,,SPI1_MISO/I2S1_MCK,,,COMP1_OUT,TIM13_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port A pin 5" ",TIM2_CH1_ETR,,TSC_G2_IO2,,SPI_SCK/I2S1_CK,,CEC,,TIM14_CH1,TIM12_CH2,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port A pin 4" ",,TIM3_CH2,TSC_G2_IO1,,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,USART2_CK,,,TIM12_CH1,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,TIM5_CH4,TSC_G1_IO4,,,SPI3_MOSI/I2S3_SD,USART2_RX,,TIM15_CH2,,TIM19_CH4,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port A pin 2" ",TIM2_CH3,TIM5_CH3,TSC_G1_IO3,,,SPI3_MISO/I2S3_MCK,USART2_TX,COMP2_OUT,TIM15_CH1,,TIM19_CH3,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port A pin 1" ",TIM2_CH2,TIM5_CH2,TSC_G1_IO2,,,SPI3_SCK/I2S3_CK,USART2_RTS,,TIM15_CH1N,,TIM19_CH2,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port A pin 0" ",TIM2_CH1_ETR,TIM5_CH1_ETR,TSC_G1_IO1,,,,USART2_CTS,COMP1_OUT,,,TIM19_CH1,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1_ETR,,TSC_SYNC,I2C1_SCL,SPI1_NSS/I2S1_WS,SPI3_NSS/I2S3_WS,,,,TIM12_CH2,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port A pin 14" "JTCK-SWCLK,,,TSC_G4_IO4,I2C1_SDA,,,,,,TIM12_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port A pin 13" "JTMS-SWDAT,TIM16_CH1N,TIM5_CH4,TSC_G4_IO3,,IR_OUT,DPI1_MISO/I2S1_MCK,USART3_CTS,,,TIM4_CH3,,,,,EVENTOUT"
|
|
textline " "
|
|
sif (cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,TIM5_CH3,,,,SPI1_SCK/I2S1_CK,USART1_RTS,COMP2_OUT,CAN_TX,TIM4_CH2,,,,,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,TIM5_CH2,,,SPI2_NSS/I2S2_WS,SPI1_NSS/I2S1_WS,USART1_CTS,COMP1_OUT,CAN_RX,TIM4_CH1,,,,,EVENTOUT"
|
|
else
|
|
textline " "
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,TIM5_CH3,,,,SPI1_SCK/I2S1_CK,USART1_RTS,COMP2_OUT,CAN_TX,TIM4_CH2,,,,USBDP,EVENTOUT"
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port A pin 11" ",,TIM5_CH2,,,SPI2_NSS/I2S2_WS,SPI1_NSS/I2S1_WS,USART1_CTS,COMP1_OUT,CAN_RX,TIM4_CH1,,,,USBDM,EVENTOUT"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,I2C2_SDA,SPI2_MOSI/I2S2_SD,,USART1_RX,,TIM14_CH1,TIM2_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port A pin 9" ",,TIM13_CH1,TSC_G4_IO1,I2C2_SCL,SPI2_MISO/I2S2_MCK,,USART1_TX,,TIM15_BKIN,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port A pin 8" "MCO,,TIM5_CH1_ETR,,I2C2_SMBAI,I2S2_SCK/I2S2_CK,,USART1_CK,,,TIM4_ETR,,,,,EVENTOUT"
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,TIM3_CH2,TSC_G2_IO4,TIM8_CH1N,SPI1_MOSI,TIM1_CH1N,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,TIM3_CH1,TSC_G2_IO3,TIM8_BKIN,SPI1_MISO,TIM1_BKIN,,COMP1_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TSC_G2_IO2,,SPI1_SCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port A pin 4" ",,TIM3_CH2,TSC_G2_IO1,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,,TSC_G1_IO4,,,,USART2_RX,,TIM15_CH2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port A pin 2" ",TIM2_CH3,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port A pin 1" "RTC_REFIN,TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS,,TIM15_CH1N,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,,TSC_G1_IO1,,,,USART2_CTS,COMP1_OUT,TIM8_BKIN,TIM8_ETR,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,TIM8_CH1,TSC_SYNC,I2C1_SCL,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_RX,,TIM1_BKIN,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port A pin 14" "SWCLK-JTCK,,,TSC_G4_IO4,I2C1_SDA,TIM8_CH2,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port A pin 13" "SWDIO-JTMS,TIM16_CH1N,,TSC_G4_IO3,,IR-OUT,,USART3_CTS,,,TIM4_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,I2SCKIN,TIM1_CH2N,USART1_RTS,COMP2_OUT,CAN_TX,TIM4_CH2,TIM1_ETR,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port A pin 11" ",,,,,SPI2_MOSI/I2S2_SD,TIM1_CH1N,USART1_CTS,COMP1_OUT,CAN_RX,TIM4_CH1,TIM1_CH4,TIM1_BKIN2,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,I2C2_SDA,SPI2_MISO/I2S2EXT_SD,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,TIM8_BKIN,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port A pin 9" ",,I2C3_SMBAL,TSC_G4_IO1,I2C2_SCL,I2S3_MCK,TIM1_CH2,USART1_TX,COMP5_OUT,TIM15_BKIN,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port A pin 8" "MCO,,,I2C3_SCL,I2C2_SMBAL,I2S2_MCK,TIM1_CH1,USART1_CK,COMP3_OUT,,TIM4_ETR,,,,,EVENTOUT"
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,TIM3_CH2,TSC_G2_IO4,,SPI1_MOSI,TIM1_CH1N,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,TIM3_CH1,TSC_G2_IO3,,SPI1_MISO,TIM1_BKIN,,COMP1_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TSC_G2_IO2,,SPI1_SCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port A pin 4" ",,TIM3_CH2,TSC_G2_IO1,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,,TSC_G1_IO4,,,,USART2_RX,,TIM15_CH2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port A pin 2" ",TIM2_CH3,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port A pin 1" "RTC_REFIN,TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS,,TIM15_CH1N,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,,TSC_G1_IO1,,,,USART2_CTS,COMP1_OUT,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,,TSC_SYNC,I2C1_SCL,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_RX,,TIM1_BKIN,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port A pin 14" "SWCLK-JTCK,,,TSC_G4_IO4,I2C1_SDA,,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port A pin 13" "SWDIO-JTMS,TIM16_CH1N,,TSC_G4_IO3,,IR-OUT,,USART3_CTS,,,TIM4_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,I2SCKIN,TIM1_CH2N,USART1_RTS,COMP2_OUT,CAN_TX,TIM4_CH2,TIM1_ETR,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port A pin 11" ",,,,,SPI2_MOSI/I2S2_SD,TIM1_CH1N,USART1_CTS,COMP1_OUT,CAN_RX,TIM4_CH1,TIM1_CH4,TIM1_BKIN2,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,I2C2_SDA,SPI2_MISO/I2S2EXT_SD,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port A pin 9" ",,I2C3_SMBAL,TSC_G4_IO1,I2C2_SCL,I2S3_MCK,TIM1_CH2,USART1_TX,,TIM15_BKIN,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port A pin 8" "MCO,,,I2C3_SCL,I2C2_SMBAL,I2S2_MCK,TIM1_CH1,USART1_CK,,,TIM4_ETR,,,,,EVENTOUT"
|
|
elif cpuis("STM32F398VE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOA_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port A pin 7" ",TIM17_CH1,TIM3_CH2,TSC_G2_IO4,TIM8_CH1N,SPI1_MOSI,TIM1_CH1N,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port A pin 6" ",TIM16_CH1,TIM3_CH1,TSC_G2_IO3,TIM8_BKIN,SPI1_MISO,TIM1_BKIN,,COMP1_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port A pin 5" ",TIM2_CH1/TIM2_ETR,,TSC_G2_IO2,,SPI1_SCK,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port A pin 4" ",,TIM3_CH2,TSC_G2_IO1,,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port A pin 3" ",TIM2_CH4,,TSC_G1_IO4,,,,USART2_RX,,TIM15_CH2,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port A pin 2" ",TIM2_CH3,,TSC_G1_IO3,,,,USART2_TX,COMP2_OUT,TIM15_CH1,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port A pin 1" "RTC_REFIN,TIM2_CH2,,TSC_G1_IO2,,,,USART2_RTS,,TIM15_CH1N,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port A pin 0" ",TIM2_CH1/TIM2_ETR,,TSC_G1_IO1,,,,USART2_CTS,COMP1_OUT,TIM8_BKIN,TIM8_ETR,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOA_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port A pin 15" "JTDI,TIM2_CH1/TIM2_ETR,TIM8_CH1,TSC_SYNC,I2C1_SCL,SPI1_NSS,SPI3_NSS/I2S3_WS,USART2_RX,,TIM1_BKIN,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port A pin 14" "SWCLK-JTCK,,,TSC_G4_IO4,I2C1_SDA,TIM8_CH2,TIM1_BKIN,USART2_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port A pin 13" "SWDIO-JTMS,TIM16_CH1N,,TSC_G4_IO3,,IR-OUT,,USART3_CTS,,,TIM4_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port A pin 12" ",TIM16_CH1,,,,I2SCKIN,TIM1_CH2N,USART1_RTS,COMP2_OUT,CAN_TX,TIM4_CH2,TIM1_ETR,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port A pin 11" ",,,,,SPI2_MOSI/I2S2_SD,TIM1_CH1N,USART1_CTS,COMP1_OUT,CAN_RX,TIM4_CH1,TIM1_CH4,TIM1_BKIN2,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port A pin 10" ",TIM17_BKIN,,TSC_G4_IO2,I2C2_SDA,SPI2_MISO/I2S2EXT_SD,TIM1_CH3,USART1_RX,COMP6_OUT,,TIM2_CH4,TIM8_BKIN,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port A pin 9" ",,I2C3_SMBAL,TSC_G4_IO1,I2C2_SCL,I2S3_MCK,TIM1_CH2,USART1_TX,COMP5_OUT,TIM15_BKIN,TIM2_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port A pin 8" "MCO,,,I2C3_SCL,I2C2_SMBAL,I2S2_MCK,TIM1_CH1,USART1_CK,COMP3_OUT,,TIM4_ETR,,,,,EVENTOUT"
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOA_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port A reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port A reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port A reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port A reset bit 12" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BR11 ,Port A reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port A reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port A reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port A reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()!="STM32F372C8"&&cpu()!="STM32F372CB"&&cpu()!="STM32F372CC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373CC"&&cpu()!="STM32F383C8"&&cpu()!="STM32F383CB"&&cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 7. " BR7 ,Port A reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " BR6 ,Port A reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port A reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port A reset bit 4" "No effect,Reset"
|
|
bitfld.long 0x00 3. " BR3 ,Port A reset bit 3" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 2. " BR2 ,Port A reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port A reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port A reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO B"
|
|
base ad:0x48000400
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOB_MODER,GPIO port B mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372V8"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372VB"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F372VC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373VC"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373V8"&&cpu()!="STM32F373R8"&&cpu()!="STM32F373VB"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC")
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373R8"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC")
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
sif (cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&cpu()!="STM32F313VC"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC"&&cpu()!="STM32F398VE")
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port B configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOB_OTYPER,GPIO port B output type register"
|
|
bitfld.long 0x04 15. " OT15 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372V8"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372VB"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F372VC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373VC"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373V8"&&cpu()!="STM32F373R8"&&cpu()!="STM32F373VB"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC")
|
|
bitfld.long 0x04 13. " OT13 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 12. " OT12 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373R8"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC")
|
|
bitfld.long 0x04 10. " OT10 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 9. " OT9 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 3. " OT3 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
sif (cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&cpu()!="STM32F313VC"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC"&&cpu()!="STM32F398VE")
|
|
bitfld.long 0x04 2. " OT2 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " OT1 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port B output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOB_OSPEEDR,GPIO port B output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372V8"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372VB"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F372VC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373VC"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373V8"&&cpu()!="STM32F373R8"&&cpu()!="STM32F373VB"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC")
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373R8"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC")
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
sif (cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&cpu()!="STM32F313VC"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC"&&cpu()!="STM32F398VE")
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port B output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOB_PUPDR,GPIO port B pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372V8"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372VB"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F372VC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373VC"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373V8"&&cpu()!="STM32F373R8"&&cpu()!="STM32F373VB"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC")
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373R8"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC")
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
sif (cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&cpu()!="STM32F313VC"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC"&&cpu()!="STM32F398VE")
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port B configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOB_IDR,GPIO port B input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port B input data" "Low,High"
|
|
textline " "
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372V8"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372VB"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F372VC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373VC"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373V8"&&cpu()!="STM32F373R8"&&cpu()!="STM32F373VB"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC")
|
|
bitfld.long 0x00 13. " IDR13 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 12. " IDR12 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373R8"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC")
|
|
bitfld.long 0x00 10. " IDR10 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " IDR9 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port B input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 3. " IDR3 ,Port B input data" "Low,High"
|
|
textline " "
|
|
sif (cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&cpu()!="STM32F313VC"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC"&&cpu()!="STM32F398VE")
|
|
bitfld.long 0x00 2. " IDR2 ,Port B input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " IDR1 ,Port B input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port B input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOB_ODR_SET/CLR,GPIO port B output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15 ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14 ,Port B output data" "Low,High"
|
|
textline " "
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372V8"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372VB"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F372VC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373VC"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373V8"&&cpu()!="STM32F373R8"&&cpu()!="STM32F373VB"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC")
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13 ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12 ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11 ,Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373R8"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC")
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10 ,Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9 ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8 ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7 ,Port B output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6 ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5 ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4 ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3 ,Port B output data" "Low,High"
|
|
textline " "
|
|
sif (cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&cpu()!="STM32F313VC"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC"&&cpu()!="STM32F398VE")
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2 ,Port B output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1 ,Port B output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0 ,Port B output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOB_LCKR,GPIO port B configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372V8"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372VB"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F372VC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373VC"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373V8"&&cpu()!="STM32F373R8"&&cpu()!="STM32F373VB"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC")
|
|
bitfld.long 0x00 13. " LCK13 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373R8"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC")
|
|
bitfld.long 0x00 10. " LCK10 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " LCK9 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
sif (cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&cpu()!="STM32F313VC"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC"&&cpu()!="STM32F398VE")
|
|
bitfld.long 0x00 2. " LCK2 ,Port B lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " LCK1 ,Port B lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port B lock bit" "Not locked,Locked"
|
|
sif ((cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,TIM4_CH2,TSC_G5_IO4,I2C1_SDA,TIM8_BKIN,,USART1_RX,,,TIM3_CH4,,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,TIM4_CH1,TSC_G5_IO3,I2C1_SCL,TIM8_CH1,TIM8_ETR,USART1_TX,,,TIM8_BKIN2,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,TIM3_CH2,TIM8_CH3N,I2C1_SMBA,SPI1_MOSI,SPI3_MOSI/I2S3_SD,USART2_CK,,,TIM17_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" "NJTRST,TIM16_CH1,TIM3_CH1,TSC_G5_IO2,TIM8_CH2N,SPI1_MISO,SPI3_MISO/I2S3EXT_SD,USART2_RX,,,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,TIM4_ETR,TSC_G5_IO1,TIM8_CH1N,SPI1_SCK,SPI3_SCK/I2S3_CK,USART2_TX,,,TIM3_ETR,,,,,EVENTOUT"
|
|
textline " "
|
|
sif (cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&cpu()!="STM32F313VC")
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B pin 2" ",,,TSC_G3_IO4,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" ",,TIM3_CH4,TSC_G3_IO3,TIM8_CH3N,,TIM1_CH3N,,COMP4_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" ",,TIM3_CH3,TSC_G3_IO2,TIM8_CH2N,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" ",TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO4,,SPI2_MISO/I2S2EXT_SD,TIM1_CH2N,USART3_RTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port B pin 13" ",,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,TIM1_CH1N,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port B pin 12" ",,,TSC_G6_IO2,I2C2_SMBA,SPI1_NSS/I2S2_WS,TIM1_BKIN,USART3_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port B pin 11" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,TIM4_CH4,,I2C1_SDA,,IR_OUT,,COMP2_OUT,CAN_TX,TIM8_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,TIM4_CH3,TSC_SYNC,I2C1_SCL,,,,COMP1_OUT,CAN_RX,TIM8_CH2,,TIM1_BKIN,,,EVENTOUT"
|
|
elif ((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,TIM4_CH2,TSC_G5_IO4,I2C1_SDA,,,USART1_RX,,TIM15_CH2,TIM3_CH4,TIM19_CH2,,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,TIM4_CH1,TSC_G5_IO3,I2C1_SCL,,,USART1_TX,,TIM15_CH1,TIM3_CH3,TIM19_CH1,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,TIM3_CH2,,I2C1_SMBAI,SPI1_MOSI/I2S1_SD,SPI3_MOSI/I2S3_SD,USART2_CK,,,TIM17_CH1,TIM19_ETR,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port B pin 4" "JTRST,TIM16_CH1,TIM3_CH1,TSC_G5_IO2,,SPI1_MISO/I2S1_MCK,SPI3_MISO/I2S3_MCK_SD,USART2_RX,,TIM15_CH1N,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port B pin 3" "JTDO/TRACESWO,TIM2_CH2,TIM4_ETR,TSC_G5_IO1,,SPI1_SCK/I2S1_CK,SPI3_SCK/I2S3_CK,USART2_TX,,TIM13_CH1,TIM3_ETR,,,,,EVENTOUT"
|
|
textline " "
|
|
sif (cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC")
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port B pin 2" ",,,,,,,,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port B pin 1" ",,TIM3_CH4,TSC_G3_IO4,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port B pin 0" ",,TIM3_CH3,TSC_G3_IO3,,SPI_MOSI/I2S1_SD,,,,,TIM3_CH2,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port B pin 15" ",TIM15_CH2,TIM15_CH1N,TSC_G6_IO2,,SPI2_MOSI/I2S2_SD,,,,TIM12_CH2,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO1,,SPI2_MISO/I2S2_MCK,,USART3_RTS,,TIM12_CH1,,,,,,EVENTOUT"
|
|
textline " "
|
|
sif (cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNCH,,SPI2_SCK/I2S2_CK,CEC,USART3_TX,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,TIM4_CH4,,I2C1_SDA,SPI2_NSS/I2S2_WS,IR-OUT,USART3_RX,COMP2_OUT,CAN_TX,,TIM19_CH4,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,TIM4_CH3,TSC_SYNC,I2C1_SCL,SPI2_SCK/I2S2_CK,CEC,USART3_TX,COMP1_OUT,CAN_RX,,TIM19_CH3,,,,EVENTOUT"
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,TIM4_CH2,TSC_G5_IO4,I2C1_SDA,TIM8_BKIN,,USART1_RX,,,TIM3_CH4,,FMC_NADV,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,TIM4_CH1,TSC_G5_IO3,I2C1_SCL,TIM8_CH1,TIM8_ETR,USART1_TX,,,TIM8_BKIN2,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,TIM3_CH2,TIM8_CH3N,I2C1_SMBAL,SPI1_MOSI,SPI3_MOSI/I2S3_SD,USART2_CK,I2C3_SDA,,TIM17_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port B pin 4" "JTRST,TIM16_CH1,TIM3_CH1,TSC_G5_IO2,TIM8_CH2N,SPI1_MISO,SPI3_MISO/I2S3EXT_SD,USART2_RX,,,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,TIM4_ETR,TSC_G5_IO1,TIM8_CH1N,SPI1_SCK,SPI3_SCK/I2S3_CK,USART2_TX,,,TIM3_ETR,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port B pin 2" ",,,TSC_G3_IO4,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port B pin 1" ",,TIM3_CH4,TSC_G3_IO3,TIM8_CH3N,,TIM1_CH3N,,COMP4_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port B pin 0" ",,TIM3_CH3,TSC_G3_IO2,TIM8_CH2N,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO4,,SPI2_MISO/I2S2EXT_SD,TIM1_CH2N,USART3_RTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port B pin 13" ",,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,TIM1_CH1N,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port B pin 12" ",,,TSC_G6_IO2,I2C2_SMBAL,SPI2_NSS/I2S2_WS,TIM1_BKIN,USART3_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port B pin 11" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,TIM4_CH4,,I2C1_SDA,,IR-OUT,USART3_TX,COMP2_OUT,CAN_TX,TIM8_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,TIM4_CH3,TSC_SYNC,I2C1_SCL,,,USART3_RX,COMP1_OUT,CAN_RX,TIM8_CH2,,TIM1_BKIN,,,EVENTOUT"
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,TIM4_CH2,TSC_G5_IO4,I2C1_SDA,,,USART1_RX,,,TIM3_CH4,,FMC_NADV,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,TIM4_CH1,TSC_G5_IO3,I2C1_SCL,,,USART1_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,TIM3_CH2,,I2C1_SMBAL,SPI1_MOSI,SPI3_MOSI/I2S3_SD,USART2_CK,I2C3_SDA,,TIM17_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port B pin 4" "JTRST,TIM16_CH1,TIM3_CH1,TSC_G5_IO2,,SPI1_MISO,SPI3_MISO/I2S3EXT_SD,USART2_RX,,,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,TIM4_ETR,TSC_G5_IO1,,SPI1_SCK,SPI3_SCK/I2S3_CK,USART2_TX,,,TIM3_ETR,,,,,EVENTOUT"
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port B pin 2" ",,,TSC_G3_IO4,,,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port B pin 1" ",,TIM3_CH4,TSC_G3_IO3,,,TIM1_CH3N,,COMP4_OUT,,,,,,,-EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port B pin 0" ",,TIM3_CH3,TSC_G3_IO2,,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO4,,SPI2_MISO/I2S2EXT_SD,TIM1_CH2N,USART3_RTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port B pin 13" ",,,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,TIM1_CH1N,USART3_CTS,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port B pin 12" ",,,TSC_G6_IO2,I2C2_SMBAL,SPI2_NSS/I2S2_WS,TIM1_BKIN,USART3_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port B pin 11" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,TIM4_CH4,,I2C1_SDA,,IR-OUT,USART3_TX,COMP2_OUT,CAN_TX,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,TIM4_CH3,TSC_SYNC,I2C1_SCL,,,USART3_RX,COMP1_OUT,CAN_RX,,,TIM1_BKIN,,,EVENTOUT"
|
|
elif cpuis("STM32F398VE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOB_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port B pin 7" ",TIM17_CH1N,TIM4_CH2,TSC_G5_IO4,I2C1_SDA,TIM8_BKIN,,USART1_RX,,,TIM3_CH4,,FMC_NADV,,,EVENTOUT"
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port B pin 6" ",TIM16_CH1N,TIM4_CH1,TSC_G5_IO3,I2C1_SCL,TIM8_CH1,TIM8_ETR,USART1_TX,,,TIM8_BKIN2,,,,,EVENTOUT"
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port B pin 5" ",TIM16_BKIN,TIM3_CH2,TIM8_CH3N,I2C1_SMBAL,SPI1_MOSI,SPI3_MOSI/I2S3_SD,USART2_CK,I2C3_SDA,,TIM17_CH1,,,,,EVENTOUT"
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port B pin 4" "JTRST,TIM16_CH1,TIM3_CH1,TSC_G5_IO2,TIM8_CH2N,SPI1_MISO,SPI3_MISO/I2S3EXT_SD,USART2_RX,,,TIM17_BKIN,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port B pin 3" "JTDO-TRACESWO,TIM2_CH2,TIM4_ETR,TSC_G5_IO1,TIM8_CH1N,SPI1_SCK,SPI3_SCK/I2S3_CK,USART2_TX,,,TIM3_ETR,,,,,EVENTOUT"
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port B pin 1" ",,TIM3_CH4,TSC_G3_IO3,TIM8_CH3N,,TIM1_CH3N,,COMP4_OUT,,,,,,,EVENTOUT"
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port B pin 0" ",,TIM3_CH3,TSC_G3_IO2,TIM8_CH2N,,TIM1_CH2N,,,,,,,,,EVENTOUT"
|
|
line.long 0x04 "GPIOB_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port B pin 15" "RTC_REFIN,TIM15_CH2,TIM15_CH1N,,TIM1_CH3N,SPI2_MOSI/I2S2_SD,,,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port B pin 14" ",TIM15_CH1,,TSC_G6_IO4,,SPI2_MISO/I2S2EXT_SD,TIM1_CH2N,USART3_RTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port B pin 13" ",,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,TIM1_CH1N,USART3_CTS,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port B pin 12" ",,,TSC_G6_IO2,I2C2_SMBAL,SPI2_NSS/I2S2_WS,TIM1_BKIN,USART3_CK,,,,,,,,EVENTOUT"
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port B pin 11" ",TIM2_CH4,,TSC_G6_IO1,,,,USART3_RX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port B pin 10" ",TIM2_CH3,,TSC_SYNC,,,,USART3_TX,,,,,,,,EVENTOUT"
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port B pin 9" ",TIM17_CH1,TIM4_CH4,,I2C1_SDA,,IR-OUT,USART3_TX,COMP2_OUT,CAN_TX,TIM8_CH3,,,,,EVENTOUT"
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port B pin 8" ",TIM16_CH1,TIM4_CH3,TSC_SYNC,I2C1_SCL,,,USART3_RX,COMP1_OUT,CAN_RX,TIM8_CH2,,TIM1_BKIN,,,EVENTOUT"
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOB_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port B reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port B reset bit 14" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372V8"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372VB"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F372VC"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373VC"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373V8"&&cpu()!="STM32F373R8"&&cpu()!="STM32F373VB"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC")
|
|
bitfld.long 0x00 13. " BR13 ,Port B reset bit 13" "No effect,Reset"
|
|
bitfld.long 0x00 12. " BR12 ,Port B reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port B reset bit 11" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB"&&cpu()!="STM32F372RC"&&cpu()!="STM32F372CC"&&cpu()!="STM32F372R8"&&cpu()!="STM32F372C8"&&cpu()!="STM32F372RB"&&cpu()!="STM32F373C8"&&cpu()!="STM32F373RB"&&cpu()!="STM32F373CB"&&cpu()!="STM32F373RC"&&cpu()!="STM32F373CC"&&cpu()!="STM32F373R8"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC")
|
|
bitfld.long 0x00 10. " BR10 ,Port B reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " BR9 ,Port B reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port B reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port B reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port B reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port B reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port B reset bit 4" "No effect,Reset"
|
|
bitfld.long 0x00 3. " BR3 ,Port B reset bit 3" "No effect,Reset"
|
|
textline " "
|
|
sif (cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&cpu()!="STM32F313VC"&&cpu()!="STM32F383CC"&&cpu()!="STM32F383RC"&&cpu()!="STM32F383VC"&&cpu()!="STM32F398VE")
|
|
bitfld.long 0x00 2. " BR2 ,Port B reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " BR1 ,Port B reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port B reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO C"
|
|
base ad:0x48000800
|
|
width 22.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOC_MODER,GPIO port C mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303RD"||cpu()=="STM32F303RE"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302RD"||cpu()=="STM32F302RE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD"||cpu()=="STM32F302ZD"||cpu()=="STM32F302ZE"||cpu()=="STM32F303ZD"||cpu()=="STM32F303ZE")
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port C configuration bits" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
line.long 0x04 "GPIOC_OTYPER,GPIO port C output type register"
|
|
bitfld.long 0x04 15. " OT15 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303RD"||cpu()=="STM32F303RE"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302RD"||cpu()=="STM32F302RE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD"||cpu()=="STM32F302ZD"||cpu()=="STM32F302ZE"||cpu()=="STM32F303ZD"||cpu()=="STM32F303ZE")
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port C output configuration bits" "Push-pull,Open-drain"
|
|
endif
|
|
line.long 0x08 "GPIOC_OSPEEDR,GPIO port C output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303RD"||cpu()=="STM32F303RE"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302RD"||cpu()=="STM32F302RE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD"||cpu()=="STM32F302ZD"||cpu()=="STM32F302ZE"||cpu()=="STM32F303ZD"||cpu()=="STM32F303ZE")
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port C output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
endif
|
|
line.long 0x0C "GPIOC_PUPDR,GPIO port C pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303RD"||cpu()=="STM32F303RE"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302RD"||cpu()=="STM32F302RE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD"||cpu()=="STM32F302ZD"||cpu()=="STM32F302ZE"||cpu()=="STM32F303ZD"||cpu()=="STM32F303ZE")
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port C configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOC_IDR,GPIO port C input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port C input data" "Low,High"
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303RD"||cpu()=="STM32F303RE"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302RD"||cpu()=="STM32F302RE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD"||cpu()=="STM32F302ZD"||cpu()=="STM32F302ZE"||cpu()=="STM32F303ZD"||cpu()=="STM32F303ZE")
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port C input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port C input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port C input data" "Low,High"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOC_ODR_SET/CLR,GPIO port C output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15 ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14 ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13 ,Port C output data" "Low,High"
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303RD"||cpu()=="STM32F303RE"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302RD"||cpu()=="STM32F302RE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD"||cpu()=="STM32F302ZD"||cpu()=="STM32F302ZE"||cpu()=="STM32F303ZD"||cpu()=="STM32F303ZE")
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12 ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11 ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10 ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9 ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8 ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7 ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6 ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5 ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4 ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3 ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2 ,Port C output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1 ,Port C output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0 ,Port C output data" "Low,High"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOC_LCKR,GPIO port C configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not Active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port C lock bit" "Not locked,Locked"
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303RD"||cpu()=="STM32F303RE"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302RD"||cpu()=="STM32F302RE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD"||cpu()=="STM32F302ZD"||cpu()=="STM32F302ZE"||cpu()=="STM32F303ZD"||cpu()=="STM32F303ZE")
|
|
textline " "
|
|
bitfld.long 0x00 12. " LCK12 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port C lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port C lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port C lock bit" "Not locked,Locked"
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C pin 7" ",EVENTOUT,TIM3_CH2,,TIM8_CH2,,I2S3_MCK,COMP5_OUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C pin 6" ",EVENTOUT,TIM3_CH1,,TIM8_CH1,,I2S2_MCK,COMP6_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C pin 5" ",EVENTOUT,,TSC_G3_IO1,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C pin 4" ",EVENTOUT,,,,,,USART1_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C pin 3" ",EVENTOUT,,,,,TIM1_BKIN2,?..."
|
|
textline " "
|
|
sif (cpu()!="STM32F313RC"&&cpu()!="STM32F313VC")
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C pin 2" ",EVENTOUT,,COMP7_OUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C pin 1" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C pin 0" ",EVENTOUT,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port C pin 13" ",,,,TIM1_CH1N,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C pin 12" ",EVENTOUT,,,TIM8_CH3N,UART5_TX,SPI3_MOS/I2S3_SD,USART3_CK,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C pin 11" ",EVENTOUT,,,TIM8_CH2N,UART4_RX,SPI3_MISO/I2S3EXT_SD,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C pin 10" ",EVENTOUT,,,TIM8_CH1N,UART4_TX,SPI3_SCK/I2S3_CK,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C pin 9" ",EVENTOUT,TIM3_CH4,,TIM8_CH4,I2S_CKIN,TIM8_BKIN2,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C pin 8" ",EVENTOUT,TIM3_CH3,,TIM8_CH3,,,COMP3_OUT,?..."
|
|
elif (cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port C pin 7" ",EVENTOUT,TIM3_CH2,,,SPI1_SCK/I2S1_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port C pin 6" ",EVENTOUT,TIM3_CH1,,,SPI1_NSS/I2S1_WS,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port C pin 5" ",EVENTOUT,,TSC_G3_IO2,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port C pin 4" ",EVENTOUT,TIM13_CH1,TSC_G3_IO1,,,,USART1_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port C pin 3" ",EVENTOUT,TIM5_CH4,,,SPI2_MOSI/I2S2_SD,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port C pin 2" ",EVENTOUT,TIM5_CH3,,,SPI2_MISO/I2S2_MCK,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port C pin 1" ",EVENTOUT,TIM5_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port C pin 0" ",EVENTOUT,TIM5_CH1_ETR,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port C pin 12" ",EVENTOUT,TIM19_CH3,,,,SPI3_MOSI/I2S3_SD,USART3_CK,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port C pin 11" ",EVENTOUT,TIM19_CH2,,,,SPI3_MISO/I2S3_MCK,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port C pin 10" ",EVENTOUT,TIM19_CH1,,,,SPI3_SCK/I2S3_CK,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port C pin 9" ",EVENTOUT,TIM3_CH4,,,SPI1_MOSI/I2S1_SD,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port C pin 8" ",EVENTOUT,TIM3_CH3,,,SPI1_MOSI/I2S1_MCK,?..."
|
|
elif (cpu()=="STM32F302CB"||cpu()=="STM32F302CC"||cpu()=="STM32F303CB"||cpu()=="STM32F303CC"||cpu()=="STM32F313CC")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 20.--23. " AFRH13 ,Alternate function selection for port C pin 13" ",,,,TIM1_CH1N,?..."
|
|
elif cpuis("STM32F398VE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port C pin 7" ",EVENTOUT,TIM3_CH2,,TIM8_CH2,,I2S3_MCK,COMP5_OUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port C pin 6" ",EVENTOUT,TIM3_CH1,,TIM8_CH1,,I2S2_MCK,COMP6_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port C pin 5" ",EVENTOUT,TIM15_BKIN,TSC_G3_IO1,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port C pin 4" ",EVENTOUT,TIM1_ETR,,,,,USART1_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port C pin 3" ",EVENTOUT,TIM1_CH4,,,,TIM1_BKIN2,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port C pin 2" ",EVENTOUT,TIM1_CH3,COMP7_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port C pin 1" ",EVENTOUT,TIM1_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port C pin 0" ",EVENTOUT,TIM1_CH1,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port C pin 15" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port C pin 14" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port C pin 13" ",EVENTOUT,,,TIM1_CH1N,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port C pin 12" ",EVENTOUT,,,TIM8_CH3N,UART5_TX,SPI3_MOSI/I2S3_SD,USART3_CK,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port C pin 11" ",EVENTOUT,,,TIM8_CH2N,UART4_RX,SPI3_MISO/I2S3EXT_SD,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port C pin 10" ",EVENTOUT,,,TIM8_CH1N,UART4_TX,SPI3_SCK/I2S3_CK,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port C pin 9" ",EVENTOUT,TIM3_CH4,I2C3_SDA,TIM8_CH4,I2SCKIN,TIM8_BKIN2,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port C pin 8" ",EVENTOUT,TIM3_CH3,,TIM8_CH3,,,COMP3_OUT,?..."
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port C pin 7" ",EVENTOUT,TIM3_CH2,,TIM8_CH2,,I2S3_MCK,COMP5_OUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port C pin 6" ",EVENTOUT,TIM3_CH1,,TIM8_CH1,,I2S2_MCK,COMP6_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port C pin 5" ",EVENTOUT,TIM15_BKIN,TSC_G3_IO1,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port C pin 4" ",EVENTOUT,TIM1_ETR,,,,,USART1_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port C pin 3" ",EVENTOUT,TIM1_CH4,,,,TIM1_BKIN2,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port C pin 2" ",EVENTOUT,TIM1_CH3,COMP7_OUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port C pin 1" ",EVENTOUT,TIM1_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port C pin 0" ",EVENTOUT,TIM1_CH1,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port C pin 15" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port C pin 14" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port C pin 13" ",EVENTOUT,,,TIM1_CH1N,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port C pin 12" ",EVENTOUT,,,TIM8_CH3N,UART5_TX,SPI3_MOSI/I2S3_SD,USART3_CK,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port C pin 11" ",EVENTOUT,,,TIM8_CH2N,UART4_RX,SPI3_MISO/I2S3EXT_SD,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port C pin 10" ",EVENTOUT,,,TIM8_CH1N,UART4_TX,SPI3_SCK/I2S3_CK,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port C pin 9" ",EVENTOUT,TIM3_CH4,I2C3_SDA,TIM8_CH4,I2SCKIN,TIM8_BKIN2,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port C pin 8" ",EVENTOUT,TIM3_CH3,,TIM8_CH3,,,COMP3_OUT,?..."
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOC_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port C pin 7" ",EVENTOUT,TIM3_CH2,,,,I2S3_MCK,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port C pin 6" ",EVENTOUT,TIM3_CH1,,,,I2S2_MCK,COMP6_OUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port C pin 5" ",EVENTOUT,TIM15_BKIN,TSC_G3_IO1,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port C pin 4" ",EVENTOUT,TIM1_ETR,,,,,USART1_TX,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port C pin 3" ",EVENTOUT,TIM1_CH4,,,,TIM1_BKIN2,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port C pin 2" ",EVENTOUT,TIM1_CH3,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port C pin 1" ",EVENTOUT,TIM1_CH2,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port C pin 0" ",EVENTOUT,TIM1_CH1,?..."
|
|
line.long 0x04 "GPIOC_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port C pin 15" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port C pin 14" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port C pin 13" ",EVENTOUT,,,TIM1_CH1N,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port C pin 12" ",EVENTOUT,,,,UART5_TX,SPI3_MOSI/I2S3_SD,USART3_CK,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port C pin 11" ",EVENTOUT,,,,UART4_RX,SPI3_MISO/I2S3EXT_SD,USART3_RX,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port C pin 10" ",EVENTOUT,,,,UART4_TX,SPI3_SCK/I2S3_CK,USART3_TX,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port C pin 9" ",EVENTOUT,TIM3_CH4,I2C3_SDA,,I2SCKIN,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port C pin 8" ",EVENTOUT,TIM3_CH3,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOC_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port C reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port C reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port C reset bit 13" "No effect,Reset"
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303RD"||cpu()=="STM32F303RE"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302RD"||cpu()=="STM32F302RE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD"||cpu()=="STM32F302ZD"||cpu()=="STM32F302ZE"||cpu()=="STM32F303ZD"||cpu()=="STM32F303ZE")
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port C reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port C reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port C reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port C reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port C reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port C reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port C reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port C reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port C reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port C reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port C reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port C reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port C reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpu()!="STM32F302CB"&&cpu()!="STM32F302CC"&&cpu()!="STM32F303CB"&&cpu()!="STM32F303CC"&&cpu()!="STM32F313CC")
|
|
tree "GPIO D"
|
|
base ad:0x48000C00
|
|
; sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F313RC"||cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
sif (cpu()=="STM32F313RC"||cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOD_MODER,GPIO port D mode register"
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F313RC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
endif
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D mode register"
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x04 8. " OT8 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F313RC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
endif
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F313RC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
endif
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F313RC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
endif
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 8. " IDR8 ,Port D input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F313RC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
endif
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port D output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F313RC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383RC")
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port D output data" "Low,High"
|
|
endif
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "GPIOD_LCKR,GPIO port D configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
textline " "
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 8. " LCK8 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F313RC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 2. " LCK2 ,Port D lock bit" "Not locked,Locked"
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383RC")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC")
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,,TIM8_BKIN,UART5_RX,?..."
|
|
else
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,?..."
|
|
endif
|
|
endif
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 0.--3. " AFRH8 ,Alternate function selection for port D pin 8" ",EVENTOUT,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,,USART3_TX,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,Port bit reset register"
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 8. " BR8 ,Port D reset bit 8" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F313RC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 2. " BR2 ,Port D reset bit 2" "No effect,Reset"
|
|
endif
|
|
width 0xB
|
|
else
|
|
width 22.
|
|
sif cpuis("STM32F303RD")||cpuis("STM32F302RD")||cpuis("STM32F303RE")||cpuis("STM32F302RE")
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOD_MODER,GPIO Port D mode register"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D output type register"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_ODR,GPIO port D output data register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2 ,Port D output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOD_LCKR,GPIO port D configuration lock register"
|
|
bitfld.long 0x00 2. " LCK2 ,Port D lock bit" "Not locked,Locked"
|
|
sif cpuis("STM32F302RD")||cpuis("STM32F302RE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,,,UART5_RX,?..."
|
|
elif cpuis("STM32F303RD")||cpuis("STM32F303RE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,,TIM8_BKIN,UART5_RX,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,Port bit reset register"
|
|
bitfld.long 0x00 2. " BR2 ,Port D reset bit 2" "No effect,Reset"
|
|
else
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOD_MODER,GPIO Port D mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port D configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOD_OTYPER,GPIO port D output type register"
|
|
bitfld.long 0x04 15. " OT15 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port D output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOD_OSPEEDR,GPIO port D output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port D output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOD_PUPDR,GPIO port D pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port D configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOD_IDR,GPIO port D input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port D input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port D input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port D input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOD_ODR_SET/CLR,GPIO port D output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15 ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14 ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13 ,Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12 ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11 ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10 ,Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9 ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8 ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7 ,Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6 ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5 ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4 ,Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3 ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2 ,Port D output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1 ,Port D output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0 ,Port D output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOD_LCKR,GPIO port D configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port D lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port D lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port D lock bit" "Not locked,Locked"
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D pin 7" ",EVENTOUT,TIM2_CH3,,,,,USART2_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D pin 6" ",EVENTOUT,TIM2_CH4,,,,,USART2_RX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D pin 5" ",EVENTOUT,,,,,,USART2_TX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D pin 4" ",EVENTOUT,TIM2_CH2,,,,,USART2_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D pin 3" ",EVENTOUT,TIM2_CH1_ETR,,,,,USART2_CTS,?..."
|
|
textline " "
|
|
sif (cpu()!="STM32F313VC")
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,,TIM8_BKIN,UART5_RX,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D pin 1" ",EVENTOUT,,,TIM8_CH4,,TIM8_BKIN2,CAN_TX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D pin 0" ",EVENTOUT,,,,,,CAN_RX,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D pin 15" ",EVENTOUT,TIM4_CH4,TSC_G8_IO4,,,SPI2_NSS,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D pin 14" ",EVENTOUT,TIM4_CH3,TSC_G8_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D pin 13" ",EVENTOUT,TIM4_CH2,TSC_G8_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D pin 12" ",EVENTOUT,TIM4_CH1,TSC_G8_IO1,,,,USART3_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D pin 11" ",EVENTOUT,,,,,,USART3_CTS,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D pin 10" ",EVENTOUT,,,,,,USART3_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D pin 9" ",EVENTOUT,,,,,,USART3_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D pin 8" ",EVENTOUT,,,,,,USART3_TX,?..."
|
|
elif (cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port D pin 7" ",EVENTOUT,,,,SPI2_SCK/I2S2_CK,,USART2_CK,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port D pin 6" ",EVENTOUT,,,,SPI2_NSS/I2S2_WS,,USART2_RX,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port D pin 5" ",EVENTOUT,,,,,,USART2_TX,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port D pin 4" ",EVENTOUT,,,,SPI2_MOSI/I2S2_SD,,USART2_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port D pin 3" ",EVENTOUT,,,,SPI2_MISO/I2S2_MCK,,USART2_CTS,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port D pin 1" ",EVENTOUT,TIM19_ETR,,,,,CAN_TX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port D pin 0" ",EVENTOUT,TIM19_CH4,,,,,CAN_RX,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port D pin 15" ",EVENTOUT,TIM4_CH4,TSC_G8_IO4,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port D pin 14" ",EVENTOUT,TIM4_CH3,TSC_G8_IO3,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port D pin 13" ",EVENTOUT,TIM4_CH2,TSC_G8_IO2,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port D pin 12" ",EVENTOUT,TIM4_CH1,TSC_G8_IO1,,,,USART3_RTS,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port D pin 11" ",EVENTOUT,,,,,,USART3_CTS,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port D pin 10" ",EVENTOUT,,,,,,USART3_CK,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port D pin 9" ",EVENTOUT,,TSC_G6_IO4,,,,USART3_RX,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port D pin 8" ",EVENTOUT,,TSC_G6_IO3,,SPI2_SCK/I2S2_CK,,USART3_TX,?..."
|
|
elif cpuis("STM32F302VD")||cpuis("STM32F302VE")||cpuis("STM32F302ZD")||cpuis("STM32F302ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port D pin 7" ",EVENTOUT,TIM2_CH3,,,,,USART2_CK,,,,,FMC_NE1/FMC_NCE2,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port D pin 6" ",EVENTOUT,TIM2_CH4,,,,,USART2_RX,,,,,FMC_NWAIT,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port D pin 5" ",EVENTOUT,,,,,,USART2_TX,,,,,FMC_NWE,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port D pin 4" ",EVENTOUT,TIM2_CH2,,,,,USART2_RTS,,,,,FMC_NOE,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port D pin 3" ",EVENTOUT,TIM2_CH1/TIM2_ETR,,,,,USART2_CTS,,,,,FMC_CLK,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,,,UART5_RX,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port D pin 1" ",EVENTOUT,,,,,,CAN_TX,,,,,FMC_D3,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port D pin 0" ",EVENTOUT,,,,,,CAN_RX,,,,,FMC_D2,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port D pin 15" ",EVENTOUT,TIM4_CH4,TSC_G8_IO4,,,SPI2_NSS,,,,,,FMC_D1,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port D pin 14" ",EVENTOUT,TIM4_CH3,TSC_G8_IO3,,,,,,,,,FMC_D0,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port D pin 13" ",EVENTOUT,TIM4_CH2,TSC_G8_IO2,,,,,,,,,FMC_A18,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port D pin 12" ",EVENTOUT,TIM4_CH1,TSC_G8_IO1,,,,USART3_RTS,,,,,FMC_A17,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port D pin 11" ",EVENTOUT,,,,,,USART3_CTS,,,,,FMC_A16,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port D pin 10" ",EVENTOUT,,,,,,USART3_CK,,,,,FMC_D15,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port D pin 9" ",EVENTOUT,,,,,,USART3_RX,,,,,FMC_D14,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port D pin 8" ",EVENTOUT,,,,,,USART3_TX,,,,,FMC_D13,?..."
|
|
elif cpuis("STM32F398VE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port D pin 7" ",EVENTOUT,TIM2_CH3,,,,,USART2_CK,,,,,FMC_NE1/FMC_NCE2,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port D pin 6" ",EVENTOUT,TIM2_CH4,,,,,USART2_RX,,,,,FMC_NWAIT,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port D pin 5" ",EVENTOUT,,,,,,USART2_TX,,,,,FMC_NWE,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port D pin 4" ",EVENTOUT,TIM2_CH2,,,,,USART2_RTS,,,,,FMC_NOE,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port D pin 3" ",EVENTOUT,TIM2_CH1/TIM2_ETR,,,,,USART2_CTS,,,,,FMC_CLK,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,,TIM8_BKIN,UART5_RX,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port D pin 1" ",EVENTOUT,,,TIM8_CH4,,TIM8_BKIN2,CAN_TX,,,,,FMC_D3,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port D pin 0" ",EVENTOUT,,,,,,CAN_RX,,,,,FMC_D2,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port D pin 15" ",EVENTOUT,TIM4_CH4,TSC_G8_IO4,,,SPI2_NSS,,,,,,FMC_D1,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port D pin 14" ",EVENTOUT,TIM4_CH3,TSC_G8_IO3,,,,,,,,,FMC_D0,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port D pin 13" ",EVENTOUT,TIM4_CH2,TSC_G8_IO2,,,,,,,,,FMC_A18,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port D pin 12" ",EVENTOUT,TIM4_CH1,TSC_G8_IO1,,,,USART3_RTS,,,,,FMC_A17,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port D pin 11" ",EVENTOUT,,,,,,USART3_CTS,,,,,FMC_A16,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port D pin 10" ",EVENTOUT,,,,,,USART3_CK,,,,,FMC_D15,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port D pin 9" ",EVENTOUT,,,,,,USART3_RX,,,,,FMC_D14,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port D pin 8" ",EVENTOUT,,,,,,USART3_TX,,,,,FMC_D13,?..."
|
|
elif cpuis("STM32F303VD")||cpuis("STM32F303VE")||cpuis("STM32F303ZD")||cpuis("STM32F303ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOD_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port D pin 7" ",EVENTOUT,TIM2_CH3,,,,,USART2_CK,,,,,FMC_NE1/FMC_NCE2,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port D pin 6" ",EVENTOUT,TIM2_CH4,,,,,USART2_RX,,,,,FMC_NWAIT,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port D pin 5" ",EVENTOUT,,,,,,USART2_TX,,,,,FMC_NWE,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port D pin 4" ",EVENTOUT,TIM2_CH2,,,,,USART2_RTS,,,,,FMC_NOE,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port D pin 3" ",EVENTOUT,TIM2_CH1/TIM2_ETR,,,,,USART2_CTS,,,,,FMC_CLK,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port D pin 2" ",EVENTOUT,TIM3_ETR,,TIM8_BKIN,UART5_RX,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port D pin 1" ",EVENTOUT,,,TIM8_CH4,,TIM8_BKIN2,CAN_TX,,,,,FMC_D3,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port D pin 0" ",EVENTOUT,,,,,,CAN_RX,,,,,FMC_D2,?..."
|
|
line.long 0x04 "GPIOD_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port D pin 15" ",EVENTOUT,TIM4_CH4,TSC_G8_IO4,,,SPI2_NSS,,,,,,FMC_D1,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port D pin 14" ",EVENTOUT,TIM4_CH3,TSC_G8_IO3,,,,,,,,,FMC_D0,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port D pin 13" ",EVENTOUT,TIM4_CH2,TSC_G8_IO2,,,,,,,,,FMC_A18,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port D pin 12" ",EVENTOUT,TIM4_CH1,TSC_G8_IO1,,,,USART3_RTS,,,,,FMC_A17,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port D pin 11" ",EVENTOUT,,,,,,USART3_CTS,,,,,FMC_A16,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port D pin 10" ",EVENTOUT,,,,,,USART3_CK,,,,,FMC_D15,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port D pin 9" ",EVENTOUT,,,,,,USART3_RX,,,,,FMC_D14,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port D pin 8" ",EVENTOUT,,,,,,USART3_TX,,,,,FMC_D13,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOD_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port D reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port D reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port D reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port D reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port D reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port D reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port D reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port D reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port D reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port D reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port D reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port D reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port D reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port D reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port D reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port D reset bit 0" "No effect,Reset"
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&!cpuis("STM32F318*8")&&!cpuis("STM32F303*6")&&!cpuis("STM32F303*8")&&!cpuis("STM32F328*8")&&!cpuis("STM32F334?4")&&!cpuis("STM32F334?6")&&!cpuis("STM32F334?8")&&cpu()!="STM32F313CC"&&cpu()!="STM32F313RC"&&!cpuis("STM32F303RD")&&!cpuis("STM32F302RD")&&!cpuis("STM32F303RE")&&!cpuis("STM32F302RE")
|
|
tree "GPIO E"
|
|
base ad:0x48001000
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
width 15.
|
|
group.long 0x00++0xF
|
|
line.long 0x00 "GPIOE_MODER,GPIO port E mode register"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOE_OTYPER,GPIO port E mode register"
|
|
bitfld.long 0x04 9. " OT9 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOE_OSPEEDR,GPIO port E output speed register"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOE_PUPDR,GPIO port E pull-up/pull-down register"
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "GPIOE_IDR,GPIO port E input data register"
|
|
bitfld.long 0x00 9. " IDR9 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port E input data" "Low,High"
|
|
group.long 0x14++0x3
|
|
line.long 0x00 "GPIOE_ODR,GPIO port E output data register"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9_set/clr ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8_set/clr ,Port E output data" "Low,High"
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "GPIOE_LCKR,GPIO port E configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 9. " LCK9 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LCK8 ,Port E lock bit" "Not locked,Locked"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 4.--7. " AFRH9 ,Alternate function selection for port E pin 9" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 0.--3. " AFRH8 ,Alternate function selection for port E pin 8" ",EVENTOUT,?..."
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOE_BRR,Port bit reset register"
|
|
bitfld.long 0x00 9. " BR9 ,Port E reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port E reset bit 8" "No effect,Reset"
|
|
width 0xB
|
|
else
|
|
width 22.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOE_MODER,GPIO port E mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port E configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOE_OTYPER,GPIO port E output type register"
|
|
bitfld.long 0x04 15. " OT15 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port E output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOE_OSPEEDR,GPIO port E output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port E output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOE_PUPDR,GPIO port E pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port E configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOE_IDR,GPIO port E input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port E input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port E input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port E input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOE_ODR_SET/CLR,GPIO port E output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15 ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14 ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13 ,Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12 ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11 ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10 ,Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9 ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8 ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7 ,Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6 ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5 ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4 ,Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3 ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2 ,Port E output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1 ,Port E output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0 ,Port E output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOE_LCKR,GPIO port E configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port E lock bit" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port E lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port E lock bit" "Not locked,Locked"
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" ",EVENTOUT,TIM1_ETR,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TRACED3,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,EVENTOUT,TIM3_CH4,TSC_G7_IO4,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E bit 4" "TRACED1,EVENTOUT,TIM3_CH3,TSC_G7_IO3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TRACED0,EVENTOUT,TIM3_CH2,TSC_G7_IO2,?..."
|
|
textline " "
|
|
sif (cpu()!="STM32F313VC")
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECK,EVENTOUT,TIM3_CH1,TSC_G7_IO1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" ",EVENTOUT,,,TIM17_CH1,,,USART1_RX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" ",EVENTOUT,TIM4_ETR,,TIM16_CH1,,,USART1_TX,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" ",EVENTOUT,TIM1_BKIN,,,,,USART3_RX,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" ",EVENTOUT,TIM1_CH4,,,,TIM1_BKIN2,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" ",EVENTOUT,TIM1_CH3,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" ",EVENTOUT,TIM1_CH3N,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" ",EVENTOUT,TIM1_CH2,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" ",EVENTOUT,TIM1_CH2N,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" ",EVENTOUT,TIM1_CH1,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" ",EVENTOUT,TIM1_CH1N,?..."
|
|
elif (cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port E bit 7" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port E bit 6" "TRACED3,EVENTOUT,?..."
|
|
bitfld.long 0x00 20.--23. " AFRL5 ,Alternate function selection for port E bit 5" "TRACED2,EVENTOUT,,TSC_G7_IO4,?..."
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port E bit 4" "TRACED1,EVENTOUT,,TSC_G7_IO3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFRL3 ,Alternate function selection for port E bit 3" "TRACED0,EVENTOUT,,TSC_G7_IO2,?..."
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port E bit 2" "TRACECLK,EVENTOUT,,TSC_G7_IO1,?..."
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port E bit 1" ",EVENTOUT,,,,,,USART1_RX,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port E bit 0" ",EVENTOUT,TIM4_ETR,,,,,USART1_TX,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFRH15 ,Alternate function selection for port E bit 15" ",EVENTOUT,,,,,,USART3_RX,?..."
|
|
bitfld.long 0x04 24.--27. " AFRH14 ,Alternate function selection for port E bit 14" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 20.--23. " AFRH13 ,Alternate function selection for port E bit 13" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 16.--19. " AFRH12 ,Alternate function selection for port E bit 12" ",EVENTOUT,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFRH11 ,Alternate function selection for port E bit 11" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFRH10 ,Alternate function selection for port E bit 10" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 4.--7. " AFRH9 ,Alternate function selection for port E bit 9" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 0.--3. " AFRH8 ,Alternate function selection for port E bit 8" ",EVENTOUT,?..."
|
|
elif cpuis("STM32F302VD")||cpuis("STM32F302VE")||cpuis("STM32F302ZD")||cpuis("STM32F302ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port E pin 7" ",EVENTOUT,TIM1_ETR,,,,,,,,,,FMC_D4,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port E pin 6" "TRACED3,EVENTOUT,,,,SPI4_MOSI,,,,,,,FMC_A22,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port E pin 5" "TRACED2,EVENTOUT,TIM3_CH4,TSC_G7_IO4,,SPI4_MISO,,,,,,,FMC_A21,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port E pin 4" "TRACED1,EVENTOUT,TIM3_CH3,TSC_G7_IO3,,SPI4_NSS,,,,,,,FMC_A20,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port E pin 3" "TRACED0,EVENTOUT,TIM3_CH2,TSC_G7_IO2,,SPI4_NSS,,,,,,,FMC_A19,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port E pin 2" "TRACECK,EVENTOUT,TIM3_CH1,TSC_G7_IO1,,SPI4_SCK,,,,,,,FMC_A23,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port E pin 1" ",EVENTOUT,,,TIM17_CH1,,,USART1_RX,,,,,FMC_NBL1,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port E pin 0" ",EVENTOUT,TIM4_ETR,,TIM16_CH1,,,USART1_TX,,,,,FMC_NBL0,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port E pin 15" ",EVENTOUT,TIM1_BKIN,,,,,USART3_RX,,,,,FMC_D12,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port E pin 14" ",EVENTOUT,TIM1_CH4,,,SPI4_MOSI,TIM1_BKIN2,,,,,,FMC_D11,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port E pin 13" ",EVENTOUT,TIM1_CH3,,,SPI4_MISO,,,,,,,FMC_D10,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port E pin 12" ",EVENTOUT,TIM1_CH3N,,,SPI4_SCK,,,,,,,FMC_D9,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port E pin 11" ",EVENTOUT,TIM1_CH2,,,SPI4_NSS,,,,,,,FMC_D8,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port E pin 10" ",EVENTOUT,TIM1_CH2N,,,,,,,,,,FMC_D7,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port E pin 9" ",EVENTOUT,TIM1_CH1,,,,,,,,,,FMC_D6,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port E pin 8" ",EVENTOUT,TIM1_CH1N,,,,,,,,,,FMC_D5,?..."
|
|
elif cpuis("STM32F303VD")||cpuis("STM32F303VE")||cpuis("STM32F303ZD")||cpuis("STM32F303ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port E pin 7" ",EVENTOUT,TIM1_ETR,,,,,,,,,,FMC_D4,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port E pin 6" "TRACED3,EVENTOUT,,,,SPI4_MOSI,TIM20_CH3N,,,,,,FMC_A22,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port E pin 5" "TRACED2,EVENTOUT,TIM3_CH4,TSC_G7_IO4,,SPI4_MISO,TIM20_CH2N,,,,,,FMC_A21,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port E pin 4" "TRACED1,EVENTOUT,TIM3_CH3,TSC_G7_IO3,,SPI4_NSS,TIM20_CH1N,,,,,,FMC_A20,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port E pin 3" "TRACED0,EVENTOUT,TIM3_CH2,TSC_G7_IO2,,SPI4_NSS,TIM20_CH2,,,,,,FMC_A19,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port E pin 2" "TRACECK,EVENTOUT,TIM3_CH1,TSC_G7_IO1,,SPI4_SCK,TIM20_CH1,,,,,,FMC_A23,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port E pin 1" ",EVENTOUT,,,TIM17_CH1,,TIM20_CH4,USART1_RX,,,,,FMC_NBL1,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port E pin 0" ",EVENTOUT,TIM4_ETR,,TIM16_CH1,,TIM20_ETR,USART1_TX,,,,,FMC_NBL0,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port E pin 15" ",EVENTOUT,TIM1_BKIN,,,,,,USART3_RX,,,,,FMC_D12,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port E pin 14" ",EVENTOUT,TIM1_CH4,,,SPI4_MOSI,TIM1_BKIN2,,,,,,FMC_D11,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port E pin 13" ",EVENTOUT,TIM1_CH3,,,SPI4_MISO,,,,,,,FMC_D10,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port E pin 12" ",EVENTOUT,TIM1_CH3N,,,SPI4_SCK,,,,,,,FMC_D9,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port E pin 11" ",EVENTOUT,TIM1_CH2,,,SPI4_NSS,,,,,,,FMC_D8,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port E pin 10" ",EVENTOUT,TIM1_CH2N,,,,,,,,,,FMC_D7,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port E pin 9" ",EVENTOUT,TIM1_CH1,,,,,,,,,,FMC_D6,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port E pin 8" ",EVENTOUT,TIM1_CH1N,,,,,,,,,,FMC_D5,?..."
|
|
elif cpuis("STM32F398VE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOE_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port E pin 7" ",EVENTOUT,TIM1_ETR,,,,,,,,,,FMC_D4,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port E pin 6" "TRACED3,EVENTOUT,,,,SPI4_MOSI,TIM20_CH3N,,,,,,FMC_A22,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port E pin 5" "TRACED2,EVENTOUT,TIM3_CH4,TSC_G7_IO4,,SPI4_MISO,TIM20_CH2N,,,,,,FMC_A21,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port E pin 4" "TRACED1,EVENTOUT,TIM3_CH3,TSC_G7_IO3,,SPI4_NSS,TIM20_CH1N,,,,,,FMC_A20,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port E pin 3" "TRACED0,EVENTOUT,TIM3_CH2,TSC_G7_IO2,,SPI4_NSS,TIM20_CH2,,,,,,FMC_A19,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port E pin 2" "TRACECK,EVENTOUT,TIM3_CH1,TSC_G7_IO1,,SPI4_SCK,TIM20_CH1,,,,,,FMC_A23,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port E pin 1" ",EVENTOUT,,,TIM17_CH1,,TIM20_CH4,USART1_RX,,,,,FMC_NBL1,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port E pin 0" ",EVENTOUT,TIM4_ETR,,TIM16_CH1,,TIM20_ETR,USART1_TX,,,,,FMC_NBL0,?..."
|
|
line.long 0x04 "GPIOE_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port E pin 15" ",EVENTOUT,TIM1_BKIN,,,,,USART3_RX,,,,,FMC_D12,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port E pin 14" ",EVENTOUT,TIM1_CH4,,,SPI4_MOSI,TIM1_BKIN2,,,,,,FMC_D11,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port E pin 13" ",EVENTOUT,TIM1_CH3,,,SPI4_MISO,,,,,,,FMC_D10,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port E pin 12" ",EVENTOUT,TIM1_CH3N,,,SPI4_SCK,,,,,,,FMC_D9,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port E pin 11" ",EVENTOUT,TIM1_CH2,,,SPI4_NSS,,,,,,,FMC_D8,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port E pin 10" ",EVENTOUT,TIM1_CH2N,,,,,,,,,,FMC_D7,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port E pin 9" ",EVENTOUT,TIM1_CH1,,,,,,,,,,FMC_D6,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port E pin 8" ",EVENTOUT,TIM1_CH1N,,,,,,,,,,FMC_D5,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOE_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port E reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port E reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port E reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port E reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port E reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port E reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port E reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port E reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port E reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port E reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port E reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port E reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port E reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port E reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port E reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port E reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "GPIO F"
|
|
base ad:0x48001400
|
|
sif (cpu()!="STM32F303ZE"&&cpu()!="STM32F303ZD"&&cpu()!="STM32F302ZE"&&cpu()!="STM32F302ZD")
|
|
width 22.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F303RE")&&!cpuis("STM32F303RD")&&!cpuis("STM32F302RD")&&!cpuis("STM32F302RE")&&!cpuis("STM32F302RE")&&!cpuis("STM32F302VE")&&!cpuis("STM32F302VD")&&!cpuis("STM32F303VE")&&!cpuis("STM32F303VD")&&cpuis("STM32F302V?")&&!cpuis("STM32F303V?")&&!cpuis("STM32F398VE")
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F output type register"
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x04 10. " OT10 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 9. " OT9 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x04 7. " OT7 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x04 4. " OT4 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x04 2. " OT2 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x00 10. " IDR10 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 9. " IDR9 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 7. " IDR7 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 4. " IDR4 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x00 2. " IDR2 ,Port F input data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR_SET/CLR,GPIO port F output data register"
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10 ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9 ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7 ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6 ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4 ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2 ,Port F output data" "Low,High"
|
|
textline " "
|
|
endif
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1 ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0 ,Port F output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
textline " "
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x00 10. " LCK10 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 7. " LCK7 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x00 6. " LCK6 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 4. " LCK4 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x00 2. " LCK2 ,Port F lock bit" "Not locked,Locked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit" "Not locked,Locked"
|
|
sif ((cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" ",EVENTOUT,TIM4_CH4,,I2C2_SCL,,,USART3_RTS,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port F bit 4" ",EVENTOUT,COMP1_OUT,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC")
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" ",EVENTOUT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" ",,,,I2C2_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" ",,,,I2C2_SDA,,TIM1_CH3N,?..."
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" ",EVENTOUT,,TIM15_CH2,,SPI2_SCK,?..."
|
|
bitfld.long 0x00 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" ",EVENTOUT,,TIM15_CH1,,SPI2_SCK,?..."
|
|
endif
|
|
elif cpuis("STM32F303VD")||cpuis("STM32F303VE")||cpuis("STM32F303RE")||cpuis("STM32F303RD")||cpuis("STM32F303VB")||cpuis("STM32F303VC")||cpuis("STM32F303RB")||cpuis("STM32F303RC")||cpuis("STM32F302VD")||cpuis("STM32F3032E")||cpuis("STM32F302RE")||cpuis("STM32F302RD")||cpuis("STM32F302VB")||cpuis("STM32F3032C")||cpuis("STM32F302RB")||cpuis("STM32F302RC")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
sif !cpuis("STM32F303RD")&&!cpuis("STM32F303RE")&&!cpuis("STM32F303RB")&&!cpuis("STM32F303RC")&&!cpuis("STM32F302RD")&&!cpuis("STM32F302RE")&&!cpuis("STM32F302RB")&&!cpuis("STM32F302RC")
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port F pin 6" ",EVENTOUT,TIM4_CH4,,I2C2_SCL,,,USART3_RTS,,,,,FMC_NIORD,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port F pin 2" ",EVENTOUT,TIM20_CH3,,,,,,,,,,FMC_A2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port F pin 1" ",EVENTOUT,,,I2C2_SCL,SPI2_SCK/I2S2_CK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port F pin 0" ",EVENTOUT,,,I2C2_SDA,SPI2_NSS/I2S2_WS,TIM1_CH3N,?..."
|
|
sif !cpuis("STM32F303RE")&&!cpuis("STM32F303RD")&&!cpuis("STM32F303RB")&&!cpuis("STM32F303RC")&&!cpuis("STM32F302RE")&&!cpuis("STM32F302RD")&&!cpuis("STM32F302RB")&&!cpuis("STM32F302RC")
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port F pin 10" ",EVENTOUT,TIM20_BKIN2,TIM15_CH2,,SPI2_SCK,,,,,,,FMC_INTR,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port F pin 9" ",EVENTOUT,TIM20_BKIN,TIM15_CH1,,SPI2_SCK,,,,,,,FMC_CD,?..."
|
|
endif
|
|
elif cpuis("STM32F398VE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port F pin 6" ",EVENTOUT,TIM4_CH4,,I2C2_SCL,,,USART3_RTS,,,,,FMC_NIORD,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port F pin 2" ",EVENTOUT,TIM20_CH3,,,,,,,,,,FMC_A2,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port F pin 1" ",EVENTOUT,,,I2C2_SCL,SPI2_SCK/I2S2_CK,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port F pin 0" ",EVENTOUT,,,I2C2_SDA,SPI2_NSS/I2S2_WS,TIM1_CH3N,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port F pin 10" ",EVENTOUT,TIM20_BKIN2,TIM15_CH2,,SPI2_SCK,,,,,,,FMC_INTR,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port F pin 9" ",EVENTOUT,TIM20_BKIN,TIM15_CH1,,SPI2_SCK,,,,,,,FMC_CD,?..."
|
|
elif cpuis("STM32F302VD")||cpuis("STM32F302VE")||cpuis("STM32F302RE")||cpuis("STM32F302RD")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
sif !cpuis("STM32F302RE")&&!cpuis("STM32F302RD")
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port F pin 6" ",EVENTOUT,TIM4_CH4,,I2C2_SCL,,,USART3_RTS,,,,,FMC_NIORD,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port F pin 2" ",EVENTOUT,,,,,,,,,,,FMC_A2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port F pin 1" ",EVENTOUT,,,I2C2_SCL,SPI2_SCK/I2S2_CK,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port F pin 0" ",EVENTOUT,,,I2C2_SDA,SPI2_NSS/I2S2_WS,TIM1_CH3N,?..."
|
|
sif !cpuis("STM32F302RE")&&!cpuis("STM32F302RD")
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port F pin 10" ",EVENTOUT,,TIM15_CH2,,SPI2_SCK,,,,,,,FMC_INTR,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port F pin 9" ",EVENTOUT,,TIM15_CH1,,SPI2_SCK,,,,,,,FMC_CD,?..."
|
|
endif
|
|
elif ((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC"))
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 28.--31. " AFRL7 ,Alternate function selection for port F bit 7" ",EVENTOUT,,,I2C2_SDA,,,USART2_CK,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 24.--27. " AFRL6 ,Alternate function selection for port F bit 6" ",EVENTOUT,TIM4_CH4,,I2C2_SCL,SPI1_MOSI/I2S1_SD,,USART3_RTS,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 16.--19. " AFRL4 ,Alternate function selection for port F bit 4" ",EVENTOUT,?..."
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 8.--11. " AFRL2 ,Alternate function selection for port F bit 2" ",EVENTOUT,,,I2C2_SMBAI,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " AFRL1 ,Alternate function selection for port F bit 1" ",,,,I2C2_SCL,?..."
|
|
bitfld.long 0x00 0.--3. " AFRL0 ,Alternate function selection for port F bit 0" ",,,,I2C2_SDA,?..."
|
|
sif (cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x00 8.--11. " AFRH10 ,Alternate function selection for port F bit 10" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFRH9 ,Alternate function selection for port F bit 9" ",EVENTOUT,TIM14_CH1,?..."
|
|
endif
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,Port bit reset register"
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x00 10. " BR10 ,Port F reset bit 10" "No effect,Reset"
|
|
bitfld.long 0x00 9. " BR9 ,Port F reset bit 9" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 7. " BR7 ,Port F reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 4. " BR4 ,Port F reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC"||cpu()=="STM32F372V8"||cpu()=="STM32F372VB"||cpu()=="STM32F372VC"||cpu()=="STM32F373V8"||cpu()=="STM32F373VB"||cpu()=="STM32F373VC"||cpu()=="STM32F383VC"||cpu()=="STM32F303VE"||cpu()=="STM32F303VD"||cpu()=="STM32F398VE"||cpu()=="STM32F302VE"||cpu()=="STM32F302VD")
|
|
bitfld.long 0x00 2. " BR2 ,Port F reset bit 2" "No effect,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
else
|
|
width 22.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOF_MODER,GPIO port F mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port F configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOF_OTYPER,GPIO port F output type register"
|
|
bitfld.long 0x04 15. " OT15 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port F output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOF_OSPEEDR,GPIO port F output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port F output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOF_PUPDR,GPIO port F pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port F configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOF_IDR,GPIO port F input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port F input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port F input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port F input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOF_ODR_SET/CLR,GPIO port F output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15 ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14 ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13 ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12 ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11 ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10 ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9 ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8 ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7 ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6 ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5 ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4 ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3 ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2 ,Port F output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1 ,Port F output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0 ,Port F output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOF_LCKR,GPIO port F configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port F lock bit 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port F lock bit 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port F lock bit 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port F lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port F lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port F lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port F lock bit 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port F lock bit 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port F lock bit 7" "Not locked,Locked"
|
|
bitfld.long 0x00 6. " LCK6 ,Port F lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port F lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port F lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port F lock bit 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port F lock bit 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port F lock bit 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port F lock bit 0" "Not locked,Locked"
|
|
sif cpuis("STM32F303ZD")||cpuis("STM32F303ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port F pin 7" ",EVENTOUT,TIM20_BKIN,,,,,,,,,,FMC_NREG,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port F pin 6" ",EVENTOUT,TIM4_CH4,,I2C2_SCL,,,USART3_RTS,,,,,FMC_NIORD,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port F pin 5" ",EVENTOUT,TIM20_CH2N,,,,,,,,,,FMC_A5,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port F pin 4" ",EVENTOUT,COMP1_OUT,TIM20_CH1N,,,,,,,,,FMC_A4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port F pin 3" ",EVENTOUT,TIM20_CH4,,,,,,,,,,FMC_A3,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port F pin 2" ",EVENTOUT,TIM20_CH3,,,,,,,,,,FMC_A2,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port F pin 1" ",EVENTOUT,,,I2C2_SCL,SPI2_SCK/I2S2_CK,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port F pin 0" ",EVENTOUT,,,I2C2_SDA,SPI2_NSS/I2S2_WS,TIM1_CH3N,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port F pin 15" ",EVENTOUT,TIM20_CH4,,,,,,,,,,FMC_A9,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port F pin 14" ",EVENTOUT,TIM20_CH3,,,,,,,,,,FMC_A8,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port F pin 13" ",EVENTOUT,TIM20_CH2,,,,,,,,,,FMC_A7,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port F pin 12" ",EVENTOUT,TIM20_CH1,,,,,,,,,,FMC_A6,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port F pin 11" ",EVENTOUT,TIM20_ETR,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port F pin 10" ",EVENTOUT,TIM20_BKIN2,TIM15_CH2,,SPI2_SCK,,,,,,,FMC_INTR,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port F pin 9" ",EVENTOUT,TIM20_BKIN,TIM15_CH1,,SPI2_SCK,,,,,,,FMC_CD,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port F pin 8" ",EVENTOUT,TIM20_BKIN2,,,,,,,,,,FMC_NIOWR,?..."
|
|
elif cpuis("STM32F302ZE")||cpuis("STM32F302ZD")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOF_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port F pin 7" ",EVENTOUT,,,,,,,,,,,FMC_NREG,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port F pin 6" ",EVENTOUT,TIM4_CH4,,I2C2_SCL,,,USART3_RTS,,,,,FMC_NIORD,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port F pin 5" ",EVENTOUT,,,,,,,,,,,FMC_A5,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port F pin 4" ",EVENTOUT,COMP1_OUT,,,,,,,,,,FMC_A4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port F pin 3" ",EVENTOUT,,,,,,,,,,,FMC_A3,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port F pin 2" ",EVENTOUT,,,,,,,,,,,FMC_A2,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port F pin 1" ",EVENTOUT,,,I2C2_SCL,SPI2_SCK/I2S2_CK,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port F pin 0" ",EVENTOUT,,,I2C2_SDA,SPI2_NSS/I2S2_WS,TIM1_CH3N,?..."
|
|
line.long 0x04 "GPIOF_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port F pin 15" ",EVENTOUT,,,,,,,,,,,FMC_A9,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port F pin 14" ",EVENTOUT,,,,,,,,,,,FMC_A8,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port F pin 13" ",EVENTOUT,,,,,,,,,,,FMC_A7,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port F pin 12" ",EVENTOUT,,,,,,,,,,,FMC_A6,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port F pin 11" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port F pin 10" ",EVENTOUT,,TIM15_CH2,,SPI2_SCK,,,,,,,FMC_INTR,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port F pin 9" ",EVENTOUT,,TIM15_CH1,,SPI2_SCK,,,,,,,FMC_CD,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port F pin 8" ",EVENTOUT,,,,,,,,,,,FMC_NIOWR,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOF_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port F reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port F reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port F reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port F reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port F reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port F reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port F reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port F reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port F reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port F reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port F reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port F reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port F reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port F reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port F reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port F reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="STM32F303ZE"||cpu()=="STM32F303ZD"||cpu()=="STM32F302ZE"||cpu()=="STM32F302ZD")
|
|
tree "GPIO G"
|
|
base ad:0x48001800
|
|
width 22.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOG_MODER,GPIO port G mode register"
|
|
bitfld.long 0x00 30.--31. " MODER15 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 28.--29. " MODER14 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 26.--27. " MODER13 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " MODER12 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 22.--23. " MODER11 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 20.--21. " MODER10 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 18.--19. " MODER9 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 16.--17. " MODER8 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 14.--15. " MODER7 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " MODER6 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 10.--11. " MODER5 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 8.--9. " MODER4 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " MODER3 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port G configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOG_OTYPER,GPIO port G output type register"
|
|
bitfld.long 0x04 15. " OT15 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 14. " OT14 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 13. " OT13 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 12. " OT12 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 11. " OT11 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 10. " OT10 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 9. " OT9 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 8. " OT8 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 7. " OT7 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 6. " OT6 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 5. " OT5 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 4. " OT4 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 3. " OT3 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 2. " OT2 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
textline " "
|
|
bitfld.long 0x04 0. " OT0 ,Port G output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOG_OSPEEDR,GPIO port G output speed register"
|
|
bitfld.long 0x08 30.--31. " OSPEEDR15 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 28.--29. " OSPEEDR14 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 26.--27. " OSPEEDR13 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 24.--25. " OSPEEDR12 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 22.--23. " OSPEEDR11 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 20.--21. " OSPEEDR10 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 18.--19. " OSPEEDR9 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 16.--17. " OSPEEDR8 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 14.--15. " OSPEEDR7 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 12.--13. " OSPEEDR6 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 10.--11. " OSPEEDR5 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 8.--9. " OSPEEDR4 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 6.--7. " OSPEEDR3 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
textline " "
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port G output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOG_PUPDR,GPIO port G pull-up/pull-down register"
|
|
bitfld.long 0x0C 30.--31. " PUPDR15 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 28.--29. " PUPDR14 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 26.--27. " PUPDR13 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 24.--25. " PUPDR12 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 22.--23. " PUPDR11 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 20.--21. " PUPDR10 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 18.--19. " PUPDR9 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 16.--17. " PUPDR8 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 14.--15. " PUPDR7 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 12.--13. " PUPDR6 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 10.--11. " PUPDR5 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 8.--9. " PUPDR4 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 6.--7. " PUPDR3 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port G configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOG_IDR,GPIO port G input data register"
|
|
bitfld.long 0x00 15. " IDR15 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 14. " IDR14 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 13. " IDR13 ,Port G input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IDR12 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 11. " IDR11 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 10. " IDR10 ,Port G input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " IDR9 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 8. " IDR8 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 7. " IDR7 ,Port G input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " IDR6 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 5. " IDR5 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 4. " IDR4 ,Port G input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 3. " IDR3 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 2. " IDR2 ,Port G input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port G input data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " IDR0 ,Port G input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOG_ODR_SET/CLR,GPIO port G output data register"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x04 31. " ODR15 ,Port G output data" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x04 30. " ODR14 ,Port G output data" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x04 29. " ODR13 ,Port G output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 12. 0x04 12. 0x04 28. " ODR12 ,Port G output data" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x04 27. " ODR11 ,Port G output data" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x04 26. " ODR10 ,Port G output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x04 9. 0x04 25. " ODR9 ,Port G output data" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x04 24. " ODR8 ,Port G output data" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x04 23. " ODR7 ,Port G output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 6. 0x04 6. 0x04 22. " ODR6 ,Port G output data" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x04 21. " ODR5 ,Port G output data" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x04 20. " ODR4 ,Port G output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x04 3. 0x04 19. " ODR3 ,Port G output data" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2 ,Port G output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1 ,Port G output data" "Low,High"
|
|
textline " "
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0 ,Port G output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOG_LCKR,GPIO port G configuration lock register"
|
|
bitfld.long 0x00 16. " LCKK ,Lock key" "Not active,Active"
|
|
bitfld.long 0x00 15. " LCK15 ,Port G lock bit 15" "Not locked,Locked"
|
|
bitfld.long 0x00 14. " LCK14 ,Port G lock bit 14" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 13. " LCK13 ,Port G lock bit 13" "Not locked,Locked"
|
|
bitfld.long 0x00 12. " LCK12 ,Port G lock bit 12" "Not locked,Locked"
|
|
bitfld.long 0x00 11. " LCK11 ,Port G lock bit 11" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 10. " LCK10 ,Port G lock bit 10" "Not locked,Locked"
|
|
bitfld.long 0x00 9. " LCK9 ,Port G lock bit 9" "Not locked,Locked"
|
|
bitfld.long 0x00 8. " LCK8 ,Port G lock bit 8" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " LCK7 ,Port G lock bit 7" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LCK6 ,Port G lock bit 6" "Not locked,Locked"
|
|
bitfld.long 0x00 5. " LCK5 ,Port G lock bit 5" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 4. " LCK4 ,Port G lock bit 4" "Not locked,Locked"
|
|
bitfld.long 0x00 3. " LCK3 ,Port G lock bit 3" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " LCK2 ,Port G lock bit 2" "Not locked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 1. " LCK1 ,Port G lock bit 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port G lock bit 0" "Not locked,Locked"
|
|
sif cpuis("STM32F303ZD")||cpuis("STM32F303ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOG_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port G pin 7" ",EVENTOUT,,,,,,,,,,,FMC_INT3,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port G pin 6" ",EVENTOUT,,,,,,,,,,,FMC_INT2,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port G pin 5" ",EVENTOUT,TIM20_ETR,,,,,,,,,,FMC_A15,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port G pin 4" ",EVENTOUT,TIM20_BKIN2,,,,,,,,,,FMC_A14,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port G pin 3" ",EVENTOUT,TIM20_BKIN,,,,,,,,,,FMC_A13,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port G pin 2" ",EVENTOUT,TIM20_CH3N,,,,,,,,,,FMC_A12,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port G pin 1" ",EVENTOUT,TIM20_CH2N,,,,,,,,,,FMC_A11,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port G pin 0" ",EVENTOUT,TIM20_CH1N,,,,,,,,,,FMC_A10,?..."
|
|
line.long 0x04 "GPIOG_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port G pin 15" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port G pin 14" ",EVENTOUT,,,,,,,,,,,FMC_A25,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port G pin 13" ",EVENTOUT,,,,,,,,,,,FMC_A24,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port G pin 12" ",EVENTOUT,,,,,,,,,,,FMC_NE4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port G pin 11" ",EVENTOUT,,,,,,,,,,,FMC_NCE4_2,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port G pin 10" ",EVENTOUT,,,,,,,,,,,FMC_NCE4_1/FMC_NE3,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port G pin 9" ",EVENTOUT,,,,,,,,,,,FMC_NE2/FMC_NCE3,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port G pin 8" ",EVENTOUT,?..."
|
|
elif cpuis("STM32F302ZD")||cpuis("STM32F3032E")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOG_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 28.--31. " AFR7 ,Alternate function selection for port G pin 7" "EVENTOUT,,,,,,,,,,,,FMC_AINT3,?..."
|
|
bitfld.long 0x00 24.--27. " AFR6 ,Alternate function selection for port G pin 6" "EVENTOUT,,,,,,,,,,,,FMC_AINT2,?..."
|
|
bitfld.long 0x00 20.--23. " AFR5 ,Alternate function selection for port G pin 5" "EVENTOUT,,,,,,,,,,,,FMC_A15,?..."
|
|
bitfld.long 0x00 16.--19. " AFR4 ,Alternate function selection for port G pin 4" "EVENTOUT,,,,,,,,,,,,FMC_A14,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " AFR3 ,Alternate function selection for port G pin 3" "EVENTOUT,,,,,,,,,,,,FMC_A13,?..."
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port G pin 2" ",EVENTOUT,,,,,,,,,,,FMC_A12,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port G pin 1" ",EVENTOUT,,,,,,,,,,,FMC_A11,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port G pin 0" ",EVENTOUT,,,,,,,,,,,FMC_A10,?..."
|
|
line.long 0x04 "GPIOG_AFRH,GPIO alternate function high register"
|
|
bitfld.long 0x04 28.--31. " AFR15 ,Alternate function selection for port G pin 15" ",EVENTOUT,?..."
|
|
bitfld.long 0x04 24.--27. " AFR14 ,Alternate function selection for port G pin 14" ",EVENTOUT,,,,,,,,,,,FMC_A25,?..."
|
|
bitfld.long 0x04 20.--23. " AFR13 ,Alternate function selection for port G pin 13" ",EVENTOUT,,,,,,,,,,,FMC_A24,?..."
|
|
bitfld.long 0x04 16.--19. " AFR12 ,Alternate function selection for port G pin 12" ",EVENTOUT,,,,,,,,,,,FMC_NE4,?..."
|
|
textline " "
|
|
bitfld.long 0x04 12.--15. " AFR11 ,Alternate function selection for port G pin 11" ",EVENTOUT,,,,,,,,,,,FMC_NCE4_2,?..."
|
|
bitfld.long 0x04 8.--11. " AFR10 ,Alternate function selection for port G pin 10" ",EVENTOUT,,,,,,,,,,,FMC_NCE4_1/FMC_NE3,?..."
|
|
bitfld.long 0x04 4.--7. " AFR9 ,Alternate function selection for port G pin 9" ",EVENTOUT,,,,,,,,,,,FMC_NE2/FMC_NCE3,?..."
|
|
bitfld.long 0x04 0.--3. " AFR8 ,Alternate function selection for port G pin 8" ",EVENTOUT,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOG_BRR,Port bit reset register"
|
|
bitfld.long 0x00 15. " BR15 ,Port G reset bit 15" "No effect,Reset"
|
|
bitfld.long 0x00 14. " BR14 ,Port G reset bit 14" "No effect,Reset"
|
|
bitfld.long 0x00 13. " BR13 ,Port G reset bit 13" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BR12 ,Port G reset bit 12" "No effect,Reset"
|
|
bitfld.long 0x00 11. " BR11 ,Port G reset bit 11" "No effect,Reset"
|
|
bitfld.long 0x00 10. " BR10 ,Port G reset bit 10" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 9. " BR9 ,Port G reset bit 9" "No effect,Reset"
|
|
bitfld.long 0x00 8. " BR8 ,Port G reset bit 8" "No effect,Reset"
|
|
bitfld.long 0x00 7. " BR7 ,Port G reset bit 7" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BR6 ,Port G reset bit 6" "No effect,Reset"
|
|
bitfld.long 0x00 5. " BR5 ,Port G reset bit 5" "No effect,Reset"
|
|
bitfld.long 0x00 4. " BR4 ,Port G reset bit 4" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BR3 ,Port G reset bit 3" "No effect,Reset"
|
|
bitfld.long 0x00 2. " BR2 ,Port G reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port G reset bit 1" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 0. " BR0 ,Port G reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPIO H"
|
|
base ad:0x48001C00
|
|
width 18.
|
|
group.long 0x00++0x0F
|
|
line.long 0x00 "GPIOH_MODER,GPIO port H mode register"
|
|
bitfld.long 0x00 4.--5. " MODER2 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 2.--3. " MODER1 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
bitfld.long 0x00 0.--1. " MODER0 ,Port H configuration bits" "Input,Output,Alternate function,Analog"
|
|
line.long 0x04 "GPIOH_OTYPER,GPIO port H output type register"
|
|
bitfld.long 0x04 2. " OT2 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 1. " OT1 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
bitfld.long 0x04 0. " OT0 ,Port H output configuration bits" "Push-pull,Open-drain"
|
|
line.long 0x08 "GPIOH_OSPEEDR,GPIO port H output speed register"
|
|
bitfld.long 0x08 4.--5. " OSPEEDR2 ,GPIO port H output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 2.--3. " OSPEEDR1 ,GPIO port H output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
bitfld.long 0x08 0.--1. " OSPEEDR0 ,GPIO port H output speed register" "2-MHz,2-MHz,10-MHz,50-MHz"
|
|
line.long 0x0C "GPIOH_PUPDR,GPIO port H pull-up/pull-down register"
|
|
bitfld.long 0x0C 4.--5. " PUPDR2 ,Port H configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 2.--3. " PUPDR1 ,Port H configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
bitfld.long 0x0C 0.--1. " PUPDR0 ,Port H configuration bits" "No pull-up\pull-down,Pull-up,Pull-down,?..."
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "GPIOH_IDR,GPIO port H input data register"
|
|
bitfld.long 0x00 2. " IDR2 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 1. " IDR1 ,Port H input data" "Low,High"
|
|
bitfld.long 0x00 0. " IDR0 ,Port H input data" "Low,High"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "GPIOH_ODR,GPIO port H output data register"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x04 18. " ODR2_set/clr ,Port H output data" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x04 17. " ODR1_set/clr ,Port H output data" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x04 16. " ODR0_set/clr ,Port H output data" "Low,High"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "GPIOH_LCKR,GPIO port H configuration lock register"
|
|
bitfld.long 0x00 2. " LCK2 ,Port H lock bit 2" "Not locked,Locked"
|
|
bitfld.long 0x00 1. " LCK1 ,Port H lock bit 1" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LCK0 ,Port H lock bit 0" "Not locked,Locked"
|
|
sif cpuis("STM32F303ZD")||cpuis("STM32F303ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOH_AFRL,GPIO alternate function low register"
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port H pin 2" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port H pin 1" ",EVENTOUT,TIM20_CH2,,,,,,,,,,FMC_A1,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port H pin 0" ",EVENTOUT,TIM20_CH1,,,,,,,,,,FMC_A0,?..."
|
|
elif cpuis("STM32F302ZD")||cpuis("STM32F302ZE")
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "GPIOH_AFRL,GPIO alternate function high register"
|
|
bitfld.long 0x00 8.--11. " AFR2 ,Alternate function selection for port H pin 2" ",EVENTOUT,?..."
|
|
bitfld.long 0x00 4.--7. " AFR1 ,Alternate function selection for port H pin 1" ",EVENTOUT,,,,,,,,,,,FMC_A1,?..."
|
|
bitfld.long 0x00 0.--3. " AFR0 ,Alternate function selection for port H pin 0" ",EVENTOUT,,,,,,,,,,,FMC_A0,?..."
|
|
endif
|
|
wgroup.long 0x28++0x03
|
|
line.long 0x00 "GPIOH_BRR,Port bit reset register"
|
|
bitfld.long 0x00 2. " BR2 ,Port H reset bit 2" "No effect,Reset"
|
|
bitfld.long 0x00 1. " BR1 ,Port H reset bit 1" "No effect,Reset"
|
|
bitfld.long 0x00 0. " BR0 ,Port H reset bit 0" "No effect,Reset"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&!cpuis("STM32F302*6")&&!cpuis("STM32F302*8")&&!cpuis("STM32F303*6")&&!cpuis("STM32F303*8")&&cpu()!="STM32F328C8"&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"&&!cpuis("STM32F334*4")&&!cpuis("STM32F334*6")&&!cpuis("STM32F334*8")&&(cpu()!="STM32F358CC")&&(cpu()!="STM32F358RC")&&(cpu()!="STM32F358VC")&&(cpu()!="STM32F378CC")&&(cpu()!="STM32F378RC")&&(cpu()!="STM32F378VC")
|
|
tree "SYSCFG (System configuration controller)"
|
|
base ad:0x40010000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SYSCFG_CFGR1,SYSCFG configuration register 1"
|
|
bitfld.long 0x00 31. " FPU_IE[5] ,Inexact interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FPU_IE[4] ,Input denormal interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FPU_IE[3] ,Overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FPU_IE[2] ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " FPU_IE[1] ,Divide-by-zero interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FPU_IE[0] ,Invalid operation interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 24. " VBAT_MON ,VBAT monitoring enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 24. " I2C3_FMP ,I2C3 fast mode plus driving capability activation" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
bitfld.long 0x00 22.--23. " ENCODER_MODE ,Encoder mode" "No redirection,TIM2/TIM15,TIM3/TIM15,TIM4/TIM15"
|
|
textline " "
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 22.--23. " ENCODER_MODE ,Encoder mode" "No redirection,TIM2/TIM15,TIM3/TIM15,?..."
|
|
textline " "
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 22.--23. " ENCODER_MODE ,Encoder mode" "No redirection,TIM2/TIM15,?..."
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.long 0x00 21. " I2C2_FMP ,I2C2 fast mode plus driving capability activation" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " I2C1_FMP ,I2C1 fast mode Plus driving capability activation" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " I2C_PB9_FMP ,Fast Mode Plus (FM+) driving capability activation bits for PB9" "Standard,I2C FM+"
|
|
textline " "
|
|
bitfld.long 0x00 18. " I2C_PB8_FMP ,Fast Mode Plus (FM+) driving capability activation bits for PB8" "Standard,I2C FM+"
|
|
bitfld.long 0x00 17. " I2C_PB7_FMP ,Fast Mode Plus (FM+) driving capability activation bits for PB7" "Standard,I2C FM+"
|
|
bitfld.long 0x00 16. " I2C_PB6_FMP ,Fast Mode Plus (FM+) driving capability activation bits for PB6" "Standard,I2C FM+"
|
|
textline " "
|
|
sif (cpu()=="STM32F372CB"||cpu()=="STM32F372RC"||cpu()=="STM32F372CC"||cpu()=="STM32F372V8"||cpu()=="STM32F372R8"||cpu()=="STM32F372VB"||cpu()=="STM32F372C8"||cpu()=="STM32F372RB"||cpu()=="STM32F372VC"||cpu()=="STM32F373C8"||cpu()=="STM32F373RB"||cpu()=="STM32F373VC"||cpu()=="STM32F373CB"||cpu()=="STM32F373RC"||cpu()=="STM32F373CC"||cpu()=="STM32F373V8"||cpu()=="STM32F373R8"||cpu()=="STM32F373VB"||cpu()=="STM32F383CC"||cpu()=="STM32F383RC"||cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 15. " TIM18_DAC2_OUT1_DMA_RMP ,TIM18 and DAC2_OUT1 DMA request remapping bit" "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F302CB"&&cpu()!="STM32F302VB"&&cpu()!="STM32F302CC"&&cpu()!="STM32F302VC"&&cpu()!="STM32F302RB"&&cpu()!="STM32F302RC")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x00 14. " TIM7_DAC1_OUT2_DMA_RMP ,TIM7 and DAC1_OUT2 DMA request remapping bit" "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " TIM6_DAC1_OUT1_DMA_RMP ,TIM6 and DAC1_OUT1 DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 12. " TIM17_DMA_RMP ,TIM17 DMA request remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 11. " TIM16_DMA_RMP ,TIM16 DMA request remapping bit" "No remap,Remap"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 8. " ADC24_DMA_RMP ,ADC24 DMA remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 7. " DAC_TRIG_RMP ,DAC trigger remap" "No remap,Remap"
|
|
bitfld.long 0x00 6. " TIM1_ITR3_RMP ,Timer 1 ITR3 selection" "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 5. " USB_IT_RMP ,USB interrupt remap" "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 0.--2. " MEM_MODE ,Memory mapping selection bits" "Main_flash,System_flash,Main_flash,Embedded_sram,Fmc_bank,Fmc_bank,Fmc_bank,Fmc_bank"
|
|
else
|
|
bitfld.long 0x00 0.--1. " MEM_MODE ,Memory mapping selection bits" "Main flash,System flash,Main flash,Embedded SRAM"
|
|
endif
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SYSCFG_RCR,SYSCFG CCM SRAM protection register"
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 15. " PAGE15_WP ,CCM SRAM page write protection bit 15" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PAGE14_WP ,CCM SRAM page write protection bit 14" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PAGE13_WP ,CCM SRAM page write protection bit 13" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " PAGE12_WP ,CCM SRAM page write protection bit 12" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PAGE11_WP ,CCM SRAM page write protection bit 11" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PAGE10_WP ,CCM SRAM page write protection bit 10" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PAGE9_WP ,CCM SRAM page write protection bit 9" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " PAGE8_WP ,CCM SRAM page write protection bit 8" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " PAGE7_WP ,CCM SRAM page write protection bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PAGE6_WP ,CCM SRAM page write protection bit 6" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " PAGE5_WP ,CCM SRAM page write protection bit 5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PAGE4_WP ,CCM SRAM page write protection bit 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PAGE3_WP ,CCM SRAM page write protection bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PAGE2_WP ,CCM SRAM page write protection bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PAGE1_WP ,CCM SRAM page write protection bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PAGE0_WP ,CCM SRAM page write protection bit 0" "Disabled,Enabled"
|
|
endif
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302CC"||cpu()=="STM32F303CB"||cpu()=="STM32F303CC"||cpu()=="STM32F313CC")
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,,,,,,,PA3,PB3,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F313CC")
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,,,,,,,,PA2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,,,,,,,PA2,PB2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,,,PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,,,PA0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,,,,,,,PA7,PB7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,,,,,,,PA6,PB6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,,,,,,,PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,,,,,,,PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,,,,,,,PA11,PB11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,,,,,,,PA10,PB10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,,,,,,,PA9,PB9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,,,,,,,PA8,PB8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,,,,,,PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,,,,,,PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,,,,,,PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,,,,,,,PA12,PB12,?..."
|
|
elif cpuis("STM32F303RE")||cpuis("STM32F303RD")||cpuis("STM32F302RD")||cpuis("STM32F302RE")
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG External Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,,,,,,PA3,PB3,PC3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,,,,,PA2,PB2,PC2,PD2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,,,PF1,,,PA1,PB1,PC1,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,,,PF0,,,PA0,PB0,PC0,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG External Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,,,,,,PA7,PB7,PC7,,,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,,,,,,PA6,PB6,PC6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,,,,,,PA5,PB5,PC5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,,,,,,PA4,PB4,PC4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG External Interrupt Configuration Register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,,,,,,PA11,PB11,PC11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,,,,,,RPA10,PB10,PC10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,,,,,,PA9,PB9,PC9,,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,,,,,,PA8,PB8,PC8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG External Interrupt Configuration Register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,,,,,,PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,,,,,,RPA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,,,,,,PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,,,,,,PA12,PB12,PC12,?..."
|
|
elif cpuis("STM32F303VE")||cpuis("STM32F303VD")||cpuis("STM32F302VD")||cpuis("STM32F302VE")
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG External Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,,,,PA3,PB3,PC3,PD3,PE3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,,,PA2,PB2,PC2,PD2,PE2,PF2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,,,PA1,PB1,PC1,PD1,PE1,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,,,PA0,PB0,PC0,PD0,PE0,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG External Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,,,,PA7,PB7,PC7,PD7,PE7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,,,PA6,PB6,PC6,PD6,PE6,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,,,,PA5,PB5,PC5,PD5,PE5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,,,,PA4,PB4,PC4,PD4,PE4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG External Interrupt Configuration Register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,,,,PA11,PB11,PC11,PD11,PE11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,,,RPA10,PB10,PC10,PD10,PE10,PF10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,,,PA9,PB9,PC9,PD9,PE9,PF9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,,,,PA8,PB8,PC8,PD8,PE8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG External Interrupt Configuration Register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,,,,PA15,PB15,PC15,PD15,PE15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,,,,RPA14,PB14,PC14,PD14,PE14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,,,,PA13,PB13,PC13,PD13,PE13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,,,,PA12,PB12,PC12,PD12,PE12,?..."
|
|
elif cpuis("STM32F303ZE")||cpuis("STM32F303ZD")||cpuis("STM32F302ZD")||cpuis("STM32F302ZE")
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG External Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,PF3,PG3,,PA3,PB3,PC3,PD3,PE3,PF3,PG3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,PG2,PH2,PA2,PB2,PC2,PD2,PE2,PF2,PG2,PH2"
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,PG1,PH1,PA1,PB1,PC1,PD1,PE1,PF1,PG1,PH1"
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,PG0,PH0,PA0,PB0,PC0,PD0,PE0,PF0,PG0,PH0"
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG External Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,PF7,PG7,,PA7,PB7,PC7,PD7,PE7,PF7,PG7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,PG6,,PA6,PB6,PC6,PD6,PE6,PF6,PG6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,PF5,PG5,,PA5,PB5,PC5,PD5,PE5,PF5,PG5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,PF4,PG4,,PA4,PB4,PC4,PD4,PE4,PF4,PG4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG External Interrupt Configuration Register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,PF11,PG11,,PA11,PB11,PC11,PD11,PE11,PF11,PG11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,PG10,,RPA10,PB10,PC10,PD10,PE10,PF10,PG10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,PG9,,PA9,PB9,PC9,PD9,PE9,PF9,PG9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,PF8,PG8,,PA8,PB8,PC8,PD8,PE8,PF8,PG8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG External Interrupt Configuration Register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,PF15,PG15,,PA15,PB15,PC15,PD15,PE15,PF15,PG15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,PF14,PG14,,RPA14,PB14,PC14,PD14,PE14,PF14,PG14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,PF13,PG13,,PA13,PB13,PC13,PD13,PE13,PF13,PG13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,PF12,PG12,,PA12,PB12,PC12,PD12,PE12,PF12,Pg12,?..."
|
|
elif CPUIS("STM32F398VE")
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG External Interrupt Configuration Register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,,,,PA3,PB3,PC3,PD3,PE3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,,PC2,PD2,PE2,PF2,,,PA2,,PC2,PD2,PE2,PF2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,,,PA1,PB1,PC1,PD1,PE1,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,,,PA0,PB0,PC0,PD0,PE0,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG External Interrupt Configuration Register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,,,,PA7,PB7,PC7,PD7,PE7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,,,PA6,PB6,PC6,PD6,PE6,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,,,,PA5,PB5,PC5,PD5,PE5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,,,,PA4,PB4,PC4,PD4,PE4,PF4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG External Interrupt Configuration Register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,,,,PA11,PB11,PC11,PD11,PE11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,,,RPA10,PB10,PC10,PD10,PE10,PF10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,,,PA9,PB9,PC9,PD9,PE9,PF9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,,,,PA8,PB8,PC8,PD8,PE8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG External Interrupt Configuration Register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,,,,PA15,PB15,PC15,PD15,PE15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,,,,RPA14,PB14,PC14,PD14,PE14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,,,,PA13,PB13,PC13,PD13,PE13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,,,,PA12,PB12,PC12,PD12,PE12,?..."
|
|
elif (cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F313RC")
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,,,,,,PA3,PB3,PC3,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F313RC")
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,,PC2,PD2,,,,,PA2,,PC2,PD2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,,,,,PA2,PB2,PC2,PD2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,,,PF1,,,PA1,PB1,PC1,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,,,PF0,,,PA0,PB0,PC0,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,,,,,,PA7,PB7,PC7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,,,,,,PA6,PB6,PC6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,,,,,,PA5,PB5,PC5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,,,PF4,,,PA4,PB4,PC4,,,PF4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,,,,,,PA11,PB11,PC11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,,,,,,PA10,PB10,PC10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,,,,,,PA9,PB9,PC9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,,,,,,PA8,PB8,PC8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,,,,,,PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,,,,,,PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,,,,,,PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,,,,,,PA12,PB12,PC12,?..."
|
|
elif (cpu()=="STM32F302VB"||cpu()=="STM32F302VC"||cpu()=="STM32F303VB"||cpu()=="STM32F303VC"||cpu()=="STM32F313VC")
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,,,,PA3,PB3,PC3,PD3,PE3,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F313VC")
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,,PC2,PD2,PE2,PF2,,,PA2,,PC2,PD2,PE2,PF2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,,,PA2,PB2,PC2,PD2,PE2,PF2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,,,PA1,PB1,PC1,PD1,PE1,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,,,PA0,PB0,PC0,PD0,PE0,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,,,,PA7,PB7,PC7,PD7,PE7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,,,PA6,PB6,PC6,PD6,PE6,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,,,,PA5,PB5,PC5,PD5,PE5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,PF4,,,PA4,PB4,PC4,PD4,PE4,PF4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PE11,,,,RPA11,PB11,PC11,PD11,PE11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,,,PA10,PB10,PC10,PD10,PE10,PF10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,,,PA9,PB9,PC9,PD9,PE9,PF9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,,,,PA8,PB8,PC8,PD8,PE8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,,,,PA15,PB15,PC15,PD15,PE15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,,,,PA14,PB14,PC14,PD14,PE14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,,,,PA13,PB13,PC13,PD13,PE13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,,,,PA12,PB12,PC12,PD12,PE12,?..."
|
|
elif (cpu()=="STM32F372C8"||cpu()=="STM32F372CB"||cpu()=="STM32F372CC"||cpu()=="STM32F373C8"||cpu()=="STM32F373CB"||cpu()=="STM32F373CC"||cpu()=="STM32F383CC")
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,,,,,,,PA3,PB3d,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F383CC")
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,,,,,,,,PA2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,,,,,,,PA2,PB2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,,,,PF1,,,PA1,PB1,,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,,,,PF0,,,A0,PB0,,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" ",PB7,,,,PF7,,,,PB7,,,,PF7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,,,,PF6,,,PA6,PB6,,,,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,,,,,,,PA5,PB5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,,,,,,,PA4,PB4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,,,,,,,,PA11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,,,,,,,,PA10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,,,PE9,,,,PA9,PB9,,,PE9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,,PD8,PE8,,,,A8,PB8,,PD8,PE8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,,,,,,PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,,,,,,PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,,PC13,,,,,,PA13,,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,,,,,,,,PA12,?..."
|
|
elif (cpu()=="STM32F372R8"||cpu()=="STM32F372RB"||cpu()=="STM32F372RC"||cpu()=="STM32F373R8"||cpu()=="STM32F373RB"||cpu()=="STM32F373RC"||cpu()=="STM32F383RC")
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,,,,,,PA3,PB3,PC3,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F383RC")
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,,PC2,PD2,,,,,PA2,,PC2,PD2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,,,,,PA2,PB2,PC2,PD2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,,,PF1,,,PA1,PB1,PC1,,,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,,,PF0,,,PA0,PB0,PC0,,,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,,,PF7,,,PA7,PB7,PC7,,,PF7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,,,PF6,,,PA6,PB6,PC6,,,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,,,,,,PA5,PB5,PC5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,,,,,,PA4,PB4,PC4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,,PC11,,,,,,PA11,,PC11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,,PC10,,,,,,PA10,,PC10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,,PE9,,,,PA9,PB9,PC9,,PE9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,,,,PA8,PB8,PC8,PD8,PE8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,,,,,,PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,,,,,,PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,,PC13,,,,,,PA13,,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,,PC12,,,,,,PA12,,PC12,?..."
|
|
else
|
|
group.long 0x08++0x13
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,,,,PA3,PB3,PC3,PD3,PE3,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,,,PA2,PB2,PC2,PD2,PE2,PF2,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,,,PA1,PB1,PC1,PD1,PE1,PF1,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,,,PA0,PB0,PC0,PD0,PE0,PF0,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,,,,PA7,PB7,PC7,PD7,PE7,?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,,,PA6,PB6,PC6,PD6,PE6,PF6,?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,,,,PA5,PB5,PC5,PD5,PE5,?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,PF4,,,PA4,PB4,PC4,PD4,PE4,PF4,?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,,PC11,PD11,PE11,,,,PA11,,PC11,PD11,PE11,?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,,,RPA10,PB10,PC10,PD10,PE10,PF10,?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,,,PA9,PB9,PC9,PD9,PE9,PF9,?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,,,,PA8,PB8,PC8,PD8,PE8,?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,,,,PA15,PB15,PC15,PD15,PE15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,,,,RPA14,PB14,PC14,PD14,PE14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,,PC13,PD13,PE13,,,,PA13,,PC13,PD13,PE13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,,PC12,PD12,PE12,,,,PA12,,PC12,PD12,PE12,?..."
|
|
endif
|
|
line.long 0x10 "SYSCFG_CFGR2,SYSCFG configuration register 2"
|
|
eventfld.long 0x10 8. " SRAM_PEF ,SRAM parity error flag" "No error,Error"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x10 4. " BYP_ADD_PAR ,Bypass address bit 29 in parity calculation" "Not bypassed,Bypassed"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x10 2. " PVD_LOCK ,PVD lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " SRAM_PARITY_LOCK ,SRAM parity lock" "Not locked,Locked"
|
|
bitfld.long 0x10 0. " LOCKUP_LOCK ,Cortex-M0 LOCKUP bit enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "SYSCFG_CFGR4,SYSCFG Configuration Register 4"
|
|
bitfld.long 0x00 13. " ADC34_JEXT14_RMP ,Controls the input trigger of ADC34 injected channel JEXT14" "TIM7_TRGO,TIM20_CC2"
|
|
bitfld.long 0x00 12. " ADC34_JEXT11_RMP ,Controls the input trigger of ADC34 injected channel JEXT11" "TIM1_CC3,TIM20_TRGO2"
|
|
bitfld.long 0x00 11. " ADC34_JEXT5_RMP ,Controls the input trigger of ADC34 injected channel JEXT5" "TIM4_CC3,TIM20_TRGO"
|
|
bitfld.long 0x00 10. " ADC34_EXT15_RMP ,Controls the input trigger of ADC34 regular channel EXT15" "TIM2_CC1,TIM20_CC1"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ADC34_EXT6_RMP ,Controls the input trigger of ADC34 regular channel EXT6" "TIM4_CC1,TIM20_TRGO2"
|
|
bitfld.long 0x00 8. " ADC34_EXT5_RMP ,Controls the input trigger of ADC34 regular channel EXT5" "EXTI_2,TIM20_TRGO"
|
|
bitfld.long 0x00 7. " ADC12_JEXT13_RMP ,Controls the input trigger of ADC12 injected channel JEXT13" "TIM3_CC1,TIM20_CC4"
|
|
bitfld.long 0x00 6. " ADC12_JEXT6_RMP ,Controls the input trigger of ADC12 injected channel JEXT6" "EXTI_15,TIM20_TRGO2"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ADC12_JEXT3_RMP ,Controls the input trigger of ADC12 injected channel EXT3" "TIM2_CC1,TIM20_TRGO"
|
|
bitfld.long 0x00 4. " ADC12_EXT15_RMP ,Controls the input trigger of ADC12 regular channel EXT15" "TIM3_CC4,TIM20_CC3"
|
|
bitfld.long 0x00 3. " ADC12_EXT13_RMP ,Controls the input trigger of ADC12 regular channel EXT13" "TIM6_TRGO,TIM20_CC2"
|
|
bitfld.long 0x00 2. " ADC12_EXT5_RMP ,Controls the input trigger of ADC12 regular channel EXT5" "TIM4_CC4,TIM20_CC1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ADC12_EXT3_RMP ,Controls the input trigger of ADC12 regular channel EXT3" "TIM2_CC2,TIM20_TRGO2"
|
|
bitfld.long 0x00 0. " ADC12_EXT2_RMP ,Controls the input trigger of ADC12 regular channel EXT2" "TIM1_CC3,TIM20_TRGO"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
else
|
|
tree "SYSCFG (System configuration controller)"
|
|
base ad:0x40010000
|
|
width 16.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SYSCFG_CFGR1,SYSCFG configuration register 1"
|
|
bitfld.long 0x00 31. " FPU_IE[5] ,Inexact interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " FPU_IE[4] ,Input denormal interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " FPU_IE[3] ,Overflow interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " FPU_IE[2] ,Underflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " FPU_IE[1] ,Divide-by-zero interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " FPU_IE[0] ,Invalid operation interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"
|
|
bitfld.long 0x00 24. " VBAT_MON ,VBAT monitoring enable" "Disabled,Enabled"
|
|
textline " "
|
|
elif CPUIS("STM32F301*6")||CPUIS("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||CPUIS("STM32F302*6")||CPUIS("STM32F302*8")
|
|
bitfld.long 0x00 24. " I2C3_FM+ ,I2C3 fast mode Plus driving capability activation" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"
|
|
sif CPUIS("STM32F303*6")||CPUIS("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"
|
|
bitfld.long 0x00 22.--23. " ENCODER_MODE ,Encoder mode" "No redirection,TIM2/TIM15,TIM3/TIM15,TIM4/TIM15"
|
|
bitfld.long 0x00 21. " I2C2_FM+ ,I2C2 fast mode Plus driving capability activation" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " I2C1_FM+ ,I2C1 fast mode Plus driving capability activation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " I2C_PB9_FM+ ,Fast Mode Plus (FM+) driving capability activation bits for PB9" "Standard,I2C FM+"
|
|
else
|
|
bitfld.long 0x00 22.--23. " ENCODER_MODE ,Encoder mode" "No redirection,TIM2/TIM15,TIM3/TIM15,TIM4/TIM15"
|
|
textline " "
|
|
bitfld.long 0x00 21. " I2C2_FM+ ,I2C2 fast mode Plus driving capability activation" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " I2C1_FM+ ,I2C1 fast mode Plus driving capability activation" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " I2C_PB9_FM+ ,Fast Mode Plus (FM+) driving capability activation bits for PB9" "Standard,I2C FM+"
|
|
endif
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 18. " I2C_PB8_FM+ ,Fast Mode Plus (FM+) driving capability activation bits for PB8" "Standard,I2C FM+"
|
|
bitfld.long 0x00 17. " I2C_PB7_FM+ ,Fast Mode Plus (FM+) driving capability activation bits for PB7" "Standard,I2C FM+"
|
|
bitfld.long 0x00 16. " I2C_PB6_FM+ ,Fast Mode Plus (FM+) driving capability activation bits for PB6" "Standard,I2C FM+"
|
|
sif CPUIS("STM32F303*6")||CPUIS("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||CPUIS("STM32F334?4")||CPUIS("STM32F334?6")||CPUIS("STM32F334?8")||cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"
|
|
bitfld.long 0x00 15. " TIM18_DAC2_OUT1_DMA_RMP ,TIM18 and DAC2_OUT1 DMA request remapping bit" "No remap,Remap"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TIM7_DAC1_OUT2_DMA_RMP ,TIM7 and DAC1_OUT2 DMA request remapping bit" "No remap,Remap"
|
|
elif CPUIS("STM32F302*")||CPUIS("STM32F303*")
|
|
bitfld.long 0x00 14. " TIM7_DAC1_OUT2_DMA_RMP ,TIM7 and DAC1_OUT2 DMA request remapping bit" "No remap,Remap"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 13. " TIM6_DAC1_OUT1_DMA_RMP ,TIM6 and DAC1_OUT1 DMA request remapping bit" "No remap,Remap"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TIM17_DMA_RMP ,TIM17 DMA request remapping bit" "No remap,Remap"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TIM16_DMA_RMP ,TIM16 DMA request remapping bit" "No remap,Remap"
|
|
textline " "
|
|
sif cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"
|
|
sif CPUIS("STM32F302*6")||CPUIS("STM32F302*8")||CPUIS("STM32F303*6")||CPUIS("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||CPUIS("STM32F302*")||CPUIS("STM32F303*")
|
|
bitfld.long 0x00 8. " ADC24_DMA_RMP ,ADC24 DMA remapping bit" "No remap,Remap"
|
|
bitfld.long 0x00 7. " DAC_TRIG_RMP ,DAC trigger remap" "No remap,Remap"
|
|
bitfld.long 0x00 6. " TIM1_ITR3_RMP ,Timer 1 ITR3 selection" "No remap,Remap"
|
|
textline " "
|
|
bitfld.long 0x00 5. " USB_IT_RMP ,USB interrupt remap" "No remap,Remap"
|
|
elif CPUIS("STM32F334?4")||CPUIS("STM32F334?6")||CPUIS("STM32F334?8")
|
|
bitfld.long 0x00 7. " DAC_TRIG_RMP ,DAC trigger remap" "No remap,Remap"
|
|
bitfld.long 0x00 6. " TIM1_ITR3_RMP ,Timer 1 ITR3 selection" "No remap,Remap"
|
|
elif CPUIS("STM32F301*6")||CPUIS("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"
|
|
bitfld.long 0x00 6. " TIM1_ITR3_RMP ,Timer 1 ITR3 selection" "No remap,Remap"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " MEM_MODE ,Memory mapping selection bits" "Main flash,System flash,Main flash,Embedded SRAM"
|
|
endif
|
|
sif CPUIS("STM32F303*6")||CPUIS("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||CPUIS("STM32F302*")||CPUIS("STM32F303*")||CPUIS("STM32F334?4")||CPUIS("STM32F334?6")||CPUIS("STM32F334?8")
|
|
textline " "
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SYSCFG_RCR,SYSCFG CCM SRAM protection register"
|
|
sif !CPUIS("STM32F303*6")&&!CPUIS("STM32F303*8")&&cpu()!="STM32F328C8"&&cpu()!="STM32F358CC"&&cpu()!="STM32F358RC"&&cpu()!="STM32F358VC"&&!CPUIS("STM32F334?4")&&!CPUIS("STM32F334?6")&&!CPUIS("STM32F334?8")
|
|
bitfld.long 0x00 7. " PAGE7_WP ,CCM SRAM page write protection bit 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PAGE6_WP ,CCM SRAM page write protection bit 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " PAGE5_WP ,CCM SRAM page write protection bit 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PAGE4_WP ,CCM SRAM page write protection bit 4" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PAGE3_WP ,CCM SRAM page write protection bit 3" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PAGE2_WP ,CCM SRAM page write protection bit 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " PAGE1_WP ,CCM SRAM page write protection bit 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PAGE0_WP ,CCM SRAM page write protection bit 0" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
group.long 0x08++0x13
|
|
sif CPUIS("STM32F301?6")||CPUIS("STM32F301?8")||cpuis("STM32F318?8")
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,,,,,,PA3,PB3,PC3,,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,,,,,PA2,PB2,PC2,PD2,,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,,,PF0,,,PA1,PB1,PC1,PD1,,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,,,PF0,,,PA0,PB0,PC0,PD0,,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,,,,,PA7,PB7,PC7?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,,,,,PA6,PB6,PC6?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,,,,,PA5,PB5,PC5?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,,,,,PA4,PB4,PC4?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,,,,,PA11,PB11,PC11?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,,,,,PA10,PB10,PC10?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,,,,,PA9,PB9,PC9?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,,,,,PA8,PB8,PC8?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,,,,,PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,,,,,PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,,,,,PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,,,,,PA12,PB12,PC12,?..."
|
|
else
|
|
line.long 0x00 "SYSCFG_EXTICR1,SYSCFG external interrupt configuration register 1"
|
|
bitfld.long 0x00 12.--15. " EXTI3 ,EXTI 3 configuration" "PA3,PB3,PC3,PD3,PE3,,,,PA3,PB3,PC3,,?..."
|
|
bitfld.long 0x00 8.--11. " EXTI2 ,EXTI 2 configuration" "PA2,PB2,PC2,PD2,PE2,PF2,,,PA2,PB2,PC2,PD2,,?..."
|
|
bitfld.long 0x00 4.--7. " EXTI1 ,EXTI 1 configuration" "PA1,PB1,PC1,PD1,PE1,PF1,,,PA1,PB1,PC1,PD1,,?..."
|
|
bitfld.long 0x00 0.--3. " EXTI0 ,EXTI 0 configuration" "PA0,PB0,PC0,PD0,PE0,PF0,,,PA0,PB0,PC0,PD0,,?..."
|
|
line.long 0x04 "SYSCFG_EXTICR2,SYSCFG external interrupt configuration register 2"
|
|
bitfld.long 0x04 12.--15. " EXTI7 ,EXTI 7 configuration" "PA7,PB7,PC7,PD7,PE7,,,PA7,PB7,PC7?..."
|
|
bitfld.long 0x04 8.--11. " EXTI6 ,EXTI 6 configuration" "PA6,PB6,PC6,PD6,PE6,PF6,,PA6,PB6,PC6?..."
|
|
bitfld.long 0x04 4.--7. " EXTI5 ,EXTI 5 configuration" "PA5,PB5,PC5,PD5,PE5,PF5,,PA5,PB5,PC5?..."
|
|
bitfld.long 0x04 0.--3. " EXTI4 ,EXTI 4 configuration" "PA4,PB4,PC4,PD4,PE4,PF4,,PA4,PB4,PC4?..."
|
|
line.long 0x08 "SYSCFG_EXTICR3,SYSCFG external interrupt configuration register 3"
|
|
bitfld.long 0x08 12.--15. " EXTI11 ,EXTI 11 configuration" "PA11,PB11,PC11,PD11,PF11,,,PA11,PB11,PC11?..."
|
|
bitfld.long 0x08 8.--11. " EXTI10 ,EXTI 10 configuration" "PA10,PB10,PC10,PD10,PE10,PF10,,PA10,PB10,PC10?..."
|
|
bitfld.long 0x08 4.--7. " EXTI9 ,EXTI 9 configuration" "PA9,PB9,PC9,PD9,PE9,PF9,,PA9,PB9,PC9?..."
|
|
bitfld.long 0x08 0.--3. " EXTI8 ,EXTI 8 configuration" "PA8,PB8,PC8,PD8,PE8,,,PA8,PB8,PC8?..."
|
|
line.long 0x0C "SYSCFG_EXTICR4,SYSCFG external interrupt configuration register 4"
|
|
bitfld.long 0x0C 12.--15. " EXTI15 ,EXTI 15 configuration" "PA15,PB15,PC15,PD15,PE15,,,PA15,PB15,PC15,?..."
|
|
bitfld.long 0x0C 8.--11. " EXTI14 ,EXTI 14 configuration" "PA14,PB14,PC14,PD14,PE14,,,PA14,PB14,PC14,?..."
|
|
bitfld.long 0x0C 4.--7. " EXTI13 ,EXTI 13 configuration" "PA13,PB13,PC13,PD13,PE13,,,PA13,PB13,PC13,?..."
|
|
bitfld.long 0x0C 0.--3. " EXTI12 ,EXTI 12 configuration" "PA12,PB12,PC12,PD12,PE12,,,PA12,PB12,PC12,?..."
|
|
endif
|
|
textline " "
|
|
sif CPUIS("STM32F301*6")||CPUIS("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SYSCFG_CFGR2,SYSCFG configuration register 2"
|
|
bitfld.long 0x00 2. " PVD_LOCK ,PVD lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " LOCKUP_LOCK ,Cortex-M0 LOCKUP bit enable" "Disabled,Enabled"
|
|
elif cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SYSCFG_CFGR2,SYSCFG configuration register 2"
|
|
eventfld.long 0x00 8. " SRAM_PEF ,SRAM parity error flag" "No error,Error"
|
|
bitfld.long 0x00 2. " PVD_LOCK ,PVD lock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SRAM_PARITY_LOCK ,SRAM parity lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LOCKUP_LOCK ,Cortex-M0 LOCKUP bit enable" "Disabled,Enabled"
|
|
elif cpu()=="STM32F318*"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SYSCFG_CFGR2,SYSCFG configuration register 2"
|
|
eventfld.long 0x00 8. " SRAM_PEF ,SRAM parity error flag" "No error,Error"
|
|
bitfld.long 0x00 4. " BYP_ADD_PAR ,Bypass address bit 29 in parity calculation" "Not bypassed,Bypassed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRAM_PARITY_LOCK ,SRAM parity lock" "Not locked,Locked"
|
|
bitfld.long 0x00 0. " LOCKUP_LOCK ,Cortex-M0 LOCKUP bit enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SYSCFG_CFGR2,SYSCFG configuration register 2"
|
|
eventfld.long 0x00 8. " SRAM_PEF ,SRAM parity error flag" "No error,Error"
|
|
bitfld.long 0x00 4. " BYP_ADD_PAR ,Bypass address bit 29 in parity calculation" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 2. " PVD_LOCK ,PVD lock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SRAM_PARITY_LOCK ,SRAM parity lock" "Not locked,Locked"
|
|
endif
|
|
sif CPUIS("STM32F302*6")||CPUIS("STM32F302*8")||CPUIS("STM32F334?4")||CPUIS("STM32F334?6")||CPUIS("STM32F334?8")
|
|
group.long 0x50++0x03
|
|
sif CPUIS("STM32F334?4")||CPUIS("STM32F334?6")||CPUIS("STM32F334?8")
|
|
line.long 0x00 "SYSCFG_CFGR3,SYSCFG configuration register 3"
|
|
bitfld.long 0x00 17. " DAC1_TRIG5_RMP ,DAC1_CH1 / DAC1_CH2 Trigger remap" "No remap,HRTIM1_DAC1_TRIG2"
|
|
bitfld.long 0x00 16. " DAC1_TRIG3_RMP ,DAC1_CH1 / DAC1_CH2 Trigger remap" "TIM15_TRGO,HRTIM1_DAC1_TRIG1"
|
|
bitfld.long 0x00 9. " ADC2_DMA_RMP[1] ,ADC2 DMA controller remapping bit" "DMA2,DMA1"
|
|
bitfld.long 0x00 8. " ADC2_DMA_RMP[0] ,ADC2 DMA channel remapping bit" "DMA1 CH2,DMA1 CH4"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " I2C1_TX_DMA_RMP ,I2C1_TX DMA remapping bit" "DMA1 CH6,DMA1 CH2,DMA1 CH4,DMA1 CH6"
|
|
bitfld.long 0x00 4.--5. " I2C1_RX_DMA_RMP ,I2C1_RX DMA remapping bit" "DMA1 CH7,DMA1 CH3,DMA1 CH5,DMA1 CH7"
|
|
bitfld.long 0x00 2.--3. " SPI1_TX_DMA_RMP ,SPI1_TX DMA remapping bit" "DMA1 CH3,DMA1 CH5,DMA1 CH7,DMA1 CH3"
|
|
bitfld.long 0x00 0.--1. " SPI1_RX_DMA_RMP ,SPI1_RX DMA remapping bit" "DMA1 CH2,DMA1 CH4,DMA1 CH6,DMA1 CH2"
|
|
else
|
|
line.long 0x00 "SYSCFG_CFGR3,SYSCFG configuration register 3"
|
|
bitfld.long 0x00 9. " ADC2_DMA_RMP[1] ,ADC2 DMA controller remapping bit" "DMA2,DMA1"
|
|
bitfld.long 0x00 8. " ADC2_DMA_RMP[0] ,ADC2 DMA channel remapping bit" "DMA1 CH2,DMA1 CH4"
|
|
bitfld.long 0x00 6.--7. " I2C1_TX_DMA_RMP ,I2C1_TX DMA remapping bit" "DMA1 CH6,DMA1 CH2,DMA1 CH4,DMA1 CH6"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " I2C1_RX_DMA_RMP ,I2C1_RX DMA remapping bit" "DMA1 CH7,DMA1 CH3,DMA1 CH5,DMA1 CH7"
|
|
bitfld.long 0x00 2.--3. " SPI1_TX_DMA_RMP ,SPI1_TX DMA remapping bit" "DMA1 CH3,DMA1 CH5,DMA1 CH7,DMA1 CH3"
|
|
bitfld.long 0x00 0.--1. " SPI1_RX_DMA_RMP ,SPI1_RX DMA remapping bit" "DMA1 CH2,DMA1 CH4,DMA1 CH6,DMA1 CH2"
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree "DMA (Direct memory access controller)"
|
|
tree "DMA1"
|
|
base ad:0x40020000
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DMA_ISR,DMA interrupt status register"
|
|
bitfld.long 0x00 27. " TEIF7 ,Channel 7 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 26. " HTIF7 ,Channel 7 Half Transfer flag" "No HT,HT occurred"
|
|
bitfld.long 0x00 25. " TCIF7 ,Channel 7 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 24. " GIF7 ,Channel 7 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TEIF6 ,Channel 6 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 22. " HTIF6 ,Channel 6 Half Transfer flag" "No HT,HT occurred"
|
|
bitfld.long 0x00 21. " TCIF6 ,Channel 6 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 20. " GIF6 ,Channel 6 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TEIF5 ,Channel 5 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 18. " HTIF5 ,Channel 5 Half Transfer flag" "No HT,HT occurred"
|
|
bitfld.long 0x00 17. " TCIF5 ,Channel 5 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " GIF5 ,Channel 5 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TEIF4 ,Channel 4 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 14. " HTIF4 ,Channel 4 Half Transfer flag" "No HT,HT occurred"
|
|
bitfld.long 0x00 13. " TCIF4 ,Channel 4 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " GIF4 ,Channel 4 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TEIF3 ,Channel 3 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 10. " HTIF3 ,Channel 3 Half Transfer flag" "No HT,HT occurred"
|
|
bitfld.long 0x00 9. " TCIF3 ,Channel 3 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " GIF3 ,Channel 3 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TEIF2 ,Channel 2 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 6. " HTIF2 ,Channel 2 Half Transfer flag" "No HT,HT occurred"
|
|
bitfld.long 0x00 5. " TCIF2 ,Channel 2 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " GIF2 ,Channel 2 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIF1 ,Channel 1 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 2. " HTIF1 ,Channel 1 Half Transfer flag" "No HT,HT occurred"
|
|
bitfld.long 0x00 1. " TCIF1 ,Channel 1 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " GIF1 ,Channel 1 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x00 27. " CTEIF7 ,Channel 7 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 26. " CHTIF7 ,Channel 7 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 25. " CTCIF7 ,Channel 7 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 24. " CGIF7 ,Channel 7 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 23. " CTEIF6 ,Channel 6 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 22. " CHTIF6 ,Channel 6 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 21. " CTCIF6 ,Channel 6 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 20. " CGIF6 ,Channel 6 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CHTIF5 ,Channel 5 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTEIF2 ,Channel 2 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CHTIF2 ,Channel 2 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CTCIF2 ,Channel 2 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CTEIF1 ,Channel 1 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CHTIF1 ,Channel 1 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CTCIF1 ,Channel 1 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
if (((per.l(ad:0x40020000+0x8))&0x300)==0x100)
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA Channel 1 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA Channel 1 Peripheral Address Register"
|
|
hexmask.long 0x08 1.--31. 1. " PA[31:1] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
hexmask.long 0x0C 1.--31. 1. " MA[31:1] ,Memory address"
|
|
elif (((per.l(ad:0x40020000+0x8))&0x300)==0x200)
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA Channel 1 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA Channel 1 Peripheral Address Register"
|
|
hexmask.long 0x08 2.--31. 1. " PA[31:2] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
hexmask.long 0x0C 2.--31. 1. " MA[31:2] ,Memory address"
|
|
else
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA Channel 1 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA Channel 1 Peripheral Address Register"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
endif
|
|
if (((per.l(ad:0x40020000+0x1C))&0x300)==0x100)
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA Channel 2 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA Channel 2 Peripheral Address Register"
|
|
hexmask.long 0x08 1.--31. 1. " PA[31:1] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
hexmask.long 0x0C 1.--31. 1. " MA[31:1] ,Memory address"
|
|
elif (((per.l(ad:0x40020000+0x1C))&0x300)==0x200)
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA Channel 2 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA Channel 2 Peripheral Address Register"
|
|
hexmask.long 0x08 2.--31. 1. " PA[31:2] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
hexmask.long 0x0C 2.--31. 1. " MA[31:2] ,Memory address"
|
|
else
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA Channel 2 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA Channel 2 Peripheral Address Register"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
endif
|
|
if (((per.l(ad:0x40020000+0x30))&0x300)==0x100)
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA Channel 3 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA Channel 3 Peripheral Address Register"
|
|
hexmask.long 0x08 1.--31. 1. " PA[31:1] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
hexmask.long 0x0C 1.--31. 1. " MA[31:1] ,Memory address"
|
|
elif (((per.l(ad:0x40020000+0x30))&0x300)==0x200)
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA Channel 3 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA Channel 3 Peripheral Address Register"
|
|
hexmask.long 0x08 2.--31. 1. " PA[31:2] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
hexmask.long 0x0C 2.--31. 1. " MA[31:2] ,Memory address"
|
|
else
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA Channel 3 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA Channel 3 Peripheral Address Register"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
endif
|
|
if (((per.l(ad:0x40020000+0x44))&0x300)==0x100)
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA Channel 4 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA Channel 4 Peripheral Address Register"
|
|
hexmask.long 0x08 1.--31. 1. " PA[31:1] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
hexmask.long 0x0C 1.--31. 1. " MA[31:1] ,Memory address"
|
|
elif (((per.l(ad:0x40020000+0x44))&0x300)==0x200)
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA Channel 4 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA Channel 4 Peripheral Address Register"
|
|
hexmask.long 0x08 2.--31. 1. " PA[31:2] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
hexmask.long 0x0C 2.--31. 1. " MA[31:2] ,Memory address"
|
|
else
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA Channel 4 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA Channel 4 Peripheral Address Register"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
endif
|
|
if (((per.l(ad:0x40020000+0x58))&0x300)==0x100)
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA Channel 5 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA Channel 5 Peripheral Address Register"
|
|
hexmask.long 0x08 1.--31. 1. " PA[31:1] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
hexmask.long 0x0C 1.--31. 1. " MA[31:1] ,Memory address"
|
|
elif (((per.l(ad:0x40020000+0x58))&0x300)==0x200)
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA Channel 5 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA Channel 5 Peripheral Address Register"
|
|
hexmask.long 0x08 2.--31. 1. " PA[31:2] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
hexmask.long 0x0C 2.--31. 1. " MA[31:2] ,Memory address"
|
|
else
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA Channel 5 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA Channel 5 Peripheral Address Register"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
endif
|
|
if (((per.l(ad:0x40020000+0x6C))&0x300)==0x100)
|
|
group.long 0x6C++0x0F "Channel 6"
|
|
line.long 0x00 "DMA_CCR6,DMA channel 6 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR6,DMA Channel 6 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR6,DMA Channel 6 Peripheral Address Register"
|
|
hexmask.long 0x08 1.--31. 1. " PA[31:1] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR6,DMA channel 6 memory address register"
|
|
hexmask.long 0x0C 1.--31. 1. " MA[31:1] ,Memory address"
|
|
elif (((per.l(ad:0x40020000+0x6C))&0x300)==0x200)
|
|
group.long 0x6C++0x0F "Channel 6"
|
|
line.long 0x00 "DMA_CCR6,DMA channel 6 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR6,DMA Channel 6 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR6,DMA Channel 6 Peripheral Address Register"
|
|
hexmask.long 0x08 2.--31. 1. " PA[31:2] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR6,DMA channel 6 memory address register"
|
|
hexmask.long 0x0C 2.--31. 1. " MA[31:2] ,Memory address"
|
|
else
|
|
group.long 0x6C++0x0F "Channel 6"
|
|
line.long 0x00 "DMA_CCR6,DMA channel 6 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR6,DMA Channel 6 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR6,DMA Channel 6 Peripheral Address Register"
|
|
line.long 0x0C "DMA_CMAR6,DMA channel 6 memory address register"
|
|
endif
|
|
if (((per.l(ad:0x40020000+0x80))&0x300)==0x100)
|
|
group.long 0x80++0x0F "Channel 7"
|
|
line.long 0x00 "DMA_CCR7,DMA channel 7 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR7,DMA Channel 7 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR7,DMA Channel 7 Peripheral Address Register"
|
|
hexmask.long 0x08 1.--31. 1. " PA[31:1] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR7,DMA channel 7 memory address register"
|
|
hexmask.long 0x0C 1.--31. 1. " MA[31:1] ,Memory address"
|
|
elif (((per.l(ad:0x40020000+0x80))&0x300)==0x200)
|
|
group.long 0x80++0x0F "Channel 7"
|
|
line.long 0x00 "DMA_CCR7,DMA channel 7 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR7,DMA Channel 7 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR7,DMA Channel 7 Peripheral Address Register"
|
|
hexmask.long 0x08 2.--31. 1. " PA[31:2] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR7,DMA channel 7 memory address register"
|
|
hexmask.long 0x0C 2.--31. 1. " MA[31:2] ,Memory address"
|
|
else
|
|
group.long 0x80++0x0F "Channel 7"
|
|
line.long 0x00 "DMA_CCR7,DMA channel 7 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR7,DMA Channel 7 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR7,DMA Channel 7 Peripheral Address Register"
|
|
line.long 0x0C "DMA_CMAR7,DMA channel 7 memory address register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F358*C")||cpuis("STM32F37*")||cpuis("STM32F303?E")||cpuis("STM32F303?D")||cpuis("STM32F398VE")
|
|
tree "DMA2"
|
|
base ad:0x40020400
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DMA_ISR,DMA interrupt status register"
|
|
bitfld.long 0x00 19. " TEIF5 ,Channel 5 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 18. " HTIF5 ,Channel 5 Half Transfer flag" "No HT,HT occurred"
|
|
bitfld.long 0x00 17. " TCIF5 ,Channel 5 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 16. " GIF5 ,Channel 5 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TEIF4 ,Channel 4 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 14. " HTIF4 ,Channel 4 Half Transfer flag" "No HT,HT occurred"
|
|
bitfld.long 0x00 13. " TCIF4 ,Channel 4 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 12. " GIF4 ,Channel 4 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TEIF3 ,Channel 3 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 10. " HTIF3 ,Channel 3 Half Transfer flag" "No HT,HT occurred"
|
|
bitfld.long 0x00 9. " TCIF3 ,Channel 3 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 8. " GIF3 ,Channel 3 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TEIF2 ,Channel 2 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 6. " HTIF2 ,Channel 2 Half Transfer flag" "No HT,HT occurred"
|
|
bitfld.long 0x00 5. " TCIF2 ,Channel 2 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 4. " GIF2 ,Channel 2 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIF1 ,Channel 1 Transfer Error flag" "No error,Error"
|
|
bitfld.long 0x00 2. " HTIF1 ,Channel 1 Half Transfer flag" "No HT,HT occurred"
|
|
bitfld.long 0x00 1. " TCIF1 ,Channel 1 Transfer Complete flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " GIF1 ,Channel 1 Global interrupt flag" "No TE/HT/TC,TE/HT/TC occurred"
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DMA_IFCR,DMA interrupt flag clear register"
|
|
bitfld.long 0x00 19. " CTEIF5 ,Channel 5 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 18. " CHTIF5 ,Channel 5 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 17. " CTCIF5 ,Channel 5 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " CGIF5 ,Channel 5 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 15. " CTEIF4 ,Channel 4 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 14. " CHTIF4 ,Channel 4 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " CTCIF4 ,Channel 4 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " CGIF4 ,Channel 4 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CTEIF3 ,Channel 3 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " CHTIF3 ,Channel 3 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " CTCIF3 ,Channel 3 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " CGIF3 ,Channel 3 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CTEIF2 ,Channel 2 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " CHTIF2 ,Channel 2 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CTCIF2 ,Channel 2 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CGIF2 ,Channel 2 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CTEIF1 ,Channel 1 Transfer Error clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CHTIF1 ,Channel 1 Half Transfer clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CTCIF1 ,Channel 1 Transfer Complete clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CGIF1 ,Channel 1 Global interrupt clear" "No effect,Clear"
|
|
textline " "
|
|
if (((per.l(ad:0x40020400+0x8))&0x300)==0x100)
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA Channel 1 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA Channel 1 Peripheral Address Register"
|
|
hexmask.long 0x08 1.--31. 1. " PA[31:1] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
hexmask.long 0x0C 1.--31. 1. " MA[31:1] ,Memory address"
|
|
elif (((per.l(ad:0x40020400+0x8))&0x300)==0x200)
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA Channel 1 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA Channel 1 Peripheral Address Register"
|
|
hexmask.long 0x08 2.--31. 1. " PA[31:2] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
hexmask.long 0x0C 2.--31. 1. " MA[31:2] ,Memory address"
|
|
else
|
|
group.long 0x8++0x0F "Channel 1"
|
|
line.long 0x00 "DMA_CCR1,DMA channel 1 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR1,DMA Channel 1 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR1,DMA Channel 1 Peripheral Address Register"
|
|
line.long 0x0C "DMA_CMAR1,DMA channel 1 memory address register"
|
|
endif
|
|
if (((per.l(ad:0x40020400+0x1C))&0x300)==0x100)
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA Channel 2 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA Channel 2 Peripheral Address Register"
|
|
hexmask.long 0x08 1.--31. 1. " PA[31:1] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
hexmask.long 0x0C 1.--31. 1. " MA[31:1] ,Memory address"
|
|
elif (((per.l(ad:0x40020400+0x1C))&0x300)==0x200)
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA Channel 2 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA Channel 2 Peripheral Address Register"
|
|
hexmask.long 0x08 2.--31. 1. " PA[31:2] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
hexmask.long 0x0C 2.--31. 1. " MA[31:2] ,Memory address"
|
|
else
|
|
group.long 0x1C++0x0F "Channel 2"
|
|
line.long 0x00 "DMA_CCR2,DMA channel 2 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR2,DMA Channel 2 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR2,DMA Channel 2 Peripheral Address Register"
|
|
line.long 0x0C "DMA_CMAR2,DMA channel 2 memory address register"
|
|
endif
|
|
if (((per.l(ad:0x40020400+0x30))&0x300)==0x100)
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA Channel 3 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA Channel 3 Peripheral Address Register"
|
|
hexmask.long 0x08 1.--31. 1. " PA[31:1] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
hexmask.long 0x0C 1.--31. 1. " MA[31:1] ,Memory address"
|
|
elif (((per.l(ad:0x40020400+0x30))&0x300)==0x200)
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA Channel 3 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA Channel 3 Peripheral Address Register"
|
|
hexmask.long 0x08 2.--31. 1. " PA[31:2] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
hexmask.long 0x0C 2.--31. 1. " MA[31:2] ,Memory address"
|
|
else
|
|
group.long 0x30++0x0F "Channel 3"
|
|
line.long 0x00 "DMA_CCR3,DMA channel 3 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR3,DMA Channel 3 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR3,DMA Channel 3 Peripheral Address Register"
|
|
line.long 0x0C "DMA_CMAR3,DMA channel 3 memory address register"
|
|
endif
|
|
if (((per.l(ad:0x40020400+0x44))&0x300)==0x100)
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA Channel 4 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA Channel 4 Peripheral Address Register"
|
|
hexmask.long 0x08 1.--31. 1. " PA[31:1] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
hexmask.long 0x0C 1.--31. 1. " MA[31:1] ,Memory address"
|
|
elif (((per.l(ad:0x40020400+0x44))&0x300)==0x200)
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA Channel 4 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA Channel 4 Peripheral Address Register"
|
|
hexmask.long 0x08 2.--31. 1. " PA[31:2] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
hexmask.long 0x0C 2.--31. 1. " MA[31:2] ,Memory address"
|
|
else
|
|
group.long 0x44++0x0F "Channel 4"
|
|
line.long 0x00 "DMA_CCR4,DMA channel 4 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR4,DMA Channel 4 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR4,DMA Channel 4 Peripheral Address Register"
|
|
line.long 0x0C "DMA_CMAR4,DMA channel 4 memory address register"
|
|
endif
|
|
if (((per.l(ad:0x40020400+0x58))&0x300)==0x100)
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA Channel 5 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA Channel 5 Peripheral Address Register"
|
|
hexmask.long 0x08 1.--31. 1. " PA[31:1] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
hexmask.long 0x0C 1.--31. 1. " MA[31:1] ,Memory address"
|
|
elif (((per.l(ad:0x40020400+0x58))&0x300)==0x200)
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA Channel 5 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA Channel 5 Peripheral Address Register"
|
|
hexmask.long 0x08 2.--31. 1. " PA[31:2] ,Peripheral address"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
hexmask.long 0x0C 2.--31. 1. " MA[31:2] ,Memory address"
|
|
else
|
|
group.long 0x58++0x0F "Channel 5"
|
|
line.long 0x00 "DMA_CCR5,DMA channel 5 configuration register"
|
|
bitfld.long 0x00 14. " MEM2MEM ,Memory to memory mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 12.--13. " PL ,Channel Priority level" "Low,Medium,High,Very high"
|
|
bitfld.long 0x00 10.--11. " MSIZE ,Memory size" "8-bits,16-bits,32-bits,?..."
|
|
bitfld.long 0x00 8.--9. " PSIZE ,Peripheral size" "8-bits,16-bits,32-bits,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " MINC ,Memory increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " PINC ,Peripheral increment mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " CIRC ,Circular mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " DIR ,Data transfer direction" "Peripheral,Memory"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TEIE ,Transfer error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " HTIE ,Half Transfer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TCIE ,Transfer complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EN ,Channel enable" "Disabled,Enabled"
|
|
line.long 0x04 "DMA_CNDTR5,DMA Channel 5 Number Of Data Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " NDT ,Number of data to transfer"
|
|
line.long 0x08 "DMA_CPAR5,DMA Channel 5 Peripheral Address Register"
|
|
line.long 0x0C "DMA_CMAR5,DMA channel 5 memory address register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "EXTI (Extended interrupts and events controller)"
|
|
base ad:0x40010400
|
|
width 14.
|
|
group.long 0x00++0x17
|
|
line.long 0x00 "EXTI_IMR1,EXTI interrupt mask register"
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||(cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"&&!cpuis("STM32F302?E")&&!cpuis("STM32F302?D"))||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 31. " MR31 ,Interrupt mask on line 31" "Masked,Not masked"
|
|
bitfld.long 0x00 30. " MR30 ,Interrupt mask on line 30" "Masked,Not masked"
|
|
bitfld.long 0x00 29. " MR29 ,Interrupt mask on line 29" "Masked,Not masked"
|
|
textline " "
|
|
elif cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x00 30. " MR30 ,Interrupt mask on line 30" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " MR28 ,Interrupt mask on line 28" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 27. " MR27 ,Interrupt mask on line 27" "Masked,Not masked"
|
|
bitfld.long 0x00 26. " MR26 ,Interrupt mask on line 26" "Masked,Not masked"
|
|
bitfld.long 0x00 25. " MR25 ,Interrupt mask on line 25" "Masked,Not masked"
|
|
bitfld.long 0x00 24. " MR24 ,Interrupt mask on line 24" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 23. " MR23 ,Interrupt mask on line 23" "Masked,Not masked"
|
|
bitfld.long 0x00 22. " MR22 ,Interrupt mask on line 22" "Masked,Not masked"
|
|
bitfld.long 0x00 21. " MR21 ,Interrupt mask on line 21" "Masked,Not masked"
|
|
bitfld.long 0x00 20. " MR20 ,Interrupt mask on line 20" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MR19 ,Interrupt mask on line 19" "Masked,Not masked"
|
|
bitfld.long 0x00 18. " MR18 ,Interrupt mask on line 18" "Masked,Not masked"
|
|
bitfld.long 0x00 17. " MR17 ,Interrupt mask on line 17" "Masked,Not masked"
|
|
bitfld.long 0x00 16. " MR16 ,Interrupt mask on line 16" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MR15 ,Interrupt mask on line 15" "Masked,Not masked"
|
|
bitfld.long 0x00 14. " MR14 ,Interrupt mask on line 14" "Masked,Not masked"
|
|
bitfld.long 0x00 13. " MR13 ,Interrupt mask on line 13" "Masked,Not masked"
|
|
bitfld.long 0x00 12. " MR12 ,Interrupt mask on line 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 11. " MR11 ,Interrupt mask on line 11" "Masked,Not masked"
|
|
bitfld.long 0x00 10. " MR10 ,Interrupt mask on line 10" "Masked,Not masked"
|
|
bitfld.long 0x00 9. " MR9 ,Interrupt mask on line 9" "Masked,Not masked"
|
|
bitfld.long 0x00 8. " MR8 ,Interrupt mask on line 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MR7 ,Interrupt mask on line 7" "Masked,Not masked"
|
|
bitfld.long 0x00 6. " MR6 ,Interrupt mask on line 6" "Masked,Not masked"
|
|
bitfld.long 0x00 5. " MR5 ,Interrupt mask on line 5" "Masked,Not masked"
|
|
bitfld.long 0x00 4. " MR4 ,Interrupt mask on line 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MR3 ,Interrupt mask on line 3" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " MR2 ,Interrupt mask on line 2" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " MR1 ,Interrupt mask on line 1" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " MR0 ,Interrupt mask on line 0" "Masked,Not masked"
|
|
line.long 0x04 "EXTI_EMR1,EXTI event mask register"
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||(cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"&&!cpuis("STM32F302?E")&&!cpuis("STM32F302?D"))||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x04 31. " MR31 ,Event mask on line 31" "Masked,Not masked"
|
|
bitfld.long 0x04 30. " MR30 ,Event mask on line 30" "Masked,Not masked"
|
|
bitfld.long 0x04 29. " MR29 ,Event mask on line 29" "Masked,Not masked"
|
|
textline " "
|
|
elif cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
bitfld.long 0x04 30. " MR30 ,Event mask on line 30" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 28. " MR28 ,Event mask on line 28" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 27. " MR27 ,Event mask on line 27" "Masked,Not masked"
|
|
bitfld.long 0x04 26. " MR26 ,Event mask on line 26" "Masked,Not masked"
|
|
bitfld.long 0x04 25. " MR25 ,Event mask on line 25" "Masked,Not masked"
|
|
bitfld.long 0x04 24. " MR24 ,Event mask on line 24" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 23. " MR23 ,Event mask on line 23" "Masked,Not masked"
|
|
bitfld.long 0x04 22. " MR22 ,Event mask on line 22" "Masked,Not masked"
|
|
bitfld.long 0x04 21. " MR21 ,Event mask on line 21" "Masked,Not masked"
|
|
bitfld.long 0x04 20. " MR20 ,Event mask on line 20" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 19. " MR19 ,Event mask on line 19" "Masked,Not masked"
|
|
bitfld.long 0x04 18. " MR18 ,Event mask on line 18" "Masked,Not masked"
|
|
bitfld.long 0x04 17. " MR17 ,Event mask on line 17" "Masked,Not masked"
|
|
bitfld.long 0x04 16. " MR16 ,Event mask on line 16" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 15. " MR15 ,Event mask on line 15" "Masked,Not masked"
|
|
bitfld.long 0x04 14. " MR14 ,Event mask on line 14" "Masked,Not masked"
|
|
bitfld.long 0x04 13. " MR13 ,Event mask on line 13" "Masked,Not masked"
|
|
bitfld.long 0x04 12. " MR12 ,Event mask on line 12" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 11. " MR11 ,Event mask on line 11" "Masked,Not masked"
|
|
bitfld.long 0x04 10. " MR10 ,Event mask on line 10" "Masked,Not masked"
|
|
bitfld.long 0x04 9. " MR9 ,Event mask on line 9" "Masked,Not masked"
|
|
bitfld.long 0x04 8. " MR8 ,Event mask on line 8" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MR7 ,Event mask on line 7" "Masked,Not masked"
|
|
bitfld.long 0x04 6. " MR6 ,Event mask on line 6" "Masked,Not masked"
|
|
bitfld.long 0x04 5. " MR5 ,Event mask on line 5" "Masked,Not masked"
|
|
bitfld.long 0x04 4. " MR4 ,Event mask on line 4" "Masked,Not masked"
|
|
textline " "
|
|
bitfld.long 0x04 3. " MR3 ,Event mask on line 3" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " MR2 ,Event mask on line 2" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " MR1 ,Event mask on line 1" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " MR0 ,Event mask on line 0" "Masked,Not masked"
|
|
line.long 0x08 "EXTI_RTSR1,EXTI rising edge trigger selection register"
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||(cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"&&!cpuis("STM32F302?E")&&!cpuis("STM32F302?D"))||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x08 31. " TR31 ,Rising edge trigger event configuration bit of line 31" "Disabled,Enabled"
|
|
bitfld.long 0x08 30. " TR30 ,Rising edge trigger event configuration bit of line 30" "Disabled,Enabled"
|
|
bitfld.long 0x08 29. " TR29 ,Rising edge trigger event configuration bit of line 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 22. " TR22 ,Rising edge trigger event configuration bit of line 22" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " TR21 ,Rising edge trigger event configuration bit of line 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " TR20 ,Rising edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x08 30. " TR30 ,Rising edge trigger event configuration bit of line 30" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " TR22 ,Rising edge trigger event configuration bit of line 22" "Disabled,Enabled"
|
|
bitfld.long 0x08 21. " TR21 ,Rising edge trigger event configuration bit of line 21" "Disabled,Enabled"
|
|
bitfld.long 0x08 20. " TR20 ,Rising edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 19. " TR19 ,Rising edge trigger event configuration bit of line 19" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||(cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x08 18. " TR18 ,Rising edge trigger event configuration bit of line 18" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 17. " TR17 ,Rising edge trigger event configuration bit of line 17" "Disabled,Enabled"
|
|
bitfld.long 0x08 16. " TR16 ,Rising edge trigger event configuration bit of line 16" "Disabled,Enabled"
|
|
bitfld.long 0x08 15. " TR15 ,Rising edge trigger event configuration bit of line 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 14. " TR14 ,Rising edge trigger event configuration bit of line 14" "Disabled,Enabled"
|
|
bitfld.long 0x08 13. " TR13 ,Rising edge trigger event configuration bit of line 13" "Disabled,Enabled"
|
|
bitfld.long 0x08 12. " TR12 ,Rising edge trigger event configuration bit of line 12" "Disabled,Enabled"
|
|
bitfld.long 0x08 11. " TR11 ,Rising edge trigger event configuration bit of line 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 10. " TR10 ,Rising edge trigger event configuration bit of line 10" "Disabled,Enabled"
|
|
bitfld.long 0x08 9. " TR9 ,Rising edge trigger event configuration bit of line 9" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " TR8 ,Rising edge trigger event configuration bit of line 8" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " TR7 ,Rising edge trigger event configuration bit of line 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " TR6 ,Rising edge trigger event configuration bit of line 6" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " TR5 ,Rising edge trigger event configuration bit of line 5" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " TR4 ,Rising edge trigger event configuration bit of line 4" "Disabled,Enabled"
|
|
bitfld.long 0x08 3. " TR3 ,Rising edge trigger event configuration bit of line 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 2. " TR2 ,Rising edge trigger event configuration bit of line 2" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " TR1 ,Rising edge trigger event configuration bit of line 1" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TR0 ,Rising edge trigger event configuration bit of line 0" "Disabled,Enabled"
|
|
line.long 0x0C "EXTI_FTSR1,Falling edge trigger selection register"
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||(cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"&&!cpuis("STM32F302?E")&&!cpuis("STM32F302?D"))||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x0C 31. " TR31 ,Falling edge trigger event configuration bit of line 31" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " TR30 ,Falling edge trigger event configuration bit of line 30" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " TR29 ,Falling edge trigger event configuration bit of line 29" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " TR22 ,Falling edge trigger event configuration bit of line 22" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " TR21 ,Falling edge trigger event configuration bit of line 21" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " TR20 ,Falling edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
textline " "
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x0C 30. " TR30 ,Falling edge trigger event configuration bit of line 30" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " TR22 ,Falling edge trigger event configuration bit of line 22" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " TR21 ,Falling edge trigger event configuration bit of line 21" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " TR20 ,Falling edge trigger event configuration bit of line 20" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 19. " TR19 ,Falling edge trigger event configuration bit of line 19" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||(cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x0C 18. " TR18 ,Falling edge trigger event configuration bit of line 18" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 17. " TR17 ,Falling edge trigger event configuration bit of line 17" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " TR16 ,Falling edge trigger event configuration bit of line 16" "Disabled,Enabled"
|
|
bitfld.long 0x0C 15. " TR15 ,Falling edge trigger event configuration bit of line 15" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 14. " TR14 ,Falling edge trigger event configuration bit of line 14" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " TR13 ,Falling edge trigger event configuration bit of line 13" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " TR12 ,Falling edge trigger event configuration bit of line 12" "Disabled,Enabled"
|
|
bitfld.long 0x0C 11. " TR11 ,Falling edge trigger event configuration bit of line 11" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " TR10 ,Falling edge trigger event configuration bit of line 10" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " TR9 ,Falling edge trigger event configuration bit of line 9" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " TR8 ,Falling edge trigger event configuration bit of line 8" "Disabled,Enabled"
|
|
bitfld.long 0x0C 7. " TR7 ,Falling edge trigger event configuration bit of line 7" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 6. " TR6 ,Falling edge trigger event configuration bit of line 6" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " TR5 ,Falling edge trigger event configuration bit of line 5" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " TR4 ,Falling edge trigger event configuration bit of line 4" "Disabled,Enabled"
|
|
bitfld.long 0x0C 3. " TR3 ,Falling edge trigger event configuration bit of line 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 2. " TR2 ,Falling edge trigger event configuration bit of line 2" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " TR1 ,Falling edge trigger event configuration bit of line 1" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TR0 ,Falling edge trigger event configuration bit of line 0" "Disabled,Enabled"
|
|
line.long 0x10 "EXTI_SWIER1,EXTI software interrupt event register"
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||(cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"&&!cpuis("STM32F302?E")&&!cpuis("STM32F302?D"))||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x10 31. " SWIER31 ,Software interrupt on line 31" "No effect,Interrupt"
|
|
bitfld.long 0x10 30. " SWIER30 ,Software interrupt on line 30" "No effect,Interrupt"
|
|
bitfld.long 0x10 29. " SWIER29 ,Software interrupt on line 29" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 22. " SWIER22 ,Software interrupt on line 22" "No effect,Interrupt"
|
|
bitfld.long 0x10 21. " SWIER21 ,Software interrupt on line 21" "No effect,Interrupt"
|
|
bitfld.long 0x10 20. " SWIER20 ,Software interrupt on line 20" "No effect,Interrupt"
|
|
textline " "
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x10 30. " SWIER30 ,Software interrupt on line 30" "No effect,Interrupt"
|
|
bitfld.long 0x10 22. " SWIER22 ,Software interrupt on line 22" "No effect,Interrupt"
|
|
bitfld.long 0x10 21. " SWIER21 ,Software interrupt on line 21" "No effect,Interrupt"
|
|
bitfld.long 0x10 20. " SWIER20 ,Software interrupt on line 20" "No effect,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 19. " SWIER19 ,Software interrupt on line 19" "No effect,Interrupt"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||(cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x10 18. " SWIER18 ,Software interrupt on line 18" "No effect,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 17. " SWIER17 ,Software interrupt on line 17" "No effect,Interrupt"
|
|
bitfld.long 0x10 16. " SWIER16 ,Software interrupt on line 16" "No effect,Interrupt"
|
|
bitfld.long 0x10 15. " SWIER15 ,Software interrupt on line 15" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 14. " SWIER14 ,Software interrupt on line 14" "No effect,Interrupt"
|
|
bitfld.long 0x10 13. " SWIER13 ,Software interrupt on line 13" "No effect,Interrupt"
|
|
bitfld.long 0x10 12. " SWIER12 ,Software interrupt on line 12" "No effect,Interrupt"
|
|
bitfld.long 0x10 11. " SWIER11 ,Software interrupt on line 11" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 10. " SWIER10 ,Software interrupt on line 10" "No effect,Interrupt"
|
|
bitfld.long 0x10 9. " SWIER9 ,Software interrupt on line 9" "No effect,Interrupt"
|
|
bitfld.long 0x10 8. " SWIER8 ,Software interrupt on line 8" "No effect,Interrupt"
|
|
bitfld.long 0x10 7. " SWIER7 ,Software interrupt on line 7" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 6. " SWIER6 ,Software interrupt on line 6" "No effect,Interrupt"
|
|
bitfld.long 0x10 5. " SWIER5 ,Software interrupt on line 5" "No effect,Interrupt"
|
|
bitfld.long 0x10 4. " SWIER4 ,Software interrupt on line 4" "No effect,Interrupt"
|
|
bitfld.long 0x10 3. " SWIER3 ,Software interrupt on line 3" "No effect,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x10 2. " SWIER2 ,Software interrupt on line 2" "No effect,Interrupt"
|
|
bitfld.long 0x10 1. " SWIER1 ,Software interrupt on line 1" "No effect,Interrupt"
|
|
bitfld.long 0x10 0. " SWIER0 ,Software interrupt on line 0" "No effect,Interrupt"
|
|
line.long 0x14 "EXTI_PR1,EXTI pending register"
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||(cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"&&!cpuis("STM32F302?E")&&!cpuis("STM32F302?D"))||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
eventfld.long 0x14 31. " PR31 ,Pending bit on line 31" "Not pending,Pending"
|
|
eventfld.long 0x14 30. " PR30 ,Pending bit on line 30" "Not pending,Pending"
|
|
eventfld.long 0x14 29. " PR29 ,Pending bit on line 29" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 22. " PR22 ,Pending bit on line 22" "Not pending,Pending"
|
|
eventfld.long 0x14 21. " PR21 ,Pending bit on line 21" "Not pending,Pending"
|
|
eventfld.long 0x14 20. " PR20 ,Pending bit on line 20" "Not pending,Pending"
|
|
textline " "
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
eventfld.long 0x14 30. " PR30 ,Pending bit on line 30" "Not pending,Pending"
|
|
eventfld.long 0x14 22. " PR22 ,Pending bit on line 22" "Not pending,Pending"
|
|
eventfld.long 0x14 21. " PR21 ,Pending bit on line 21" "Not pending,Pending"
|
|
eventfld.long 0x14 20. " PR20 ,Pending bit on line 20" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x14 19. " PR19 ,Pending bit on line 19" "Not pending,Pending"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB"||cpu()=="STM32F302VB"||cpu()=="STM32F302CC"||cpu()=="STM32F302VC"||cpu()=="STM32F302RB"||cpu()=="STM32F302RC"||cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||(cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
eventfld.long 0x14 18. " PR18 ,Pending bit on line 18" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x14 17. " PR17 ,Pending bit on line 17" "Not pending,Pending"
|
|
eventfld.long 0x14 16. " PR16 ,Pending bit on line 16" "Not pending,Pending"
|
|
eventfld.long 0x14 15. " PR15 ,Pending bit on line 15" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 14. " PR14 ,Pending bit on line 14" "Not pending,Pending"
|
|
eventfld.long 0x14 13. " PR13 ,Pending bit on line 13" "Not pending,Pending"
|
|
eventfld.long 0x14 12. " PR12 ,Pending bit on line 12" "Not pending,Pending"
|
|
eventfld.long 0x14 11. " PR11 ,Pending bit on line 11" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 10. " PR10 ,Pending bit on line 10" "Not pending,Pending"
|
|
eventfld.long 0x14 9. " PR9 ,Pending bit on line 9" "Not pending,Pending"
|
|
eventfld.long 0x14 8. " PR8 ,Pending bit on line 8" "Not pending,Pending"
|
|
eventfld.long 0x14 7. " PR7 ,Pending bit on line 7" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 6. " PR6 ,Peanding bit on line 6" "Not pending,Pending"
|
|
eventfld.long 0x14 5. " PR5 ,Pending bit on line 5" "Not pending,Pending"
|
|
eventfld.long 0x14 4. " PR4 ,Pending bit on line 4" "Not pending,Pending"
|
|
eventfld.long 0x14 3. " PR3 ,Pending bit on line 3" "Not pending,Pending"
|
|
textline " "
|
|
eventfld.long 0x14 2. " PR2 ,Pending bit on line 2" "Not pending,Pending"
|
|
eventfld.long 0x14 1. " PR1 ,Pending bit on line 1" "Not pending,Pending"
|
|
eventfld.long 0x14 0. " PR0 ,Pending bit on line 0" "Not pending,Pending"
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||cpuis("STM32F334*")||(cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")
|
|
group.long 0x18++0x17
|
|
line.long 0x00 "EXTI_IMR2,EXTI interrupt mask register"
|
|
bitfld.long 0x00 3. " MR35 ,Interrupt mask on line 35" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " MR34 ,Interrupt mask on line 34" "Masked,Not masked"
|
|
bitfld.long 0x00 1. " MR33 ,Interrupt mask on line 33" "Masked,Not masked"
|
|
bitfld.long 0x00 0. " MR32 ,Interrupt mask on line 32" "Masked,Not masked"
|
|
line.long 0x04 "EXTI_EMR2,EXTI event mask register"
|
|
bitfld.long 0x04 3. " MR35 ,Event mask on line 35" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " MR34 ,Event mask on line 34" "Masked,Not masked"
|
|
bitfld.long 0x04 1. " MR33 ,Event mask on line 33" "Masked,Not masked"
|
|
bitfld.long 0x04 0. " MR32 ,Event mask on line 32" "Masked,Not masked"
|
|
line.long 0x08 "EXTI_RTSR2,EXTI rising edge trigger selection register"
|
|
bitfld.long 0x08 1. " TR33 ,Rising edge trigger event configuration bit of line 33" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TR32 ,Rising edge trigger event configuration bit of line 32" "Disabled,Enabled"
|
|
line.long 0x0C "EXTI_FTSR2,Falling edge trigger selection register"
|
|
bitfld.long 0x0C 1. " TR33 ,Falling edge trigger event configuration bit of line 33" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TR32 ,Falling edge trigger event configuration bit of line 32" "Disabled,Enabled"
|
|
line.long 0x10 "EXTI_SWIER2,EXTI software interrupt event register"
|
|
bitfld.long 0x10 1. " SWIER33 ,Software interrupt on line 33" "No effect,Interrupt"
|
|
bitfld.long 0x10 0. " SWIER32 ,Software interrupt on line 32" "No effect,Interrupt"
|
|
line.long 0x14 "EXTI_PR2,EXTI pending register"
|
|
eventfld.long 0x14 1. " PR33 ,Pending bit on line 33" "Not pending,Pending"
|
|
eventfld.long 0x14 0. " PR32 ,Pending bit on line 32" "Not pending,Pending"
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x20++0x17
|
|
line.long 0x00 "EXTI_IMR2,EXTI interrupt mask register"
|
|
bitfld.long 0x00 3. " MR35 ,Interrupt mask on line 35" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " MR34 ,Interrupt mask on line 34" "Masked,Not masked"
|
|
textline " "
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x00 1. " MR33 ,Interrupt mask on line 33" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " MR32 ,Interrupt mask on line 32" "Masked,Not masked"
|
|
line.long 0x04 "EXTI_EMR2,EXTI event mask register"
|
|
bitfld.long 0x04 3. " MR35 ,Event mask on line 35" "Masked,Not masked"
|
|
bitfld.long 0x04 2. " MR34 ,Event mask on line 34" "Masked,Not masked"
|
|
textline " "
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x04 1. " MR33 ,Event mask on line 33" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " MR32 ,Event mask on line 32" "Masked,Not masked"
|
|
line.long 0x08 "EXTI_RTSR2,EXTI rising edge trigger selection register"
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x08 1. " TR33 ,Rising edge trigger event configuration bit of line 33" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0. " TR32 ,Rising edge trigger event configuration bit of line 32" "Disabled,Enabled"
|
|
line.long 0x0C "EXTI_FTSR2,Falling edge trigger selection register"
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x0C 1. " TR33 ,Falling edge trigger event configuration bit of line 33" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 0. " TR32 ,Falling edge trigger event configuration bit of line 32" "Disabled,Enabled"
|
|
line.long 0x10 "EXTI_SWIER2,EXTI software interrupt event register"
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x10 1. " SWIER33 ,Software interrupt on line 33" "No effect,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 0. " SWIER32 ,Software interrupt on line 32" "No effect,Interrupt"
|
|
line.long 0x14 "EXTI_PR2,EXTI pending register"
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
eventfld.long 0x14 1. " PR33 ,Pending bit on line 33" "Not pending,Pending"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x14 0. " PR32 ,Pending bit on line 32" "Not pending,Pending"
|
|
elif !cpuis("STM32F37*")
|
|
sif cpuis("STM32F302*")||cpuis("STM32F303*")||cpuis("STM32F398VE")
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x20++0x13
|
|
line.long 0x00 "EXTI_IMR2,EXTI interrupt mask register"
|
|
bitfld.long 0x00 3. " MR35 ,Interrupt mask on line 35" "Masked,Not masked"
|
|
bitfld.long 0x00 2. " MR34 ,Interrupt mask on line 34" "Masked,Not masked"
|
|
textline " "
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x00 1. " MR33 ,Interrupt mask on line 33" "Masked,Not masked"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " MR32 ,Interrupt mask on line 32" "Masked,Not masked"
|
|
line.long 0x04 "EXTI_RTSR2,Rising trigger selection register"
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x04 1. " TR33 ,Rising trigger event configuration bit of line 33" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 0. " TR32 ,Rising trigger event configuration bit of line 32" "Disabled,Enabled"
|
|
line.long 0x08 "EXTI_FTSR1,Falling trigger selection register"
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x08 1. " TR33 ,Falling trigger event configuration bit of line 33" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0. " TR32 ,Falling trigger event configuration bit of line 32" "Disabled,Enabled"
|
|
line.long 0x0C "EXTI_SWIER2,Software interrupt event register"
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x0C 1. " SWIER33 ,Software interrupt on line 33" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 0. " SWIER32 ,Software interrupt on line 32" "No interrupt,Interrupt"
|
|
line.long 0x10 "EXTI_PR2,Pending register"
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
eventfld.long 0x10 1. " PR33 ,Pending bit on line 33" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x10 0. " PR32 ,Pending bit on line 32" "Not occurred,Occurred"
|
|
else
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "EXTI_RTSR2,Rising trigger selection register "
|
|
bitfld.long 0x00 1. " TR33 ,Rising trigger event configuration bit of line 33" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TR32 ,Rising trigger event configuration bit of line 32" "Disabled,Enabled"
|
|
line.long 0x04 "EXTI_FTSR1,Falling trigger selection register "
|
|
bitfld.long 0x04 1. " TR33 ,Falling trigger event configuration bit of line 33" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " TR32 ,Falling trigger event configuration bit of line 32" "Disabled,Enabled"
|
|
line.long 0x08 "EXTI_SWIER2,Software interrupt event register"
|
|
bitfld.long 0x08 1. " SWIER33 ,Software interrupt on line 33" "No interrupt,Interrupt"
|
|
bitfld.long 0x08 0. " SWIER32 ,Software interrupt on line 32" "No interrupt,Interrupt"
|
|
line.long 0x0C "EXTI_PR2,Pending register "
|
|
eventfld.long 0x0C 1. " PR33 ,Pending bit on line 33" "Not occurred,Occurred"
|
|
eventfld.long 0x0C 0. " PR32 ,Pending bit on line 32" "Not occurred,Occurred"
|
|
endif
|
|
else
|
|
group.long 0x20++0x0F
|
|
line.long 0x00 "EXTI_IMR2,Interrupt mask register"
|
|
bitfld.long 0x00 3. " MR35 ,Interrupt Mask on external/internal line 35" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " MR34 ,Interrupt Mask on external/internal line 34" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " MR33 ,Interrupt Mask on external/internal line 33" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " MR32 ,Interrupt Mask on external/internal line 32" "No interrupt,Interrupt"
|
|
line.long 0x04 "EXTI_EMR2,Event mask register"
|
|
bitfld.long 0x04 3. " MR35 ,Event Mask on external/internal line 35" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 2. " MR34 ,Event Mask on external/internal line 34" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 1. " MR33 ,Event Mask on external/internal line 33" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 0. " MR32 ,Event Mask on external/internal line 32" "No interrupt,Interrupt"
|
|
line.long 0x08 "EXTI_RTSR2,Rising trigger selection register"
|
|
bitfld.long 0x08 1. " TR33 ,Rising trigger event configuration bit of line 33" "Disabled,Enabled"
|
|
bitfld.long 0x08 0. " TR32 ,Rising trigger event configuration bit of line 32" "Disabled,Enabled"
|
|
line.long 0x0C "EXTI_FTSR1,Falling trigger selection register"
|
|
bitfld.long 0x0C 1. " TR33 ,Falling trigger event configuration bit of line 33" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " TR32 ,Falling trigger event configuration bit of line 32" "Disabled,Enabled"
|
|
endif
|
|
sif !cpuis("STM32F302*")&&!cpuis("STM32F303*")
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "EXTI_SWIER2N,Software interrupt event register"
|
|
bitfld.long 0x00 1. " SWIER33 ,Software interrupt on line 33" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 0. " SWIER32 ,Software interrupt on line 32" "No interrupt,Interrupt"
|
|
line.long 0x04 "EXTI_PR2,Pending register"
|
|
eventfld.long 0x04 1. " PR33 ,Pending bit on line 33" "Not occurred,Occurred"
|
|
eventfld.long 0x04 0. " PR32 ,Pending bit on line 32" "Not occurred,Occurred"
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x30++0x07
|
|
line.long 0x00 "EXTI_SWIER2N,Software interrupt event register"
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x00 1. " SWIER33 ,Software interrupt on line 33" "No interrupt,Interrupt"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " SWIER32 ,Software interrupt on line 32" "No interrupt,Interrupt"
|
|
line.long 0x04 "EXTI_PR2,Pending register"
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
eventfld.long 0x04 1. " PR33 ,Pending bit on line 33" "Not occurred,Occurred"
|
|
textline " "
|
|
endif
|
|
eventfld.long 0x04 0. " PR32 ,Pending bit on line 32" "Not occurred,Occurred"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC (Analog-to-digital converters)"
|
|
sif ((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC")
|
|
base ad:0x40012400
|
|
width 11.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "ADC_SR,ADC status register"
|
|
bitfld.long 0x00 4. " STRT ,Regular channel Start flag" "Not started,Started"
|
|
bitfld.long 0x00 3. " JSTRT ,Injected channel Start flag" "Not started,Started"
|
|
bitfld.long 0x00 2. " JEOC ,Injected channel end of conversion" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOC ,End of conversion" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " AWD ,Analog watchdog flag" "Not occurred,Occurred"
|
|
line.long 0x04 "ADC_CR1,ADC control register 1"
|
|
bitfld.long 0x04 23. " AWDEN ,Analog watchdog enable on regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 22. " JAWDEN ,Analog watchdog enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 13.--15. " DISCNUM ,Discontinuous mode channel count" "1 channel,2 channels,3 channels,4 channels,5 channels,6 channels,7 channels,8 channels"
|
|
bitfld.long 0x04 12. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 11. " DISCEN ,Discontinuous mode on regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " JAUTO ,Automatic Injected Group conversion" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 9. " AWDSGL ,Enable the watchdog on a single channel in scan mode" "All,Single"
|
|
bitfld.long 0x04 8. " SCAN ,Scan mode" "Disabled,Enabled"
|
|
bitfld.long 0x04 7. " JEOCIE ,Interrupt enable for injected channels" "Disabled,Enabled"
|
|
bitfld.long 0x04 6. " AWDIE ,Analog Watchdog interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 5. " EOCIE ,Interrupt enable for EOC" "Disabled,Enabled"
|
|
bitfld.long 0x04 0.--4. " AWDCH ,Analog watchdog channel select bits" "ADC_IN0,ADC_IN1,ADC_IN2,ADC_IN3,ADC_IN4,ADC_IN5,ADC_IN6,ADC_IN7,ADC_IN8,ADC_IN9,ADC_IN10,ADC_IN11,ADC_IN12,ADC_IN13,ADC_IN14,ADC_IN15,ADC_IN16,ADC_IN17,?..."
|
|
line.long 0x08 "ADC_CR2,ADC control register 2"
|
|
bitfld.long 0x08 23. " TSVREFE ,Temperature sensor and V_REFINT enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 22. " SWSTART ,Start Conversion of regular channels" "Reset,Start"
|
|
bitfld.long 0x08 21. " JSWSTART ,Start Conversion of injected channels" "Reset,Started"
|
|
textline " "
|
|
bitfld.long 0x08 20. " EXTTRIG ,External trigger conversion mode for regular channels" "Disabled,Enabled"
|
|
bitfld.long 0x08 17.--19. " EXTSEL ,External event select for regular group" "TIM19_TRGO,TIM19_TRGO,TIM19_CC4,TIM2_CC2,TIM3_TRGO,TIM4_CC4,EXTI_11,SWSTART"
|
|
bitfld.long 0x08 15. " JEXTTRIG ,External trigger conversion mode for injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 12.--14. " JEXTSEL ,External event select for injected group" "TIM19_CC1,TIM19_CC2,TIM2_TRGO,TIM2_CC1,TIM3_CC4,TIM4_TRGO,EXTI_15,JSWSTART"
|
|
bitfld.long 0x08 11. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x08 8. " DMA ,Direct Memory access mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " RSTCAL ,Reset calibration" "No effect,Reset"
|
|
bitfld.long 0x08 2. " CAL ,A/D Calibration" "Completed,Enabled"
|
|
bitfld.long 0x08 1. " CONT ,Continuous Conversion" "Single,Continuous"
|
|
textline " "
|
|
bitfld.long 0x08 0. " ADON ,A/D Converter ON/OFF" "Disabled,Enabled"
|
|
line.long 0x0C "ADC_SMPR1,ADC sample time register 1"
|
|
sif cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"
|
|
bitfld.long 0x0C 24.--26. " SMP18 ,Channel 18 Sample time selection (cycles)" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 21.--23. " SMP17 ,Channel 17 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x0C 18.--20. " SMP16 ,Channel 16 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x0C 15.--17. " SMP15 ,Channel 15 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x0C 12.--14. " SMP14 ,Channel 14 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
textline " "
|
|
bitfld.long 0x0C 9.--11. " SMP13 ,Channel 13 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x0C 6.--8. " SMP12 ,Channel 12 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x0C 3.--5. " SMP11 ,Channel 11 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x0C 0.--2. " SMP10 ,Channel 10 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
line.long 0x10 "ADC_SMPR2,ADC sample time register 2"
|
|
bitfld.long 0x10 27.--29. " SMP9 ,Channel 9 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x10 24.--26. " SMP8 ,Channel 8 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x10 21.--23. " SMP7 ,Channel 7 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x10 18.--20. " SMP6 ,Channel 6 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
textline " "
|
|
bitfld.long 0x10 15.--17. " SMP5 ,Channel 5 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x10 12.--14. " SMP4 ,Channel 4 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x10 9.--11. " SMP3 ,Channel 3 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x10 6.--8. " SMP2 ,Channel 2 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
textline " "
|
|
bitfld.long 0x10 3.--5. " SMP1 ,Channel 1 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
bitfld.long 0x10 0.--2. " SMP0 ,Channel 0 Sample time selection" "1.5 cycles,7.5 cycles,13.5 cycles,28.5 cycles,41.5 cycles,55.5 cycles,71.5 cycles,239.5"
|
|
width 11.
|
|
textline ""
|
|
group.long 0x14++0x27
|
|
line.long 0x0 "ADC_JOFR1,ADC injected channel data offset register 1"
|
|
hexmask.long.word 0x0 0.--11. 1. " JOFFSET1 ,Data offset for injected channel 1"
|
|
line.long 0x4 "ADC_JOFR2,ADC injected channel data offset register 2"
|
|
hexmask.long.word 0x4 0.--11. 1. " JOFFSET2 ,Data offset for injected channel 2"
|
|
line.long 0x8 "ADC_JOFR3,ADC injected channel data offset register 3"
|
|
hexmask.long.word 0x8 0.--11. 1. " JOFFSET3 ,Data offset for injected channel 3"
|
|
line.long 0xC "ADC_JOFR4,ADC injected channel data offset register 4"
|
|
hexmask.long.word 0xC 0.--11. 1. " JOFFSET4 ,Data offset for injected channel 4"
|
|
line.long 0x10 "ADC_HTR,ADC watchdog high threshold register"
|
|
hexmask.long.word 0x10 0.--11. 1. " HT ,Analog watchdog higher threshold"
|
|
line.long 0x14 "ADC_LTR,ADC watchdog low threshold register"
|
|
hexmask.long.word 0x14 0.--11. 1. " LT ,Analog watchdog lower threshold"
|
|
line.long 0x18 "ADC_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x18 20.--23. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x18 15.--19. " SQ16 ,16th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x18 10.--14. " SQ15 ,15th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x18 5.--9. " SQ14 ,14th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x18 0.--4. " SQ13 ,13th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
line.long 0x1C "ADC_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x1C 25.--29. " SQ12 ,12th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x1C 20.--24. " SQ11 ,11th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x1C 15.--19. " SQ10 ,10th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x1C 10.--14. " SQ9 ,9th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x1C 5.--9. " SQ8 ,8th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x1C 0.--4. " SQ7 ,7th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
line.long 0x20 "ADC_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x20 25.--29. " SQ6 ,6th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 20.--24. " SQ5 ,5th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 15.--19. " SQ4 ,4th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 10.--14. " SQ3 ,3th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x20 5.--9. " SQ2 ,2th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x20 0.--4. " SQ1 ,1th conversion in regular sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
line.long 0x24 "ADC_JSQR,ADC injected sequence register"
|
|
bitfld.long 0x24 20.--21. " JL ,Injected Sequence length" "1,2,3,4"
|
|
bitfld.long 0x24 15.--19. " JSQ4 ,4th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 10.--14. " JSQ3 ,3th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
bitfld.long 0x24 5.--9. " JSQ2 ,2th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
textline " "
|
|
bitfld.long 0x24 0.--4. " JSQ1 ,1th conversion in injected sequence" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
rgroup.long 0x3C++0x13
|
|
line.long 0x0 "ADC_JDR1,ADC injected data register 1"
|
|
hexmask.long.word 0x0 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x4 "ADC_JDR2,ADC injected data register 2"
|
|
hexmask.long.word 0x4 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x8 "ADC_JDR3,ADC injected data register 3"
|
|
hexmask.long.word 0x8 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0xC "ADC_JDR4,ADC injected data register 4"
|
|
hexmask.long.word 0xC 0.--15. 1. " JDATA ,Injected data"
|
|
line.long 0x10 "ADC_DR,ADC regular data register"
|
|
hexmask.long.word 0x10 0.--15. 1. " DATA ,Regular data"
|
|
width 0xB
|
|
elif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"
|
|
tree "ADC1"
|
|
base ad:0x50000000
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADC1_ISR,ADC interrupt and status register"
|
|
eventfld.long 0x00 10. " JQOVF ,Injected context queue overflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " AWD3 ,Analog watchdog 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " AWD2 ,Analog watchdog 2 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 7. " AWD1 ,Analog watchdog 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " JEOS ,Injected channel end of sequence flag" "Not completed,Completed"
|
|
eventfld.long 0x00 5. " JEOC ,Injected channel end of conversion flag" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " OVR ,ADC overrun" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " EOSEQ ,End of sequence flag" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " EOC ,End of conversion flag" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EOSMP ,End of sampling flag" "Not reached,Reached"
|
|
eventfld.long 0x00 0. " ADRDY ,ADC ready" "Not ready,Ready"
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x0C)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ADC1_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC1_IER,ADC interrupt enable register"
|
|
rbitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC1_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC1_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x9000003F)==0x10000000)||(((per.l(ad:0x50000000+0x08))&0x8000003F)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
bitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
bitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
bitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0F)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0F)==0x0C)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0F)==0x0D)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0D)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x07)==0x05)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0B)==0x09)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x07)==0x04)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0B)==0x08)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x03)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x08)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x04)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
rbitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x0C)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x08)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x04)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
rbitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x0C)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "ADC1_SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Sampling time selection 9" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Sampling time selection 8" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Sampling time selection 7" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Sampling time selection 6" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Sampling time selection 5" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Sampling time selection 4" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Sampling time selection 3" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Sampling time selection 2" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Sampling time selection 1" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
line.long 0x04 "ADC1_SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x04 24.--26. " SMP18 ,Sampling time selection 18" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 21.--23. " SMP17 ,Sampling time selection 17" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 18.--20. " SMP16 ,Sampling time selection 16" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " SMP15 ,Sampling time selection 15" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 12.--14. " SMP14 ,Sampling time selection 14" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 9.--11. " SMP13 ,Sampling time selection 13" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " SMP12 ,Sampling time selection 12" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 3.--5. " SMP11 ,Sampling time selection 11" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 0.--2. " SMP10 ,Sampling time selection 10" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "ADC1_TR1,ADC watchdog threshold register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog higher threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog lower threshold"
|
|
line.long 0x04 "ADC1_TR2,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog lower threshold"
|
|
line.long 0x08 "ADC1_TR3,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog lower threshold"
|
|
else
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "ADC1_SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Sampling time selection 9" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Sampling time selection 8" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Sampling time selection 7" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Sampling time selection 6" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Sampling time selection 5" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Sampling time selection 4" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Sampling time selection 3" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Sampling time selection 2" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Sampling time selection 1" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
line.long 0x04 "ADC1_SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x04 24.--26. " SMP18 ,Sampling time selection 18" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 21.--23. " SMP17 ,Sampling time selection 17" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 18.--20. " SMP16 ,Sampling time selection 16" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " SMP15 ,Sampling time selection 15" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 12.--14. " SMP14 ,Sampling time selection 14" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 9.--11. " SMP13 ,Sampling time selection 13" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " SMP12 ,Sampling time selection 12" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 3.--5. " SMP11 ,Sampling time selection 11" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 0.--2. " SMP10 ,Sampling time selection 10" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
rgroup.long 0x20++0x0B
|
|
line.long 0x00 "ADC1_TR1,ADC watchdog threshold register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog higher threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog lower threshold"
|
|
line.long 0x04 "ADC1_TR2,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog lower threshold"
|
|
line.long 0x08 "ADC1_TR3,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog lower threshold"
|
|
endif
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"
|
|
if (((per.l(ad:0x50000000+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC1_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC1_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x50000000+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC1_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC1_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
elif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
if (((per.l(ad:0x50000000+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC1_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC1_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ADC1_DR,ADC data register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Regular Data converted"
|
|
if (((per.l(ad:0x50000000+0x08)&0x01)==0x01))
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "ADC1_JSQR,ADC injected sequence register"
|
|
bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1,2,3,4"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ADC1_JSQR,ADC injected sequence register"
|
|
bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1,2,3,4"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0x60++0x0F
|
|
line.long 0x00 "ADC1_OFR1,ADC offset register 1"
|
|
bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Data offset 1 for the channel"
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "ADC1_JDR1,ADC data register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x60++0x0F
|
|
line.long 0x00 "ADC1_OFR1,ADC offset register 1"
|
|
bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Data offset 1 for the channel"
|
|
rgroup.long 0x80++0x0F
|
|
line.long 0x00 "ADC1_JDR1,ADC data register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0x64++0x0F
|
|
line.long 0x00 "ADC1_OFR2,ADC offset register 2"
|
|
bitfld.long 0x00 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Data offset 2 for the channel"
|
|
group.long 0x84++0x0F
|
|
line.long 0x00 "ADC1_JDR2,ADC data register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x64++0x0F
|
|
line.long 0x00 "ADC1_OFR2,ADC offset register 2"
|
|
bitfld.long 0x00 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Data offset 2 for the channel"
|
|
rgroup.long 0x84++0x0F
|
|
line.long 0x00 "ADC1_JDR2,ADC data register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "ADC1_OFR3,ADC offset register 3"
|
|
bitfld.long 0x00 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET3 ,Data offset 3 for the channel"
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "ADC1_JDR3,ADC data register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x68++0x0F
|
|
line.long 0x00 "ADC1_OFR3,ADC offset register 3"
|
|
bitfld.long 0x00 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET3 ,Data offset 3 for the channel"
|
|
rgroup.long 0x88++0x0F
|
|
line.long 0x00 "ADC1_JDR3,ADC data register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0x6C++0x0F
|
|
line.long 0x00 "ADC1_OFR4,ADC offset register 4"
|
|
bitfld.long 0x00 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET4 ,Data offset 4 for the channel"
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "ADC1_JDR4,ADC data register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x6C++0x0F
|
|
line.long 0x00 "ADC1_OFR4,ADC offset register 4"
|
|
bitfld.long 0x00 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET4 ,Data offset 4 for the channel"
|
|
rgroup.long 0x8C++0x0F
|
|
line.long 0x00 "ADC1_JDR4,ADC data register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "ADC1_AWD2CR,ADC Analog Watchdog 2 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD2CH18 ,Analog watchdog 2 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD2CH17 ,Analog watchdog 2 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD2CH16 ,Analog watchdog 2 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD2CH15 ,Analog watchdog 2 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD2CH14 ,Analog watchdog 2 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD2CH13 ,Analog watchdog 2 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD2CH12 ,Analog watchdog 2 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD2CH11 ,Analog watchdog 2 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD2CH10 ,Analog watchdog 2 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD2CH9 ,Analog watchdog 2 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD2CH8 ,Analog watchdog 2 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD2CH7 ,Analog watchdog 2 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD2CH6 ,Analog watchdog 2 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD2CH5 ,Analog watchdog 2 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD2CH4 ,Analog watchdog 2 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD2CH3 ,Analog watchdog 2 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD2CH2 ,Analog watchdog 2 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD2CH1 ,Analog watchdog 2 channel selection 1" "Not monitored,Monitored"
|
|
else
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "ADC1_AWD2CR,ADC Analog Watchdog 2 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD2CH18 ,Analog watchdog 2 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD2CH17 ,Analog watchdog 2 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD2CH16 ,Analog watchdog 2 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD2CH15 ,Analog watchdog 2 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD2CH14 ,Analog watchdog 2 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD2CH13 ,Analog watchdog 2 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD2CH12 ,Analog watchdog 2 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD2CH11 ,Analog watchdog 2 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD2CH10 ,Analog watchdog 2 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD2CH9 ,Analog watchdog 2 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD2CH8 ,Analog watchdog 2 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD2CH7 ,Analog watchdog 2 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD2CH6 ,Analog watchdog 2 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD2CH5 ,Analog watchdog 2 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD2CH4 ,Analog watchdog 2 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD2CH3 ,Analog watchdog 2 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD2CH2 ,Analog watchdog 2 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD2CH1 ,Analog watchdog 2 channel selection 1" "Not monitored,Monitored"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0xA4++0x07
|
|
line.long 0x00 "ADC1_AWD3CR,ADC Analog Watchdog 3 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD3CH18 ,Analog watchdog 3 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD3CH17 ,Analog watchdog 3 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD3CH16 ,Analog watchdog 3 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD3CH15 ,Analog watchdog 3 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD3CH14 ,Analog watchdog 3 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD3CH13 ,Analog watchdog 3 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD3CH12 ,Analog watchdog 3 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD3CH11 ,Analog watchdog 3 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD3CH10 ,Analog watchdog 3 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3CH9 ,Analog watchdog 3 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD3CH8 ,Analog watchdog 3 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD3CH7 ,Analog watchdog 3 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD3CH6 ,Analog watchdog 3 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD3CH5 ,Analog watchdog 3 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD3CH4 ,Analog watchdog 3 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD3CH3 ,Analog watchdog 3 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD3CH2 ,Analog watchdog 3 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD3CH1 ,Analog watchdog 3 channel selection 1" "Not monitored,Monitored"
|
|
else
|
|
rgroup.long 0xA4++0x07
|
|
line.long 0x00 "ADC1_AWD3CR,ADC Analog Watchdog 3 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD3CH18 ,Analog watchdog 3 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD3CH17 ,Analog watchdog 3 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD3CH16 ,Analog watchdog 3 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD3CH15 ,Analog watchdog 3 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD3CH14 ,Analog watchdog 3 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD3CH13 ,Analog watchdog 3 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD3CH12 ,Analog watchdog 3 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD3CH11 ,Analog watchdog 3 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD3CH10 ,Analog watchdog 3 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3CH9 ,Analog watchdog 3 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD3CH8 ,Analog watchdog 3 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD3CH7 ,Analog watchdog 3 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD3CH6 ,Analog watchdog 3 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD3CH5 ,Analog watchdog 3 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD3CH4 ,Analog watchdog 3 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD3CH3 ,Analog watchdog 3 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD3CH2 ,Analog watchdog 3 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD3CH1 ,Analog watchdog 3 channel selection 1" "Not monitored,Monitored"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x8000003F)==0x00)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "ADC1_DIFSEL,ADC Differential Mode Selection Register 2"
|
|
rbitfld.long 0x00 18. " DIFSEL18 ,Differential mode for channels 18" "Single ended,Differential"
|
|
rbitfld.long 0x00 17. " DIFSEL17 ,Differential mode for channels 17" "Single ended,Differential"
|
|
rbitfld.long 0x00 16. " DIFSEL16 ,Differential mode for channels 16" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFSEL15 ,Differential mode for channels 15" "Single ended,Differential"
|
|
bitfld.long 0x00 14. " DIFSEL14 ,Differential mode for channels 14" "Single ended,Differential"
|
|
bitfld.long 0x00 13. " DIFSEL13 ,Differential mode for channels 13" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIFSEL12 ,Differential mode for channels 12" "Single ended,Differential"
|
|
bitfld.long 0x00 11. " DIFSEL11 ,Differential mode for channels 11" "Single ended,Differential"
|
|
bitfld.long 0x00 10. " DIFSEL10 ,Differential mode for channels 10" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DIFSEL9 ,Differential mode for channels 9" "Single ended,Differential"
|
|
bitfld.long 0x00 8. " DIFSEL8 ,Differential mode for channels 8" "Single ended,Differential"
|
|
bitfld.long 0x00 7. " DIFSEL7 ,Differential mode for channels 7" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DIFSEL6 ,Differential mode for channels 6" "Single ended,Differential"
|
|
bitfld.long 0x00 5. " DIFSEL5 ,Differential mode for channels 5" "Single ended,Differential"
|
|
bitfld.long 0x00 4. " DIFSEL4 ,Differential mode for channels 4" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIFSEL3 ,Differential mode for channels 3" "Single ended,Differential"
|
|
bitfld.long 0x00 2. " DIFSEL2 ,Differential mode for channels 2" "Single ended,Differential"
|
|
bitfld.long 0x00 1. " DIFSEL1 ,Differential mode for channels 1" "Single ended,Differential"
|
|
else
|
|
group.long 0xB0++0x07
|
|
line.long 0x00 "ADC1_DIFSEL,ADC Differential Mode Selection Register 2"
|
|
rbitfld.long 0x00 18. " DIFSEL18 ,Differential mode for channels 18" "Single ended,Differential"
|
|
rbitfld.long 0x00 17. " DIFSEL17 ,Differential mode for channels 17" "Single ended,Differential"
|
|
rbitfld.long 0x00 16. " DIFSEL16 ,Differential mode for channels 16" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " DIFSEL15 ,Differential mode for channels 15" "Single ended,Differential"
|
|
rbitfld.long 0x00 14. " DIFSEL14 ,Differential mode for channels 14" "Single ended,Differential"
|
|
rbitfld.long 0x00 13. " DIFSEL13 ,Differential mode for channels 13" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " DIFSEL12 ,Differential mode for channels 12" "Single ended,Differential"
|
|
rbitfld.long 0x00 11. " DIFSEL11 ,Differential mode for channels 11" "Single ended,Differential"
|
|
rbitfld.long 0x00 10. " DIFSEL10 ,Differential mode for channels 10" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DIFSEL9 ,Differential mode for channels 9" "Single ended,Differential"
|
|
rbitfld.long 0x00 8. " DIFSEL8 ,Differential mode for channels 8" "Single ended,Differential"
|
|
rbitfld.long 0x00 7. " DIFSEL7 ,Differential mode for channels 7" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " DIFSEL6 ,Differential mode for channels 6" "Single ended,Differential"
|
|
rbitfld.long 0x00 5. " DIFSEL5 ,Differential mode for channels 5" "Single ended,Differential"
|
|
rbitfld.long 0x00 4. " DIFSEL4 ,Differential mode for channels 4" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " DIFSEL3 ,Differential mode for channels 3" "Single ended,Differential"
|
|
rbitfld.long 0x00 2. " DIFSEL2 ,Differential mode for channels 2" "Single ended,Differential"
|
|
rbitfld.long 0x00 1. " DIFSEL1 ,Differential mode for channels 1" "Single ended,Differential"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0D)==0x01)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "ADC1_CALFACT,ADC Calibration Factors"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CALFACT_D ,Calibration factors in differential mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CALFACT_S ,Calibration factors in Single-Ended mode"
|
|
else
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "ADC1_CALFACT,ADC Calibration Factors"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CALFACT_D ,Calibration factors in differential mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CALFACT_S ,Calibration factors in Single-Ended mode"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "ADC1"
|
|
base ad:0x50000000
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADC1_ISR,ADC interrupt and status register"
|
|
eventfld.long 0x00 10. " JQOVF ,Injected context queue overflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " AWD3 ,Analog watchdog 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " AWD2 ,Analog watchdog 2 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 7. " AWD1 ,Analog watchdog 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " JEOS ,Injected channel end of sequence flag" "Not completed,Completed"
|
|
eventfld.long 0x00 5. " JEOC ,Injected channel end of conversion flag" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " OVR ,ADC overrun" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " EOSEQ ,End of sequence flag" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " EOC ,End of conversion flag" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EOSMP ,End of sampling flag" "Not reached,Reached"
|
|
eventfld.long 0x00 0. " ADRDY ,ADC ready" "Not ready,Ready"
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x0C)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ADC1_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC1_IER,ADC interrupt enable register"
|
|
rbitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC1_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC1_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x9000003F)==0x10000000)||(((per.l(ad:0x50000000+0x08))&0x8000003F)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
bitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
bitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
bitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0F)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0F)==0x0C)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0F)==0x0D)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0D)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x07)==0x05)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0B)==0x09)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x07)==0x04)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0B)==0x08)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x03)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC1_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x08)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x04)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
rbitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x0C)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x08)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x04)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
rbitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000000+0x08))&0x0C)==0x0C)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC1_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "ADC1_SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Sampling time selection 9" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Sampling time selection 8" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Sampling time selection 7" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Sampling time selection 6" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Sampling time selection 5" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Sampling time selection 4" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Sampling time selection 3" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Sampling time selection 2" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Sampling time selection 1" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
line.long 0x04 "ADC1_SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x04 24.--26. " SMP18 ,Sampling time selection 18" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 21.--23. " SMP17 ,Sampling time selection 17" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 18.--20. " SMP16 ,Sampling time selection 16" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " SMP15 ,Sampling time selection 15" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 12.--14. " SMP14 ,Sampling time selection 14" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 9.--11. " SMP13 ,Sampling time selection 13" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " SMP12 ,Sampling time selection 12" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 3.--5. " SMP11 ,Sampling time selection 11" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 0.--2. " SMP10 ,Sampling time selection 10" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "ADC1_TR1,ADC watchdog threshold register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog higher threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog lower threshold"
|
|
line.long 0x04 "ADC1_TR2,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog lower threshold"
|
|
line.long 0x08 "ADC1_TR3,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog lower threshold"
|
|
else
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "ADC1_SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Sampling time selection 9" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Sampling time selection 8" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Sampling time selection 7" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Sampling time selection 6" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Sampling time selection 5" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Sampling time selection 4" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Sampling time selection 3" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Sampling time selection 2" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Sampling time selection 1" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
line.long 0x04 "ADC1_SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x04 24.--26. " SMP18 ,Sampling time selection 18" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 21.--23. " SMP17 ,Sampling time selection 17" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 18.--20. " SMP16 ,Sampling time selection 16" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " SMP15 ,Sampling time selection 15" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 12.--14. " SMP14 ,Sampling time selection 14" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 9.--11. " SMP13 ,Sampling time selection 13" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " SMP12 ,Sampling time selection 12" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 3.--5. " SMP11 ,Sampling time selection 11" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 0.--2. " SMP10 ,Sampling time selection 10" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
rgroup.long 0x20++0x0B
|
|
line.long 0x00 "ADC1_TR1,ADC watchdog threshold register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog higher threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog lower threshold"
|
|
line.long 0x04 "ADC1_TR2,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog lower threshold"
|
|
line.long 0x08 "ADC1_TR3,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog lower threshold"
|
|
endif
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"
|
|
if (((per.l(ad:0x50000000+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC1_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC1_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x50000000+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC1_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC1_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
elif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
if (((per.l(ad:0x50000000+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC1_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC1_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC1_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC1_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC1_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ADC1_DR,ADC data register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Regular Data converted"
|
|
if (((per.l(ad:0x50000000+0x08)&0x01)==0x01))
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "ADC1_JSQR,ADC injected sequence register"
|
|
bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1,2,3,4"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ADC1_JSQR,ADC injected sequence register"
|
|
bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1,2,3,4"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0x60++0x0F
|
|
line.long 0x00 "ADC1_OFR1,ADC offset register 1"
|
|
bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Data offset 1 for the channel"
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "ADC1_JDR1,ADC data register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x60++0x0F
|
|
line.long 0x00 "ADC1_OFR1,ADC offset register 1"
|
|
bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Data offset 1 for the channel"
|
|
rgroup.long 0x80++0x0F
|
|
line.long 0x00 "ADC1_JDR1,ADC data register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0x64++0x0F
|
|
line.long 0x00 "ADC1_OFR2,ADC offset register 2"
|
|
bitfld.long 0x00 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Data offset 2 for the channel"
|
|
group.long 0x84++0x0F
|
|
line.long 0x00 "ADC1_JDR2,ADC data register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x64++0x0F
|
|
line.long 0x00 "ADC1_OFR2,ADC offset register 2"
|
|
bitfld.long 0x00 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Data offset 2 for the channel"
|
|
rgroup.long 0x84++0x0F
|
|
line.long 0x00 "ADC1_JDR2,ADC data register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "ADC1_OFR3,ADC offset register 3"
|
|
bitfld.long 0x00 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET3 ,Data offset 3 for the channel"
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "ADC1_JDR3,ADC data register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x68++0x0F
|
|
line.long 0x00 "ADC1_OFR3,ADC offset register 3"
|
|
bitfld.long 0x00 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET3 ,Data offset 3 for the channel"
|
|
rgroup.long 0x88++0x0F
|
|
line.long 0x00 "ADC1_JDR3,ADC data register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0x6C++0x0F
|
|
line.long 0x00 "ADC1_OFR4,ADC offset register 4"
|
|
bitfld.long 0x00 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET4 ,Data offset 4 for the channel"
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "ADC1_JDR4,ADC data register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x6C++0x0F
|
|
line.long 0x00 "ADC1_OFR4,ADC offset register 4"
|
|
bitfld.long 0x00 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET4 ,Data offset 4 for the channel"
|
|
rgroup.long 0x8C++0x0F
|
|
line.long 0x00 "ADC1_JDR4,ADC data register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "ADC1_AWD2CR,ADC Analog Watchdog 2 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD2CH18 ,Analog watchdog 2 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD2CH17 ,Analog watchdog 2 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD2CH16 ,Analog watchdog 2 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD2CH15 ,Analog watchdog 2 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD2CH14 ,Analog watchdog 2 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD2CH13 ,Analog watchdog 2 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD2CH12 ,Analog watchdog 2 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD2CH11 ,Analog watchdog 2 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD2CH10 ,Analog watchdog 2 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD2CH9 ,Analog watchdog 2 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD2CH8 ,Analog watchdog 2 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD2CH7 ,Analog watchdog 2 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD2CH6 ,Analog watchdog 2 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD2CH5 ,Analog watchdog 2 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD2CH4 ,Analog watchdog 2 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD2CH3 ,Analog watchdog 2 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD2CH2 ,Analog watchdog 2 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD2CH1 ,Analog watchdog 2 channel selection 1" "Not monitored,Monitored"
|
|
else
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "ADC1_AWD2CR,ADC Analog Watchdog 2 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD2CH18 ,Analog watchdog 2 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD2CH17 ,Analog watchdog 2 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD2CH16 ,Analog watchdog 2 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD2CH15 ,Analog watchdog 2 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD2CH14 ,Analog watchdog 2 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD2CH13 ,Analog watchdog 2 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD2CH12 ,Analog watchdog 2 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD2CH11 ,Analog watchdog 2 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD2CH10 ,Analog watchdog 2 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD2CH9 ,Analog watchdog 2 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD2CH8 ,Analog watchdog 2 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD2CH7 ,Analog watchdog 2 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD2CH6 ,Analog watchdog 2 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD2CH5 ,Analog watchdog 2 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD2CH4 ,Analog watchdog 2 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD2CH3 ,Analog watchdog 2 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD2CH2 ,Analog watchdog 2 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD2CH1 ,Analog watchdog 2 channel selection 1" "Not monitored,Monitored"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0C)==0x00)
|
|
group.long 0xA4++0x07
|
|
line.long 0x00 "ADC1_AWD3CR,ADC Analog Watchdog 3 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD3CH18 ,Analog watchdog 3 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD3CH17 ,Analog watchdog 3 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD3CH16 ,Analog watchdog 3 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD3CH15 ,Analog watchdog 3 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD3CH14 ,Analog watchdog 3 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD3CH13 ,Analog watchdog 3 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD3CH12 ,Analog watchdog 3 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD3CH11 ,Analog watchdog 3 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD3CH10 ,Analog watchdog 3 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3CH9 ,Analog watchdog 3 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD3CH8 ,Analog watchdog 3 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD3CH7 ,Analog watchdog 3 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD3CH6 ,Analog watchdog 3 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD3CH5 ,Analog watchdog 3 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD3CH4 ,Analog watchdog 3 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD3CH3 ,Analog watchdog 3 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD3CH2 ,Analog watchdog 3 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD3CH1 ,Analog watchdog 3 channel selection 1" "Not monitored,Monitored"
|
|
else
|
|
rgroup.long 0xA4++0x07
|
|
line.long 0x00 "ADC1_AWD3CR,ADC Analog Watchdog 3 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD3CH18 ,Analog watchdog 3 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD3CH17 ,Analog watchdog 3 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD3CH16 ,Analog watchdog 3 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD3CH15 ,Analog watchdog 3 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD3CH14 ,Analog watchdog 3 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD3CH13 ,Analog watchdog 3 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD3CH12 ,Analog watchdog 3 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD3CH11 ,Analog watchdog 3 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD3CH10 ,Analog watchdog 3 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3CH9 ,Analog watchdog 3 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD3CH8 ,Analog watchdog 3 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD3CH7 ,Analog watchdog 3 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD3CH6 ,Analog watchdog 3 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD3CH5 ,Analog watchdog 3 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD3CH4 ,Analog watchdog 3 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD3CH3 ,Analog watchdog 3 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD3CH2 ,Analog watchdog 3 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD3CH1 ,Analog watchdog 3 channel selection 1" "Not monitored,Monitored"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x8000003F)==0x00)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "ADC1_DIFSEL,ADC Differential Mode Selection Register 2"
|
|
rbitfld.long 0x00 18. " DIFSEL18 ,Differential mode for channels 18" "Single ended,Differential"
|
|
rbitfld.long 0x00 17. " DIFSEL17 ,Differential mode for channels 17" "Single ended,Differential"
|
|
rbitfld.long 0x00 16. " DIFSEL16 ,Differential mode for channels 16" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFSEL15 ,Differential mode for channels 15" "Single ended,Differential"
|
|
bitfld.long 0x00 14. " DIFSEL14 ,Differential mode for channels 14" "Single ended,Differential"
|
|
bitfld.long 0x00 13. " DIFSEL13 ,Differential mode for channels 13" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIFSEL12 ,Differential mode for channels 12" "Single ended,Differential"
|
|
bitfld.long 0x00 11. " DIFSEL11 ,Differential mode for channels 11" "Single ended,Differential"
|
|
bitfld.long 0x00 10. " DIFSEL10 ,Differential mode for channels 10" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DIFSEL9 ,Differential mode for channels 9" "Single ended,Differential"
|
|
bitfld.long 0x00 8. " DIFSEL8 ,Differential mode for channels 8" "Single ended,Differential"
|
|
bitfld.long 0x00 7. " DIFSEL7 ,Differential mode for channels 7" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DIFSEL6 ,Differential mode for channels 6" "Single ended,Differential"
|
|
bitfld.long 0x00 5. " DIFSEL5 ,Differential mode for channels 5" "Single ended,Differential"
|
|
bitfld.long 0x00 4. " DIFSEL4 ,Differential mode for channels 4" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIFSEL3 ,Differential mode for channels 3" "Single ended,Differential"
|
|
bitfld.long 0x00 2. " DIFSEL2 ,Differential mode for channels 2" "Single ended,Differential"
|
|
bitfld.long 0x00 1. " DIFSEL1 ,Differential mode for channels 1" "Single ended,Differential"
|
|
else
|
|
group.long 0xB0++0x07
|
|
line.long 0x00 "ADC1_DIFSEL,ADC Differential Mode Selection Register 2"
|
|
rbitfld.long 0x00 18. " DIFSEL18 ,Differential mode for channels 18" "Single ended,Differential"
|
|
rbitfld.long 0x00 17. " DIFSEL17 ,Differential mode for channels 17" "Single ended,Differential"
|
|
rbitfld.long 0x00 16. " DIFSEL16 ,Differential mode for channels 16" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " DIFSEL15 ,Differential mode for channels 15" "Single ended,Differential"
|
|
rbitfld.long 0x00 14. " DIFSEL14 ,Differential mode for channels 14" "Single ended,Differential"
|
|
rbitfld.long 0x00 13. " DIFSEL13 ,Differential mode for channels 13" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " DIFSEL12 ,Differential mode for channels 12" "Single ended,Differential"
|
|
rbitfld.long 0x00 11. " DIFSEL11 ,Differential mode for channels 11" "Single ended,Differential"
|
|
rbitfld.long 0x00 10. " DIFSEL10 ,Differential mode for channels 10" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DIFSEL9 ,Differential mode for channels 9" "Single ended,Differential"
|
|
rbitfld.long 0x00 8. " DIFSEL8 ,Differential mode for channels 8" "Single ended,Differential"
|
|
rbitfld.long 0x00 7. " DIFSEL7 ,Differential mode for channels 7" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " DIFSEL6 ,Differential mode for channels 6" "Single ended,Differential"
|
|
rbitfld.long 0x00 5. " DIFSEL5 ,Differential mode for channels 5" "Single ended,Differential"
|
|
rbitfld.long 0x00 4. " DIFSEL4 ,Differential mode for channels 4" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " DIFSEL3 ,Differential mode for channels 3" "Single ended,Differential"
|
|
rbitfld.long 0x00 2. " DIFSEL2 ,Differential mode for channels 2" "Single ended,Differential"
|
|
rbitfld.long 0x00 1. " DIFSEL1 ,Differential mode for channels 1" "Single ended,Differential"
|
|
endif
|
|
if (((per.l(ad:0x50000000+0x08))&0x0D)==0x01)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "ADC1_CALFACT,ADC Calibration Factors"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CALFACT_D ,Calibration factors in differential mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CALFACT_S ,Calibration factors in Single-Ended mode"
|
|
else
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "ADC1_CALFACT,ADC Calibration Factors"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CALFACT_D ,Calibration factors in differential mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CALFACT_S ,Calibration factors in Single-Ended mode"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC2"
|
|
base ad:0x50000100
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADC2_ISR,ADC interrupt and status register"
|
|
eventfld.long 0x00 10. " JQOVF ,Injected context queue overflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " AWD3 ,Analog watchdog 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " AWD2 ,Analog watchdog 2 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 7. " AWD1 ,Analog watchdog 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " JEOS ,Injected channel end of sequence flag" "Not completed,Completed"
|
|
eventfld.long 0x00 5. " JEOC ,Injected channel end of conversion flag" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " OVR ,ADC overrun" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " EOSEQ ,End of sequence flag" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " EOC ,End of conversion flag" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EOSMP ,End of sampling flag" "Not reached,Reached"
|
|
eventfld.long 0x00 0. " ADRDY ,ADC ready" "Not ready,Ready"
|
|
if (((per.l(ad:0x50000100+0x08))&0x0C)==0x0C)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ADC2_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0C)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC2_IER,ADC interrupt enable register"
|
|
rbitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0C)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC2_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC2_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000100+0x08))&0x9000003F)==0x10000000)||(((per.l(ad:0x50000100+0x08))&0x8000003F)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC2_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
bitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
bitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
bitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0F)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC2_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0F)==0x0C)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC2_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0F)==0x0D)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC2_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0D)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC2_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x07)==0x05)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC2_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0B)==0x09)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC2_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x07)==0x04)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC2_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0B)==0x08)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC2_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x03)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC2_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC2_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000100+0x08))&0x0C)==0x00)&&(((per.l(ad:0x50000100+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC2_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0C)==0x08)&&(((per.l(ad:0x50000100+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC2_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0C)==0x04)&&(((per.l(ad:0x50000100+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC2_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
rbitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0C)==0x0C)&&(((per.l(ad:0x50000100+0x0C))&0x01)==0x01)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC2_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0C)==0x00)&&(((per.l(ad:0x50000100+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC2_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0C)==0x08)&&(((per.l(ad:0x50000100+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC2_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0C)==0x04)&&(((per.l(ad:0x50000100+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC2_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
rbitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000100+0x08))&0x0C)==0x0C)&&(((per.l(ad:0x50000100+0x0C))&0x01)==0x00)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC2_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000100+0x08))&0x0C)==0x00)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "ADC2_SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Sampling time selection 9" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Sampling time selection 8" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Sampling time selection 7" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Sampling time selection 6" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Sampling time selection 5" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Sampling time selection 4" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Sampling time selection 3" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Sampling time selection 2" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Sampling time selection 1" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
line.long 0x04 "ADC2_SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x04 24.--26. " SMP18 ,Sampling time selection 18" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 21.--23. " SMP17 ,Sampling time selection 17" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 18.--20. " SMP16 ,Sampling time selection 16" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " SMP15 ,Sampling time selection 15" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 12.--14. " SMP14 ,Sampling time selection 14" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 9.--11. " SMP13 ,Sampling time selection 13" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " SMP12 ,Sampling time selection 12" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 3.--5. " SMP11 ,Sampling time selection 11" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 0.--2. " SMP10 ,Sampling time selection 10" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "ADC2_TR1,ADC watchdog threshold register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog higher threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog lower threshold"
|
|
line.long 0x04 "ADC2_TR2,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog lower threshold"
|
|
line.long 0x08 "ADC2_TR3,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog lower threshold"
|
|
else
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "ADC2_SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Sampling time selection 9" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Sampling time selection 8" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Sampling time selection 7" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Sampling time selection 6" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Sampling time selection 5" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Sampling time selection 4" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Sampling time selection 3" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Sampling time selection 2" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Sampling time selection 1" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
line.long 0x04 "ADC2_SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x04 24.--26. " SMP18 ,Sampling time selection 18" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 21.--23. " SMP17 ,Sampling time selection 17" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 18.--20. " SMP16 ,Sampling time selection 16" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " SMP15 ,Sampling time selection 15" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 12.--14. " SMP14 ,Sampling time selection 14" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 9.--11. " SMP13 ,Sampling time selection 13" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " SMP12 ,Sampling time selection 12" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 3.--5. " SMP11 ,Sampling time selection 11" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 0.--2. " SMP10 ,Sampling time selection 10" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
rgroup.long 0x20++0x0B
|
|
line.long 0x00 "ADC2_TR1,ADC watchdog threshold register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog higher threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog lower threshold"
|
|
line.long 0x04 "ADC2_TR2,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog lower threshold"
|
|
line.long 0x08 "ADC2_TR3,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog lower threshold"
|
|
endif
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"
|
|
if (((per.l(ad:0x50000100+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC2_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC2_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC2_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC2_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC2_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC2_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC2_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC2_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x50000100+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC2_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC2_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC2_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC2_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC2_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC2_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC2_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC2_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
elif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
if (((per.l(ad:0x50000100+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC2_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC2_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC2_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC2_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC2_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC2_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC2_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC2_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ADC2_DR,ADC data register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Regular Data converted"
|
|
if (((per.l(ad:0x50000100+0x08)&0x01)==0x01))
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "ADC2_JSQR,ADC injected sequence register"
|
|
bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1,2,3,4"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ADC2_JSQR,ADC injected sequence register"
|
|
bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1,2,3,4"
|
|
endif
|
|
if (((per.l(ad:0x50000100+0x08))&0x0C)==0x00)
|
|
group.long 0x60++0x0F
|
|
line.long 0x00 "ADC2_OFR1,ADC offset register 1"
|
|
bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Data offset 1 for the channel"
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "ADC2_JDR1,ADC data register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x60++0x0F
|
|
line.long 0x00 "ADC2_OFR1,ADC offset register 1"
|
|
bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Data offset 1 for the channel"
|
|
rgroup.long 0x80++0x0F
|
|
line.long 0x00 "ADC2_JDR1,ADC data register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000100+0x08))&0x0C)==0x00)
|
|
group.long 0x64++0x0F
|
|
line.long 0x00 "ADC2_OFR2,ADC offset register 2"
|
|
bitfld.long 0x00 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Data offset 2 for the channel"
|
|
group.long 0x84++0x0F
|
|
line.long 0x00 "ADC2_JDR2,ADC data register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x64++0x0F
|
|
line.long 0x00 "ADC2_OFR2,ADC offset register 2"
|
|
bitfld.long 0x00 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Data offset 2 for the channel"
|
|
rgroup.long 0x84++0x0F
|
|
line.long 0x00 "ADC2_JDR2,ADC data register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000100+0x08))&0x0C)==0x00)
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "ADC2_OFR3,ADC offset register 3"
|
|
bitfld.long 0x00 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET3 ,Data offset 3 for the channel"
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "ADC2_JDR3,ADC data register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x68++0x0F
|
|
line.long 0x00 "ADC2_OFR3,ADC offset register 3"
|
|
bitfld.long 0x00 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET3 ,Data offset 3 for the channel"
|
|
rgroup.long 0x88++0x0F
|
|
line.long 0x00 "ADC2_JDR3,ADC data register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000100+0x08))&0x0C)==0x00)
|
|
group.long 0x6C++0x0F
|
|
line.long 0x00 "ADC2_OFR4,ADC offset register 4"
|
|
bitfld.long 0x00 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET4 ,Data offset 4 for the channel"
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "ADC2_JDR4,ADC data register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x6C++0x0F
|
|
line.long 0x00 "ADC2_OFR4,ADC offset register 4"
|
|
bitfld.long 0x00 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET4 ,Data offset 4 for the channel"
|
|
rgroup.long 0x8C++0x0F
|
|
line.long 0x00 "ADC2_JDR4,ADC data register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000100+0x08))&0x0C)==0x00)
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "ADC2_AWD2CR,ADC Analog Watchdog 2 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD2CH18 ,Analog watchdog 2 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD2CH17 ,Analog watchdog 2 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD2CH16 ,Analog watchdog 2 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD2CH15 ,Analog watchdog 2 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD2CH14 ,Analog watchdog 2 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD2CH13 ,Analog watchdog 2 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD2CH12 ,Analog watchdog 2 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD2CH11 ,Analog watchdog 2 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD2CH10 ,Analog watchdog 2 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD2CH9 ,Analog watchdog 2 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD2CH8 ,Analog watchdog 2 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD2CH7 ,Analog watchdog 2 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD2CH6 ,Analog watchdog 2 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD2CH5 ,Analog watchdog 2 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD2CH4 ,Analog watchdog 2 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD2CH3 ,Analog watchdog 2 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD2CH2 ,Analog watchdog 2 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD2CH1 ,Analog watchdog 2 channel selection 1" "Not monitored,Monitored"
|
|
else
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "ADC2_AWD2CR,ADC Analog Watchdog 2 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD2CH18 ,Analog watchdog 2 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD2CH17 ,Analog watchdog 2 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD2CH16 ,Analog watchdog 2 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD2CH15 ,Analog watchdog 2 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD2CH14 ,Analog watchdog 2 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD2CH13 ,Analog watchdog 2 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD2CH12 ,Analog watchdog 2 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD2CH11 ,Analog watchdog 2 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD2CH10 ,Analog watchdog 2 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD2CH9 ,Analog watchdog 2 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD2CH8 ,Analog watchdog 2 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD2CH7 ,Analog watchdog 2 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD2CH6 ,Analog watchdog 2 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD2CH5 ,Analog watchdog 2 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD2CH4 ,Analog watchdog 2 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD2CH3 ,Analog watchdog 2 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD2CH2 ,Analog watchdog 2 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD2CH1 ,Analog watchdog 2 channel selection 1" "Not monitored,Monitored"
|
|
endif
|
|
if (((per.l(ad:0x50000100+0x08))&0x0C)==0x00)
|
|
group.long 0xA4++0x07
|
|
line.long 0x00 "ADC2_AWD3CR,ADC Analog Watchdog 3 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD3CH18 ,Analog watchdog 3 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD3CH17 ,Analog watchdog 3 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD3CH16 ,Analog watchdog 3 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD3CH15 ,Analog watchdog 3 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD3CH14 ,Analog watchdog 3 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD3CH13 ,Analog watchdog 3 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD3CH12 ,Analog watchdog 3 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD3CH11 ,Analog watchdog 3 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD3CH10 ,Analog watchdog 3 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3CH9 ,Analog watchdog 3 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD3CH8 ,Analog watchdog 3 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD3CH7 ,Analog watchdog 3 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD3CH6 ,Analog watchdog 3 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD3CH5 ,Analog watchdog 3 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD3CH4 ,Analog watchdog 3 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD3CH3 ,Analog watchdog 3 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD3CH2 ,Analog watchdog 3 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD3CH1 ,Analog watchdog 3 channel selection 1" "Not monitored,Monitored"
|
|
else
|
|
rgroup.long 0xA4++0x07
|
|
line.long 0x00 "ADC2_AWD3CR,ADC Analog Watchdog 3 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD3CH18 ,Analog watchdog 3 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD3CH17 ,Analog watchdog 3 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD3CH16 ,Analog watchdog 3 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD3CH15 ,Analog watchdog 3 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD3CH14 ,Analog watchdog 3 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD3CH13 ,Analog watchdog 3 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD3CH12 ,Analog watchdog 3 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD3CH11 ,Analog watchdog 3 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD3CH10 ,Analog watchdog 3 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3CH9 ,Analog watchdog 3 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD3CH8 ,Analog watchdog 3 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD3CH7 ,Analog watchdog 3 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD3CH6 ,Analog watchdog 3 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD3CH5 ,Analog watchdog 3 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD3CH4 ,Analog watchdog 3 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD3CH3 ,Analog watchdog 3 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD3CH2 ,Analog watchdog 3 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD3CH1 ,Analog watchdog 3 channel selection 1" "Not monitored,Monitored"
|
|
endif
|
|
if (((per.l(ad:0x50000100+0x08))&0x8000003F)==0x00)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "ADC2_DIFSEL,ADC Differential Mode Selection Register 2"
|
|
rbitfld.long 0x00 18. " DIFSEL18 ,Differential mode for channels 18" "Single ended,Differential"
|
|
rbitfld.long 0x00 17. " DIFSEL17 ,Differential mode for channels 17" "Single ended,Differential"
|
|
rbitfld.long 0x00 16. " DIFSEL16 ,Differential mode for channels 16" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFSEL15 ,Differential mode for channels 15" "Single ended,Differential"
|
|
bitfld.long 0x00 14. " DIFSEL14 ,Differential mode for channels 14" "Single ended,Differential"
|
|
bitfld.long 0x00 13. " DIFSEL13 ,Differential mode for channels 13" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIFSEL12 ,Differential mode for channels 12" "Single ended,Differential"
|
|
bitfld.long 0x00 11. " DIFSEL11 ,Differential mode for channels 11" "Single ended,Differential"
|
|
bitfld.long 0x00 10. " DIFSEL10 ,Differential mode for channels 10" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DIFSEL9 ,Differential mode for channels 9" "Single ended,Differential"
|
|
bitfld.long 0x00 8. " DIFSEL8 ,Differential mode for channels 8" "Single ended,Differential"
|
|
bitfld.long 0x00 7. " DIFSEL7 ,Differential mode for channels 7" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DIFSEL6 ,Differential mode for channels 6" "Single ended,Differential"
|
|
bitfld.long 0x00 5. " DIFSEL5 ,Differential mode for channels 5" "Single ended,Differential"
|
|
bitfld.long 0x00 4. " DIFSEL4 ,Differential mode for channels 4" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIFSEL3 ,Differential mode for channels 3" "Single ended,Differential"
|
|
bitfld.long 0x00 2. " DIFSEL2 ,Differential mode for channels 2" "Single ended,Differential"
|
|
bitfld.long 0x00 1. " DIFSEL1 ,Differential mode for channels 1" "Single ended,Differential"
|
|
else
|
|
group.long 0xB0++0x07
|
|
line.long 0x00 "ADC2_DIFSEL,ADC Differential Mode Selection Register 2"
|
|
rbitfld.long 0x00 18. " DIFSEL18 ,Differential mode for channels 18" "Single ended,Differential"
|
|
rbitfld.long 0x00 17. " DIFSEL17 ,Differential mode for channels 17" "Single ended,Differential"
|
|
rbitfld.long 0x00 16. " DIFSEL16 ,Differential mode for channels 16" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " DIFSEL15 ,Differential mode for channels 15" "Single ended,Differential"
|
|
rbitfld.long 0x00 14. " DIFSEL14 ,Differential mode for channels 14" "Single ended,Differential"
|
|
rbitfld.long 0x00 13. " DIFSEL13 ,Differential mode for channels 13" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " DIFSEL12 ,Differential mode for channels 12" "Single ended,Differential"
|
|
rbitfld.long 0x00 11. " DIFSEL11 ,Differential mode for channels 11" "Single ended,Differential"
|
|
rbitfld.long 0x00 10. " DIFSEL10 ,Differential mode for channels 10" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DIFSEL9 ,Differential mode for channels 9" "Single ended,Differential"
|
|
rbitfld.long 0x00 8. " DIFSEL8 ,Differential mode for channels 8" "Single ended,Differential"
|
|
rbitfld.long 0x00 7. " DIFSEL7 ,Differential mode for channels 7" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " DIFSEL6 ,Differential mode for channels 6" "Single ended,Differential"
|
|
rbitfld.long 0x00 5. " DIFSEL5 ,Differential mode for channels 5" "Single ended,Differential"
|
|
rbitfld.long 0x00 4. " DIFSEL4 ,Differential mode for channels 4" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " DIFSEL3 ,Differential mode for channels 3" "Single ended,Differential"
|
|
rbitfld.long 0x00 2. " DIFSEL2 ,Differential mode for channels 2" "Single ended,Differential"
|
|
rbitfld.long 0x00 1. " DIFSEL1 ,Differential mode for channels 1" "Single ended,Differential"
|
|
endif
|
|
if (((per.l(ad:0x50000100+0x08))&0x0D)==0x01)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "ADC2_CALFACT,ADC Calibration Factors"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CALFACT_D ,Calibration factors in differential mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CALFACT_S ,Calibration factors in Single-Ended mode"
|
|
else
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "ADC2_CALFACT,ADC Calibration Factors"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CALFACT_D ,Calibration factors in differential mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CALFACT_S ,Calibration factors in Single-Ended mode"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC")&&!cpuis("STM32F334?4")&&!cpuis("STM32F334?6")&&!cpuis("STM32F334?8")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
tree "ADC3"
|
|
base ad:0x50000400
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADC3_ISR,ADC interrupt and status register"
|
|
eventfld.long 0x00 10. " JQOVF ,Injected context queue overflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " AWD3 ,Analog watchdog 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " AWD2 ,Analog watchdog 2 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 7. " AWD1 ,Analog watchdog 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " JEOS ,Injected channel end of sequence flag" "Not completed,Completed"
|
|
eventfld.long 0x00 5. " JEOC ,Injected channel end of conversion flag" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " OVR ,ADC overrun" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " EOSEQ ,End of sequence flag" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " EOC ,End of conversion flag" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EOSMP ,End of sampling flag" "Not reached,Reached"
|
|
eventfld.long 0x00 0. " ADRDY ,ADC ready" "Not ready,Ready"
|
|
if (((per.l(ad:0x50000400+0x08))&0x0C)==0x0C)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ADC3_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0C)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC3_IER,ADC interrupt enable register"
|
|
rbitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0C)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC3_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC3_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000400+0x08))&0x9000003F)==0x10000000)||(((per.l(ad:0x50000400+0x08))&0x8000003F)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC3_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
bitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
bitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
bitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0F)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC3_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0F)==0x0C)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC3_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0F)==0x0D)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC3_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0D)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC3_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x07)==0x05)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC3_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0B)==0x09)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC3_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x07)==0x04)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC3_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0B)==0x08)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC3_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x03)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC3_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC3_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000400+0x08))&0x0C)==0x00)&&(((per.l(ad:0x50000400+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC3_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0C)==0x08)&&(((per.l(ad:0x50000400+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC3_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0C)==0x04)&&(((per.l(ad:0x50000400+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC3_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
rbitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0C)==0x0C)&&(((per.l(ad:0x50000400+0x0C))&0x01)==0x01)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC3_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0C)==0x00)&&(((per.l(ad:0x50000400+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC3_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0C)==0x08)&&(((per.l(ad:0x50000400+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC3_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0C)==0x04)&&(((per.l(ad:0x50000400+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC3_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
rbitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000400+0x08))&0x0C)==0x0C)&&(((per.l(ad:0x50000400+0x0C))&0x01)==0x00)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC3_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000400+0x08))&0x0C)==0x00)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "ADC3_SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Sampling time selection 9" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Sampling time selection 8" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Sampling time selection 7" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Sampling time selection 6" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Sampling time selection 5" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Sampling time selection 4" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Sampling time selection 3" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Sampling time selection 2" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Sampling time selection 1" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
line.long 0x04 "ADC3_SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x04 24.--26. " SMP18 ,Sampling time selection 18" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 21.--23. " SMP17 ,Sampling time selection 17" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 18.--20. " SMP16 ,Sampling time selection 16" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " SMP15 ,Sampling time selection 15" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 12.--14. " SMP14 ,Sampling time selection 14" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 9.--11. " SMP13 ,Sampling time selection 13" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " SMP12 ,Sampling time selection 12" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 3.--5. " SMP11 ,Sampling time selection 11" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 0.--2. " SMP10 ,Sampling time selection 10" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "ADC3_TR1,ADC watchdog threshold register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog higher threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog lower threshold"
|
|
line.long 0x04 "ADC3_TR2,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog lower threshold"
|
|
line.long 0x08 "ADC3_TR3,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog lower threshold"
|
|
else
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "ADC3_SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Sampling time selection 9" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Sampling time selection 8" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Sampling time selection 7" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Sampling time selection 6" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Sampling time selection 5" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Sampling time selection 4" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Sampling time selection 3" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Sampling time selection 2" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Sampling time selection 1" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
line.long 0x04 "ADC3_SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x04 24.--26. " SMP18 ,Sampling time selection 18" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 21.--23. " SMP17 ,Sampling time selection 17" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 18.--20. " SMP16 ,Sampling time selection 16" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " SMP15 ,Sampling time selection 15" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 12.--14. " SMP14 ,Sampling time selection 14" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 9.--11. " SMP13 ,Sampling time selection 13" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " SMP12 ,Sampling time selection 12" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 3.--5. " SMP11 ,Sampling time selection 11" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 0.--2. " SMP10 ,Sampling time selection 10" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
rgroup.long 0x20++0x0B
|
|
line.long 0x00 "ADC3_TR1,ADC watchdog threshold register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog higher threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog lower threshold"
|
|
line.long 0x04 "ADC3_TR2,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog lower threshold"
|
|
line.long 0x08 "ADC3_TR3,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog lower threshold"
|
|
endif
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"
|
|
if (((per.l(ad:0x50000400+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC3_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC3_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC3_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC3_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC3_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC3_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC3_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC3_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x50000400+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC3_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC3_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC3_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC3_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC3_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC3_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC3_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC3_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
elif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
if (((per.l(ad:0x50000400+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC3_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC3_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC3_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC3_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC3_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC3_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC3_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC3_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ADC3_DR,ADC data register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Regular Data converted"
|
|
if (((per.l(ad:0x50000400+0x08)&0x01)==0x01))
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "ADC3_JSQR,ADC injected sequence register"
|
|
bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1,2,3,4"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ADC3_JSQR,ADC injected sequence register"
|
|
bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1,2,3,4"
|
|
endif
|
|
if (((per.l(ad:0x50000400+0x08))&0x0C)==0x00)
|
|
group.long 0x60++0x0F
|
|
line.long 0x00 "ADC3_OFR1,ADC offset register 1"
|
|
bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Data offset 1 for the channel"
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "ADC3_JDR1,ADC data register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x60++0x0F
|
|
line.long 0x00 "ADC3_OFR1,ADC offset register 1"
|
|
bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Data offset 1 for the channel"
|
|
rgroup.long 0x80++0x0F
|
|
line.long 0x00 "ADC3_JDR1,ADC data register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000400+0x08))&0x0C)==0x00)
|
|
group.long 0x64++0x0F
|
|
line.long 0x00 "ADC3_OFR2,ADC offset register 2"
|
|
bitfld.long 0x00 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Data offset 2 for the channel"
|
|
group.long 0x84++0x0F
|
|
line.long 0x00 "ADC3_JDR2,ADC data register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x64++0x0F
|
|
line.long 0x00 "ADC3_OFR2,ADC offset register 2"
|
|
bitfld.long 0x00 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Data offset 2 for the channel"
|
|
rgroup.long 0x84++0x0F
|
|
line.long 0x00 "ADC3_JDR2,ADC data register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000400+0x08))&0x0C)==0x00)
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "ADC3_OFR3,ADC offset register 3"
|
|
bitfld.long 0x00 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET3 ,Data offset 3 for the channel"
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "ADC3_JDR3,ADC data register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x68++0x0F
|
|
line.long 0x00 "ADC3_OFR3,ADC offset register 3"
|
|
bitfld.long 0x00 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET3 ,Data offset 3 for the channel"
|
|
rgroup.long 0x88++0x0F
|
|
line.long 0x00 "ADC3_JDR3,ADC data register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000400+0x08))&0x0C)==0x00)
|
|
group.long 0x6C++0x0F
|
|
line.long 0x00 "ADC3_OFR4,ADC offset register 4"
|
|
bitfld.long 0x00 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET4 ,Data offset 4 for the channel"
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "ADC3_JDR4,ADC data register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x6C++0x0F
|
|
line.long 0x00 "ADC3_OFR4,ADC offset register 4"
|
|
bitfld.long 0x00 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET4 ,Data offset 4 for the channel"
|
|
rgroup.long 0x8C++0x0F
|
|
line.long 0x00 "ADC3_JDR4,ADC data register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000400+0x08))&0x0C)==0x00)
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "ADC3_AWD2CR,ADC Analog Watchdog 2 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD2CH18 ,Analog watchdog 2 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD2CH17 ,Analog watchdog 2 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD2CH16 ,Analog watchdog 2 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD2CH15 ,Analog watchdog 2 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD2CH14 ,Analog watchdog 2 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD2CH13 ,Analog watchdog 2 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD2CH12 ,Analog watchdog 2 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD2CH11 ,Analog watchdog 2 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD2CH10 ,Analog watchdog 2 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD2CH9 ,Analog watchdog 2 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD2CH8 ,Analog watchdog 2 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD2CH7 ,Analog watchdog 2 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD2CH6 ,Analog watchdog 2 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD2CH5 ,Analog watchdog 2 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD2CH4 ,Analog watchdog 2 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD2CH3 ,Analog watchdog 2 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD2CH2 ,Analog watchdog 2 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD2CH1 ,Analog watchdog 2 channel selection 1" "Not monitored,Monitored"
|
|
else
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "ADC3_AWD2CR,ADC Analog Watchdog 2 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD2CH18 ,Analog watchdog 2 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD2CH17 ,Analog watchdog 2 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD2CH16 ,Analog watchdog 2 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD2CH15 ,Analog watchdog 2 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD2CH14 ,Analog watchdog 2 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD2CH13 ,Analog watchdog 2 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD2CH12 ,Analog watchdog 2 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD2CH11 ,Analog watchdog 2 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD2CH10 ,Analog watchdog 2 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD2CH9 ,Analog watchdog 2 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD2CH8 ,Analog watchdog 2 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD2CH7 ,Analog watchdog 2 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD2CH6 ,Analog watchdog 2 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD2CH5 ,Analog watchdog 2 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD2CH4 ,Analog watchdog 2 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD2CH3 ,Analog watchdog 2 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD2CH2 ,Analog watchdog 2 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD2CH1 ,Analog watchdog 2 channel selection 1" "Not monitored,Monitored"
|
|
endif
|
|
if (((per.l(ad:0x50000400+0x08))&0x0C)==0x00)
|
|
group.long 0xA4++0x07
|
|
line.long 0x00 "ADC3_AWD3CR,ADC Analog Watchdog 3 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD3CH18 ,Analog watchdog 3 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD3CH17 ,Analog watchdog 3 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD3CH16 ,Analog watchdog 3 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD3CH15 ,Analog watchdog 3 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD3CH14 ,Analog watchdog 3 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD3CH13 ,Analog watchdog 3 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD3CH12 ,Analog watchdog 3 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD3CH11 ,Analog watchdog 3 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD3CH10 ,Analog watchdog 3 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3CH9 ,Analog watchdog 3 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD3CH8 ,Analog watchdog 3 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD3CH7 ,Analog watchdog 3 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD3CH6 ,Analog watchdog 3 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD3CH5 ,Analog watchdog 3 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD3CH4 ,Analog watchdog 3 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD3CH3 ,Analog watchdog 3 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD3CH2 ,Analog watchdog 3 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD3CH1 ,Analog watchdog 3 channel selection 1" "Not monitored,Monitored"
|
|
else
|
|
rgroup.long 0xA4++0x07
|
|
line.long 0x00 "ADC3_AWD3CR,ADC Analog Watchdog 3 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD3CH18 ,Analog watchdog 3 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD3CH17 ,Analog watchdog 3 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD3CH16 ,Analog watchdog 3 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD3CH15 ,Analog watchdog 3 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD3CH14 ,Analog watchdog 3 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD3CH13 ,Analog watchdog 3 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD3CH12 ,Analog watchdog 3 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD3CH11 ,Analog watchdog 3 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD3CH10 ,Analog watchdog 3 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3CH9 ,Analog watchdog 3 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD3CH8 ,Analog watchdog 3 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD3CH7 ,Analog watchdog 3 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD3CH6 ,Analog watchdog 3 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD3CH5 ,Analog watchdog 3 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD3CH4 ,Analog watchdog 3 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD3CH3 ,Analog watchdog 3 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD3CH2 ,Analog watchdog 3 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD3CH1 ,Analog watchdog 3 channel selection 1" "Not monitored,Monitored"
|
|
endif
|
|
if (((per.l(ad:0x50000400+0x08))&0x8000003F)==0x00)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "ADC3_DIFSEL,ADC Differential Mode Selection Register 2"
|
|
rbitfld.long 0x00 18. " DIFSEL18 ,Differential mode for channels 18" "Single ended,Differential"
|
|
rbitfld.long 0x00 17. " DIFSEL17 ,Differential mode for channels 17" "Single ended,Differential"
|
|
rbitfld.long 0x00 16. " DIFSEL16 ,Differential mode for channels 16" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFSEL15 ,Differential mode for channels 15" "Single ended,Differential"
|
|
bitfld.long 0x00 14. " DIFSEL14 ,Differential mode for channels 14" "Single ended,Differential"
|
|
bitfld.long 0x00 13. " DIFSEL13 ,Differential mode for channels 13" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIFSEL12 ,Differential mode for channels 12" "Single ended,Differential"
|
|
bitfld.long 0x00 11. " DIFSEL11 ,Differential mode for channels 11" "Single ended,Differential"
|
|
bitfld.long 0x00 10. " DIFSEL10 ,Differential mode for channels 10" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DIFSEL9 ,Differential mode for channels 9" "Single ended,Differential"
|
|
bitfld.long 0x00 8. " DIFSEL8 ,Differential mode for channels 8" "Single ended,Differential"
|
|
bitfld.long 0x00 7. " DIFSEL7 ,Differential mode for channels 7" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DIFSEL6 ,Differential mode for channels 6" "Single ended,Differential"
|
|
bitfld.long 0x00 5. " DIFSEL5 ,Differential mode for channels 5" "Single ended,Differential"
|
|
bitfld.long 0x00 4. " DIFSEL4 ,Differential mode for channels 4" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIFSEL3 ,Differential mode for channels 3" "Single ended,Differential"
|
|
bitfld.long 0x00 2. " DIFSEL2 ,Differential mode for channels 2" "Single ended,Differential"
|
|
bitfld.long 0x00 1. " DIFSEL1 ,Differential mode for channels 1" "Single ended,Differential"
|
|
else
|
|
group.long 0xB0++0x07
|
|
line.long 0x00 "ADC3_DIFSEL,ADC Differential Mode Selection Register 2"
|
|
rbitfld.long 0x00 18. " DIFSEL18 ,Differential mode for channels 18" "Single ended,Differential"
|
|
rbitfld.long 0x00 17. " DIFSEL17 ,Differential mode for channels 17" "Single ended,Differential"
|
|
rbitfld.long 0x00 16. " DIFSEL16 ,Differential mode for channels 16" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " DIFSEL15 ,Differential mode for channels 15" "Single ended,Differential"
|
|
rbitfld.long 0x00 14. " DIFSEL14 ,Differential mode for channels 14" "Single ended,Differential"
|
|
rbitfld.long 0x00 13. " DIFSEL13 ,Differential mode for channels 13" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " DIFSEL12 ,Differential mode for channels 12" "Single ended,Differential"
|
|
rbitfld.long 0x00 11. " DIFSEL11 ,Differential mode for channels 11" "Single ended,Differential"
|
|
rbitfld.long 0x00 10. " DIFSEL10 ,Differential mode for channels 10" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DIFSEL9 ,Differential mode for channels 9" "Single ended,Differential"
|
|
rbitfld.long 0x00 8. " DIFSEL8 ,Differential mode for channels 8" "Single ended,Differential"
|
|
rbitfld.long 0x00 7. " DIFSEL7 ,Differential mode for channels 7" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " DIFSEL6 ,Differential mode for channels 6" "Single ended,Differential"
|
|
rbitfld.long 0x00 5. " DIFSEL5 ,Differential mode for channels 5" "Single ended,Differential"
|
|
rbitfld.long 0x00 4. " DIFSEL4 ,Differential mode for channels 4" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " DIFSEL3 ,Differential mode for channels 3" "Single ended,Differential"
|
|
rbitfld.long 0x00 2. " DIFSEL2 ,Differential mode for channels 2" "Single ended,Differential"
|
|
rbitfld.long 0x00 1. " DIFSEL1 ,Differential mode for channels 1" "Single ended,Differential"
|
|
endif
|
|
if (((per.l(ad:0x50000400+0x08))&0x0D)==0x01)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "ADC3_CALFACT,ADC Calibration Factors"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CALFACT_D ,Calibration factors in differential mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CALFACT_S ,Calibration factors in Single-Ended mode"
|
|
else
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "ADC3_CALFACT,ADC Calibration Factors"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CALFACT_D ,Calibration factors in differential mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CALFACT_S ,Calibration factors in Single-Ended mode"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC4"
|
|
base ad:0x50000500
|
|
width 17.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "ADC4_ISR,ADC interrupt and status register"
|
|
eventfld.long 0x00 10. " JQOVF ,Injected context queue overflow" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " AWD3 ,Analog watchdog 3 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 8. " AWD2 ,Analog watchdog 2 flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 7. " AWD1 ,Analog watchdog 1 flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " JEOS ,Injected channel end of sequence flag" "Not completed,Completed"
|
|
eventfld.long 0x00 5. " JEOC ,Injected channel end of conversion flag" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 4. " OVR ,ADC overrun" "Not occurred,Occurred"
|
|
eventfld.long 0x00 3. " EOSEQ ,End of sequence flag" "Not completed,Completed"
|
|
eventfld.long 0x00 2. " EOC ,End of conversion flag" "Not completed,Completed"
|
|
textline " "
|
|
eventfld.long 0x00 1. " EOSMP ,End of sampling flag" "Not reached,Reached"
|
|
eventfld.long 0x00 0. " ADRDY ,ADC ready" "Not ready,Ready"
|
|
if (((per.l(ad:0x50000500+0x08))&0x0C)==0x0C)
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ADC4_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0C)==0x08)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC4_IER,ADC interrupt enable register"
|
|
rbitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0C)==0x04)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC4_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ADC4_IER,ADC interrupt enable register"
|
|
bitfld.long 0x00 10. " JQOVFIE ,Injected context queue overflow interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " AWD3IE ,Analog watchdog 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " AWD2IE ,Analog watchdog 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " AWD1IE ,Analog watchdog 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " JEOSIE ,End of injected sequence of conversions interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " JEOCIE ,End of injected conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " OVRIE ,Overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " EOSIE ,End of conversion sequence interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " EOCIE ,End of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " EOSMPIE ,End of sampling flag interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ADRDYIE ,ADC ready interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000500+0x08))&0x9000003F)==0x10000000)||(((per.l(ad:0x50000500+0x08))&0x8000003F)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC4_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
bitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
bitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
bitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0F)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC4_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0F)==0x0C)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC4_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0F)==0x0D)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC4_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0D)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC4_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
bitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x07)==0x05)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC4_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0B)==0x09)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC4_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x07)==0x04)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC4_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0B)==0x08)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC4_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
bitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x03)==0x01)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC4_CR,ADC control register"
|
|
rbitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
bitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC4_CR,ADC control register"
|
|
bitfld.long 0x00 31. " ADCAL ,ADC calibration" "Completed,In progress"
|
|
rbitfld.long 0x00 30. " ADCALDIF ,Differential mode for calibration" "Single-ended,Differential"
|
|
rbitfld.long 0x00 28.--29. " ADVREGEN ,ADC voltage regulator enable" "Intermediate state,Enabled,Disabled,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 5. " JADSTP ,ADC stop of injected conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 4. " ADSTP ,ADC stop of regular conversion command" "No effect,Stop"
|
|
rbitfld.long 0x00 3. " JADSTART ,ADC start of injected conversion" "No effect,Start"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " ADSTART ,ADC start of regular conversion command" "No effect,Start"
|
|
rbitfld.long 0x00 1. " ADDIS ,ADC disable command" "No,Yes"
|
|
rbitfld.long 0x00 0. " ADEN ,ADC enable command" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000500+0x08))&0x0C)==0x00)&&(((per.l(ad:0x50000500+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC4_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0C)==0x08)&&(((per.l(ad:0x50000500+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC4_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0C)==0x04)&&(((per.l(ad:0x50000500+0x0C))&0x01)==0x01)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC4_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
rbitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
rbitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0C)==0x0C)&&(((per.l(ad:0x50000500+0x0C))&0x01)==0x01)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC4_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
bitfld.long 0x00 1. " DMACFG ,Direct memory access configuration" "One shot,Circular"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0C)==0x00)&&(((per.l(ad:0x50000500+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC4_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0C)==0x08)&&(((per.l(ad:0x50000500+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC4_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
rbitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rbitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0C)==0x04)&&(((per.l(ad:0x50000500+0x0C))&0x01)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ADC4_CFGR,ADC configuration register"
|
|
rbitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
rbitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
rbitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
rbitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
rbitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
rbitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
rbitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x50000500+0x08))&0x0C)==0x0C)&&(((per.l(ad:0x50000500+0x0C))&0x01)==0x00)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "ADC4_CFGR,ADC configuration register"
|
|
bitfld.long 0x00 26.--30. " AWDCH ,Analog watchdog channel selection" ",Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,Channel 9,Channel 10,Channel 11,Channel 12,Channel 13,Channel 14,Channel 15,Channel 16,Channel 17,?..."
|
|
bitfld.long 0x00 25. " JAUTO ,Automatic injected group conversion enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " JAWD1EN ,Analog watchdog 1 enable on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1EN ,Analog watchdog enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " AWD1SGL ,Enable the watchdog on a single channel or on all channels" "All,Single"
|
|
bitfld.long 0x00 21. " JQM ,JSQR queue mode" "Mode 0,Mode 1"
|
|
textline " "
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 20. " JDISCEN ,Discontinuous mode on injected channels" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17.--19. " DISCNUM ,Discontinuous mode channel count" "1 Channel,2 Channels,3 Channels,4 Channels,5 Channels,6 Channels,7 Channels,8 Channels"
|
|
bitfld.long 0x00 16. 13. " DISCEN/CONT ,Discontinuous Mode/(Single / continuous) conversion mode" "Disabled/single,Disabled/continuous,Enabled/single,?..."
|
|
bitfld.long 0x00 14. " AUTDLY ,Delayed conversion mode" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OVRMOD ,Overrun management mode" "Preserved,Overwritten"
|
|
bitfld.long 0x00 10.--11. " EXTEN ,External trigger enable and polarity selection" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 6.--9. " EXTSEL ,External trigger selection" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 5. " ALIGN ,Data alignment" "Right,Left"
|
|
bitfld.long 0x00 3.--4. " RES ,Data resolution" "12 bits,10 bits,8 bits,6 bits"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DMAEN ,Direct memory access enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x50000500+0x08))&0x0C)==0x00)
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "ADC4_SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Sampling time selection 9" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Sampling time selection 8" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Sampling time selection 7" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Sampling time selection 6" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Sampling time selection 5" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Sampling time selection 4" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Sampling time selection 3" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Sampling time selection 2" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Sampling time selection 1" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
line.long 0x04 "ADC4_SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x04 24.--26. " SMP18 ,Sampling time selection 18" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 21.--23. " SMP17 ,Sampling time selection 17" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 18.--20. " SMP16 ,Sampling time selection 16" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " SMP15 ,Sampling time selection 15" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 12.--14. " SMP14 ,Sampling time selection 14" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 9.--11. " SMP13 ,Sampling time selection 13" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " SMP12 ,Sampling time selection 12" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 3.--5. " SMP11 ,Sampling time selection 11" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 0.--2. " SMP10 ,Sampling time selection 10" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
group.long 0x20++0x0B
|
|
line.long 0x00 "ADC4_TR1,ADC watchdog threshold register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog higher threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog lower threshold"
|
|
line.long 0x04 "ADC4_TR2,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog lower threshold"
|
|
line.long 0x08 "ADC4_TR3,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog lower threshold"
|
|
else
|
|
rgroup.long 0x14++0x07
|
|
line.long 0x00 "ADC4_SMPR1,ADC sampling time register 1"
|
|
bitfld.long 0x00 27.--29. " SMP9 ,Sampling time selection 9" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 24.--26. " SMP8 ,Sampling time selection 8" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 21.--23. " SMP7 ,Sampling time selection 7" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " SMP6 ,Sampling time selection 6" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 15.--17. " SMP5 ,Sampling time selection 5" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 12.--14. " SMP4 ,Sampling time selection 4" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x00 9.--11. " SMP3 ,Sampling time selection 3" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 6.--8. " SMP2 ,Sampling time selection 2" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x00 3.--5. " SMP1 ,Sampling time selection 1" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
line.long 0x04 "ADC4_SMPR2,ADC sampling time register 2"
|
|
bitfld.long 0x04 24.--26. " SMP18 ,Sampling time selection 18" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 21.--23. " SMP17 ,Sampling time selection 17" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 18.--20. " SMP16 ,Sampling time selection 16" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 15.--17. " SMP15 ,Sampling time selection 15" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 12.--14. " SMP14 ,Sampling time selection 14" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 9.--11. " SMP13 ,Sampling time selection 13" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
textline " "
|
|
bitfld.long 0x04 6.--8. " SMP12 ,Sampling time selection 12" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 3.--5. " SMP11 ,Sampling time selection 11" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
bitfld.long 0x04 0.--2. " SMP10 ,Sampling time selection 10" "1.5 cycles,2.5 cycles,4.5 cycles,7.5 cycles,19.5 cycles,61.5 cycles,181.5 cycles,601.5 cycles"
|
|
rgroup.long 0x20++0x0B
|
|
line.long 0x00 "ADC4_TR1,ADC watchdog threshold register"
|
|
hexmask.long.word 0x00 16.--27. 1. " HT1 ,Analog watchdog higher threshold"
|
|
hexmask.long.word 0x00 0.--11. 1. " LT1 ,Analog watchdog lower threshold"
|
|
line.long 0x04 "ADC4_TR2,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x04 16.--23. 1. " HT2 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x04 0.--7. 1. " LT2 ,Analog watchdog lower threshold"
|
|
line.long 0x08 "ADC4_TR3,ADC watchdog threshold register"
|
|
hexmask.long.byte 0x08 16.--23. 1. " HT3 ,Analog watchdog higher threshold"
|
|
hexmask.long.byte 0x08 0.--7. 1. " LT3 ,Analog watchdog lower threshold"
|
|
endif
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"
|
|
if (((per.l(ad:0x50000500+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC4_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC4_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC4_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC4_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC4_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC4_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC4_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC4_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x50000500+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC4_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC4_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC4_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC4_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC4_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC4_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC4_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC4_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
elif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
if (((per.l(ad:0x50000500+0x08)&0x40)==0x40))
|
|
rgroup.long 0x30++0x0F
|
|
line.long 0x00 "ADC4_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC4_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC4_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC4_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
else
|
|
group.long 0x30++0x0F
|
|
line.long 0x00 "ADC4_SQR1,ADC regular sequence register 1"
|
|
bitfld.long 0x00 24.--28. " SQ4 ,4th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 18.--22. " SQ3 ,3rd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 12.--16. " SQ2 ,2nd conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 6.--10. " SQ1 ,1st conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 0.--3. " L ,Regular channel sequence length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
line.long 0x04 "ADC4_SQR2,ADC regular sequence register 2"
|
|
bitfld.long 0x04 24.--28. " SQ9 ,9th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 18.--22. " SQ8 ,8th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 12.--16. " SQ7 ,7th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x04 6.--10. " SQ6 ,6th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x04 0.--4. " SQ5 ,5th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x08 "ADC4_SQR3,ADC regular sequence register 3"
|
|
bitfld.long 0x08 24.--28. " SQ14 ,14th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 18.--22. " SQ13 ,13th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 12.--16. " SQ12 ,12th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x08 6.--10. " SQ11 ,11th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x08 0.--4. " SQ10 ,10th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
line.long 0x0C "ADC4_SQR4,ADC regular sequence register 4"
|
|
bitfld.long 0x0C 6.--10. " SQ16 ,16th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x0C 0.--4. " SQ15 ,15th conversion in regular sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
endif
|
|
endif
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "ADC4_DR,ADC data register"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA ,Regular Data converted"
|
|
if (((per.l(ad:0x50000500+0x08)&0x01)==0x01))
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "ADC4_JSQR,ADC injected sequence register"
|
|
bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1,2,3,4"
|
|
else
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "ADC4_JSQR,ADC injected sequence register"
|
|
bitfld.long 0x00 26.--30. " JSQ4 ,4th conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 20.--24. " JSQ3 ,3rd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 14.--18. " JSQ2 ,2nd conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.long 0x00 8.--12. " JSQ1 ,1st conversion in the injected sequence" ",1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.long 0x00 6.--7. " JEXTEN ,External Trigger Enable and Polarity Selection for injected channels" "Disabled,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 2.--5. " JEXTSEL ,External Trigger Selection for injected group" "Event 0,Event 1,Event 2,Event 3,Event 4,Event 5,Event 6,Event 7,Event 8,Event 9,Event 10,Event 11,Event 12,Event 13,Event 14,Event 15"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " JL ,Injected channel sequence length" "1,2,3,4"
|
|
endif
|
|
if (((per.l(ad:0x50000500+0x08))&0x0C)==0x00)
|
|
group.long 0x60++0x0F
|
|
line.long 0x00 "ADC4_OFR1,ADC offset register 1"
|
|
bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Data offset 1 for the channel"
|
|
group.long 0x80++0x0F
|
|
line.long 0x00 "ADC4_JDR1,ADC data register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x60++0x0F
|
|
line.long 0x00 "ADC4_OFR1,ADC offset register 1"
|
|
bitfld.long 0x00 31. " OFFSET1_EN ,Offset 1 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET1_CH ,Channel selection for the Data offset 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Data offset 1 for the channel"
|
|
rgroup.long 0x80++0x0F
|
|
line.long 0x00 "ADC4_JDR1,ADC data register 1"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000500+0x08))&0x0C)==0x00)
|
|
group.long 0x64++0x0F
|
|
line.long 0x00 "ADC4_OFR2,ADC offset register 2"
|
|
bitfld.long 0x00 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Data offset 2 for the channel"
|
|
group.long 0x84++0x0F
|
|
line.long 0x00 "ADC4_JDR2,ADC data register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x64++0x0F
|
|
line.long 0x00 "ADC4_OFR2,ADC offset register 2"
|
|
bitfld.long 0x00 31. " OFFSET2_EN ,Offset 2 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET2_CH ,Channel selection for the Data offset 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Data offset 2 for the channel"
|
|
rgroup.long 0x84++0x0F
|
|
line.long 0x00 "ADC4_JDR2,ADC data register 2"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000500+0x08))&0x0C)==0x00)
|
|
group.long 0x68++0x0F
|
|
line.long 0x00 "ADC4_OFR3,ADC offset register 3"
|
|
bitfld.long 0x00 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET3 ,Data offset 3 for the channel"
|
|
group.long 0x88++0x0F
|
|
line.long 0x00 "ADC4_JDR3,ADC data register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x68++0x0F
|
|
line.long 0x00 "ADC4_OFR3,ADC offset register 3"
|
|
bitfld.long 0x00 31. " OFFSET3_EN ,Offset 3 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET3_CH ,Channel selection for the Data offset 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET3 ,Data offset 3 for the channel"
|
|
rgroup.long 0x88++0x0F
|
|
line.long 0x00 "ADC4_JDR3,ADC data register 3"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000500+0x08))&0x0C)==0x00)
|
|
group.long 0x6C++0x0F
|
|
line.long 0x00 "ADC4_OFR4,ADC offset register 4"
|
|
bitfld.long 0x00 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET4 ,Data offset 4 for the channel"
|
|
group.long 0x8C++0x0F
|
|
line.long 0x00 "ADC4_JDR4,ADC data register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
else
|
|
rgroup.long 0x6C++0x0F
|
|
line.long 0x00 "ADC4_OFR4,ADC offset register 4"
|
|
bitfld.long 0x00 31. " OFFSET4_EN ,Offset 4 Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26.--30. " OFFSET4_CH ,Channel selection for the Data offset 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET4 ,Data offset 4 for the channel"
|
|
rgroup.long 0x8C++0x0F
|
|
line.long 0x00 "ADC4_JDR4,ADC data register 4"
|
|
hexmask.long.word 0x00 0.--15. 1. " JDATA ,Injected data"
|
|
endif
|
|
if (((per.l(ad:0x50000500+0x08))&0x0C)==0x00)
|
|
group.long 0xA0++0x07
|
|
line.long 0x00 "ADC4_AWD2CR,ADC Analog Watchdog 2 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD2CH18 ,Analog watchdog 2 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD2CH17 ,Analog watchdog 2 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD2CH16 ,Analog watchdog 2 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD2CH15 ,Analog watchdog 2 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD2CH14 ,Analog watchdog 2 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD2CH13 ,Analog watchdog 2 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD2CH12 ,Analog watchdog 2 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD2CH11 ,Analog watchdog 2 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD2CH10 ,Analog watchdog 2 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD2CH9 ,Analog watchdog 2 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD2CH8 ,Analog watchdog 2 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD2CH7 ,Analog watchdog 2 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD2CH6 ,Analog watchdog 2 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD2CH5 ,Analog watchdog 2 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD2CH4 ,Analog watchdog 2 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD2CH3 ,Analog watchdog 2 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD2CH2 ,Analog watchdog 2 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD2CH1 ,Analog watchdog 2 channel selection 1" "Not monitored,Monitored"
|
|
else
|
|
rgroup.long 0xA0++0x07
|
|
line.long 0x00 "ADC4_AWD2CR,ADC Analog Watchdog 2 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD2CH18 ,Analog watchdog 2 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD2CH17 ,Analog watchdog 2 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD2CH16 ,Analog watchdog 2 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD2CH15 ,Analog watchdog 2 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD2CH14 ,Analog watchdog 2 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD2CH13 ,Analog watchdog 2 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD2CH12 ,Analog watchdog 2 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD2CH11 ,Analog watchdog 2 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD2CH10 ,Analog watchdog 2 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD2CH9 ,Analog watchdog 2 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD2CH8 ,Analog watchdog 2 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD2CH7 ,Analog watchdog 2 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD2CH6 ,Analog watchdog 2 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD2CH5 ,Analog watchdog 2 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD2CH4 ,Analog watchdog 2 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD2CH3 ,Analog watchdog 2 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD2CH2 ,Analog watchdog 2 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD2CH1 ,Analog watchdog 2 channel selection 1" "Not monitored,Monitored"
|
|
endif
|
|
if (((per.l(ad:0x50000500+0x08))&0x0C)==0x00)
|
|
group.long 0xA4++0x07
|
|
line.long 0x00 "ADC4_AWD3CR,ADC Analog Watchdog 3 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD3CH18 ,Analog watchdog 3 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD3CH17 ,Analog watchdog 3 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD3CH16 ,Analog watchdog 3 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD3CH15 ,Analog watchdog 3 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD3CH14 ,Analog watchdog 3 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD3CH13 ,Analog watchdog 3 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD3CH12 ,Analog watchdog 3 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD3CH11 ,Analog watchdog 3 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD3CH10 ,Analog watchdog 3 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3CH9 ,Analog watchdog 3 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD3CH8 ,Analog watchdog 3 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD3CH7 ,Analog watchdog 3 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD3CH6 ,Analog watchdog 3 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD3CH5 ,Analog watchdog 3 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD3CH4 ,Analog watchdog 3 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD3CH3 ,Analog watchdog 3 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD3CH2 ,Analog watchdog 3 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD3CH1 ,Analog watchdog 3 channel selection 1" "Not monitored,Monitored"
|
|
else
|
|
rgroup.long 0xA4++0x07
|
|
line.long 0x00 "ADC4_AWD3CR,ADC Analog Watchdog 3 Configuration Register"
|
|
bitfld.long 0x00 18. " AWD3CH18 ,Analog watchdog 3 channel selection 18" "Not monitored,Monitored"
|
|
bitfld.long 0x00 17. " AWD3CH17 ,Analog watchdog 3 channel selection 17" "Not monitored,Monitored"
|
|
bitfld.long 0x00 16. " AWD3CH16 ,Analog watchdog 3 channel selection 16" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 15. " AWD3CH15 ,Analog watchdog 3 channel selection 15" "Not monitored,Monitored"
|
|
bitfld.long 0x00 14. " AWD3CH14 ,Analog watchdog 3 channel selection 14" "Not monitored,Monitored"
|
|
bitfld.long 0x00 13. " AWD3CH13 ,Analog watchdog 3 channel selection 13" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 12. " AWD3CH12 ,Analog watchdog 3 channel selection 12" "Not monitored,Monitored"
|
|
bitfld.long 0x00 11. " AWD3CH11 ,Analog watchdog 3 channel selection 11" "Not monitored,Monitored"
|
|
bitfld.long 0x00 10. " AWD3CH10 ,Analog watchdog 3 channel selection 10" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3CH9 ,Analog watchdog 3 channel selection 9" "Not monitored,Monitored"
|
|
bitfld.long 0x00 8. " AWD3CH8 ,Analog watchdog 3 channel selection 8" "Not monitored,Monitored"
|
|
bitfld.long 0x00 7. " AWD3CH7 ,Analog watchdog 3 channel selection 7" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 6. " AWD3CH6 ,Analog watchdog 3 channel selection 6" "Not monitored,Monitored"
|
|
bitfld.long 0x00 5. " AWD3CH5 ,Analog watchdog 3 channel selection 5" "Not monitored,Monitored"
|
|
bitfld.long 0x00 4. " AWD3CH4 ,Analog watchdog 3 channel selection 4" "Not monitored,Monitored"
|
|
textline " "
|
|
bitfld.long 0x00 3. " AWD3CH3 ,Analog watchdog 3 channel selection 3" "Not monitored,Monitored"
|
|
bitfld.long 0x00 2. " AWD3CH2 ,Analog watchdog 3 channel selection 2" "Not monitored,Monitored"
|
|
bitfld.long 0x00 1. " AWD3CH1 ,Analog watchdog 3 channel selection 1" "Not monitored,Monitored"
|
|
endif
|
|
if (((per.l(ad:0x50000500+0x08))&0x8000003F)==0x00)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "ADC4_DIFSEL,ADC Differential Mode Selection Register 2"
|
|
rbitfld.long 0x00 18. " DIFSEL18 ,Differential mode for channels 18" "Single ended,Differential"
|
|
rbitfld.long 0x00 17. " DIFSEL17 ,Differential mode for channels 17" "Single ended,Differential"
|
|
rbitfld.long 0x00 16. " DIFSEL16 ,Differential mode for channels 16" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DIFSEL15 ,Differential mode for channels 15" "Single ended,Differential"
|
|
bitfld.long 0x00 14. " DIFSEL14 ,Differential mode for channels 14" "Single ended,Differential"
|
|
bitfld.long 0x00 13. " DIFSEL13 ,Differential mode for channels 13" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DIFSEL12 ,Differential mode for channels 12" "Single ended,Differential"
|
|
bitfld.long 0x00 11. " DIFSEL11 ,Differential mode for channels 11" "Single ended,Differential"
|
|
bitfld.long 0x00 10. " DIFSEL10 ,Differential mode for channels 10" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DIFSEL9 ,Differential mode for channels 9" "Single ended,Differential"
|
|
bitfld.long 0x00 8. " DIFSEL8 ,Differential mode for channels 8" "Single ended,Differential"
|
|
bitfld.long 0x00 7. " DIFSEL7 ,Differential mode for channels 7" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DIFSEL6 ,Differential mode for channels 6" "Single ended,Differential"
|
|
bitfld.long 0x00 5. " DIFSEL5 ,Differential mode for channels 5" "Single ended,Differential"
|
|
bitfld.long 0x00 4. " DIFSEL4 ,Differential mode for channels 4" "Single ended,Differential"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DIFSEL3 ,Differential mode for channels 3" "Single ended,Differential"
|
|
bitfld.long 0x00 2. " DIFSEL2 ,Differential mode for channels 2" "Single ended,Differential"
|
|
bitfld.long 0x00 1. " DIFSEL1 ,Differential mode for channels 1" "Single ended,Differential"
|
|
else
|
|
group.long 0xB0++0x07
|
|
line.long 0x00 "ADC4_DIFSEL,ADC Differential Mode Selection Register 2"
|
|
rbitfld.long 0x00 18. " DIFSEL18 ,Differential mode for channels 18" "Single ended,Differential"
|
|
rbitfld.long 0x00 17. " DIFSEL17 ,Differential mode for channels 17" "Single ended,Differential"
|
|
rbitfld.long 0x00 16. " DIFSEL16 ,Differential mode for channels 16" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " DIFSEL15 ,Differential mode for channels 15" "Single ended,Differential"
|
|
rbitfld.long 0x00 14. " DIFSEL14 ,Differential mode for channels 14" "Single ended,Differential"
|
|
rbitfld.long 0x00 13. " DIFSEL13 ,Differential mode for channels 13" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " DIFSEL12 ,Differential mode for channels 12" "Single ended,Differential"
|
|
rbitfld.long 0x00 11. " DIFSEL11 ,Differential mode for channels 11" "Single ended,Differential"
|
|
rbitfld.long 0x00 10. " DIFSEL10 ,Differential mode for channels 10" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DIFSEL9 ,Differential mode for channels 9" "Single ended,Differential"
|
|
rbitfld.long 0x00 8. " DIFSEL8 ,Differential mode for channels 8" "Single ended,Differential"
|
|
rbitfld.long 0x00 7. " DIFSEL7 ,Differential mode for channels 7" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " DIFSEL6 ,Differential mode for channels 6" "Single ended,Differential"
|
|
rbitfld.long 0x00 5. " DIFSEL5 ,Differential mode for channels 5" "Single ended,Differential"
|
|
rbitfld.long 0x00 4. " DIFSEL4 ,Differential mode for channels 4" "Single ended,Differential"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " DIFSEL3 ,Differential mode for channels 3" "Single ended,Differential"
|
|
rbitfld.long 0x00 2. " DIFSEL2 ,Differential mode for channels 2" "Single ended,Differential"
|
|
rbitfld.long 0x00 1. " DIFSEL1 ,Differential mode for channels 1" "Single ended,Differential"
|
|
endif
|
|
if (((per.l(ad:0x50000500+0x08))&0x0D)==0x01)
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "ADC4_CALFACT,ADC Calibration Factors"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CALFACT_D ,Calibration factors in differential mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CALFACT_S ,Calibration factors in Single-Ended mode"
|
|
else
|
|
rgroup.long 0xB4++0x03
|
|
line.long 0x00 "ADC4_CALFACT,ADC Calibration Factors"
|
|
hexmask.long.byte 0x00 16.--22. 1. " CALFACT_D ,Calibration factors in differential mode"
|
|
hexmask.long.byte 0x00 0.--6. 1. " CALFACT_S ,Calibration factors in Single-Ended mode"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
sif cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"&&cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"
|
|
tree "Common Registers"
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"
|
|
tree "ADC1"
|
|
base ad:0x50000300
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC12_CSR,ADC Common status register"
|
|
bitfld.long 0x00 26. " JQOVF_SLV ,Injected Context Queue Overflow flag of the slave ADC" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " AWD3_SLV ,Analog watchdog 3 flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 24. " AWD2_SLV ,Analog watchdog 2 flag of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1_SLV ,Analog watchdog 1 flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 22. " JEOS_SLV ,End of injected sequence flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 21. " JEOC_SLV ,End of injected conversion flag of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " OVR_SLV ,Overrun flag of the slave ADC" "No overrun,Overrun"
|
|
bitfld.long 0x00 19. " EOS_SLV ,End of regular sequence flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 18. " EOC_SLV ,End of regular conversion of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EOSMP_SLV ,End of Sampling phase flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 16. " ADRDY_SLV ,Slave ADC ready" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " JQOVF_MST ,Injected Context Queue Overflow flag of the master ADC" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3_MST ,Analog watchdog 3 flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 8. " AWD2_MST ,Analog watchdog 2 flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 7. " AWD1_MST ,Analog watchdog 1 flag of the master ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " JEOS_MST ,End of injected sequence flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 5. " JEOC_MST ,End of injected conversion flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 4. " OVR_MST ,Overrun flag of the master ADC" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EOS_MST ,End of regular sequence flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 2. " EOC_MST ,End of regular conversion of the master ADC" "Low,High"
|
|
bitfld.long 0x00 1. " EOSMP_MST ,End of Sampling phase flag of the master ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADRDY_MST ,Master ADC ready" "Not ready,Ready"
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC12_CCR,ADC common control register"
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"&&!cpuis("STM32F302*")&&!cpuis("STM32F303*")
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 13. " DMACFG ,DMA configuration" "One Shot Mode,Circular Mode"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent Mode,Regular/Injected,Regular/Alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
endif
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
sif cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")
|
|
rgroup.long 0x0C++0x03
|
|
else
|
|
rgroup.long 0x0A++0x03
|
|
endif
|
|
line.long 0x00 "ADC12_CDR,ADC common regular data register for dual mode"
|
|
hexmask.long.word 0x00 16.--31. 1. " RDATA_SLV ,Regular data of the slave ADC"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA_MST ,Regular data of the master ADC"
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
else
|
|
tree "ADC12"
|
|
base ad:0x50000300
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC12_CSR,ADC Common status register"
|
|
bitfld.long 0x00 26. " JQOVF_SLV ,Injected Context Queue Overflow flag of the slave ADC" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " AWD3_SLV ,Analog watchdog 3 flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 24. " AWD2_SLV ,Analog watchdog 2 flag of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1_SLV ,Analog watchdog 1 flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 22. " JEOS_SLV ,End of injected sequence flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 21. " JEOC_SLV ,End of injected conversion flag of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " OVR_SLV ,Overrun flag of the slave ADC" "No overrun,Overrun"
|
|
bitfld.long 0x00 19. " EOS_SLV ,End of regular sequence flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 18. " EOC_SLV ,End of regular conversion of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EOSMP_SLV ,End of Sampling phase flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 16. " ADRDY_SLV ,Slave ADC ready" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " JQOVF_MST ,Injected Context Queue Overflow flag of the master ADC" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3_MST ,Analog watchdog 3 flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 8. " AWD2_MST ,Analog watchdog 2 flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 7. " AWD1_MST ,Analog watchdog 1 flag of the master ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " JEOS_MST ,End of injected sequence flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 5. " JEOC_MST ,End of injected conversion flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 4. " OVR_MST ,Overrun flag of the master ADC" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EOS_MST ,End of regular sequence flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 2. " EOC_MST ,End of regular conversion of the master ADC" "Low,High"
|
|
bitfld.long 0x00 1. " EOSMP_MST ,End of Sampling phase flag of the master ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADRDY_MST ,Master ADC ready" "Not ready,Ready"
|
|
if ((((per.l(ad:0x50000000+0x08))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)&&(((per.l(ad:0x50000000+0x108))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x10C))&0x01)==0x01))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC12_CCR,ADC Common Control Register"
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 13. " DMACFG ,DMA configuration" "One shot mode,Circular mode"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
elif ((((per.l(ad:0x50000000+0x08))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x108))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x10C))&0x01)==0x00))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC12_CCR,ADC Common Control Register"
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
elif ((((per.l(ad:0x50000000+0x08))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)&&(((per.l(ad:0x50000000+0x108))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x10C))&0x01)==0x01))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC12_CCR,ADC Common Control Register"
|
|
rbitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 13. " DMACFG ,DMA configuration" "One shot mode,Circular mode"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
rbitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
elif ((((per.l(ad:0x50000000+0x08))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x108))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x10C))&0x01)==0x00))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC12_CCR,ADC Common Control Register"
|
|
rbitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
rbitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC12_CCR,ADC Common Control Register"
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
endif
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
sif cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rgroup.long 0x0C++0x03
|
|
else
|
|
rgroup.long 0x0A++0x03
|
|
endif
|
|
line.long 0x00 "ADC12_CDR,ADC common regular data register for dual mode"
|
|
hexmask.long.word 0x00 16.--31. 1. " RDATA_SLV ,Regular data of the slave ADC"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA_MST ,Regular data of the master ADC"
|
|
endif
|
|
width 0xB
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC12_CSR,ADC Common status register"
|
|
bitfld.long 0x00 26. " JQOVF_SLV ,Injected Context Queue Overflow flag of the slave ADC" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " AWD3_SLV ,Analog watchdog 3 flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 24. " AWD2_SLV ,Analog watchdog 2 flag of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1_SLV ,Analog watchdog 1 flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 22. " JEOS_SLV ,End of injected sequence flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 21. " JEOC_SLV ,End of injected conversion flag of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " OVR_SLV ,Overrun flag of the slave ADC" "No overrun,Overrun"
|
|
bitfld.long 0x00 19. " EOS_SLV ,End of regular sequence flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 18. " EOC_SLV ,End of regular conversion of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EOSMP_SLV ,End of Sampling phase flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 16. " ADRDY_SLV ,Slave ADC ready" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " JQOVF_MST ,Injected Context Queue Overflow flag of the master ADC" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3_MST ,Analog watchdog 3 flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 8. " AWD2_MST ,Analog watchdog 2 flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 7. " AWD1_MST ,Analog watchdog 1 flag of the master ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " JEOS_MST ,End of injected sequence flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 5. " JEOC_MST ,End of injected conversion flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 4. " OVR_MST ,Overrun flag of the master ADC" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EOS_MST ,End of regular sequence flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 2. " EOC_MST ,End of regular conversion of the master ADC" "Low,High"
|
|
bitfld.long 0x00 1. " EOSMP_MST ,End of Sampling phase flag of the master ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADRDY_MST ,Master ADC ready" "Not ready,Ready"
|
|
if ((((per.l(ad:0x50000000+0x08))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)&&(((per.l(ad:0x50000000+0x108))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x10C))&0x01)==0x01)&&((((per.l(ad:0x50000000+0x408))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x40C))&0x01)==0x01))&&((((per.l(ad:0x50000000+0x508))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x50C))&0x01)==0x01)))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC12_CCR,ADC Common Control Register"
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 13. " DMACFG ,DMA configuration" "One shot mode,Circular mode"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
elif ((((per.l(ad:0x50000000+0x08))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x108))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x10C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x408))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x40C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x508))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x50C))&0x01)==0x00))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC12_CCR,ADC Common Control Register"
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
elif ((((per.l(ad:0x50000000+0x08))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)&&(((per.l(ad:0x50000000+0x108))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x10C))&0x01)==0x01)&&(((per.l(ad:0x50000000+0x408))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x40C))&0x01)==0x01)&&(((per.l(ad:0x50000000+0x508))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x50C))&0x01)==0x01))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC12_CCR,ADC Common Control Register"
|
|
rbitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 13. " DMACFG ,DMA configuration" "One shot mode,Circular mode"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
rbitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
elif ((((per.l(ad:0x50000000+0x08))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x108))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x10C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x08))&0x404)==0x00)&&(((per.l(ad:0x50000000+0x40C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x508))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x50C))&0x01)==0x00))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC12_CCR,ADC Common Control Register"
|
|
rbitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
rbitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC12_CCR,ADC Common Control Register"
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
endif
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
sif cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rgroup.long 0x0C++0x03
|
|
else
|
|
rgroup.long 0x0A++0x03
|
|
endif
|
|
line.long 0x00 "ADC12_CDR,ADC common regular data register for dual mode"
|
|
hexmask.long.word 0x00 16.--31. 1. " RDATA_SLV ,Regular data of the slave ADC"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA_MST ,Regular data of the master ADC"
|
|
endif
|
|
width 0xB
|
|
else
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC12_CSR,ADC Common status register"
|
|
bitfld.long 0x00 26. " JQOVF_SLV ,Injected Context Queue Overflow flag of the slave ADC" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " AWD3_SLV ,Analog watchdog 3 flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 24. " AWD2_SLV ,Analog watchdog 2 flag of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1_SLV ,Analog watchdog 1 flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 22. " JEOS_SLV ,End of injected sequence flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 21. " JEOC_SLV ,End of injected conversion flag of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " OVR_SLV ,Overrun flag of the slave ADC" "No overrun,Overrun"
|
|
bitfld.long 0x00 19. " EOS_SLV ,End of regular sequence flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 18. " EOC_SLV ,End of regular conversion of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EOSMP_SLV ,End of Sampling phase flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 16. " ADRDY_SLV ,Slave ADC ready" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " JQOVF_MST ,Injected Context Queue Overflow flag of the master ADC" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3_MST ,Analog watchdog 3 flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 8. " AWD2_MST ,Analog watchdog 2 flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 7. " AWD1_MST ,Analog watchdog 1 flag of the master ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " JEOS_MST ,End of injected sequence flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 5. " JEOC_MST ,End of injected conversion flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 4. " OVR_MST ,Overrun flag of the master ADC" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EOS_MST ,End of regular sequence flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 2. " EOC_MST ,End of regular conversion of the master ADC" "Low,High"
|
|
bitfld.long 0x00 1. " EOSMP_MST ,End of Sampling phase flag of the master ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADRDY_MST ,Master ADC ready" "Not ready,Ready"
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC12_CCR,ADC common control register"
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"&&!cpuis("STM32F302*")&&!cpuis("STM32F303*")
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 13. " DMACFG ,DMA configuration" "One Shot Mode,Circular Mode"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent Mode,Regular/Injected,Regular/Alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
endif
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
sif cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")
|
|
rgroup.long 0x0C++0x03
|
|
else
|
|
rgroup.long 0x0A++0x03
|
|
endif
|
|
line.long 0x00 "ADC12_CDR,ADC common regular data register for dual mode"
|
|
hexmask.long.word 0x00 16.--31. 1. " RDATA_SLV ,Regular data of the slave ADC"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA_MST ,Regular data of the master ADC"
|
|
endif
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="STM32F303RB"||cpu()=="STM32F303RC"||cpu()=="STM32F303CB"||cpu()=="STM32F303VB"||cpu()=="STM32F303CC"||cpu()=="STM32F303VC"||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||(!cpuis("STM32F302*6")&&!cpuis("STM32F302*8")&&!cpuis("STM32F334?4")&&!cpuis("STM32F334?6")&&!cpuis("STM32F334?8"))||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
tree "ADC34"
|
|
base ad:0x50000700
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC34_CSR,ADC Common status register"
|
|
bitfld.long 0x00 26. " JQOVF_SLV ,Injected Context Queue Overflow flag of the slave ADC" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " AWD3_SLV ,Analog watchdog 3 flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 24. " AWD2_SLV ,Analog watchdog 2 flag of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1_SLV ,Analog watchdog 1 flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 22. " JEOS_SLV ,End of injected sequence flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 21. " JEOC_SLV ,End of injected conversion flag of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " OVR_SLV ,Overrun flag of the slave ADC" "No overrun,Overrun"
|
|
bitfld.long 0x00 19. " EOS_SLV ,End of regular sequence flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 18. " EOC_SLV ,End of regular conversion of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EOSMP_SLV ,End of Sampling phase flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 16. " ADRDY_SLV ,Slave ADC ready" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " JQOVF_MST ,Injected Context Queue Overflow flag of the master ADC" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3_MST ,Analog watchdog 3 flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 8. " AWD2_MST ,Analog watchdog 2 flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 7. " AWD1_MST ,Analog watchdog 1 flag of the master ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " JEOS_MST ,End of injected sequence flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 5. " JEOC_MST ,End of injected conversion flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 4. " OVR_MST ,Overrun flag of the master ADC" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EOS_MST ,End of regular sequence flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 2. " EOC_MST ,End of regular conversion of the master ADC" "Low,High"
|
|
bitfld.long 0x00 1. " EOSMP_MST ,End of Sampling phase flag of the master ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADRDY_MST ,Master ADC ready" "Not ready,Ready"
|
|
if ((((per.l(ad:0x50000000+0x08))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)&&(((per.l(ad:0x50000000+0x108))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x10C))&0x01)==0x01)&&((((per.l(ad:0x50000000+0x408))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x40C))&0x01)==0x01))&&((((per.l(ad:0x50000000+0x508))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x50C))&0x01)==0x01)))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC34_CCR,ADC Common Control Register"
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 13. " DMACFG ,DMA configuration" "One shot mode,Circular mode"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
elif ((((per.l(ad:0x50000000+0x08))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x108))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x10C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x408))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x40C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x508))&0x8000003F)==0x00)&&(((per.l(ad:0x50000000+0x50C))&0x01)==0x00))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC34_CCR,ADC Common Control Register"
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
elif ((((per.l(ad:0x50000000+0x08))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x01)&&(((per.l(ad:0x50000000+0x108))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x10C))&0x01)==0x01)&&(((per.l(ad:0x50000000+0x408))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x40C))&0x01)==0x01)&&(((per.l(ad:0x50000000+0x508))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x50C))&0x01)==0x01))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC34_CCR,ADC Common Control Register"
|
|
rbitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 13. " DMACFG ,DMA configuration" "One shot mode,Circular mode"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
rbitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
elif ((((per.l(ad:0x50000000+0x08))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x0C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x108))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x10C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x08))&0x404)==0x00)&&(((per.l(ad:0x50000000+0x40C))&0x01)==0x00)&&(((per.l(ad:0x50000000+0x508))&0x04)==0x00)&&(((per.l(ad:0x50000000+0x50C))&0x01)==0x00))
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC34_CCR,ADC Common Control Register"
|
|
rbitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
rbitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC34_CCR,ADC Common Control Register"
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
textline " "
|
|
bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent mode,Regular/injected,Regular/alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
endif
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
sif cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
rgroup.long 0x0C++0x03
|
|
else
|
|
rgroup.long 0x0A++0x03
|
|
endif
|
|
line.long 0x00 "ADC34_CDR,ADC common regular data register for dual mode"
|
|
hexmask.long.word 0x00 16.--31. 1. " RDATA_SLV ,Regular data of the slave ADC"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA_MST ,Regular data of the master ADC"
|
|
endif
|
|
width 0xB
|
|
else
|
|
width 13.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "ADC34_CSR,ADC Common status register"
|
|
bitfld.long 0x00 26. " JQOVF_SLV ,Injected Context Queue Overflow flag of the slave ADC" "No overflow,Overflow"
|
|
bitfld.long 0x00 25. " AWD3_SLV ,Analog watchdog 3 flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 24. " AWD2_SLV ,Analog watchdog 2 flag of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 23. " AWD1_SLV ,Analog watchdog 1 flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 22. " JEOS_SLV ,End of injected sequence flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 21. " JEOC_SLV ,End of injected conversion flag of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 20. " OVR_SLV ,Overrun flag of the slave ADC" "No overrun,Overrun"
|
|
bitfld.long 0x00 19. " EOS_SLV ,End of regular sequence flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 18. " EOC_SLV ,End of regular conversion of the slave ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 17. " EOSMP_SLV ,End of Sampling phase flag of the slave ADC" "Low,High"
|
|
bitfld.long 0x00 16. " ADRDY_SLV ,Slave ADC ready" "Not ready,Ready"
|
|
bitfld.long 0x00 10. " JQOVF_MST ,Injected Context Queue Overflow flag of the master ADC" "No overflow,Overflow"
|
|
textline " "
|
|
bitfld.long 0x00 9. " AWD3_MST ,Analog watchdog 3 flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 8. " AWD2_MST ,Analog watchdog 2 flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 7. " AWD1_MST ,Analog watchdog 1 flag of the master ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 6. " JEOS_MST ,End of injected sequence flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 5. " JEOC_MST ,End of injected conversion flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 4. " OVR_MST ,Overrun flag of the master ADC" "No overrun,Overrun"
|
|
textline " "
|
|
bitfld.long 0x00 3. " EOS_MST ,End of regular sequence flag of the master ADC" "Low,High"
|
|
bitfld.long 0x00 2. " EOC_MST ,End of regular conversion of the master ADC" "Low,High"
|
|
bitfld.long 0x00 1. " EOSMP_MST ,End of Sampling phase flag of the master ADC" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADRDY_MST ,Master ADC ready" "Not ready,Ready"
|
|
textline " "
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ADC34_CCR,ADC common control register"
|
|
bitfld.long 0x00 24. " VBATEN ,VBAT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " TSEN ,Temperature sensor enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " VREFEN ,V_REFINT enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16.--17. " CKMODE ,ADC clock mode" "Asynchronous,Synchronous/1,Synchronous/2,Synchronous/4"
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"&&!cpuis("STM32F302*")&&!cpuis("STM32F303*")
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " MDMA ,Direct memory access mode for dual ADC mode" "Disabled,,12 and 10-bit,8 and 6-bit"
|
|
bitfld.long 0x00 13. " DMACFG ,DMA configuration" "One Shot Mode,Circular Mode"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " DELAY ,Delay between 2 sampling phases [resolution - 12|10|8|6-bit]" "1 * TADC_CLK,2 * TADC_CLK,3 * TADC_CLK,4 * TADC_CLK,5 * TADC_CLK,6 * TADC_CLK,7|7|7|6 * TADC_CLK,8|8|8|6 * TADC_CLK,9|9|8|6 * TADC_CLK,10|10|8|6 * TADC_CLK,11|10|8|6 * TADC_CLK,12|10|8|6 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK,12 * TADC_CLK"
|
|
bitfld.long 0x00 0.--4. " DUAL ,Dual ADC mode selection" "Independent Mode,Regular/Injected,Regular/Alternate trigger,,,Injected,Regular,Interleaved,,Alternate trigger,?..."
|
|
endif
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
sif cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")
|
|
rgroup.long 0x0C++0x03
|
|
else
|
|
rgroup.long 0x0A++0x03
|
|
endif
|
|
line.long 0x00 "ADC34_CDR,ADC common regular data register for dual mode"
|
|
hexmask.long.word 0x00 16.--31. 1. " RDATA_SLV ,Regular data of the slave ADC"
|
|
hexmask.long.word 0x00 0.--15. 1. " RDATA_MST ,Regular data of the master ADC"
|
|
endif
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"
|
|
tree.open "SDADC (Sigma-delta analog-to-digital converter)"
|
|
tree "SDADC1"
|
|
base ad:0x40016000
|
|
width 10.
|
|
if (((per.l(ad:0x40016000+0x04))&0x01)==0x01)&&(((per.l(ad:0x40016000+0x08))&0x80000000)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,SDADC1 control register 1"
|
|
bitfld.long 0x00 31. " INIT ,Initialization mode request" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RDMAEN ,DMA channel enabled to read data for the regular channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDI ,Enter power down mode when idle" "Not entered,Entered"
|
|
bitfld.long 0x00 11. " SBI ,Enter Standby mode when idle" "Not put,Put"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SLOWCK ,Slow clock mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " REFV ,Reference voltage selection" "External/VREF,Internal/1.2V,Internal/1.8V,Internal/VDDSDx & VREFSD+"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOCALIE ,End of calibration interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40016000+0x04))&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,SDADC1 control register 1"
|
|
bitfld.long 0x00 31. " INIT ,Initialization mode request" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RDMAEN ,DMA channel enabled to read data for the regular channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " PDI ,Enter power down mode when idle" "Not entered,Entered"
|
|
rbitfld.long 0x00 11. " SBI ,Enter Standby mode when idle" "Not put,Put"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SLOWCK ,Slow clock mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " REFV ,Reference voltage selection" "External/VREF,Internal/1.2V,Internal/1.8V,Internal/VDDSDx & VREFSD+"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOCALIE ,End of calibration interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,SDADC1 control register 1"
|
|
bitfld.long 0x00 31. " INIT ,Initialization mode request" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RDMAEN ,DMA channel enabled to read data for the regular channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDI ,Enter power down mode when idle" "Not entered,Entered"
|
|
bitfld.long 0x00 11. " SBI ,Enter Standby mode when idle" "Not put,Put"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SLOWCK ,Slow clock mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " REFV ,Reference voltage selection" "External/VREF,Internal/1.2V,Internal/1.8V,Internal/VDDSDx & VREFSD+"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOCALIE ,End of calibration interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,SDADC1 control register 2"
|
|
bitfld.long 0x00 24. " FAST ,Fast conversion mode selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeated"
|
|
bitfld.long 0x00 16.--19. " RCH ,Regular channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Started"
|
|
bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM13_CH1,TIM14_CH1,TIM15_CH2,TIM3_CH1,TIM4_CH1,TIM19_CH2,EXTI15,EXTI11"
|
|
textline " "
|
|
bitfld.long 0x00 6. " JDS ,Delay start of injected conversions" "ASAP,Delayed"
|
|
bitfld.long 0x00 5. " JCONT ,Continuous mode selection for injected conversions" "Once,Repeated"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STARTCALIB ,Start calibration" "No effect,Start"
|
|
bitfld.long 0x00 1.--2. " CALIBCNT ,Number of calibration sequences to be performed" "One,Two,Three,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADON ,SDADC1 enable" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ISR,SDADC1 interrupt and status register"
|
|
bitfld.long 0x00 31. " INITRDY ,Initialization mode is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 15. " STABIP ,Stabilization in progress status" "Stabilized/Power down/Standby,In progress"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "Not issued,In progress/Requested"
|
|
bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "Not issued,In progress/Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CALIBIP ,Calibration in progress status" "Bot issued,In progress/Requested"
|
|
bitfld.long 0x00 4. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " REOCF ,End of regular conversion flag" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not injected,Injected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JEOCF ,End of injected conversion flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " EOCALF ,End of calibration flag" "Not completed,Completed"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLRISR,SDADC1 interrupt and status clear register"
|
|
eventfld.long 0x00 4. " CLRROVRF ,Clear the regular conversion overrun flag" "No effect,Cleared"
|
|
eventfld.long 0x00 2. " CLRJOVRF ,Clear the injected conversion overrun flag" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 0. " CLREOCALF ,Clear the end of calibration flag" "No effect,Cleared"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "JCHGR,SDADC1 injected channel group selection register"
|
|
hexmask.long.word 0x00 0.--8. 1. " JCHG ,Injected channel group selection"
|
|
if (((per.l(ad:0x40016000+0x04))&0x01)==0x01)&&(((per.l(ad:0x40016000+0x08))&0x80000000)==0x00)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CONF0R,SDADC1 configuration 0 register"
|
|
bitfld.long 0x00 30.--31. " COMMON0 ,Common mode for configuration 0" "Ground,VCM (VDD/2),VDD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE0 ,Single-ended mode for configuration 0" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN0 ,Gain setting for configuration 0" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET0 ,Twelve-bit calibration offset for configuration 0"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CONF1R,SDADC1 configuration 1 register"
|
|
bitfld.long 0x00 30.--31. " COMMON1 ,Common mode for configuration 1" "Ground,VCM (VDD/2),VDD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE1 ,Single-ended mode for configuration 1" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN1 ,Gain setting for configuration 1" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Twelve-bit calibration offset for configuration 1"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CONF2R,SDADC1 configuration 2 register"
|
|
bitfld.long 0x00 30.--31. " COMMON2 ,Common mode for configuration 2" "VSSSD,VDDSDx/2,VDDSDx,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE2 ,Single-ended mode for configuration 2" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN2 ,Gain setting for configuration 2" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Twelve-bit calibration offset for configuration 2"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CONFCHR1,SDADC1 channel configuration register 1"
|
|
bitfld.long 0x00 28.--29. " CONFCH7 ,Channel 7 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 24.--25. " CONFCH6 ,Channel 6 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " CONFCH5 ,Channel 5 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 16.--17. " CONFCH4 ,Channel 4 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CONFCH3 ,Channel 3 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 8.--9. " CONFCH2 ,Channel 2 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CONFCH1 ,Channel 1 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 0.--1. " CONFCH0 ,Channel 0 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CONFCHR2,SDADC1 channel configuration register 2"
|
|
bitfld.long 0x00 0.--1. " CONFCH8 ,Channel 8 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CONF0R,SDADC1 configuration 0 register"
|
|
bitfld.long 0x00 30.--31. " COMMON0 ,Common mode for configuration 0" "Ground,VCM (VDD/2),VDD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE0 ,Single-ended mode for configuration 0" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN0 ,Gain setting for configuration 0" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET0 ,Twelve-bit calibration offset for configuration 0"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CONF1R,SDADC1 configuration 1 register"
|
|
bitfld.long 0x00 30.--31. " COMMON1 ,Common mode for configuration 1" "Ground,VCM (VDD/2),VDD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE1 ,Single-ended mode for configuration 1" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN1 ,Gain setting for configuration 1" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Twelve-bit calibration offset for configuration 1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CONF2R,SDADC1 configuration 2 register"
|
|
bitfld.long 0x00 30.--31. " COMMON2 ,Common mode for configuration 2" "VSSSD,VDDSDx/2,VDDSDx,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE2 ,Single-ended mode for configuration 2" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN2 ,Gain setting for configuration 2" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Twelve-bit calibration offset for configuration 2"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CONFCHR1,SDADC1 channel configuration register 1"
|
|
bitfld.long 0x00 28.--29. " CONFCH7 ,Channel 7 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 24.--25. " CONFCH6 ,Channel 6 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " CONFCH5 ,Channel 5 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 16.--17. " CONFCH4 ,Channel 4 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CONFCH3 ,Channel 3 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 8.--9. " CONFCH2 ,Channel 2 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CONFCH1 ,Channel 1 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 0.--1. " CONFCH0 ,Channel 0 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CONFCHR2,SDADC1 channel configuration register 2"
|
|
bitfld.long 0x00 0.--1. " CONFCH8 ,Channel 8 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
endif
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "JDATAR,SDADC1 data register for injected group"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "RDATAR,SDADC1 data register for the regular channel"
|
|
in
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")
|
|
if (((per.l(ad:0x40016400+0x00))&0x4000)==0x4000)
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "JDATA12R,SDADC1 and SDADC2 injected data register"
|
|
else
|
|
hgroup.long 0x70++0x03
|
|
hide.long 0x00 "JDATA12R,SDADC1 and SDADC2 injected data register"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40016400+0x00))&0x8000)==0x8000)
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "RDATA12R,SDADC1 and SDADC2 regular data register"
|
|
else
|
|
hgroup.long 0x74++0x03
|
|
hide.long 0x00 "RDATA12R,SDADC1 and SDADC2 regular data register"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40016800+0x00))&0x4000)==0x4000)
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "JDATA13R,SDADC1 and SDADC3 injected data register"
|
|
else
|
|
hgroup.long 0x78++0x03
|
|
hide.long 0x00 "JDATA13R,SDADC1 and SDADC3 injected data register"
|
|
in
|
|
endif
|
|
if (((per.l(ad:0x40016800+0x00))&0x8000)==0x8000)
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x0c "RDATA13R,SDADC1 and SDADC3 regular data register"
|
|
else
|
|
hgroup.long 0x7C++0x03
|
|
hide.long 0x0c "RDATA13R,SDADC1 and SDADC3 regular data register"
|
|
in
|
|
endif
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
sif (cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"
|
|
tree "SDADC2"
|
|
base ad:0x40016400
|
|
width 10.
|
|
if (((per.l(ad:0x40016400+0x04))&0x01)==0x01)&&(((per.l(ad:0x40016400+0x08))&0x80000000)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,SDADC2 control register 1"
|
|
bitfld.long 0x00 31. " INIT ,Initialization mode request" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RDMAEN ,DMA channel enabled to read data for the regular channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " RSYNC ,Launch regular conversion synchronously with SDADC1" "Not launched,Launched"
|
|
rbitfld.long 0x00 14. " JSYNC ,Launch a injected conversion synchronously with SDADC1" "Not launched,Launched"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDI ,Enter power down mode when idle" "Not entered,Entered"
|
|
bitfld.long 0x00 11. " SBI ,Enter Standby mode when idle" "Not put,Put"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SLOWCK ,Slow clock mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOCALIE ,End of calibration interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40016400+0x04))&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,SDADC2 control register 1"
|
|
bitfld.long 0x00 31. " INIT ,Initialization mode request" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RDMAEN ,DMA channel enabled to read data for the regular channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RSYNC ,Launch regular conversion synchronously with SDADC1" "Not launched,Launched"
|
|
bitfld.long 0x00 14. " JSYNC ,Launch a injected conversion synchronously with SDADC1" "Not launched,Launched"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " PDI ,Enter power down mode when idle" "Not entered,Entered"
|
|
rbitfld.long 0x00 11. " SBI ,Enter Standby mode when idle" "Not put,Put"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SLOWCK ,Slow clock mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOCALIE ,End of calibration interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,SDADC2 control register 1"
|
|
bitfld.long 0x00 31. " INIT ,Initialization mode request" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RDMAEN ,DMA channel enabled to read data for the regular channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RSYNC ,Launch regular conversion synchronously with SDADC1" "Not launched,Launched"
|
|
bitfld.long 0x00 14. " JSYNC ,Launch a injected conversion synchronously with SDADC1" "Not launched,Launched"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDI ,Enter power down mode when idle" "Not entered,Entered"
|
|
bitfld.long 0x00 11. " SBI ,Enter Standby mode when idle" "Not put,Put"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SLOWCK ,Slow clock mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOCALIE ,End of calibration interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,SDADC2 control register 2"
|
|
bitfld.long 0x00 24. " FAST ,Fast conversion mode selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeated"
|
|
bitfld.long 0x00 16.--19. " RCH ,Regular channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Started"
|
|
bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM17_CH1,TIM12_CH1,TIM2_CH3,TIM3_CH2,TIM4_CH2,TIM19_CH3,EXTI15,EXTI11"
|
|
textline " "
|
|
bitfld.long 0x00 6. " JDS ,Delay start of injected conversions" "ASAP,Delayed"
|
|
bitfld.long 0x00 5. " JCONT ,Continuous mode selection for injected conversions" "Once,Repeated"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STARTCALIB ,Start calibration" "No effect,Start"
|
|
bitfld.long 0x00 1.--2. " CALIBCNT ,Number of calibration sequences to be performed" "One,Two,Three,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADON ,SDADC2 enable" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ISR,SDADC2 interrupt and status register"
|
|
bitfld.long 0x00 31. " INITRDY ,Initialization mode is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 15. " STABIP ,Stabilization in progress status" "Stabilized/Power down/Standby,In progress"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "Not issued,In progress/Requested"
|
|
bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "Not issued,In progress/Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CALIBIP ,Calibration in progress status" "Bot issued,In progress/Requested"
|
|
bitfld.long 0x00 4. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " REOCF ,End of regular conversion flag" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not injected,Injected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JEOCF ,End of injected conversion flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " EOCALF ,End of calibration flag" "Not completed,Completed"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLRISR,SDADC2 interrupt and status clear register"
|
|
eventfld.long 0x00 4. " CLRROVRF ,Clear the regular conversion overrun flag" "No effect,Cleared"
|
|
eventfld.long 0x00 2. " CLRJOVRF ,Clear the injected conversion overrun flag" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 0. " CLREOCALF ,Clear the end of calibration flag" "No effect,Cleared"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "JCHGR,SDADC2 injected channel group selection register"
|
|
hexmask.long.word 0x00 0.--8. 1. " JCHG ,Injected channel group selection"
|
|
if (((per.l(ad:0x40016400+0x04))&0x01)==0x01)&&(((per.l(ad:0x40016400+0x08))&0x80000000)==0x00)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CONF0R,SDADC2 configuration 0 register"
|
|
bitfld.long 0x00 30.--31. " COMMON0 ,Common mode for configuration 0" "Ground,VCM (VDD/2),VDD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE0 ,Single-ended mode for configuration 0" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN0 ,Gain setting for configuration 0" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET0 ,Twelve-bit calibration offset for configuration 0"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CONF1R,SDADC2 configuration 1 register"
|
|
bitfld.long 0x00 30.--31. " COMMON1 ,Common mode for configuration 1" "Ground,VCM (VDD/2),VDD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE1 ,Single-ended mode for configuration 1" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN1 ,Gain setting for configuration 1" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Twelve-bit calibration offset for configuration 1"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CONF2R,SDADC2 configuration 2 register"
|
|
bitfld.long 0x00 30.--31. " COMMON2 ,Common mode for configuration 2" "VSSSD,VDDSDx/2,VDDSDx,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE2 ,Single-ended mode for configuration 2" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN2 ,Gain setting for configuration 2" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Twelve-bit calibration offset for configuration 2"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CONFCHR1,SDADC2 channel configuration register 1"
|
|
bitfld.long 0x00 28.--29. " CONFCH7 ,Channel 7 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 24.--25. " CONFCH6 ,Channel 6 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " CONFCH5 ,Channel 5 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 16.--17. " CONFCH4 ,Channel 4 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CONFCH3 ,Channel 3 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 8.--9. " CONFCH2 ,Channel 2 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CONFCH1 ,Channel 1 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 0.--1. " CONFCH0 ,Channel 0 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CONFCHR2,SDADC2 channel configuration register 2"
|
|
bitfld.long 0x00 0.--1. " CONFCH8 ,Channel 8 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CONF0R,SDADC2 configuration 0 register"
|
|
bitfld.long 0x00 30.--31. " COMMON0 ,Common mode for configuration 0" "Ground,VCM (VDD/2),VDD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE0 ,Single-ended mode for configuration 0" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN0 ,Gain setting for configuration 0" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET0 ,Twelve-bit calibration offset for configuration 0"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CONF1R,SDADC2 configuration 1 register"
|
|
bitfld.long 0x00 30.--31. " COMMON1 ,Common mode for configuration 1" "Ground,VCM (VDD/2),VDD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE1 ,Single-ended mode for configuration 1" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN1 ,Gain setting for configuration 1" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Twelve-bit calibration offset for configuration 1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CONF2R,SDADC2 configuration 2 register"
|
|
bitfld.long 0x00 30.--31. " COMMON2 ,Common mode for configuration 2" "VSSSD,VDDSDx/2,VDDSDx,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE2 ,Single-ended mode for configuration 2" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN2 ,Gain setting for configuration 2" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Twelve-bit calibration offset for configuration 2"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CONFCHR1,SDADC2 channel configuration register 1"
|
|
bitfld.long 0x00 28.--29. " CONFCH7 ,Channel 7 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 24.--25. " CONFCH6 ,Channel 6 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " CONFCH5 ,Channel 5 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 16.--17. " CONFCH4 ,Channel 4 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CONFCH3 ,Channel 3 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 8.--9. " CONFCH2 ,Channel 2 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CONFCH1 ,Channel 1 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 0.--1. " CONFCH0 ,Channel 0 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CONFCHR2,SDADC2 channel configuration register 2"
|
|
bitfld.long 0x00 0.--1. " CONFCH8 ,Channel 8 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
endif
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "JDATAR,SDADC2 data register for injected group"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "RDATAR,SDADC2 data register for the regular channel"
|
|
in
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
tree "SDADC3"
|
|
base ad:0x40016800
|
|
width 10.
|
|
if (((per.l(ad:0x40016800+0x04))&0x01)==0x01)&&(((per.l(ad:0x40016800+0x08))&0x80000000)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,SDADC3 control register 1"
|
|
bitfld.long 0x00 31. " INIT ,Initialization mode request" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RDMAEN ,DMA channel enabled to read data for the regular channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " RSYNC ,Launch regular conversion synchronously with SDADC1" "Not launched,Launched"
|
|
rbitfld.long 0x00 14. " JSYNC ,Launch a injected conversion synchronously with SDADC1" "Not launched,Launched"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDI ,Enter power down mode when idle" "Not entered,Entered"
|
|
bitfld.long 0x00 11. " SBI ,Enter Standby mode when idle" "Not put,Put"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SLOWCK ,Slow clock mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOCALIE ,End of calibration interrupt enable" "Disabled,Enabled"
|
|
elif (((per.l(ad:0x40016800+0x04))&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,SDADC3 control register 1"
|
|
bitfld.long 0x00 31. " INIT ,Initialization mode request" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RDMAEN ,DMA channel enabled to read data for the regular channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RSYNC ,Launch regular conversion synchronously with SDADC1" "Not launched,Launched"
|
|
bitfld.long 0x00 14. " JSYNC ,Launch a injected conversion synchronously with SDADC1" "Not launched,Launched"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " PDI ,Enter power down mode when idle" "Not entered,Entered"
|
|
rbitfld.long 0x00 11. " SBI ,Enter Standby mode when idle" "Not put,Put"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SLOWCK ,Slow clock mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOCALIE ,End of calibration interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR1,SDADC3 control register 1"
|
|
bitfld.long 0x00 31. " INIT ,Initialization mode request" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " RDMAEN ,DMA channel enabled to read data for the regular channel" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " JDMAEN ,DMA channel enabled to read data for the injected channel group" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RSYNC ,Launch regular conversion synchronously with SDADC1" "Not launched,Launched"
|
|
bitfld.long 0x00 14. " JSYNC ,Launch a injected conversion synchronously with SDADC1" "Not launched,Launched"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDI ,Enter power down mode when idle" "Not entered,Entered"
|
|
bitfld.long 0x00 11. " SBI ,Enter Standby mode when idle" "Not put,Put"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SLOWCK ,Slow clock mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ROVRIE ,Regular data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " REOCIE ,Regular end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " JOVRIE ,Injected data overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " JEOCIE ,Injected end of conversion interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOCALIE ,End of calibration interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CR2,SDADC3 control register 2"
|
|
bitfld.long 0x00 24. " FAST ,Fast conversion mode selection" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " RSWSTART ,Software start of a conversion on the regular channel" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 22. " RCONT ,Continuous mode selection for regular conversions" "Once,Repeated"
|
|
bitfld.long 0x00 16.--19. " RCH ,Regular channel selection" "Channel 0,Channel 1,Channel 2,Channel 3,Channel 4,Channel 5,Channel 6,Channel 7,Channel 8,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " JSWSTART ,Start a conversion of the injected group of channels" "No effect,Started"
|
|
bitfld.long 0x00 13.--14. " JEXTEN ,Trigger enable and trigger edge selection for injected conversions" "Disabled,Rising,Falling,Both"
|
|
textline " "
|
|
bitfld.long 0x00 8.--10. " JEXTSEL ,Trigger signal selection for launching injected conversions" "TIM16_CH1,TIM12_CH2,TIM2_CH4,TIM3_CH3,TIM4_CH3,TIM19_CH4,EXTI15,EXTI11"
|
|
textline " "
|
|
bitfld.long 0x00 6. " JDS ,Delay start of injected conversions" "ASAP,Delayed"
|
|
bitfld.long 0x00 5. " JCONT ,Continuous mode selection for injected conversions" "Once,Repeated"
|
|
textline " "
|
|
bitfld.long 0x00 4. " STARTCALIB ,Start calibration" "No effect,Start"
|
|
bitfld.long 0x00 1.--2. " CALIBCNT ,Number of calibration sequences to be performed" "One,Two,Three,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " ADON ,SDADC3 enable" "Disabled,Enabled"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ISR,SDADC3 interrupt and status register"
|
|
bitfld.long 0x00 31. " INITRDY ,Initialization mode is ready" "Not ready,Ready"
|
|
bitfld.long 0x00 15. " STABIP ,Stabilization in progress status" "Stabilized/Power down/Standby,In progress"
|
|
textline " "
|
|
bitfld.long 0x00 14. " RCIP ,Regular conversion in progress status" "Not issued,In progress/Requested"
|
|
bitfld.long 0x00 13. " JCIP ,Injected conversion in progress status" "Not issued,In progress/Requested"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CALIBIP ,Calibration in progress status" "Bot issued,In progress/Requested"
|
|
bitfld.long 0x00 4. " ROVRF ,Regular conversion overrun flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " REOCF ,End of regular conversion flag" "Not completed,Completed"
|
|
bitfld.long 0x00 2. " JOVRF ,Injected conversion overrun flag" "Not injected,Injected"
|
|
textline " "
|
|
bitfld.long 0x00 1. " JEOCF ,End of injected conversion flag" "Not completed,Completed"
|
|
bitfld.long 0x00 0. " EOCALF ,End of calibration flag" "Not completed,Completed"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CLRISR,SDADC3 interrupt and status clear register"
|
|
eventfld.long 0x00 4. " CLRROVRF ,Clear the regular conversion overrun flag" "No effect,Cleared"
|
|
eventfld.long 0x00 2. " CLRJOVRF ,Clear the injected conversion overrun flag" "No effect,Cleared"
|
|
textline " "
|
|
eventfld.long 0x00 0. " CLREOCALF ,Clear the end of calibration flag" "No effect,Cleared"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "JCHGR,SDADC3 injected channel group selection register"
|
|
hexmask.long.word 0x00 0.--8. 1. " JCHG ,Injected channel group selection"
|
|
if (((per.l(ad:0x40016800+0x04))&0x01)==0x01)&&(((per.l(ad:0x40016800+0x08))&0x80000000)==0x00)
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CONF0R,SDADC3 configuration 0 register"
|
|
bitfld.long 0x00 30.--31. " COMMON0 ,Common mode for configuration 0" "Ground,VCM (VDD/2),VDD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE0 ,Single-ended mode for configuration 0" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN0 ,Gain setting for configuration 0" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET0 ,Twelve-bit calibration offset for configuration 0"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CONF1R,SDADC3 configuration 1 register"
|
|
bitfld.long 0x00 30.--31. " COMMON1 ,Common mode for configuration 1" "Ground,VCM (VDD/2),VDD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE1 ,Single-ended mode for configuration 1" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN1 ,Gain setting for configuration 1" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Twelve-bit calibration offset for configuration 1"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CONF2R,SDADC3 configuration 2 register"
|
|
bitfld.long 0x00 30.--31. " COMMON2 ,Common mode for configuration 2" "VSSSD,VDDSDx/2,VDDSDx,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE2 ,Single-ended mode for configuration 2" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN2 ,Gain setting for configuration 2" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Twelve-bit calibration offset for configuration 2"
|
|
rgroup.long 0x40++0x03
|
|
line.long 0x00 "CONFCHR1,SDADC3 channel configuration register 1"
|
|
bitfld.long 0x00 28.--29. " CONFCH7 ,Channel 7 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 24.--25. " CONFCH6 ,Channel 6 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " CONFCH5 ,Channel 5 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 16.--17. " CONFCH4 ,Channel 4 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CONFCH3 ,Channel 3 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 8.--9. " CONFCH2 ,Channel 2 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CONFCH1 ,Channel 1 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 0.--1. " CONFCH0 ,Channel 0 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CONFCHR2,SDADC3 channel configuration register 2"
|
|
bitfld.long 0x00 0.--1. " CONFCH8 ,Channel 8 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CONF0R,SDADC3 configuration 0 register"
|
|
bitfld.long 0x00 30.--31. " COMMON0 ,Common mode for configuration 0" "Ground,VCM (VDD/2),VDD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE0 ,Single-ended mode for configuration 0" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN0 ,Gain setting for configuration 0" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET0 ,Twelve-bit calibration offset for configuration 0"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CONF1R,SDADC3 configuration 1 register"
|
|
bitfld.long 0x00 30.--31. " COMMON1 ,Common mode for configuration 1" "Ground,VCM (VDD/2),VDD,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE1 ,Single-ended mode for configuration 1" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN1 ,Gain setting for configuration 1" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET1 ,Twelve-bit calibration offset for configuration 1"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CONF2R,SDADC3 configuration 2 register"
|
|
bitfld.long 0x00 30.--31. " COMMON2 ,Common mode for configuration 2" "VSSSD,VDDSDx/2,VDDSDx,?..."
|
|
textline " "
|
|
bitfld.long 0x00 26.--27. " SE2 ,Single-ended mode for configuration 2" "Differential,Single-ended offset,,Single-ended zero-volt reference"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " GAIN2 ,Gain setting for configuration 2" "1,2,4,8,16,32,,0.5"
|
|
hexmask.long.word 0x00 0.--11. 1. " OFFSET2 ,Twelve-bit calibration offset for configuration 2"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CONFCHR1,SDADC3 channel configuration register 1"
|
|
bitfld.long 0x00 28.--29. " CONFCH7 ,Channel 7 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 24.--25. " CONFCH6 ,Channel 6 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " CONFCH5 ,Channel 5 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 16.--17. " CONFCH4 ,Channel 4 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " CONFCH3 ,Channel 3 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 8.--9. " CONFCH2 ,Channel 2 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " CONFCH1 ,Channel 1 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
bitfld.long 0x00 0.--1. " CONFCH0 ,Channel 0 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CONFCHR2,SDADC3 channel configuration register 2"
|
|
bitfld.long 0x00 0.--1. " CONFCH8 ,Channel 8 configuration" "CONFR0,CONFR1,CONFR2,?..."
|
|
endif
|
|
hgroup.long 0x60++0x03
|
|
hide.long 0x00 "JDATAR,SDADC3 data register for injected group"
|
|
in
|
|
hgroup.long 0x64++0x03
|
|
hide.long 0x00 "RDATAR,SDADC3 data register for the regular channel"
|
|
in
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")
|
|
endif
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.open "DAC (Digital To Analog Converter)"
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&!cpuis("STM32F302*6")&&!cpuis("STM32F302*8")&&!cpuis("STM32F303*6")&&!cpuis("STM32F303*8")&&cpu()!="STM32F328C8"&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"&&!cpuis("STM32F334*4")&&!cpuis("STM32F334*6")&&!cpuis("STM32F334*8")&&(cpu()!="STM32F358CC")&&(cpu()!="STM32F358RC")&&(cpu()!="STM32F358VC")&&(cpu()!="STM32F378CC")&&(cpu()!="STM32F378RC")&&(cpu()!="STM32F378VC")&&!cpuis("STM32F302*")&&!cpuis("STM32F303*")
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")
|
|
tree "DAC1"
|
|
base ad:0x40007400
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
width 17.
|
|
if ((per.l(ad:0x40007400)&0x04)==0x04)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC1 channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC1 channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC1 channel 1 mask(unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC1 channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3/8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,,,Timer 15 TRGO,Timer 2 TRGO,,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 18 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TEN1 ,DAC1 channel 1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC1 channel 1 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " EN1 ,DAC1 channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC1 channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC1 channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC1 channel 1 mask(unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC1 channel 1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC1 channel 1 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " EN1 ,DAC1 channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC1_SWTRIGR,DAC1 Software Trigger Register"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,DAC1 channel 1 software trigger" "Disable,Enable"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "DAC1_DHR12R1,DAC1 channel 1 12-bit Right-aligned Data Holding Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC1C1DHR ,DAC1 channel 1 12-bit Right aligned data"
|
|
line.long 0x04 "DAC1_DHR12L1,DAC1 channel 1 12-bit Left aligned Data Holding Register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DAC1C1DHR ,DAC1 channel 1 12-bit Left aligned data"
|
|
line.long 0x08 "DAC1_DHR8R1,DAC1 channel 1 8-bit Right aligned Data Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " DAC1C1DHR ,DAC1 channel 1 8-bit Right aligned data"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DAC1_DOR1,DAC1 channel 1 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC1C1DOR ,DAC1 channel 1 data output"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC1_SR,DAC1 status register"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,DAC1 channel 1 DMA underrun flag" "No error,Error"
|
|
width 0xb
|
|
else
|
|
width 17.
|
|
if ((per.l(ad:0x40007400)&0x40004)==0x40004)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,Channel 2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 3/8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,Channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3/8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 18 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x00004)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,Channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3/8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 18 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x40000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,Channel 2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 3/8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC1_SWTRIGR,DAC1 software trigger register"
|
|
bitfld.long 0x00 1. " SWTRIG2 ,Channel 2 software trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,Channel 1 software trigger" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x08++0x23
|
|
line.long 0x00 "DAC1_DHR12R1,DAC1 channel 1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC1C1DHR ,Channel 1 12-bit right-aligned data"
|
|
line.long 0x04 "DAC1_DHR12L1,DAC1 channel 1 12-bit left-aligned data holding register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DAC1C1DHR ,Channel 1 12-bit left-aligned data"
|
|
line.long 0x08 "DAC1_DHR8R1,DAC1 channel 1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DAC1C1DHR ,Channel 1 8-bit right-aligned data"
|
|
line.long 0x0C "DAC1_DHR12R2,DAC1 channel 2 12-bit right aligned data holding register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " DAC1C2DHR ,Channel 2 12-bit right-aligned data"
|
|
line.long 0x10 "DAC1_DHR12L2,DAC1 channel 2 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x10 4.--15. 1. " DAC1C2DHR ,Channel 2 12-bit left-aligned data"
|
|
line.long 0x14 "DAC1_DHR8R2,DAC1 channel 2 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DAC1C2DHR ,Channel 2 8-bit right-aligned data"
|
|
line.long 0x18 "DAC1_DHR12RD,Dual DAC1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x18 16.--27. 1. " DAC1C2DHR ,Channel 2 12-bit right-aligned data"
|
|
hexmask.long.word 0x18 0.--11. 1. " DAC1C1DHR ,Channel 1 12-bit right-aligned data"
|
|
line.long 0x1C "DAC1_DHR12LD,DUAL DAC1 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x1C 20.--31. 1. " DAC1C2DHR ,Channel 2 12-bit left-aligned data"
|
|
hexmask.long.word 0x1C 4.--15. 1. " DAC1C1DHR ,Channel 1 12-bit left-aligned data"
|
|
line.long 0x20 "DAC1_DHR8RD,DUAL DAC1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x20 8.--15. 1. " DAC1C2DHR ,Channel 2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x20 0.--7. 1. " DAC1C1DHR ,Channel 1 8-bit right-aligned data"
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "DAC1_DOR1,DAC1 channel 1 data output register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC1C1DOR ,Channel 1 data output"
|
|
line.long 0x04 "DAC1_DOR2,DAC1 channel 2 data output register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DAC1C2DOR ,Channel 2 data output"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC1_SR,Status register"
|
|
eventfld.long 0x00 29. " DMAUDR2 ,Channel 2 DMA underrun flag" "No error,Error"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,Channel 1 DMA underrun flag" "No error,Error"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
tree "DAC2"
|
|
base ad:0x40009800
|
|
width 17.
|
|
if ((per.l(ad:0x40009800)&0x04)==0x04)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC2_CR,DAC2 control register"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC2 channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC2 channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC2 channel 1 mask(unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC2 channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC2 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3/8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC2 channel 1 Trigger selection" "Timer 6 TRGO,,,Timer 15 TRGO,Timer 2 TRGO,,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC2 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 18 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TEN1 ,DAC2 channel 1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC2 channel 1 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " EN1 ,DAC2 channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC2_CR,DAC2 control register"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC2 channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC2 channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC2 channel 1 mask(unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC2 channel 1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC2 channel 1 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " EN1 ,DAC2 channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC2_SWTRIGR,DAC2 Software Trigger Register"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,DAC2 channel 1 software trigger" "Disable,Enable"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "DAC2_DHR12R1,DAC2 channel 1 12-bit Right-aligned Data Holding Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC2C1DHR ,DAC2 channel 1 12-bit Right aligned data"
|
|
line.long 0x04 "DAC2_DHR12L1,DAC2 channel 1 12-bit Left aligned Data Holding Register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DAC2C1DHR ,DAC2 channel 1 12-bit Left aligned data"
|
|
line.long 0x08 "DAC2_DHR8R1,DAC2 channel 1 8-bit Right aligned Data Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " DAC2C1DHR ,DAC2 channel 1 8-bit Right aligned data"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DAC2_DOR1,DAC2 channel 1 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC2C1DOR ,DAC2 channel 1 data output"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC2_SR,DAC2 status register"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,DAC2 channel 1 DMA underrun flag" "No error,Error"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
elif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")
|
|
tree "DAC1"
|
|
base ad:0x40007400
|
|
width 14.
|
|
if ((per.l(ad:0x40007400)&0x04)==0x04)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC1 channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC1 channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC1 channel 1 mask(unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC1 channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 18 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC1 channel 1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC1 channel 1 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " EN1 ,DAC1 channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC1 channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC1 channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC1 channel 1 mask(unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC1 channel 1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC1 channel 1 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " EN1 ,DAC1 channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC1_SWTRIGR,DAC1 Software Trigger Register"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,DAC1 channel 1 software trigger" "Disable,Enable"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "DAC1_DHR12R1,DAC1 channel 1 12-bit Right-aligned Data Holding Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC1C1DHR ,DAC1 channel 1 12-bit Right aligned data"
|
|
line.long 0x04 "DAC1_DHR12L1,DAC1 channel 1 12-bit Left aligned Data Holding Register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DAC1C1DHR ,DAC1 channel 1 12-bit Left aligned data"
|
|
line.long 0x08 "DAC1_DHR8R1,DAC1 channel 1 8-bit Right aligned Data Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " DAC1C1DHR ,DAC1 channel 1 8-bit Right aligned data"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DAC1_DOR1,DAC1 channel 1 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC1C1DOR ,DAC1 channel 1 data output"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC1_SR,DAC1 status register"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,DAC1 channel 1 DMA underrun flag" "No error,Error"
|
|
width 0xb
|
|
tree.end
|
|
else
|
|
tree "DAC1"
|
|
base ad:0x40007400
|
|
width 13.
|
|
if ((per.l(ad:0x40007400)&0x40004)==0x40004)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,Channel 2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,Channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 18 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x00004)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,Channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 18 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x40000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,Channel 2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC1_SWTRIGR,DAC1 software trigger register"
|
|
bitfld.long 0x00 1. " SWTRIG2 ,Channel 2 software trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,Channel 1 software trigger" "Disabled,Enabled"
|
|
group.long 0x08++0x23
|
|
line.long 0x00 "DAC1_DHR12R1,DAC1 channel 1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC1C1DHR ,Channel 1 12-bit right-aligned data"
|
|
line.long 0x04 "DAC1_DHR12L1,DAC1 channel 1 12-bit left-aligned data holding register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DAC1C1DHR ,Channel 1 12-bit left-aligned data"
|
|
line.long 0x08 "DAC1_DHR8R1,DAC1 channel 1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DAC1C1DHR ,Channel 1 8-bit right-aligned data"
|
|
line.long 0x0C "DAC1_DHR12R2,DAC1 channel 2 12-bit right aligned data holding register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " DAC1C2DHR ,Channel 2 12-bit right-aligned data"
|
|
line.long 0x10 "DAC1_DHR12L2,DAC1 channel 2 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x10 4.--15. 1. " DAC1C2DHR ,Channel 2 12-bit left-aligned data"
|
|
line.long 0x14 "DAC1_DHR8R2,DAC1 channel 2 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DAC1C2DHR ,Channel 2 8-bit right-aligned data"
|
|
line.long 0x18 "DAC1_DHR12RD,Dual DAC1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x18 16.--27. 1. " DAC1C2DHR ,Channel 2 12-bit right-aligned data"
|
|
hexmask.long.word 0x18 0.--11. 1. " DAC1C1DHR ,Channel 1 12-bit right-aligned data"
|
|
line.long 0x1C "DAC1_DHR12LD,DUAL DAC1 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x1C 20.--31. 1. " DAC1C2DHR ,Channel 2 12-bit left-aligned data"
|
|
hexmask.long.word 0x1C 4.--15. 1. " DAC1C1DHR ,Channel 1 12-bit left-aligned data"
|
|
line.long 0x20 "DAC1_DHR8RD,DUAL DAC1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x20 8.--15. 1. " DAC1C2DHR ,Channel 2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x20 0.--7. 1. " DAC1C1DHR ,Channel 1 8-bit right-aligned data"
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "DAC1_DOR1,DAC1 channel 1 data output register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC1C1DOR ,Channel 1 data output"
|
|
line.long 0x04 "DAC1_DOR2,DAC1 channel 2 data output register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DAC1C2DOR ,Channel 2 data output"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC1_SR,Status register"
|
|
eventfld.long 0x00 29. " DMAUDR2 ,Channel 2 DMA underrun flag" "No error,Error"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,Channel 1 DMA underrun flag" "No error,Error"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"
|
|
tree "DAC2"
|
|
base ad:0x40009800
|
|
width 13.
|
|
if ((per.l(ad:0x40009800)&0x40004)==0x40004)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC2_CR,DAC2 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,Channel 2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,Channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC2 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 18 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40009800)&0x40004)==0x00004)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC2_CR,DAC2 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,Channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC2 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 18 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40009800)&0x40004)==0x40000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC2_CR,DAC2 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,Channel 2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC2_CR,DAC2 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC2_SWTRIGR,DAC2 software trigger register"
|
|
bitfld.long 0x00 1. " SWTRIG2 ,Channel 2 software trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,Channel 1 software trigger" "Disabled,Enabled"
|
|
group.long 0x08++0x23
|
|
line.long 0x00 "DAC2_DHR12R1,DAC2 channel 1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC2C1DHR ,Channel 1 12-bit right-aligned data"
|
|
line.long 0x04 "DAC2_DHR12L1,DAC2 channel 1 12-bit left-aligned data holding register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DAC2C1DHR ,Channel 1 12-bit left-aligned data"
|
|
line.long 0x08 "DAC2_DHR8R1,DAC2 channel 1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DAC2C1DHR ,Channel 1 8-bit right-aligned data"
|
|
line.long 0x0C "DAC2_DHR12R2,DAC2 channel 2 12-bit right aligned data holding register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " DAC2C2DHR ,Channel 2 12-bit right-aligned data"
|
|
line.long 0x10 "DAC2_DHR12L2,DAC2 channel 2 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x10 4.--15. 1. " DAC2C2DHR ,Channel 2 12-bit left-aligned data"
|
|
line.long 0x14 "DAC2_DHR8R2,DAC2 channel 2 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DAC2C2DHR ,Channel 2 8-bit right-aligned data"
|
|
line.long 0x18 "DAC2_DHR12RD,Dual DAC2 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x18 16.--27. 1. " DAC2C2DHR ,Channel 2 12-bit right-aligned data"
|
|
hexmask.long.word 0x18 0.--11. 1. " DAC2C1DHR ,Channel 1 12-bit right-aligned data"
|
|
line.long 0x1C "DAC2_DHR12LD,DUAL DAC2 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x1C 20.--31. 1. " DAC2C2DHR ,Channel 2 12-bit left-aligned data"
|
|
hexmask.long.word 0x1C 4.--15. 1. " DAC2C1DHR ,Channel 1 12-bit left-aligned data"
|
|
line.long 0x20 "DAC2_DHR8RD,DUAL DAC2 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x20 8.--15. 1. " DAC2C2DHR ,Channel 2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x20 0.--7. 1. " DAC2C1DHR ,Channel 1 8-bit right-aligned data"
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "DAC2_DOR1,DAC2 channel 1 data output register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC2C1DOR ,Channel 1 data output"
|
|
line.long 0x04 "DAC2_DOR2,DAC2 channel 2 data output register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DAC2C2DOR ,Channel 2 data output"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC2_SR,Status register"
|
|
eventfld.long 0x00 29. " DMAUDR2 ,Channel 2 DMA underrun flag" "No error,Error"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,Channel 1 DMA underrun flag" "No error,Error"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?E")||cpuis("STM32F302?D")
|
|
tree "DAC1"
|
|
base ad:0x40007400
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
width 17.
|
|
if ((per.l(ad:0x40007400)&0x04)==0x04)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC1 channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC1 channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC1 channel 1 mask(unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,DAC1 channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3/8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,,,Timer 15 TRGO,Timer 2 TRGO,,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 18 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TEN1 ,DAC1 channel 1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC1 channel 1 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " EN1 ,DAC1 channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,DAC1 channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,DAC1 channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,DAC1 channel 1 mask(unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,DAC1 channel 1 Trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,DAC1 channel 1 output buffer disable" "Enabled,Disabled"
|
|
bitfld.long 0x00 0. " EN1 ,DAC1 channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC1_SWTRIGR,DAC1 Software Trigger Register"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,DAC1 channel 1 software trigger" "Disable,Enable"
|
|
group.long 0x08++0x0B
|
|
line.long 0x00 "DAC1_DHR12R1,DAC1 channel 1 12-bit Right-aligned Data Holding Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC1C1DHR ,DAC1 channel 1 12-bit Right aligned data"
|
|
line.long 0x04 "DAC1_DHR12L1,DAC1 channel 1 12-bit Left aligned Data Holding Register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DAC1C1DHR ,DAC1 channel 1 12-bit Left aligned data"
|
|
line.long 0x08 "DAC1_DHR8R1,DAC1 channel 1 8-bit Right aligned Data Holding Register"
|
|
hexmask.long.byte 0x8 0.--7. 1. " DAC1C1DHR ,DAC1 channel 1 8-bit Right aligned data"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "DAC1_DOR1,DAC1 channel 1 Data Output Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC1C1DOR ,DAC1 channel 1 data output"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC1_SR,DAC1 status register"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,DAC1 channel 1 DMA underrun flag" "No error,Error"
|
|
width 0xb
|
|
else
|
|
width 17.
|
|
if ((per.l(ad:0x40007400)&0x40004)==0x40004)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,Channel 2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 3/8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,Channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3/8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 18 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x00004)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 6.--7. " WAVE1 ,Channel 1 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3/8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 3.--5. " TSEL1 ,DAC1 channel 1 Trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 18 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007400)&0x40004)==0x40000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
bitfld.long 0x00 22.--23. " WAVE2 ,Channel 2 noise/triangle wave generation enable" "Disabled,Noise,Triangle,Triangle"
|
|
textline " "
|
|
sif (cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F398VE")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 3/8 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 19.--21. " TSEL2 ,Channel 2 trigger selection" "Timer 6 TRGO,Timer 3 TRGO,Timer 7 TRGO,Timer 5 TRGO,Timer 2 TRGO,Timer 4 TRGO,External line9,Software trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DAC1_CR,DAC1 control register"
|
|
bitfld.long 0x00 29. " DMAUDRIE2 ,Channel 2 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " DMAEN2 ,Channel 2 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--27. " MAMP2 ,Channel 2 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TEN2 ,Channel 2 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BOFF2 ,Channel 2 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 16. " EN2 ,Channel 2" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DMAUDRIE1 ,Channel 1 DMA underrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DMAEN1 ,Channel 1 DMA enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " MAMP1 ,Channel 1 mask (unmask bits of LFSR)/amplitude selector" "0/1,[1:0]/3,[2:0]/7,[3:0]/15,[4:0]/31,[5:0]/63,[6:0]/127,[7:0]/255,[8:0]/511,[9:0]/1023,[10:0]/2047,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095,[11:0]/4095"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TEN1 ,Channel 1 trigger enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BOFF1 ,Channel 1 output buffer disable" "No,Yes"
|
|
bitfld.long 0x00 0. " EN1 ,Channel 1 enable" "Disabled,Enabled"
|
|
endif
|
|
wgroup.long 0x04++0x03
|
|
line.long 0x00 "DAC1_SWTRIGR,DAC1 software trigger register"
|
|
bitfld.long 0x00 1. " SWTRIG2 ,Channel 2 software trigger" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SWTRIG1 ,Channel 1 software trigger" "Disabled,Enabled"
|
|
textline " "
|
|
group.long 0x08++0x23
|
|
line.long 0x00 "DAC1_DHR12R1,DAC1 channel 1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC1C1DHR ,Channel 1 12-bit right-aligned data"
|
|
line.long 0x04 "DAC1_DHR12L1,DAC1 channel 1 12-bit left-aligned data holding register"
|
|
hexmask.long.word 0x04 4.--15. 1. " DAC1C1DHR ,Channel 1 12-bit left-aligned data"
|
|
line.long 0x08 "DAC1_DHR8R1,DAC1 channel 1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DAC1C1DHR ,Channel 1 8-bit right-aligned data"
|
|
line.long 0x0C "DAC1_DHR12R2,DAC1 channel 2 12-bit right aligned data holding register"
|
|
hexmask.long.word 0x0C 0.--11. 1. " DAC1C2DHR ,Channel 2 12-bit right-aligned data"
|
|
line.long 0x10 "DAC1_DHR12L2,DAC1 channel 2 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x10 4.--15. 1. " DAC1C2DHR ,Channel 2 12-bit left-aligned data"
|
|
line.long 0x14 "DAC1_DHR8R2,DAC1 channel 2 8-bit right-aligned data holding register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " DAC1C2DHR ,Channel 2 8-bit right-aligned data"
|
|
line.long 0x18 "DAC1_DHR12RD,Dual DAC1 12-bit right-aligned data holding register"
|
|
hexmask.long.word 0x18 16.--27. 1. " DAC1C2DHR ,Channel 2 12-bit right-aligned data"
|
|
hexmask.long.word 0x18 0.--11. 1. " DAC1C1DHR ,Channel 1 12-bit right-aligned data"
|
|
line.long 0x1C "DAC1_DHR12LD,DUAL DAC1 12-bit left aligned data holding register"
|
|
hexmask.long.word 0x1C 20.--31. 1. " DAC1C2DHR ,Channel 2 12-bit left-aligned data"
|
|
hexmask.long.word 0x1C 4.--15. 1. " DAC1C1DHR ,Channel 1 12-bit left-aligned data"
|
|
line.long 0x20 "DAC1_DHR8RD,DUAL DAC1 8-bit right aligned data holding register"
|
|
hexmask.long.byte 0x20 8.--15. 1. " DAC1C2DHR ,Channel 2 8-bit right-aligned data"
|
|
hexmask.long.byte 0x20 0.--7. 1. " DAC1C1DHR ,Channel 1 8-bit right-aligned data"
|
|
rgroup.long 0x2C++0x07
|
|
line.long 0x00 "DAC1_DOR1,DAC1 channel 1 data output register"
|
|
hexmask.long.word 0x00 0.--11. 1. " DAC1C1DOR ,Channel 1 data output"
|
|
line.long 0x04 "DAC1_DOR2,DAC1 channel 2 data output register"
|
|
hexmask.long.word 0x04 0.--11. 1. " DAC1C2DOR ,Channel 2 data output"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DAC1_SR,Status register"
|
|
eventfld.long 0x00 29. " DMAUDR2 ,Channel 2 DMA underrun flag" "No error,Error"
|
|
eventfld.long 0x00 13. " DMAUDR1 ,Channel 1 DMA underrun flag" "No error,Error"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "COMP (Comparator)"
|
|
base ad:0x40010000
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
width 10.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "COMP_CSR,COMP control and status register"
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")
|
|
bitfld.long 0x00 31. " COMP2LOCK ,Comparator 2 lock" "Read-write,Read-only"
|
|
bitfld.long 0x00 30. " COMP2OUT ,Comparator 2 output" "Low,High"
|
|
bitfld.long 0x00 28.--29. " COMP2HYST ,Comparator 2 hysteresis" "No,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " COMP2POL ,Comparator 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 24.--26. " COMP2OUTSEL ,Comparator 2 output selection" "No selection,Timer 16 break input,Timer 4 Input capture 1,Timer 4 OCrefclear input,Timer 2 input capture 4,Timer 2 OCrefclear input,Timer 3 input capture 1,Timer 3 OCrefclear input"
|
|
bitfld.long 0x00 23. " WNDWEN ,Window mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " COMP2INSEL ,Comparator 2 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,DAC1_OUT1/PA4,PA5/DAC1_OUT2,PA2,PA6/DAC2_OUT1"
|
|
bitfld.long 0x00 18.--19. " COMP2MODE ,Comparator 2 mode" "High speed,Medium speed,Low power,Ultra-low power"
|
|
bitfld.long 0x00 16. " COMP2EN ,Comparator 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " COMP1LOCK ,Comparator 1 lock" "Read-write,Read-only"
|
|
bitfld.long 0x00 14. " COMP1OUT ,Comparator 1 output" "Low,High"
|
|
bitfld.long 0x00 12.--13. " COMP1HYST ,Comparator 1 hysteresis" "No,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP1POL ,Comparator 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8.--10. " COMP1OUTSEL ,Comparator 1 output selection" "No selection,Timer 15 break input,Timer 3 Input capture 1,Timer 3 OCrefclear input,Timer 2 input capture 4,Timer 2 OCrefclear input,Timer 5 input capture 4,Timer 5 OCrefclear input"
|
|
bitfld.long 0x00 4.--6. " COMP1INSEL ,Comparator 1 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,DAC1_OUT1/PA4,PA5/DAC1_OUT2,PA0,PA6/DAC2_OUT1"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " COMP1MODE ,Comparator 1 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
bitfld.long 0x00 1. " COMP1SW1 ,This bit closes a switch between comparator 1 non-inverting input on PA0 and PA4 (DAC) I/O" "Opened,Closed"
|
|
bitfld.long 0x00 0. " COMP1EN ,Comparator 1 enable" "Disabled,Enabled"
|
|
width 0xB
|
|
elif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"
|
|
width 10.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "COMP2_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 2 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 2 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 2 output blanking source" "No blanking,TIM1 OC5,TIM2 OC3,TIM3 OC3,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " POL ,Comparator 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 2 output selection" "No selection,Timer 1 break input 1,Timer 1 break input 2,,,Timer 1 break input 2,Timer 1 OCREF_CLR input,Timer 1 input capture 1,Timer 2 input capture 4,Timer 2 OCREF_CLR input,,,?..."
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 2 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1,,PA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " INP_DAC ,Comparator 2 non inverting input connection to DAC output" "Open,Closed"
|
|
bitfld.long 0x00 0. " EN ,Comparator 2 enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "COMP4_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 4 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 4 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 4 blanking source" "No blanking,,,TIM15 OC1,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " POL ,Comparator 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 4 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,Timer 1 break input 2,,,Timer 15 input capture 2,,Timer 15 OCrefclear input,,?..."
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 4 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1,,,PB2"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Comparator 4 enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "COMP6_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 6 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 6 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 6 blanking source" "No blanking,,,TIM2_OC4,TIM15_OC2,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " POL ,Comparator 6 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 6 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,Timer 1 break input 2,Timer 2 input capture 2,,Timer 2 OCrefclear input,Timer 16 OCrefclear input,Timer 16 input capture 1,,?..."
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 6 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1,,,PB15"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Comparator 6 enable" "Disabled,Enabled"
|
|
width 0xB
|
|
elif cpuis("STM32F302*6")||cpuis("STM32F302*8")
|
|
width 10.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "COMP2_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 2 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 2 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 2 output blanking source" "No blanking,TIM1 OC5,TIM2 OC3,TIM3 OC3,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " COMP2POL ,Comparator 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 2 output selection" "No selection,Timer 1 break input 1,Timer 1 break input 2,,,Timer 1 break input 2,Timer 1 OCREF_CLR input,Timer 1 input capture 1,Timer 2 input capture 4,Timer 2 OCREF_CLR input,Timer 3 input capture 1,Timer 3 OCrefclear input,?..."
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 2 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1,,PA2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 1. " INP_DAC ,Comparator 2 non inverting input connection to DAC output" "Open,Closed"
|
|
bitfld.long 0x00 0. " EN ,Comparator 2 enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "COMP4_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 4 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 4 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 4 blanking source" "No blanking,,,TIM15 OC1,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " POL ,Comparator 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 4 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,Timer 1 break input 2,,,Timer 15 input capture 2,,Timer 15 OCrefclear input,,?..."
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 4 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1,,,PB2"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Comparator 4 enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "COMP6_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 6 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 6 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 6 blanking source" "No blanking,,,TIM3_OC4,,TIM15_OC1,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " POL ,Comparator 6 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 6 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,Timer 1 break input 2,Timer 2 input capture 2,,Timer 2 OCREF_CLR input,Timer 16 OCREF_CLR input,Timer 16 input capture 1,,?..."
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 6 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1,,PD10,PB15"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Comparator 6 enable" "Disabled,Enabled"
|
|
;COMP6 -> OUTSEL -> 1011: Timer 4 input capture 4 (only in STM32F302xB/C)
|
|
width 0xB
|
|
elif cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
width 11.
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "COMP1_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 1 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 1 output" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 1 blanking source" "No blanking,TIM1_OC5,TIM2_OC3,TIM3_OC3,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 1 hysteresis" "None,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " POL ,Comparator 1 output polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 1 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1+2 break input 2,Timer 1 OCREF_CLR input,Timer 1 input capture 1,Timer 2 input capture 4,Timer 2 OCREF_CLR input,Timer 3 input capture 1,Timer 3 OCREF_CLR input,Timer 20 break input 1,Timer 20 break input 2,Timer 1/8/20 break input 2,?..."
|
|
textline " "
|
|
elif !cpuis("STM32F398VE")
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 1 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1+2 break input 2,Timer 1 OCREF_CLR input,Timer 1 input capture 1,Timer 2 input capture 4,Timer 2 OCREF_CLR input,Timer 3 input capture 1,Timer 3 OCREF_CLR input,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 1 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1,PA5 or DAC2,PA0,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 1 mode" "High speed,Medium speed,Low power,Ultra-low power"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " INP_DAC , Comparator 1 non inverting input connection to DAC output" "Opened,Closed"
|
|
bitfld.long 0x00 0. " EN ,Comparator 1 enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "COMP2_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 2 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 2 output" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 2 blanking source" "No blanking,TIM2_OC5,TIM2_OC3,TIM3_OC3,?..."
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 1 hysteresis" "None,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " POL ,Comparator 2 output polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 2 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1 break input2 + Timer 8 break input 2,Timer 1 OCREF_CLR input,Timer 1 input capture 1,Timer 2 input capture 4,Timer 2 OCREF_CLR input,Timer 3 input capture 1,Timer 3 OCREF_CLR input,?..."
|
|
textline " "
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 2 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1 break input2 + Timer 8 break input 2,Timer 1 OCREF_CLR input,Timer 1 input capture 1,Timer 2 input capture 4,Timer 2 OCREF_CLR input,Timer 3 input capture 1,Timer 3 OCREF_CLR input,Timer 20 Break Input selected,Timer 20 Break2 Input selected,Timer 1/8/20 Break2,Timer 20 OCREF_CLR input selected"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 2 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,,,Timer 1 OCREF_CLR input,Timer 1 input capture 1,Timer 2 input capture 4,Timer 2 OCREF_CLR input,,,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 9. " WINMODE ,Comparator 2 window mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 2 non inverting input selection" "PA7,PA3"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 4.--6. 22. " INMSEL ,Comparator 2 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1 output,PA5 or DAC1_CH2 output,PA2,,DAC2_CH1 output,?..."
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 2 mode" "High speed,Medium speed,Low power,Ultra-low power"
|
|
textline " "
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 2 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4/DAC1_CH1,,PA2,DAC2_CH1 output"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 2 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1 output,DAC1_CH2 output,PA2,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")
|
|
bitfld.long 0x00 1. " INP_DAC , Comparator 2 non inverting input connection to DAC output" "Switch open,Switch closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN ,Comparator 2 enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "COMP3_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 3 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 3 output" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 3 blanking source" "No blanking,TIM1_OC5,,TIM2_OC4,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 3 hysteresis" "None,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " POL ,Comparator 3 output polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 3 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1+2 break input 2,Timer 1 OCREF_CLR input,Timer 4 input capture 1,Timer 3 input capture 2,Timer 2 OCREF_CLR input,Timer 15 input capture 1,Timer 15 break input,Timer 20 Break Input selected,Timer 20 Break2 Input selected,Timer 1/8/20 Break2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 3 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1+2 break input 2,Timer 1 OCREF_CLR input,Timer 4 input capture 1,Timer 3 input capture 2,Timer 2 OCREF_CLR input,Timer 15 input capture 1,Timer 15 break input,?..."
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 2 non inverting input selection" "PB14,PD14"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 3 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4/DAC1,PA5/DAC2,PD15,PB12"
|
|
textline " "
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 3 mode" "Ultra-low,Low power,Medium speed power,High speed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN ,Comparator 3 enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "COMP4_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 4 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 4 output" "Low,High"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 4 blanking source" "No blanking,TIM3_OC4,TIM8_OC5,TIM15_OC1,?..."
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 3 hysteresis" "None,Low,Medium,High"
|
|
textline " "
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 4 blanking source" "No blanking,TIM3_OC4,,TIM15_OC1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 4 blanking source" "No blanking,TIM3_OC4,TIM8_OC5,TIM15_OC1,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " POL ,Comparator 4 output polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 4 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1+2 break input 2,Timer 3 input care 3,Timer 8 OCREF_CLR input,Timer 15 input capture 2,Timer 4 input care 2,Timer 15 OCREF_CLR input,Timer 3 OCREF_CLR input,?..."
|
|
textline " "
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 4 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,,Timer 3 input care 3,,Timer 15 input capture 2,,Timer 15 OCREF_CLR input,Timer 3 OCREF_CLR input,Timer 20 Break Input selected,Timer 20 Break2 Input selected,Timer 1/8/20 Break2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 4 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,,Timer 3 input care 3,,Timer 15 input capture 2,,Timer 15 OCREF_CLR input,Timer 3 OCREF_CLR input,?..."
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 9. " WINMODE ,Comparator 4 window mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 4 non inverting input selection" "PB0,PE7"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")
|
|
bitfld.long 0x00 4.--6. 22. " INMSEL ,Comparator 4 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1,PA5/DAC1_CH2,PE8,PB2,DAC2_CH1,?..."
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 4 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
textline " "
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 4 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4/DAC1_CH1,DAC1_CH2 output,PE8,PB2"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 4 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1,PA5 or DAC1_CH2,PE8,PB2"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN ,Comparator 4 enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "COMP5_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 5 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 5 output" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 5 blanking source" "No blanking,,TIM8_OC5,TIM3_OC3,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 5 hysteresis" "None,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " POL ,Comparator 5 output polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 5 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer (1 or 8) break input 2,Timer 2 input capture 1,Timer 8 OCREF_CLR input,Timer 17 input capture 1,Timer 4 input capture 3,Timer 16 break input,Timer 3 OCREF_CLR input,Timer 20 Break Input selected,Timer 20 Break2 Input selected,Timer 1/8/20 Break2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 5 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer (1 or 8) break input 2,Timer 2 input capture 1,Timer 8 OCREF_CLR input,Timer 17 input capture 1,Timer 4 input capture 3,Timer 16 break input,Timer 3 OCREF_CLR input,?..."
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 5 non inverting input selection" "PB12,PD13"
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 5 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PEA4/DAC1 output,PEA5/DAC2 output,PD13,PB10"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 5 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN ,Comparator 5 enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "COMP6_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 6 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 6 output" "Low,High"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 6 blanking source" "No blanking,,TIM8_OC5,TIM2_OC4,TIM15_OC2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 6 blanking source" "No blanking,,,TIM2_OC4,TIM15_OC2,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " POL ,Comparator 6 output polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 6 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1+2 break input 2,Timer 2 input capture 2,Timer 8 OCREF_CLR input,Timer 2 OCREF_CLR input,Timer 16 OCREF_CLR input,Timer 16 input capture 1,Timer 4 input capture 4,?..."
|
|
textline " "
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 6 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,,Timer 2 input capture 2,,Timer 2 OCREF_CLR input,Timer 16 OCREF_CLR input,Timer 16 input capture 1,,Timer 20 Break Input selected,Timer 20 Break2 Input selected,Timer 1/8/20 Break2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 6 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,,Timer 2 input capture 2,,Timer 2 OCREF_CLR input,Timer 16 OCREF_CLR input,Timer 16 input capture 1,?..."
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F398VE")
|
|
bitfld.long 0x00 9. " WINMODE ,Comparator 6 window mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")
|
|
bitfld.long 0x00 4.--6. 22. " INMSEL ,Comparator 6 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1,PA5 or DAC1_CH2 output,PD10,PB15,DAC2_CH1,?..."
|
|
textline " "
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 6 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4/DAC1_CH1,,PD10,PB15"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 6 non inverting input selection" "PD11,PB11"
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 6 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1,DAC1_CH2 output,PD10,PB15"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 6 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN ,Comparator 6 enable" "Disabled,Enabled"
|
|
sif cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F358*C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "COMP7_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 7 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 7 output" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 1 blanking source" "No blanking,TIM1_OC5,TIM8_OC5,,TIM15_OC2,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 7 hysteresis" "None,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " POL ,Comparator 7 output polarity" "Not inverted,Inverted"
|
|
textline " "
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 7 output selection" ",Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1+2 break input 2,Timer 1 OCREF_CLR input,Timer 8 OCREF_CLR input,Timer 2 input capture 3,Timer 1 input capture 2,Timer 17 OCREF_CLR input,Timer 17 break input,Timer 20 Break Input selected,Timer 20 Break2 Input selected,Timer 1/8/20 Break2,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 7 output selection" ",Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1+2 break input 2,Timer 1 OCREF_CLR input,Timer 8 OCREF_CLR input,Timer 2 input capture 3,Timer 1 input capture 2,Timer 17 OCREF_CLR input,Timer 17 break input,?..."
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 7 non inverting input selection" "PA0,PC1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 7 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1,PA4 or DAC2,PC0,"
|
|
textline " "
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 7 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " EN ,Comparator 7 enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xB
|
|
elif cpuis("STM32F302*")
|
|
width 11.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "COMP1_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 1 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 1 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 1 blanking source" "No blanking,TIM1_OC5,TIM2_OC3,TIM3_OC3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 1 hysteresis" "None,Low,Medium,High"
|
|
bitfld.long 0x00 15. " POL ,Comparator 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 1 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,Timer 1 break input 2/Timer 8 break input 2,Timer 1 OCrefclear input,Timer 1 input capture 1,Timer 2 input capture 4,Timer 2 OCrefclear input,Timer 3 input capture 1,Timer 3 OCrefclear input,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 1 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1 out,PA5,PA0,?..."
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 1 mode" "High speed,Medium speed,Low power,Ultra-low power"
|
|
bitfld.long 0x00 1. " SW1 ,This bit closes a switch between comparator 1 non-inverting input on PA0 and PA4 (DAC) I/O" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COMP1EN ,Comparator 1 enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "COMP2_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 2 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 2 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 2 blanking source" "No blanking,TIM1_OC5,TIM2_OC3,TIM3_OC3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 2 hysteresis" "None,Low,Medium,High"
|
|
bitfld.long 0x00 15. " POL ,Comparator 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 2 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,Timer 1 break input 2,Timer 1 OCREF_CLR input,Timer 1 input capture 1,Timer 2 input capture 4,Timer 2 OCREF_CLR input,Timer 3 input capture 1,Timer 3 OCrefclear input,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " WINMODE ,Comparator 2 window mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 2 non inverting input selection" "PA7,PA3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 2 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1 out,PA2,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 2 mode" "High speed,Medium speed,Low power,Ultra-low power"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " COMP2EN ,Comparator 2 enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "COMP4_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 4 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 4 output" "Low,High"
|
|
textline " "
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 4 blanking source" "No blanking,TIM3 OC4,,TIM5_OC1,?..."
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 4 blanking source" "No blanking,TIM4_OC4,,TIM5_OC1,?..."
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 4 hysteresis" "None,Low,Medium,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 15. " POL ,Comparator 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 4 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,Timer 1 break input 2,Timer 3 input care 3,,Timer 15 input capture 2,Timer 4 input care 2,Timer 15 OCREF_CLR input,Timer 3 OCrefclear input,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x00 9. " WINMODE ,Comparator 4 window mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 4 non inverting input selection" "PA7,PA3"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 4 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1 out,,PE8,PB8"
|
|
textline " "
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 4 mode" "High speed,Medium speed,Low power,Ultra-low power"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " COMP4EN ,Comparator 4 enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "COMP6_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 6 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 6 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 6 blanking source" "No blanking,,TIM8_OC5,TIM2_OC4,TIM15_OC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 6 hysteresis" "None,Low,Medium,High"
|
|
bitfld.long 0x00 15. " POL ,Comparator 6 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 6 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,Timer 1 break input 2,Timer 2 input capture 2,,Timer 2 OCREF_CLR input,Timer 16 OCREF_CLR input,Timer 16 input capture 1,Timer 4 input capture 4,?..."
|
|
textline " "
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x00 9. " WINMODE ,Comparator 6 window mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 6 non inverting input selection" "PD11,PB11"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 6 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1 out,PD10,PAD15,?..."
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 6 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
bitfld.long 0x00 0. " COMP6EN ,Comparator 6 enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
elif cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")
|
|
width 10.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "COMP2_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 2 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 2 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 2 output blanking source" "No blanking,TIM1 OC5,TIM2 OC3,TIM3 OC3,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " POL ,Comparator 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 2 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,Timer 1 break input2,Timer 1 OCREF_CLR input,Timer 1 input capture 1,Timer 2 input capture 4,Timer 2 OCREF_CLR input,Timer 3 input capture 1,Timer 3 OCrefclear input,?..."
|
|
bitfld.long 0x00 4.--6. 22. " INMSEL ,Comparator 2 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1 output,DAC1_CH2 output,PA2,,DAC2_CH1 output.?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Comparator 2 enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "COMP4_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 4 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 4 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 4 blanking source" "No blanking,TIM3 OC4,,TIM15 OC1,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " POL ,Comparator 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 4 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,Timer 1 break input 2,Timer 3 input capture 3,,Timer 15 input capture 2,,Timer 15 input capture 2,,Timer 15 OCREF_CLR input,Timer 3 OCrefclear input,?..."
|
|
bitfld.long 0x00 4.--6. 22. " INMSEL ,Comparator 4 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1,DAC1_CH2,,PB2,DAC2_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Comparator 4 enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "COMP6_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 6 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " OUT ,Comparator 6 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 6 blanking source" "No blanking,,,TIM2_OC4,TIM15_OC2,,?..."
|
|
textline " "
|
|
bitfld.long 0x00 15. " POL ,Comparator 6 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 6 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,,,Timer 1 break input 2,Timer 3 input capture 3,,Timer 15 input capture 2,,Timer 15 OCREF_CLR input,Timer 3 OCrefclear input,?..."
|
|
bitfld.long 0x00 4.--6. 22. " INMSEL ,Comparator 6 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,PA4 or DAC1_CH1,DAC1_CH2,,PB2,DAC2_CH1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0. " EN ,Comparator 6 enable" "Disabled,Enabled"
|
|
width 0xB
|
|
elif cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"
|
|
width 10.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "COMP_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " COMP2LOCK ,Comparator 2 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 30. " COMP2OUT ,Comparator 2 output" "Low,High"
|
|
bitfld.long 0x00 28.--29. " COMP2HYST ,Comparator 2 hysteresis" "No,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x00 27. " COMP2POL ,Comparator 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 24.--26. " COMP2OUTSEL ,Comparator 2 output selection" "No selection,Timer 16 break input,Timer 4 input capture,Timer 4 OCrefclear input,Timer 2 input capture 4,Timer 2 OCrefclear input,Timer 3 input capture 1,Timer 3 OCrefclear input"
|
|
bitfld.long 0x00 23. " WNDWEN ,Window mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--22. " COMP2COMP2INSEL ,Comparator 2 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,DAC1_OUT1,PA5,PA2,PA6"
|
|
bitfld.long 0x00 18.--19. " COMP2MODE ,Comparator 2 mode" "High speed,Medium speed,Low power,Ultra-low power"
|
|
bitfld.long 0x00 16. " COMP2EN ,Comparator 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " COMP1LOCK , Comparator 1 lock" "Read-write,Read-only"
|
|
rbitfld.long 0x00 14. " COMP1OUT ,Comparator 1 output" "Low,High"
|
|
bitfld.long 0x00 12.--13. " COMP1HYST ,Comparator 3 hysteresis" "No,Low,Medium,High"
|
|
textline " "
|
|
bitfld.long 0x00 11. " COMP1POL ,Comparator 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 8.--10. " COMP1OUTSEL ,Comparator 1 output selection" "No selection,Timer 15 break input,Timer 3 input capture,Timer 3 OCrefclear input,Timer 2 input capture 4,Timer 2 OCrefclear input,Timer 5 input capture 4,Timer 5 OCrefclear input"
|
|
bitfld.long 0x00 4.--6. " COMP1INMSEL ,Comparator 1 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,DAC1_OUT1,PA5,PA0,PA6"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " COMP1MODE ,Comparator 1 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
bitfld.long 0x00 1. " COMP1_INP_DAC , Comparator 1 non inverting input connection to DAC output" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COMP1EN ,Comparator 1 enable" "Disabled,Enabled"
|
|
else
|
|
width 10.
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "COMP1_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 1 lock" "Read-write,Read-only"
|
|
bitfld.long 0x00 30. " OUT ,Comparator 1 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 1 blanking source" "No blanking,TIM1_OC5,TIM2_OC3,TIM3_OC3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 1 hysteresis" "No,Low,Medium,High"
|
|
bitfld.long 0x00 15. " POL ,Comparator 1 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 1 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1 break input 2/Timer 8 break input 2,Timer 1 OCrefclear input,Timer 1 input capture 1,Timer 2 input capture 4,Timer 2 OCrefclear input,Timer 3 input capture 1,Timer 3 OCrefclear input,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 1 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,COMP1_INM4,COMP1_INM5,COMP1_INM6,?..."
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 1 mode" "High speed,Medium speed,Low power,Ultra-low power"
|
|
bitfld.long 0x00 1. " SW1 ,This bit closes a switch between comparator 1 non-inverting input on PA0 and PA4 (DAC) I/O" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COMP1EN ,Comparator 1 enable" "Disabled,Enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "COMP2_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 2 lock" "Read-write,Read-only"
|
|
bitfld.long 0x00 30. " OUT ,Comparator 2 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 2 blanking source" "No blanking,TIM1_OC5,TIM2_OC3,TIM3_OC3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 2 hysteresis" "No,Low,Medium,High"
|
|
bitfld.long 0x00 15. " POL ,Comparator 2 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 2 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1 break input 2/Timer 8 break input 2,Timer 1 OCrefclear input,Timer 1 input capture 1,Timer 2 input capture 4,Timer 2 OCrefclear input,Timer 3 input capture 1,Timer 3 OCrefclear input,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " WINMODE ,Comparator 2 window mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 2 non inverting input selection" "PA7,PA3"
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 2 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,COMP2_INM4,COMP2_INM5,COMP2_INM6,?..."
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 2 mode" "High speed,Medium speed,Low power,Ultra-low power"
|
|
bitfld.long 0x00 0. " COMP2EN ,Comparator 2 enable" "Disabled,Enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "COMP3_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 3 lock" "Read-write,Read-only"
|
|
bitfld.long 0x00 30. " OUT ,Comparator 3 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 3 blanking source" "No blanking,TIM1_OC5,,TIM2_OC4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 3 hysteresis" "No,Low,Medium,High"
|
|
bitfld.long 0x00 15. " POL ,Comparator 3 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 3 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1 break input 2/Timer 8 break input 2,Timer 1 OCrefclear input,Timer 4 input capture 1,Timer 3 input capture 2,Timer 2 OCrefclear input,Timer 15 input capture 1,Timer 15 break input,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 3 non inverting input selection" "PB14,PD14"
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 3 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,COMP3_INM4,COMP3_INM5,COMP3_INM6,COMP3_NIM7"
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 3 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COMP3EN ,Comparator 3 enable" "Disabled,Enabled"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "COMP4_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 4 lock" "Read-write,Read-only"
|
|
bitfld.long 0x00 30. " OUT ,Comparator 4 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 4 blanking source" "No blanking,TIM3_OC4,TIM8_OC5,TIM15_OC1,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 4 hysteresis" "No,Low,Medium,High"
|
|
bitfld.long 0x00 15. " POL ,Comparator 4 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 4 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1 break input 2/Timer 8 break input 2,Timer 3 input capture 3,Timer 8 OCrefclear input,Timer 15 input capture 2,Timer 4 input capture 2,Timer 15 OCrefclear input,Timer 3 OCrefclear input,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " WINMODE ,Comparator 4 window mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 4 non inverting input selection" "PB0,PE7"
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 4 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,COMP4_INM4,COMP4_INM5,COMP4_INM6,COMP4_INM7"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 4 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
bitfld.long 0x00 0. " COMP4EN ,Comparator 4 enable" "Disabled,Enabled"
|
|
sif (cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "COMP5_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 5 lock" "Read-write,Read-only"
|
|
bitfld.long 0x00 30. " OUT ,Comparator 5 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 5 blanking source" "No blanking,,TIM8_OC5,TIM3_OC3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 5 hysteresis" "No,Low,Medium,High"
|
|
bitfld.long 0x00 15. " POL ,Comparator 5 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 5 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1 break input 2/Timer 8 break input 2,Timer 2 input capture 1,Timer 8 OCrefclear input,Timer 17 input capture 1,Timer 4 input capture 3,Timer 16 break input,Timer 3 OCrefclear input,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 5 non inverting input selection" "PD12,PB13"
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 5 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,COMP5_INM4,COMP5_INM5,COMP5_INM6,COMP5_INM7"
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 5 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COMP5EN ,Comparator 5 enable" "Disabled,Enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "COMP6_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 6 lock" "Read-write,Read-only"
|
|
bitfld.long 0x00 30. " OUT ,Comparator 6 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 6 blanking source" "No blanking,,TIM8_OC5,TIM2_OC4,TIM15_OC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 6 hysteresis" "No,Low,Medium,High"
|
|
bitfld.long 0x00 15. " POL ,Comparator 6 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 6 output selection" "No selection,Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1 break input 2/Timer 8 break input 2,Timer 2 input capture 2,Timer 8 OCrefclear input,Timer 2 OCrefclear input,Timer 16 OCrefclear input,Timer 16 input capture 1,Timer 4 input capture 4,?..."
|
|
textline " "
|
|
bitfld.long 0x00 9. " WINMODE ,Comparator 6 window mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 6 non inverting input selection" "PD11,PB11"
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 6 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,COMP4_INM4,COMP4_INM5,COMP4_INM6,COMP4_INM7"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 6 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
bitfld.long 0x00 0. " COMP6EN ,Comparator 6 enable" "Disabled,Enabled"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "COMP7_CSR,COMP control and status register"
|
|
bitfld.long 0x00 31. " LOCK ,Comparator 7 lock" "Read-write,Read-only"
|
|
bitfld.long 0x00 30. " OUT ,Comparator 7 output" "Low,High"
|
|
bitfld.long 0x00 18.--20. " BLANKING ,Comparator 7 blanking source" "No blanking,TIM1_OC5,TIM8_OC5,,TIM15_OC2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--17. " HYST ,Comparator 7 hysteresis" "No,Low,Medium,High"
|
|
bitfld.long 0x00 15. " POL ,Comparator 7 output polarity" "Not inverted,Inverted"
|
|
bitfld.long 0x00 10.--13. " OUTSEL ,Comparator 7 output selection" ",Timer 1 break input,Timer 1 break input 2,Timer 8 break input,Timer 8 break input 2,Timer 1 break input 2/Timer 8 break input 2,Timer 1 OCrefclear input,Timer 8 OCrefclear input,Timer 2 input capture 3,Timer 1 input capture 2,Timer 17 OCrefclear input,Timer 17 break input,?..."
|
|
textline " "
|
|
bitfld.long 0x00 7. " INPSEL ,Comparator 7 non inverting input selection" "PA0,PC1"
|
|
bitfld.long 0x00 4.--6. " INMSEL ,Comparator 7 inverting input selection" "1/4 of Vrefint,1/2 of Vrefint,3/4 of Vrefint,Vrefint,COMP5_INM4,COMP5_INM5,COMP5_INM6,?..."
|
|
bitfld.long 0x00 2.--3. " MODE ,Comparator 7 mode" "Ultra-low power,Low power,Medium speed,High speed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " COMP7EN ,Comparator 7 enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree "OPAMP (Operational amplifier)"
|
|
base ad:0x40010000
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F318*8")||cpuis("STM32F334*")
|
|
width 12.
|
|
if (((per.l(ad:0x40010000+0x3C))&0x80000000)==0x00)
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "OPAMP2_CSR,OPAMP2 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 2 lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2|FB VM0,Non-Inv G=4|FB VM0,Non-Inv G=8|FB VM0,Non-Inv G=16|FB VM0,Non-Inv G=2|FB VM1,Non-Inv G=4|FB VM1,Non-Inv G=8|FB VM1,Non-Inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP2 Non inverting input secondary selection" ",PD14,PB0,PA7"
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP2 inverting input secondary selection" "PC5,PA5"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP2 inverting input selection" "PC5,PA5,PGA,Follower"
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP2 Non inverting input selection" ",PB14,PB0,PA7"
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP2_EN ,OPAMP2 enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x00 "OPAMP2_CSR,OPAMP2 Control Register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 2 lock" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2|FB VM0,Non-Inv G=4|FB VM0,Non-Inv G=8|FB VM0,Non-Inv G=16|FB VM0,Non-Inv G=2|FB VM1,Non-Inv G=4|FB VM1,Non-Inv G=8|FB VM1,Non-Inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP2 Non inverting input secondary selection" ",PD14,PB0,PA7"
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP2 inverting input secondary selection" "PC5,PA5"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP2 inverting input selection" "PC5,PA5,PGA,Follower"
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP2 Non inverting input selection" ",PB14,PB0,PA7"
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP2_EN ,OPAMP2 enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xB
|
|
elif cpuis("STM32F302?B")||cpuis("STM32F302?C")||cpuis("STM32F302?8")||cpuis("STM32F302?6")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
width 12.
|
|
sif cpuis("STM32F302?B")||cpuis("STM32F302?C")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
if (((per.l(ad:0x40010000+0x38))&0x80000000)==0x00)
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "OPAMP1_CSR,OPAMP1 control register "
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 1 lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2|FB VM0,Non-Inv G=4|FB VM0,Non-Inv G=8|FB VM0,Non-Inv G=16|FB VM0,Non-Inv G=2|FB VM1,Non-Inv G=4|FB VM1,Non-Inv G=8|FB VM1,Non-Inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP1 Non inverting input secondary selection" "PA7,PA5,PA3,PA1"
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP1 inverting input secondary selection" "PC5 (VM0),PA3 (VM1)"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP1 inverting input selection" "PC5,PA3,PGA,Follower"
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP1 Non inverting input selection" "PA7,PA5,PA3,PA1"
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP1_EN ,OPAMP1 enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "OPAMP1_CSR,OPAMP1 control register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 1 lock" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2|FB VM0,Non-Inv G=4|FB VM0,Non-Inv G=8|FB VM0,Non-Inv G=16|FB VM0,Non-Inv G=2|FB VM1,Non-Inv G=4|FB VM1,Non-Inv G=8|FB VM1,Non-Inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP1 Non inverting input secondary selection" "PA7,PA5,PA3,PA1"
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP1 inverting input secondary selection" "PC5 (VM0),PA3 (VM1)"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP1 inverting input selection" "PC5,PA3,PGA,Follower"
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP1 Non inverting input selection" "PA7,PA5,PA3,PA1"
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP1_EN ,OPAMP1 enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x3C))&0x80000000)==0x00)
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "OPAMP2_CSR,OPAMP2 control register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 2 lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2|FB VM0,Non-Inv G=4|FB VM0,Non-Inv G=8|FB VM0,Non-Inv G=16|FB VM0,Non-Inv G=2|FB VM1,Non-Inv G=4|FB VM1,Non-Inv G=8|FB VM1,Non-Inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP2 Non inverting input secondary selection" "PD14,PB14,PB0,PA7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP2 Non inverting input secondary selection" ",PB14,PB0,PA7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP2 inverting input secondary selection" "PC5,PA5"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP2 inverting input selection" "PC5,PA5,PGA,Follower"
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP2 Non inverting input selection" "PD14,PB14,PB0,PA7"
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP2_EN ,OPAMP2 enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x00 "OPAMP2_CSR,OPAMP2 control register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 2 lock" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2|FB VM0,Non-Inv G=4|FB VM0,Non-Inv G=8|FB VM0,Non-Inv G=16|FB VM0,Non-Inv G=2|FB VM1,Non-Inv G=4|FB VM1,Non-Inv G=8|FB VM1,Non-Inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP2 Non inverting input secondary selection" "PD14,PB14,PB0,PA7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP2 Non inverting input secondary selection" ",PB14,PB0,PA7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP2 inverting input secondary selection" "PC5,PA5"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP2 inverting input selection" "PC5,PA5,PGA,Follower"
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP2 Non inverting input selection" "PD14,PB14,PB0,PA7"
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP2_EN ,OPAMP2 enable" "Disabled,Enabled"
|
|
endif
|
|
width 0xB
|
|
else
|
|
width 12.
|
|
sif cpuis("STM32F303?B")||cpuis("STM32F303?C")||cpuis("STM32F358?C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40010000+0x38))&0x80000000)==0x00)
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "OPAMP1_CSR,OPAMP1 control register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 1 lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2|FB VM0,Non-Inv G=4|FB VM0,Non-Inv G=8|FB VM0,Non-Inv G=16|FB VM0,Non-Inv G=2|FB VM1,Non-Inv G=4|FB VM1,Non-Inv G=8|FB VM1,Non-Inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP1 Non inverting input secondary selection" "PA7,PA5,PA3,PA1"
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP1 inverting input secondary selection" "PC5 (VM0),PA3 (VM1)"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP1 inverting input selection" "PC5,PA3,PGA,Follower"
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP1 Non inverting input selection" "PA7,PA5,PA3,PA1"
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP1_EN ,OPAMP1 enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x38++0x3
|
|
line.long 0x00 "OPAMP1_CSR,OPAMP1 control register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 1 lock" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2|FB VM0,Non-Inv G=4|FB VM0,Non-Inv G=8|FB VM0,Non-Inv G=16|FB VM0,Non-Inv G=2|FB VM1,Non-Inv G=4|FB VM1,Non-Inv G=8|FB VM1,Non-Inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP1 Non inverting input secondary selection" "PA7,PA5,PA3,PA1"
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP1 inverting input secondary selection" "PC5 (VM0),PA3 (VM1)"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP1 inverting input selection" "PC5,PA3,PGA,Follower"
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP1 Non inverting input selection" "PA7,PA5,PA3,PA1"
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP1_EN ,OPAMP1 enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x3C))&0x80000000)==0x00)
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "OPAMP2_CSR,OPAMP2 control register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 2 lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2|FB VM0,Non-Inv G=4|FB VM0,Non-Inv G=8|FB VM0,Non-Inv G=16|FB VM0,Non-Inv G=2|FB VM1,Non-Inv G=4|FB VM1,Non-Inv G=8|FB VM1,Non-Inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303?B")||cpuis("STM32F303?C")||cpuis("STM32F358?C")
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP2 Non inverting input secondary selection" "PD14,PB14,PB0,PA7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP2 Non inverting input secondary selection" ",PB14,PB0,PA7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP2 inverting input secondary selection" "PC5,PA5"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP2 inverting input selection" "PC5,PA5,PGA,Follower"
|
|
textline " "
|
|
sif cpuis("STM32F303?B")||cpuis("STM32F303?C")||cpuis("STM32F358?C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP2 Non inverting input selection" "PD14,PB14,PB0,PA7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP2 Non inverting input selection" ",PB14,PB0,PA7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP2_EN ,OPAMP2 enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x3C++0x3
|
|
line.long 0x00 "OPAMP2_CSR,OPAMP2 control register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 2 lock" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2,Non-Inv G=4,Non-Inv G=8,Non-Inv G=16,Non-Inv G=2|FB VM0,Non-Inv G=4|FB VM0,Non-Inv G=8|FB VM0,Non-Inv G=16|FB VM0,Non-Inv G=2|FB VM1,Non-Inv G=4|FB VM1,Non-Inv G=8|FB VM1,Non-Inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F303?B")||cpuis("STM32F303?C")||cpuis("STM32F358?C")
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP2 Non inverting input secondary selection" "PD14,PB14,PB0,PA7"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP2 Non inverting input secondary selection" ",PB14,PB0,PA7"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP2 inverting input secondary selection" "PC5,PA5"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP2 inverting input selection" "PC5,PA5,PGA,Follower"
|
|
sif cpuis("STM32F303?B")||cpuis("STM32F303?C")||cpuis("STM32F358?C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP2 Non inverting input selection" "PD14,PB14,PB0,PA7"
|
|
else
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP2 Non inverting input selection" ",PB14,PB0,PA7"
|
|
endif
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP2_EN ,OPAMP2 enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("STM32F303?B")||cpuis("STM32F303?C")||cpuis("STM32F358?C")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40010000+0x40))&0x80000000)==0x00)
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "OPAMP3_CSR,OPAMP3 control register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 3 lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-inv G=2,Non-inv G=4,Non-inv G=8,Non-inv G=16,Non-inv G=2,Non-inv G=4,Non-inv G=8,Non-inv G=16,Non-inv G=2|FB VM0,Non-inv G=4|FB VM0,Non-inv G=8|FB VM0,Non-inv G=16|FB VM0,Non-inv G=2|FB VM1,Non-inv G=4|FB VM1,Non-inv G=8|FB VM1,Non-inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP3 Non inverting input secondary selection" "PB13,PA5,PA1,PB0"
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP3 inverting input secondary selection" "PB10,PB2"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP3 inverting input selection" "PB10,PB2,PGA,Follower"
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP3 Non inverting input selection" "PB13,PA5,PA1,PB0"
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP3_EN ,OPAMP3 enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x40++0x3
|
|
line.long 0x00 "OPAMP3_CSR,OPAMP3 control register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 3 lock" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-inv G=2,Non-inv G=4,Non-inv G=8,Non-inv G=16,Non-inv G=2,Non-inv G=4,Non-inv G=8,Non-inv G=16,Non-inv G=2|FB VM0,Non-inv G=4|FB VM0,Non-inv G=8|FB VM0,Non-inv G=16|FB VM0,Non-inv G=2|FB VM1,Non-inv G=4|FB VM1,Non-inv G=8|FB VM1,Non-inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP3 Non inverting input secondary selection" "PB13,PA5,PA1,PB0"
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP3 inverting input secondary selection" "PB10,PB2"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP3 inverting input selection" "PB10,PB2,PGA,Follower"
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP3 Non inverting input selection" "PB13,PA5,PA1,PB0"
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP3_EN ,OPAMP3 enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40010000+0x44))&0x80000000)==0x00)
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "OPAMP4_CSR,OPAMP4 control register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 4 lock" "Not locked,Locked"
|
|
rbitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-inv G=2,Non-inv G=4,Non-inv G=8,Non-inv G=16,Non-inv G=2,Non-inv G=4,Non-inv G=8,Non-inv G=16,Non-inv G=2|FB VM0,Non-inv G=4|FB VM0,Non-inv G=8|FB VM0,Non-inv G=16|FB VM0,Non-inv G=2|FB VM1,Non-inv G=4|FB VM1,Non-inv G=8|FB VM1,Non-inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP4 Non inverting input secondary selection" "PD11,PB11,PA4,PB13"
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP4 inverting input secondary selection" "PB10,PD8"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP4 inverting input selection" "PB10,PD8,PGA,Follower"
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP4 Non inverting input selection" "PD11,PB11,PA4,PB13"
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP4_EN ,OPAMP4 enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x44++0x3
|
|
line.long 0x00 "OPAMP4_CSR,OPAMP4 control register"
|
|
bitfld.long 0x00 31. " LOCK ,OPAMP 4 lock" "Not locked,Locked"
|
|
bitfld.long 0x00 30. " OUTCAL ,OPAMP output status flag" "Non-Inv < Inv,Non-Inv > Inv"
|
|
bitfld.long 0x00 29. " TSTREF ,Output the internal reference voltage (V_refint)" "Output,Not output"
|
|
textline " "
|
|
bitfld.long 0x00 24.--28. " TRIMOFFSETN ,Offset trimming value (NMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 19.--23. " TRIMOFFSETP ,Offset trimming value (PMOS)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 18. " USER_TRIM ,User trimming enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--17. " PGA_GAIN ,Gain in PGA mode" "Non-inv G=2,Non-inv G=4,Non-inv G=8,Non-inv G=16,Non-inv G=2,Non-inv G=4,Non-inv G=8,Non-inv G=16,Non-inv G=2|FB VM0,Non-inv G=4|FB VM0,Non-inv G=8|FB VM0,Non-inv G=16|FB VM0,Non-inv G=2|FB VM1,Non-inv G=4|FB VM1,Non-inv G=8|FB VM1,Non-inv G=16|FB VM1"
|
|
bitfld.long 0x00 12.--13. " CALSEL ,Calibration selection" "3.3% VDDA,10% VDDA,50% VDDA,90% VDDA"
|
|
bitfld.long 0x00 11. " CALON ,Calibration mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " VPS_SEL ,OPAMP4 Non inverting input secondary selection" "PD11,PB11,PA4,PB13"
|
|
bitfld.long 0x00 8. " VMS_SEL ,OPAMP4 inverting input secondary selection" "PB10,PD8"
|
|
bitfld.long 0x00 7. " TCM_EN ,Timer controlled Mux mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5.--6. " VM_SEL ,OPAMP4 inverting input selection" "PB10,PD8,PGA,Follower"
|
|
bitfld.long 0x00 2.--3. " VP_SEL ,OPAMP4 Non inverting input selection" "PD11,PB11,PA4,PB13"
|
|
bitfld.long 0x00 1. " FORCE_VP ,Forces a calibration reference voltage on non-inverting input and disables external connections" "Normal,Calobration"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OPAMP4_EN ,OPAMP4 enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")||cpuis("STM32F378*")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
tree "TSC (Touch sensing controller)"
|
|
base ad:0x40024000
|
|
sif !cpuis("STM32F334?4")&&!cpuis("STM32F334?6")&&!cpuis("STM32F334?8")&&!cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
width 13.
|
|
if (((per.l(ad:0x40024000+0x00))&0x2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSC_CR,TSC control register"
|
|
bitfld.long 0x00 28.--31. " CTPH ,Charge transfer pulse high" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 24.--27. " CTPL ,Charge transfer pulse low" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.byte 0x00 17.--23. 1. " SSD ,Spread spectrum deviation"
|
|
bitfld.long 0x00 16. " SSE ,Spread spectrum enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SSPSC ,Spread spectrum prescaler (Clock divider)" "/1,/2"
|
|
bitfld.long 0x00 12.--14. " PGPSC ,Pulse generator prescaler (Clock divider)" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 5.--7. " MCV ,Max count value (transfer pulses)" "255,511,1023,4095,8191,16383,?..."
|
|
bitfld.long 0x00 4. " IODEF ,I/O Default mode" "Output push-pull low,Input floating"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCPOL ,Synchronization pin polarity (edge)" "Falling,Rising"
|
|
bitfld.long 0x00 2. " AM ,Acquisition mode" "Normal,Synchronized"
|
|
bitfld.long 0x00 1. " START ,Start a new acquisition" "Not started,Started"
|
|
bitfld.long 0x00 0. " TSCE ,Touch sensing controller enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "TSC_CR,TSC control register"
|
|
rbitfld.long 0x00 28.--31. " CTPH ,Charge transfer pulse high" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
rbitfld.long 0x00 24.--27. " CTPL ,Charge transfer pulse low" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.byte 0x00 17.--23. 1. " SSD ,Spread spectrum deviation"
|
|
rbitfld.long 0x00 16. " SSE ,Spread spectrum enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " SSPSC ,Spread spectrum prescaler (Clock divider)" "/1,/2"
|
|
rbitfld.long 0x00 12.--14. " PGPSC ,Pulse generator prescaler (Clock divider)" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
rbitfld.long 0x00 5.--7. " MCV ,Max count value (transfer pulses)" "255,511,1023,4095,8191,16383,?..."
|
|
rbitfld.long 0x00 4. " IODEF ,I/O Default mode" "Output push-pull low,Input floating"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " SYNCPOL ,Synchronization pin polarity (edge)" "Falling,Rising"
|
|
rbitfld.long 0x00 2. " AM ,Acquisition mode" "Normal,Synchronized"
|
|
bitfld.long 0x00 1. " START ,Start a new acquisition" "Not started,Started"
|
|
bitfld.long 0x00 0. " TSCE ,Touch sensing controller enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "TSC_IER,TSC interrupt enable register"
|
|
bitfld.long 0x00 1. " MCEIE ,Max count error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EOAIE ,End of acquisition interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "TSC_ICR,TSC interrupt clear register"
|
|
bitfld.long 0x04 1. " MCEIC ,Max count error interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x04 0. " EOAIC ,End of acquisition interrupt clear" "No effect,Cleared"
|
|
line.long 0x08 "TSC_ISR,TSC interrupt status register "
|
|
bitfld.long 0x08 1. " MCEF ,Max count error flag" "No error,Error"
|
|
bitfld.long 0x08 0. " EOAF ,End of acquisition flag" "Not completed,Completed"
|
|
line.long 0x0C "TSC_IOHCR,TSC I/O hysteresis control register"
|
|
bitfld.long 0x0C 31. " G8_IO4 ,G8_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 30. " G8_IO3 ,G8_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 29. " G8_IO2 ,G8_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 28. " G8_IO1 ,G8_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 27. " G7_IO4 ,G7_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 26. " G7_IO3 ,G7_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 25. " G7_IO2 ,G7_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 24. " G7_IO1 ,G7_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 23. " G6_IO4 ,G6_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " G6_IO3 ,G6_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " G6_IO2 ,G6_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " G6_IO1 ,G6_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " G5_IO4 ,G5_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " G5_IO3 ,G5_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " G5_IO2 ,G5_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " G5_IO1 ,G5_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 15. " G4_IO4 ,G4_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " G4_IO3 ,G4_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " G4_IO2 ,G4_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " G4_IO1 ,G4_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F398VE")
|
|
bitfld.long 0x0C 11. " G3_IO4 ,G3_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x0C 10. " G3_IO3 ,G3_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " G3_IO2 ,G3_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " G3_IO1 ,G3_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " G2_IO4 ,G2_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " G2_IO3 ,G2_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " G2_IO2 ,G2_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " G2_IO1 ,G2_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x0C 3. " G1_IO4 ,G1_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " G1_IO3 ,G1_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " G1_IO2 ,G1_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " G1_IO1 ,G1_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TSC_IOASCR,TSC I/O analog switch control register"
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 Analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 Analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 Analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 Analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 Analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !cpuis("STM32F398VE")
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 Analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 Analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 Analog switch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 Analog switch enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40024000+0x00))&0x2)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TSC_IOSCR,TSC I/O sampling control register"
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
sif !cpuis("STM32F398VE")
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 Sampling control register" "Unused,Used"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TSC_IOCCR,TSC I/O channel control register"
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
sif !cpuis("STM32F398VE")
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 Channel control register" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 Channel control register" "Unused,Used"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TSC_IOSCR,TSC I/O sampling control register"
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
sif !cpuis("STM32F398VE")
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 Sampling control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 Sampling control register" "Unused,Used"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TSC_IOCCR,TSC I/O channel control register"
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
sif !cpuis("STM32F398VE")
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 Channel control register" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 Channel control register" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 Channel control register" "Unused,Used"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TSC_IOGCSR,TSC I/O group control status register"
|
|
rbitfld.long 0x00 23. " G8S ,Analog I/O group 8 status" "Not started,Completed"
|
|
rbitfld.long 0x00 22. " G7S ,Analog I/O group 7 status" "Not started,Completed"
|
|
rbitfld.long 0x00 21. " G6S ,Analog I/O group 6 status" "Not started,Completed"
|
|
rbitfld.long 0x00 20. " G5S ,Analog I/O group 5 status" "Not started,Completed"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " G4S ,Analog I/O group 4 status" "Not started,Completed"
|
|
rbitfld.long 0x00 18. " G3S ,Analog I/O group 3 status" "Not started,Completed"
|
|
rbitfld.long 0x00 17. " G2S ,Analog I/O group 2 status" "Not started,Completed"
|
|
rbitfld.long 0x00 16. " G1S ,Analog I/O group 1 status" "Not started,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 7. " G8E ,Analog I/O group 8 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " G7E ,Analog I/O group 7 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " G6E ,Analog I/O group 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " G5E ,Analog I/O group 5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " G4E ,Analog I/O group 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " G3E ,Analog I/O group 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G2E ,Analog I/O group 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G1E ,Analog I/O group 1 enable" "Disabled,Enabled"
|
|
rgroup.long 0x34++0x1F
|
|
line.long 0x0 "TSC_IOG1CR,TSC I/O group 1 counter register"
|
|
hexmask.long.word 0x0 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0x4 "TSC_IOG2CR,TSC I/O group 2 counter register"
|
|
hexmask.long.word 0x4 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0x8 "TSC_IOG3CR,TSC I/O group 3 counter register"
|
|
hexmask.long.word 0x8 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0xC "TSC_IOG4CR,TSC I/O group 4 counter register"
|
|
hexmask.long.word 0xC 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0x10 "TSC_IOG5CR,TSC I/O group 5 counter register"
|
|
hexmask.long.word 0x10 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0x14 "TSC_IOG6CR,TSC I/O group 6 counter register"
|
|
hexmask.long.word 0x14 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0x18 "TSC_IOG7CR,TSC I/O group 7 counter register"
|
|
hexmask.long.word 0x18 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0x1C "TSC_IOG8CR,TSC I/O group 8 counter register"
|
|
hexmask.long.word 0x1C 0.--13. 1. " CNT ,Counter value"
|
|
width 0x0B
|
|
else
|
|
width 11.
|
|
if (((per.l(ad:0x40024000+0x00))&0x2)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSC_CR,TSC control register"
|
|
bitfld.long 0x00 28.--31. " CTPH ,Charge transfer pulse high" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
bitfld.long 0x00 24.--27. " CTPL ,Charge transfer pulse low" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.byte 0x00 17.--23. 1. " SSD ,Spread spectrum deviation"
|
|
bitfld.long 0x00 16. " SSE ,Spread spectrum enable" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x00 15. " SSPSC ,Spread spectrum prescaler (Clock divider)" "/1,/2"
|
|
bitfld.long 0x00 12.--14. " PGPSC ,Pulse generator prescaler (Clock divider)" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.long 0x00 5.--7. " MCV ,Max count value (transfer pulses)" "255,511,1023,4095,8191,16383,?..."
|
|
bitfld.long 0x00 4. " IODEF ,I/O Default mode" "Output push-pull low,Input floating"
|
|
textline ""
|
|
bitfld.long 0x00 3. " SYNCPOL ,Synchronization pin polarity (edge)" "Falling,Rising"
|
|
bitfld.long 0x00 2. " AM ,Acquisition mode" "Normal,Synchronized"
|
|
bitfld.long 0x00 1. " START ,Start a new acquisition" "Not started,Started"
|
|
bitfld.long 0x00 0. " TSCE ,Touch sensing controller enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "TSC_CR,TSC control register"
|
|
rbitfld.long 0x00 28.--31. " CTPH ,Charge transfer pulse high" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
rbitfld.long 0x00 24.--27. " CTPL ,Charge transfer pulse low" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16"
|
|
hexmask.long.byte 0x00 17.--23. 1. " SSD ,Spread spectrum deviation"
|
|
rbitfld.long 0x00 16. " SSE ,Spread spectrum enable" "Disabled,Enabled"
|
|
textline ""
|
|
rbitfld.long 0x00 15. " SSPSC ,Spread spectrum prescaler (Clock divider)" "/1,/2"
|
|
rbitfld.long 0x00 12.--14. " PGPSC ,Pulse generator prescaler (Clock divider)" "/1,/2,/4,/8,/16,/32,/64,/128"
|
|
rbitfld.long 0x00 5.--7. " MCV ,Max count value (transfer pulses)" "255,511,1023,4095,8191,16383,?..."
|
|
rbitfld.long 0x00 4. " IODEF ,I/O Default mode" "Output push-pull low,Input floating"
|
|
textline ""
|
|
rbitfld.long 0x00 3. " SYNCPOL ,Synchronization pin polarity (edge)" "Falling,Rising"
|
|
rbitfld.long 0x00 2. " AM ,Acquisition mode" "Normal,Synchronized"
|
|
bitfld.long 0x00 1. " START ,Start a new acquisition" "Not started,Started"
|
|
bitfld.long 0x00 0. " TSCE ,Touch sensing controller enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x0F
|
|
line.long 0x00 "TSC_IER,TSC interrupt enable register"
|
|
bitfld.long 0x00 1. " MCEIE ,Max count error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EOAIE ,End of acquisition interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "TSC_ICR,TSC interrupt clear register"
|
|
bitfld.long 0x04 1. " MCEIC ,Max count error interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x04 0. " EOAIC ,End of acquisition interrupt clear" "No effect,Cleared"
|
|
line.long 0x08 "TSC_ISR,TSC interrupt status register "
|
|
bitfld.long 0x08 1. " MCEF ,Max count error flag" "No error,Error"
|
|
bitfld.long 0x08 0. " EOAF ,End of acquisition flag" "Not completed,Completed"
|
|
line.long 0x0C "TSC_IOHCR,TSC I/O hysteresis control register"
|
|
bitfld.long 0x0C 23. " G6_IO4 ,G6_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 22. " G6_IO3 ,G6_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 21. " G6_IO2 ,G6_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 20. " G6_IO1 ,G6_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x0C 19. " G5_IO4 ,G5_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 18. " G5_IO3 ,G5_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 17. " G5_IO2 ,G5_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 16. " G5_IO1 ,G5_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x0C 15. " G4_IO4 ,G4_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 14. " G4_IO3 ,G4_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 13. " G4_IO2 ,G4_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 12. " G4_IO1 ,G4_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x0C 11. " G3_IO4 ,G3_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 10. " G3_IO3 ,G3_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 9. " G3_IO2 ,G3_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8. " G3_IO1 ,G3_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x0C 7. " G2_IO4 ,G2_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 6. " G2_IO3 ,G2_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 5. " G2_IO2 ,G2_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 4. " G2_IO1 ,G2_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x0C 3. " G1_IO4 ,G1_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 2. " G1_IO3 ,G1_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 1. " G1_IO2 ,G1_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x0C 0. " G1_IO1 ,G1_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TSC_IOASCR,TSC I/O analog switch control register"
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 Analog switch enable" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 Analog switch enable" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 Analog switch enable" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 Analog switch enable" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 Analog switch enable" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 Analog switch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 Analog switch enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40024000+0x00))&0x2)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TSC_IOSCR,TSC I/O sampling control register"
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 Sampling control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 Sampling control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 Sampling control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 Sampling control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 Sampling control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 Sampling control register" "Unused,Used"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TSC_IOCCR,TSC I/O channel control register"
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 Channel control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 Channel control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 Channel control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 Channel control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 Channel control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 Channel control register" "Unused,Used"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "TSC_IOSCR,TSC I/O sampling control register"
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 Sampling control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 Sampling control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 Sampling control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 Sampling control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 Sampling control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 Sampling control register" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 Sampling control register" "Unused,Used"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "TSC_IOCCR,TSC I/O channel control register"
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 Channel control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 Channel control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 Channel control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 Channel control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 Channel control register" "Unused,Used"
|
|
textline ""
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 Channel control register" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 Channel control register" "Unused,Used"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TSC_IOGCSR,TSC I/O group control status register"
|
|
rbitfld.long 0x00 21. " G6S ,Analog I/O group 6 status" "Not started,Completed"
|
|
rbitfld.long 0x00 20. " G5S ,Analog I/O group 5 status" "Not started,Completed"
|
|
rbitfld.long 0x00 19. " G4S ,Analog I/O group 4 status" "Not started,Completed"
|
|
rbitfld.long 0x00 18. " G3S ,Analog I/O group 3 status" "Not started,Completed"
|
|
textline ""
|
|
rbitfld.long 0x00 17. " G2S ,Analog I/O group 2 status" "Not started,Completed"
|
|
rbitfld.long 0x00 16. " G1S ,Analog I/O group 1 status" "Not started,Completed"
|
|
bitfld.long 0x00 5. " G6E ,Analog I/O group 6 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " G5E ,Analog I/O group 5 enable" "Disabled,Enabled"
|
|
textline ""
|
|
bitfld.long 0x00 3. " G4E ,Analog I/O group 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " G3E ,Analog I/O group 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " G2E ,Analog I/O group 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " G1E ,Analog I/O group 1 enable" "Disabled,Enabled"
|
|
rgroup.long 0x34++0x1F
|
|
line.long 0x0 "TSC_IOG1CR,TSC I/O group 1 counter register"
|
|
hexmask.long.word 0x0 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0x4 "TSC_IOG2CR,TSC I/O group 2 counter register"
|
|
hexmask.long.word 0x4 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0x8 "TSC_IOG3CR,TSC I/O group 3 counter register"
|
|
hexmask.long.word 0x8 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0xC "TSC_IOG4CR,TSC I/O group 4 counter register"
|
|
hexmask.long.word 0xC 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0x10 "TSC_IOG5CR,TSC I/O group 5 counter register"
|
|
hexmask.long.word 0x10 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0x14 "TSC_IOG6CR,TSC I/O group 6 counter register"
|
|
hexmask.long.word 0x14 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0x18 "TSC_IOG7CR,TSC I/O group 7 counter register"
|
|
hexmask.long.word 0x18 0.--13. 1. " CNT ,Counter value"
|
|
line.long 0x1C "TSC_IOG8CR,TSC I/O group 8 counter register"
|
|
hexmask.long.word 0x1C 0.--13. 1. " CNT ,Counter value"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
tree.open "ACT (Advanced-control timers)"
|
|
tree "TIM 1"
|
|
base ad:0x40012C00
|
|
width 15.
|
|
if (((per.l(ad:0x40012C00+0x00)&0x60))!=0x00)||(((per.l(ad:0x40012C00+0x08)&0x7))==0x2)||(((per.l(ad:0x40012C00+0x08)&0x7))==0x3)||(((per.l(ad:0x40012C00+0x08)&0x7))==0x4)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM1_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM1_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "TIM1_CR2,Control register 2"
|
|
bitfld.long 0x00 20.--23. " MMS2 ,Master Mode Selection 2" "Reset,Enable,Update,Compare pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF,Compare OC5REF,Compare OC6REF,Compare Pulse OC4REF,Compare Pulse OC6REF,Compare Pulse OC4REF/OC6REF,Compare Pulse OC4REF/OC6REF,Compare Pulse OC5REF/OC6REF,Compare Pulse OC5REF/OC6REF"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OIS6 ,OC6 output" "0,1"
|
|
bitfld.long 0x00 16. " OIS5 ,OC5 output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
bitfld.long 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
bitfld.long 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
bitfld.long 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
bitfld.long 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
bitfld.long 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COMG bit only,COMG bit/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIM1_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM1_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIM1_SR,Status register"
|
|
eventfld.long 0x00 17. " CC6IF ,Capture/Compare 6 interrupt Flag" "No match,Matched"
|
|
eventfld.long 0x00 16. " CC5IF ,Capture/Compare 5 interrupt Flag" "No match,Matched"
|
|
textline " "
|
|
eventfld.long 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " B2IF ,Break 2 interrupt Flag" "No break,Break"
|
|
eventfld.long 0x00 7. " BIF ,Break interrupt Flag" "No break,Break"
|
|
textline " "
|
|
eventfld.long 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
eventfld.long 0x00 5. " COMIF ,COM interrupt Flag" "No COM,COM"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
eventfld.long 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
eventfld.long 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UIF ,Update interrupt Flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM1_EGR,Event generation register"
|
|
bitfld.word 0x00 8. " B2G ,Break 2 Generation" "No action,Break"
|
|
bitfld.word 0x00 7. " BG ,Break Generation" "No action,Break"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare Control Update Generation" "No action,Update"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.l((ad:0x40012C00+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40012C00+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40012C00+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.l((ad:0x40012C00+0x1C)))&0x303)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40012C00+0x1C)))&0x3)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40012C00+0x1C)))&0x300)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output Polarity input/output" "High,Low"
|
|
bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable input/output" "Off,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output Polarity input/output" "High,Low"
|
|
bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable input/output" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 5. 7. " CCP2 ,Capture/Compare 2 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
if ((per.w(ad:0x40012C00)&0x800)==0x0)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM1_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM1_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM1_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM1_ARR,Auto-reload register"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "TIM1_RCR,Repetition counter register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM1_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM1_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM1_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM1_CCR4,Capture/compare register 4"
|
|
if (((per.l(ad:0x40012C00+0x44)&0x300))==0x100)
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM1_BDTR,Break and dead-time register"
|
|
rbitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
rbitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
elif (((per.l(ad:0x40012C00+0x44)&0x300))==0x200)
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM1_BDTR,Break and dead-time register"
|
|
bitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
else
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM1_BDTR,Break and dead-time register"
|
|
bitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
endif
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM1_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM1_CR1,TIM1_CR2,TIM1_SMCR,TIM1_DIER,TIM1_SR,TIM1_EGR,TIM1_CCMR1,TIM1_CCMR2,TIM1_CCER,TIM1_CNT,TIM1_PSC,TIM1_ARR,TIM1_RCR,TIM1_CCR1,TIM1_CCR2,TIM1_CCR3,TIM1_CCR4,TIM1_BDTR,TIM1_DCR,TIM1_DMAR,,TIM1_CCMR3,TIM1_CCR5,TIM1_CCR6,TIM1_OR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM1_DMAR,DMA address for full transfer"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "TIM1_OR,Option register"
|
|
bitfld.long 0x00 2.--3. " ETR_ADC4 ,ETR_ADC4 remapping capability" "No connection,ETR-->ADC4_AWD1,ETR-->ADC4_AWD2,ETR-->ADC4_AWD3"
|
|
bitfld.long 0x00 0.--1. " ETR_ADC1 ,ETR_ADC1 remapping capability" "No connection,ETR-->ADC1_AWD1,ETR-->ADC1_AWD2,ETR-->ADC1_AWD3"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "TIM1_CCMR3,Capture/compare mode register 3"
|
|
bitfld.long 0x00 15. " OC6CE ,Output Compare 6 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC6M ,Output Compare 6 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC6PE ,Output Compare 6 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC6FE ,Output Compare 6 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC5CE ,Output Compare 5 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC5M ,Output Compare 5 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC5PE ,Output Compare 5 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC5FE ,Output Compare 5 Fast enable" "Disabled,Enabled"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "TIM1_CCR5,Capture/compare register 5"
|
|
bitfld.long 0x00 31. " GC5C3 ,Group Channel 5 and Channel 3" "No effect,OC3REFC and OC5REF"
|
|
bitfld.long 0x00 30. " GC5C2 ,Group Channel 5 and Channel 2" "No effect,OC2REFC and OC5REF"
|
|
textline " "
|
|
bitfld.long 0x00 29. " GC5C1 ,Group Channel 5 and Channel 1" "No effect,OC1REFC and OC5REF"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR5 ,Capture/Compare 5 value"
|
|
group.word 0x5C++0x1
|
|
line.word 0x00 "TIM1_CCR6,Capture/compare register 6"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302VB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F302VC")&&(cpu()!="STM32F302RB")&&(cpu()!="STM32F302RC")
|
|
tree "TIM 8"
|
|
base ad:0x40013400
|
|
width 15.
|
|
if (((per.l(ad:0x40013400+0x00)&0x60))!=0x00)||(((per.l(ad:0x40013400+0x08)&0x7))==0x2)||(((per.l(ad:0x40013400+0x08)&0x7))==0x3)||(((per.l(ad:0x40013400+0x08)&0x7))==0x4)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM8_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM8_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "TIM8_CR2,Control register 2"
|
|
bitfld.long 0x00 20.--23. " MMS2 ,Master Mode Selection 2" "Reset,Enable,Update,Compare pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF,Compare OC5REF,Compare OC6REF,Compare Pulse OC4REF,Compare Pulse OC6REF,Compare Pulse OC4REF/OC6REF,Compare Pulse OC4REF/OC6REF,Compare Pulse OC5REF/OC6REF,Compare Pulse OC5REF/OC6REF"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OIS6 ,OC6 output" "0,1"
|
|
bitfld.long 0x00 16. " OIS5 ,OC5 output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
bitfld.long 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
bitfld.long 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
bitfld.long 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
bitfld.long 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
bitfld.long 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COMG bit only,COMG bit/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIM8_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM8_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIM8_SR,Status register"
|
|
eventfld.long 0x00 17. " CC6IF ,Capture/Compare 6 interrupt Flag" "No match,Matched"
|
|
eventfld.long 0x00 16. " CC5IF ,Capture/Compare 5 interrupt Flag" "No match,Matched"
|
|
textline " "
|
|
eventfld.long 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " B2IF ,Break 2 interrupt Flag" "No break,Break"
|
|
eventfld.long 0x00 7. " BIF ,Break interrupt Flag" "No break,Break"
|
|
textline " "
|
|
eventfld.long 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
eventfld.long 0x00 5. " COMIF ,COM interrupt Flag" "No COM,COM"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
eventfld.long 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
eventfld.long 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UIF ,Update interrupt Flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM8_EGR,Event generation register"
|
|
bitfld.word 0x00 8. " B2G ,Break 2 Generation" "No action,Break"
|
|
bitfld.word 0x00 7. " BG ,Break Generation" "No action,Break"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare Control Update Generation" "No action,Update"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.l((ad:0x40013400+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40013400+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40013400+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.l((ad:0x40013400+0x1C)))&0x303)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40013400+0x1C)))&0x3)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40013400+0x1C)))&0x300)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output Polarity input/output" "High,Low"
|
|
bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable input/output" "Off,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output Polarity input/output" "High,Low"
|
|
bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable input/output" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 5. 7. " CCP2 ,Capture/Compare 2 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
if ((per.w(ad:0x40013400)&0x800)==0x0)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM8_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM8_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM8_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM8_ARR,Auto-reload register"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "TIM8_RCR,Repetition counter register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM8_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM8_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM8_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM8_CCR4,Capture/compare register 4"
|
|
if (((per.l(ad:0x40013400+0x44)&0x300))==0x100)
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM8_BDTR,Break and dead-time register"
|
|
rbitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
rbitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
elif (((per.l(ad:0x40013400+0x44)&0x300))==0x200)
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM8_BDTR,Break and dead-time register"
|
|
bitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
else
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM8_BDTR,Break and dead-time register"
|
|
bitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
endif
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM8_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM8_CR1,TIM8_CR2,TIM8_SMCR,TIM8_DIER,TIM8_SR,TIM8_EGR,TIM8_CCMR1,TIM8_CCMR2,TIM8_CCER,TIM8_CNT,TIM8_PSC,TIM8_ARR,TIM8_RCR,TIM8_CCR1,TIM8_CCR2,TIM8_CCR3,TIM8_CCR4,TIM8_BDTR,TIM8_DCR,TIM8_DMAR,,TIM8_CCMR3,TIM8_CCR5,TIM8_CCR6,TIM8_OR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM8_DMAR,DMA address for full transfer"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "TIM8_OR,Option register"
|
|
bitfld.long 0x00 2.--3. " ETR_ADC3 ,ETR_ADC3 remapping capability" "No connection,ETR-->ADC3_AWD1,ETR-->ADC3_AWD2,ETR-->ADC3_AWD3"
|
|
bitfld.long 0x00 0.--1. " ETR_ADC2 ,ETR_ADC2 remapping capability" "No connection,ETR-->ADC2_AWD1,ETR-->ADC2_AWD2,ETR-->ADC2_AWD3"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "TIM8_CCMR3,Capture/compare mode register 3"
|
|
bitfld.long 0x00 15. " OC6CE ,Output Compare 6 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC6M ,Output Compare 6 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC6PE ,Output Compare 6 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC6FE ,Output Compare 6 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC5CE ,Output Compare 5 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC5M ,Output Compare 5 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC5PE ,Output Compare 5 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC5FE ,Output Compare 5 Fast enable" "Disabled,Enabled"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "TIM8_CCR5,Capture/compare register 5"
|
|
bitfld.long 0x00 31. " GC5C3 ,Group Channel 5 and Channel 3" "No effect,OC3REFC and OC5REF"
|
|
bitfld.long 0x00 30. " GC5C2 ,Group Channel 5 and Channel 2" "No effect,OC2REFC and OC5REF"
|
|
textline " "
|
|
bitfld.long 0x00 29. " GC5C1 ,Group Channel 5 and Channel 1" "No effect,OC1REFC and OC5REF"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR5 ,Capture/Compare 5 value"
|
|
group.word 0x5C++0x1
|
|
line.word 0x00 "TIM8_CCR6,Capture/compare register 6"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
tree "TIM 20"
|
|
base ad:0x40015000
|
|
width 15.
|
|
if (((per.l(ad:0x40015000+0x00)&0x60))!=0x00)||(((per.l(ad:0x40015000+0x08)&0x7))==0x2)||(((per.l(ad:0x40015000+0x08)&0x7))==0x3)||(((per.l(ad:0x40015000+0x08)&0x7))==0x4)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM20_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM20_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "TIM20_CR2,Control register 2"
|
|
bitfld.long 0x00 20.--23. " MMS2 ,Master Mode Selection 2" "Reset,Enable,Update,Compare pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF,Compare OC5REF,Compare OC6REF,Compare Pulse OC4REF,Compare Pulse OC6REF,Compare Pulse OC4REF/OC6REF,Compare Pulse OC4REF/OC6REF,Compare Pulse OC5REF/OC6REF,Compare Pulse OC5REF/OC6REF"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OIS6 ,OC6 output" "0,1"
|
|
bitfld.long 0x00 16. " OIS5 ,OC5 output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
bitfld.long 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
bitfld.long 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
bitfld.long 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
bitfld.long 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
bitfld.long 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COMG bit only,COMG bit/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIM20_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM20_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIM20_SR,Status register"
|
|
eventfld.long 0x00 17. " CC6IF ,Capture/Compare 6 interrupt Flag" "No match,Matched"
|
|
eventfld.long 0x00 16. " CC5IF ,Capture/Compare 5 interrupt Flag" "No match,Matched"
|
|
textline " "
|
|
eventfld.long 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " B2IF ,Break 2 interrupt Flag" "No break,Break"
|
|
eventfld.long 0x00 7. " BIF ,Break interrupt Flag" "No break,Break"
|
|
textline " "
|
|
eventfld.long 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
eventfld.long 0x00 5. " COMIF ,COM interrupt Flag" "No COM,COM"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
eventfld.long 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
eventfld.long 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UIF ,Update interrupt Flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM20_EGR,Event generation register"
|
|
bitfld.word 0x00 8. " B2G ,Break 2 Generation" "No action,Break"
|
|
bitfld.word 0x00 7. " BG ,Break Generation" "No action,Break"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare Control Update Generation" "No action,Update"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.l((ad:0x40015000+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM20_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40015000+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM20_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40015000+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM20_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM20_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.l((ad:0x40015000+0x1C)))&0x303)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM20_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40015000+0x1C)))&0x3)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM20_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40015000+0x1C)))&0x300)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM20_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM20_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "TIM20_CCER,Capture/compare enable register"
|
|
bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output Polarity input/output" "High,Low"
|
|
bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable input/output" "Off,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output Polarity input/output" "High,Low"
|
|
bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable input/output" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 5. 7. " CCP2 ,Capture/Compare 2 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
if ((per.w(ad:0x40015000)&0x800)==0x0)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM20_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM20_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM20_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM20_ARR,Auto-reload register"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "TIM20_RCR,Repetition counter register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM20_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM20_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM20_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM20_CCR4,Capture/compare register 4"
|
|
if (((per.l(ad:0x40015000+0x44)&0x300))==0x100)
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM20_BDTR,Break and dead-time register"
|
|
rbitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
rbitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
elif (((per.l(ad:0x40015000+0x44)&0x300))==0x200)
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM20_BDTR,Break and dead-time register"
|
|
bitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
else
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM20_BDTR,Break and dead-time register"
|
|
bitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
endif
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM20_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM20_CR1,TIM20_CR2,TIM20_SMCR,TIM20_DIER,TIM20_SR,TIM20_EGR,TIM20_CCMR1,TIM20_CCMR2,TIM20_CCER,TIM20_CNT,TIM20_PSC,TIM20_ARR,TIM20_RCR,TIM20_CCR1,TIM20_CCR2,TIM20_CCR3,TIM20_CCR4,TIM20_BDTR,TIM20_DCR,TIM20_DMAR,,TIM20_CCMR3,TIM20_CCR5,TIM20_CCR6,TIM20_OR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM20_DMAR,DMA address for full transfer"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "TIM20_OR,Option register"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "TIM20_CCMR3,Capture/compare mode register 3"
|
|
bitfld.long 0x00 15. " OC6CE ,Output Compare 6 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC6M ,Output Compare 6 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC6PE ,Output Compare 6 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC6FE ,Output Compare 6 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC5CE ,Output Compare 5 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC5M ,Output Compare 5 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC5PE ,Output Compare 5 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC5FE ,Output Compare 5 Fast enable" "Disabled,Enabled"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "TIM20_CCR5,Capture/compare register 5"
|
|
bitfld.long 0x00 31. " GC5C3 ,Group Channel 5 and Channel 3" "No effect,OC3REFC and OC5REF"
|
|
bitfld.long 0x00 30. " GC5C2 ,Group Channel 5 and Channel 2" "No effect,OC2REFC and OC5REF"
|
|
textline " "
|
|
bitfld.long 0x00 29. " GC5C1 ,Group Channel 5 and Channel 1" "No effect,OC1REFC and OC5REF"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR5 ,Capture/Compare 5 value"
|
|
group.word 0x5C++0x1
|
|
line.word 0x00 "TIM20_CCR6,Capture/compare register 6"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
elif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F302*")||cpuis("STM32F303*")||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")
|
|
tree.open "ACT (Advanced-control timers)"
|
|
tree "TIM 1"
|
|
base ad:0x40012C00
|
|
width 15.
|
|
if (((per.l(ad:0x40012C00+0x00)&0x60))!=0x00)||(((per.l(ad:0x40012C00+0x08)&0x7))==0x2)||(((per.l(ad:0x40012C00+0x08)&0x7))==0x3)||(((per.l(ad:0x40012C00+0x08)&0x7))==0x4)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM1_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM1_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "TIM1_CR2,Control register 2"
|
|
bitfld.long 0x00 20.--23. " MMS2 ,Master Mode Selection 2" "Reset,Enable,Update,Compare pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF,Compare OC5REF,Compare OC6REF,Compare Pulse OC4REF,Compare Pulse OC6REF,Compare Pulse OC4REF/OC6REF,Compare Pulse OC4REF/OC6REF,Compare Pulse OC5REF/OC6REF,Compare Pulse OC5REF/OC6REF"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OIS6 ,OC6 output" "0,1"
|
|
bitfld.long 0x00 16. " OIS5 ,OC5 output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
bitfld.long 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
bitfld.long 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
bitfld.long 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
bitfld.long 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
bitfld.long 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COMG bit only,COMG bit/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIM1_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM1_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIM1_SR,Status register"
|
|
eventfld.long 0x00 17. " CC6IF ,Capture/Compare 6 interrupt Flag" "No match,Matched"
|
|
eventfld.long 0x00 16. " CC5IF ,Capture/Compare 5 interrupt Flag" "No match,Matched"
|
|
textline " "
|
|
eventfld.long 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " B2IF ,Break 2 interrupt Flag" "No break,Break"
|
|
eventfld.long 0x00 7. " BIF ,Break interrupt Flag" "No break,Break"
|
|
textline " "
|
|
eventfld.long 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
eventfld.long 0x00 5. " COMIF ,COM interrupt Flag" "No COM,COM"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
eventfld.long 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
eventfld.long 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UIF ,Update interrupt Flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM1_EGR,Event generation register"
|
|
bitfld.word 0x00 8. " B2G ,Break 2 Generation" "No action,Break"
|
|
bitfld.word 0x00 7. " BG ,Break Generation" "No action,Break"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare Control Update Generation" "No action,Update"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.l((ad:0x40012C00+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40012C00+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40012C00+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM1_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.l((ad:0x40012C00+0x1C)))&0x303)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40012C00+0x1C)))&0x3)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40012C00+0x1C)))&0x300)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM1_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "TIM1_CCER,Capture/compare enable register"
|
|
bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output Polarity input/output" "High,Low"
|
|
bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable input/output" "Off,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output Polarity input/output" "High,Low"
|
|
bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable input/output" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 5. 7. " CCP2 ,Capture/Compare 2 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
if ((per.w(ad:0x40012C00)&0x800)==0x0)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM1_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM1_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM1_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM1_ARR,Auto-reload register"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "TIM1_RCR,Repetition counter register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM1_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM1_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM1_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM1_CCR4,Capture/compare register 4"
|
|
if (((per.l(ad:0x40012C00+0x44)&0x300))==0x100)
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM1_BDTR,Break and dead-time register"
|
|
rbitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
rbitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
elif (((per.l(ad:0x40012C00+0x44)&0x300))==0x200)
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM1_BDTR,Break and dead-time register"
|
|
bitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
else
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM1_BDTR,Break and dead-time register"
|
|
bitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
endif
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM1_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM1_CR1,TIM1_CR2,TIM1_SMCR,TIM1_DIER,TIM1_SR,TIM1_EGR,TIM1_CCMR1,TIM1_CCMR2,TIM1_CCER,TIM1_CNT,TIM1_PSC,TIM1_ARR,TIM1_RCR,TIM1_CCR1,TIM1_CCR2,TIM1_CCR3,TIM1_CCR4,TIM1_BDTR,TIM1_DCR,TIM1_DMAR,,TIM1_CCMR3,TIM1_CCR5,TIM1_CCR6,TIM1_OR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM1_DMAR,DMA address for full transfer"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "TIM1_OR,Option register"
|
|
bitfld.long 0x00 2.--3. " ETR_ADC4 ,ETR_ADC4 remapping capability" "No connection,ETR-->ADC4_AWD1,ETR-->ADC4_AWD2,ETR-->ADC4_AWD3"
|
|
bitfld.long 0x00 0.--1. " ETR_ADC1 ,ETR_ADC1 remapping capability" "No connection,ETR-->ADC1_AWD1,ETR-->ADC1_AWD2,ETR-->ADC1_AWD3"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "TIM1_CCMR3,Capture/compare mode register 3"
|
|
bitfld.long 0x00 15. " OC6CE ,Output Compare 6 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC6M ,Output Compare 6 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC6PE ,Output Compare 6 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC6FE ,Output Compare 6 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC5CE ,Output Compare 5 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC5M ,Output Compare 5 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC5PE ,Output Compare 5 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC5FE ,Output Compare 5 Fast enable" "Disabled,Enabled"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "TIM1_CCR5,Capture/compare register 5"
|
|
bitfld.long 0x00 31. " GC5C3 ,Group Channel 5 and Channel 3" "No effect,OC3REFC and OC5REF"
|
|
bitfld.long 0x00 30. " GC5C2 ,Group Channel 5 and Channel 2" "No effect,OC2REFC and OC5REF"
|
|
textline " "
|
|
bitfld.long 0x00 29. " GC5C1 ,Group Channel 5 and Channel 1" "No effect,OC1REFC and OC5REF"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR5 ,Capture/Compare 5 value"
|
|
group.word 0x5C++0x1
|
|
line.word 0x00 "TIM1_CCR6,Capture/compare register 6"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32F302*")||cpuis("STM32F303*")||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"
|
|
sif !cpuis("STM32F303*6")&&!cpuis("STM32F303*8")&&!cpuis("STM32F302*6")&&!cpuis("STM32F302*8")&&!cpuis("STM32F302*B")&&!cpuis("STM32F302*C")
|
|
tree "TIM 8"
|
|
base ad:0x40013400
|
|
width 15.
|
|
if (((per.l(ad:0x40013400+0x00)&0x60))!=0x00)||(((per.l(ad:0x40013400+0x08)&0x7))==0x2)||(((per.l(ad:0x40013400+0x08)&0x7))==0x3)||(((per.l(ad:0x40013400+0x08)&0x7))==0x4)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM8_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
rbitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM8_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
endif
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "TIM8_CR2,Control register 2"
|
|
bitfld.long 0x00 20.--23. " MMS2 ,Master Mode Selection 2" "Reset,Enable,Update,Compare pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF,Compare OC5REF,Compare OC6REF,Compare Pulse OC4REF,Compare Pulse OC6REF,Compare Pulse OC4REF/OC6REF,Compare Pulse OC4REF/OC6REF,Compare Pulse OC5REF/OC6REF,Compare Pulse OC5REF/OC6REF"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OIS6 ,OC6 output" "0,1"
|
|
bitfld.long 0x00 16. " OIS5 ,OC5 output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 14. " OIS4 ,OC4 output" "0,1"
|
|
bitfld.long 0x00 13. " OIS3N ,OC3N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 12. " OIS3 ,OC3 output" "0,1"
|
|
bitfld.long 0x00 11. " OIS2N ,OC2N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OIS2 ,OC2 output" "0,1"
|
|
bitfld.long 0x00 9. " OIS1N ,OC1N output" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8. " OIS1 ,OC1 output" "0,1"
|
|
bitfld.long 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
bitfld.long 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CCUS ,Capture/Compare Control Update Selection" "COMG bit only,COMG bit/Rising edge"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCPC ,Capture/Compare Preloaded Control" "Not preloaded,Preloaded"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIM8_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM8_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "TIM8_SR,Status register"
|
|
eventfld.long 0x00 17. " CC6IF ,Capture/Compare 6 interrupt Flag" "No match,Matched"
|
|
eventfld.long 0x00 16. " CC5IF ,Capture/Compare 5 interrupt Flag" "No match,Matched"
|
|
textline " "
|
|
eventfld.long 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " B2IF ,Break 2 interrupt Flag" "No break,Break"
|
|
eventfld.long 0x00 7. " BIF ,Break interrupt Flag" "No break,Break"
|
|
textline " "
|
|
eventfld.long 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
eventfld.long 0x00 5. " COMIF ,COM interrupt Flag" "No COM,COM"
|
|
textline " "
|
|
eventfld.long 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
eventfld.long 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
eventfld.long 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
eventfld.long 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
eventfld.long 0x00 0. " UIF ,Update interrupt Flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM8_EGR,Event generation register"
|
|
bitfld.word 0x00 8. " B2G ,Break 2 Generation" "No action,Break"
|
|
bitfld.word 0x00 7. " BG ,Break Generation" "No action,Break"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare Control Update Generation" "No action,Update"
|
|
textline " "
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.l((ad:0x40013400+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40013400+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output Compare 1 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40013400+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output Compare 2 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x3
|
|
line.long 0x00 "TIM8_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.l((ad:0x40013400+0x1C)))&0x303)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40013400+0x1C)))&0x3)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40013400+0x1C)))&0x300)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM8_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.long 0x20++0x3
|
|
line.long 0x00 "TIM8_CCER,Capture/compare enable register"
|
|
bitfld.long 0x00 21. " CC6P ,Capture/Compare 6 output Polarity input/output" "High,Low"
|
|
bitfld.long 0x00 20. " CC6E ,Capture/Compare 6 output enable input/output" "Off,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CC5P ,Capture/Compare 5 output Polarity input/output" "High,Low"
|
|
bitfld.long 0x00 16. " CC5E ,Capture/Compare 5 output enable input/output" "Off,On"
|
|
textline " "
|
|
bitfld.long 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 5. 7. " CCP2 ,Capture/Compare 2 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.long 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output (at output CCxP|CCxNP)" "Non-inverted|Rising/High|High,Inverted|Falling/Low|High,/High|Low,Non-inverted|Both/Low|Low"
|
|
bitfld.long 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
if ((per.w(ad:0x40013400)&0x800)==0x0)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM8_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM8_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM8_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM8_ARR,Auto-reload register"
|
|
group.word 0x30++0x1
|
|
line.word 0x00 "TIM8_RCR,Repetition counter register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM8_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM8_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM8_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM8_CCR4,Capture/compare register 4"
|
|
if (((per.l(ad:0x40013400+0x44)&0x300))==0x100)
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM8_BDTR,Break and dead-time register"
|
|
rbitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
rbitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
rbitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
elif (((per.l(ad:0x40013400+0x44)&0x300))==0x200)
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM8_BDTR,Break and dead-time register"
|
|
bitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
else
|
|
group.long 0x44++0x3
|
|
line.long 0x00 "TIM8_BDTR,Break and dead-time register"
|
|
bitfld.long 0x00 25. " BK2P ,Break 2 Polarity" "Low,High"
|
|
bitfld.long 0x00 24. " BK2E ,Break 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " BK2F ,Break 2 filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MOE ,Main Output enable" "Disabled/Forced,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic Output enable" "Only software,Software or auto"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break Polarity" "Low,High"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OSSR ,Off-State Selection for Run mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OSSI ,Off-State Selection for Idle mode" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock Configuration" "Off,Level 1,Level 2,Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-Time Generator set-up"
|
|
endif
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM8_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM8_CR1,TIM8_CR2,TIM8_SMCR,TIM8_DIER,TIM8_SR,TIM8_EGR,TIM8_CCMR1,TIM8_CCMR2,TIM8_CCER,TIM8_CNT,TIM8_PSC,TIM8_ARR,TIM8_RCR,TIM8_CCR1,TIM8_CCR2,TIM8_CCR3,TIM8_CCR4,TIM8_BDTR,TIM8_DCR,TIM8_DMAR,,TIM8_CCMR3,TIM8_CCR5,TIM8_CCR6,TIM8_OR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM8_DMAR,DMA address for full transfer"
|
|
group.long 0x50++0x3
|
|
line.long 0x00 "TIM8_OR,Option register"
|
|
bitfld.long 0x00 2.--3. " ETR_ADC3 ,ETR_ADC3 remapping capability" "No connection,ETR-->ADC3_AWD1,ETR-->ADC3_AWD2,ETR-->ADC3_AWD3"
|
|
bitfld.long 0x00 0.--1. " ETR_ADC2 ,ETR_ADC2 remapping capability" "No connection,ETR-->ADC2_AWD1,ETR-->ADC2_AWD2,ETR-->ADC2_AWD3"
|
|
group.long 0x54++0x3
|
|
line.long 0x00 "TIM8_CCMR3,Capture/compare mode register 3"
|
|
bitfld.long 0x00 15. " OC6CE ,Output Compare 6 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC6M ,Output Compare 6 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC6PE ,Output Compare 6 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC6FE ,Output Compare 6 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC5CE ,Output Compare 5 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC5M ,Output Compare 5 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1,PWM2,Retrigerrable OPM1,Retrigerrable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC5PE ,Output Compare 5 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC5FE ,Output Compare 5 Fast enable" "Disabled,Enabled"
|
|
group.long 0x58++0x3
|
|
line.long 0x00 "TIM8_CCR5,Capture/compare register 5"
|
|
bitfld.long 0x00 31. " GC5C3 ,Group Channel 5 and Channel 3" "No effect,OC3REFC and OC5REF"
|
|
bitfld.long 0x00 30. " GC5C2 ,Group Channel 5 and Channel 2" "No effect,OC2REFC and OC5REF"
|
|
textline " "
|
|
bitfld.long 0x00 29. " GC5C1 ,Group Channel 5 and Channel 1" "No effect,OC1REFC and OC5REF"
|
|
hexmask.long.word 0x00 0.--15. 1. " CCR5 ,Capture/Compare 5 value"
|
|
group.word 0x5C++0x1
|
|
line.word 0x00 "TIM8_CCR6,Capture/compare register 6"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree.open "GPT (General-purpose timers)"
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")
|
|
tree "TIM2"
|
|
base ad:0x40000000
|
|
sif cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"
|
|
width 15.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM2_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM2_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIM2_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM2_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM2_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM2_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.l((ad:0x40000000+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000000+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000000+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.l((ad:0x40000000+0x1C)))&0x303)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000000+0x1C)))&0x3)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000000+0x1C)))&0x300)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
textline " "
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
if ((per.w(ad:0x40000000)&0x800)==0x0)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM2_CNT,Counter"
|
|
hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,Most significant part counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Least significant part of counter value"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM2_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--30. 1. " CNT[30:16] ,Most significant part counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM2_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM2_ARR,Auto-reload register"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "TIM2_CCR1,Capture/compare register 1"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TIM2_CCR2,Capture/compare register 2"
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TIM2_CCR3,Capture/compare register 3"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TIM2_CCR4,Capture/compare register 4"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM2_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,,TIM2_DCR,TIM2_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM2_DMAR,DMA address for full transfer"
|
|
width 0x0B
|
|
else
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM2_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM2_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
width 13.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM2_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 13.
|
|
textline ""
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM2_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM2_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM2_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
textline ""
|
|
if (((per.w((ad:0x40000000+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM2_CNT,Counter"
|
|
hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,High counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Low counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM2_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM2_ARR,Auto-reload register"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "TIM2_CCR1,Capture/compare register 1"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TIM2_CCR2,Capture/compare register 2"
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TIM2_CCR3,Capture/compare register 3"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TIM2_CCR4,Capture/compare register 4"
|
|
width 13.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM2_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,,TIM2_DCR,TIM2_DMAR,TIM2_OR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM2_DMAR,DMA address for burst mode"
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM16_OR,TIM16 option register"
|
|
bitfld.word 0x00 10.--11. " TI1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,PTP->TIM2_ITR1,OTG_FS_SOF->TIM2_ITR1,OTG_FS_SOF->TIM2_ITR1"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"&&cpu()!="STM32F302?6"&&cpu()!="STM32F302?8"
|
|
tree "TIM3"
|
|
base ad:0x40000400
|
|
sif cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"
|
|
width 15.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM3_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM3_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIM3_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM3_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM3_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM3_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.l((ad:0x40000000+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000000+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000000+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.l((ad:0x40000000+0x1C)))&0x303)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000000+0x1C)))&0x3)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000000+0x1C)))&0x300)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
textline " "
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
if ((per.w(ad:0x40000000)&0x800)==0x0)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM3_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM3_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM3_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM3_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM3_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM3_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM3_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM3_CCR4,Capture/compare register 4"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM3_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM3_CR1,TIM3_CR2,TIM3_SMCR,TIM3_DIER,TIM3_SR,TIM3_EGR,TIM3_CCMR1,TIM3_CCMR2,TIM3_CCER,TIM3_CNT,TIM3_PSC,TIM3_ARR,,TIM3_CCR1,TIM3_CCR2,TIM3_CCR3,TIM3_CCR4,,TIM3_DCR,TIM3_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM3_DMAR,DMA address for full transfer"
|
|
width 0x0B
|
|
else
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM3_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM3_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
width 13.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM3_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 13.
|
|
textline ""
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM3_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM3_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM3_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
textline ""
|
|
if (((per.w((ad:0x40000000+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM3_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM3_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM3_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM3_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM3_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM3_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM3_CCR4,Capture/compare register 4"
|
|
width 13.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM3_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM3_CR1,TIM3_CR2,TIM3_SMCR,TIM3_DIER,TIM3_SR,TIM3_EGR,TIM3_CCMR1,TIM3_CCMR2,TIM3_CCER,TIM3_CNT,TIM3_PSC,TIM3_ARR,,TIM3_CCR1,TIM3_CCR2,TIM3_CCR3,TIM3_CCR4,,TIM3_DCR,TIM3_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM3_DMAR,DMA address for burst mode"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
sif !cpuis("STM32F334?4")&&!cpuis("STM32F334?6")&&!cpuis("STM32F334?8")&&!cpuis("STM32F303?6")&&!cpuis("STM32F303?8")&&!cpuis("STM32F328?8")
|
|
tree "TIM4"
|
|
base ad:0x40000800
|
|
sif cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"
|
|
width 15.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM4_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM4_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIM4_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM4_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM4_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM4_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.l((ad:0x40000800+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000800+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000800+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.l((ad:0x40000800+0x1C)))&0x303)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000800+0x1C)))&0x3)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000800+0x1C)))&0x300)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
textline " "
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
if ((per.w(ad:0x40000800)&0x800)==0x0)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM4_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM4_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM4_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM4_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM4_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM4_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM4_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM4_CCR4,Capture/compare register 4"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM4_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM4_CR1,TIM4_CR2,TIM4_SMCR,TIM4_DIER,TIM4_SR,TIM4_EGR,TIM4_CCMR1,TIM4_CCMR2,TIM4_CCER,TIM4_CNT,TIM4_PSC,TIM4_ARR,,TIM4_CCR1,TIM4_CCR2,TIM4_CCR3,TIM4_CCR4,,TIM4_DCR,TIM4_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM4_DMAR,DMA address for full transfer"
|
|
width 0x0B
|
|
else
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM4_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM4_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
width 13.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM4_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 13.
|
|
textline ""
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM4_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM4_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM4_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
textline ""
|
|
if (((per.w((ad:0x40000800+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000800+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000800+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40000800+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000800+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000800+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM4_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM4_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM4_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM4_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM4_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM4_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM4_CCR4,Capture/compare register 4"
|
|
width 13.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM4_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM4_CR1,TIM4_CR2,TIM4_SMCR,TIM4_DIER,TIM4_SR,TIM4_EGR,TIM4_CCMR1,TIM4_CCMR2,TIM4_CCER,TIM4_CNT,TIM4_PSC,TIM4_ARR,,TIM4_CCR1,TIM4_CCR2,TIM4_CCR3,TIM4_CCR4,,TIM4_DCR,TIM4_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM4_DMAR,DMA address for burst mode"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
endif
|
|
endif
|
|
sif cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"
|
|
tree "TIM5"
|
|
base ad:0x40000C00
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM5_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM5_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
width 13.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM5_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 13.
|
|
textline ""
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM5_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM5_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM5_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
textline ""
|
|
if (((per.w((ad:0x40000C00+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000C00+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000C00+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM5_CNT,Counter"
|
|
hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,High counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Low counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM5_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM5_ARR,Auto-reload register"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "TIM5_CCR1,Capture/compare register 1"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TIM5_CCR2,Capture/compare register 2"
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TIM5_CCR3,Capture/compare register 3"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TIM5_CCR4,Capture/compare register 4"
|
|
width 13.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM5_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM5_CR1,TIM5_CR2,TIM5_SMCR,TIM5_DIER,TIM5_SR,TIM5_EGR,TIM5_CCMR1,TIM5_CCMR2,TIM5_CCER,TIM5_CNT,TIM5_PSC,TIM5_ARR,,TIM5_CCR1,TIM5_CCR2,TIM5_CCR3,TIM5_CCR4,,TIM5_DCR,TIM5_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM5_DMAR,DMA address for burst mode"
|
|
width 0xB
|
|
tree.end
|
|
tree "TIM12"
|
|
base ad:0x40001800
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM12_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM12_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM12_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM12_SR,Status register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM12_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "Not generated,Generated"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generated"
|
|
if (((per.w((ad:0x40001800+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40001800+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40001800+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
width 13.
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM12_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
width 13.
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM12_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM12_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM12_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM12_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM12_CCR2,Capture/compare register 2"
|
|
width 0xb
|
|
tree.end
|
|
tree "TIM13"
|
|
base ad:0x40001C00
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM13_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM13_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM13_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM13_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generated"
|
|
if (((per.w((ad:0x40001C00+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM13_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,?..."
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM13_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=8,fCK_INT|N=5,fCK_INT|N=6,fDTS/2|N=8,fDTS/2|N=5,fDTS/4|N=6,fDTS/4|N=8,?..."
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM13_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM13_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM13_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM13_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM13_CCR1,Capture/compare register 1"
|
|
width 0xb
|
|
tree.end
|
|
tree "TIM14"
|
|
base ad:0x40002000
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM14_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM14_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM14_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM14_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generated"
|
|
if (((per.w((ad:0x40002000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM14_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,?..."
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM14_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=8,fCK_INT|N=5,fCK_INT|N=6,fDTS/2|N=8,fDTS/2|N=5,fDTS/4|N=6,fDTS/4|N=8,?..."
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM14_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM14_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM14_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM14_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM14_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM14_OR,TIM14 option register 1"
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,Timer Input 1 remap" "TIM14_CH1->GPIO,RTC_CLK->TIM14_CH1,TIM14_CH1->HSE/32,TIM14_CH1->MCO"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "TIM15"
|
|
base ad:0x40014000
|
|
width 15.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM15_CR1,Control register 1"
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave update,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM15_CR2,Control register 2"
|
|
bitfld.word 0x00 10. " OIS2 ,Output idle state 2 (OC2 output)" "0,1"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1N output)" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
textline " "
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 7. " TI1S ,TI1 selection" "TIM15_CH1,TIM15_CH1/CH2"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,?..."
|
|
bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "CCx event,Update"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/compare control update selection" "COMG bit,COMG bit/Rising edge"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CCPC ,Capture/compare preload control" "Not preloaded,Preloaded"
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM15_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM15_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM15_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM15_SR,Status register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM15_EGR,Event generation register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "Not generated,Generated"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No update,Generated"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture|Compare/Capture"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture|Compare/Capture"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generated"
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l((ad:0x40014000+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM mode 1,PWM mode 2,,,,,Combined PWM mode 1,Combined PWM mode 2,?..."
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Inactive,Active,PWM mode 1,PWM mode 2,,,,,Combined PWM mode 1,Combined PWM mode 2,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40014000+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Inactive,Active,PWM mode 1,PWM mode 2,,,,,Combined PWM mode 1,Combined PWM mode 2,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40014000+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Inactive,Active,PWM mode 1,PWM mode 2,,,,,Combined PWM mode 1,Combined PWM mode 2,?..."
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014000+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM mode 1,PWM mode 2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM mode 1,PWM mode 2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM mode 1,PWM mode 2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM mode 1,PWM mode 2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
endif
|
|
if (((per.w((ad:0x40014000+0x18)))&0x303)==0x000)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM15_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low"
|
|
textline " "
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On"
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM15_CCER,Capture/compare enable register"
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/Rising edge,Inverted/Falling Edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On"
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x300)==0x000)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM15_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low"
|
|
textline " "
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On"
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/Rising edge,Inverted/Falling Edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM15_CCER,Capture/compare enable register"
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/Rising edge,Inverted/Falling Edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On"
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/Rising edge,Inverted/Falling Edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM15_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" "Not updated,Updated"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM15_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM15_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM15_ARR,Auto-reload register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "TIM15_RCR,Repetition counter register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM15_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM15_CCR2,Capture/compare register 2"
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM15_BDTR,Break and Dead-time register"
|
|
bitfld.long 0x00 16.--19. " BKF[3:0] ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode (OC/OCN)" "Disabled,Forced"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM15_BDTR,Break and Dead-time register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for Idle mode (OC/OCN)" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM15_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM15_CR1,TIM15_CR2,TIM15_SMCR,TIM15_DIER,TIM15_SR,TIM15_EGR,TIM15_CCMR1,,TIM15_CCER,TIM15_CNT,TIM15_PSC,TIM15_ARR,TIM15_RCR,TIM15_CCR1,TIM15_CCR2,,,TIM15_BDTR,TIM15_DCR,TIM15_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM15_DMAR,DMA address for full transfer"
|
|
width 0x0b
|
|
tree.end
|
|
tree "TIM16"
|
|
base ad:0x40014400
|
|
width 13.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM16_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.w(ad:0x40014400+0x044))&0x300)==0x300)||(((per.w(ad:0x40014400+0x044))&0x300)==0x200)||(((per.w(ad:0x40014400+0x044))&0x300)==0x100)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM16_CR2,Control Register 2"
|
|
rbitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
rbitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM16_CR2,Control Register 2"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM16_DIER,DMA/Interrupt Enable Register"
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&(!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE"))
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM16_SR,Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 over-capture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM16_EGR,Event Generation Register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Generate"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No update,Update"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((((per.w(ad:0x40014400+0x044))&0x300)==0x300)||(((per.w(ad:0x40014400+0x044))&0x300)==0x200))
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.w(ad:0x40014400)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if ((per.w(ad:0x40014400)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM16_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM16_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM16_ARR,Auto-Reload Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "TIM16_RCR,Repetition Counter Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM16_CCR1,Capture/Compare Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if (((per.w(ad:0x40014400+0x044))&0x300)==0x300)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x200)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40014400+0x044))&0x300)==0x300)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x200)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x100)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for Idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM16_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM16_CR1,TIM16_CR2,,TIM16_DIER,TIM16_SR,TIM16_EGR,TIM16_CMR1,,TIM16_CCER,TIM16_CNT,TIM16_PSC,TIM16_ARR,TIM16_RCR,TIM16_CCR1,,,,TIM16_BDTR,TIM16_DCR,TIM16_DMAR,TIM16_OR,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM16_CR1,TIM16_CR2,,TIM16_DIER,TIM16_SR,TIM16_EGR,TIM16_CMR1,,TIM16_CCER,TIM16_CNT,TIM16_PSC,TIM16_ARR,TIM16_RCR,TIM16_CCR1,,,,TIM16_BDTR,TIM16_DCR,TIM16_DMAR,?..."
|
|
endif
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM16_DMAR,DMA Address for Full Transfer"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TIM16_OR,TIM16 Option Register"
|
|
bitfld.long 0x00 0.--1. " TI1_RMP ,Timer 16 input 1 connection" "GPIO,RTC_clock,HSE/32,MCO"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM17"
|
|
base ad:0x40014800
|
|
width 13.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM17_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.w(ad:0x40014800+0x044))&0x300)==0x300)||(((per.w(ad:0x40014800+0x044))&0x300)==0x200)||(((per.w(ad:0x40014800+0x044))&0x300)==0x100)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM17_CR2,Control Register 2"
|
|
rbitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
rbitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM17_CR2,Control Register 2"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM17_DIER,DMA/Interrupt Enable Register"
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&(!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE"))
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM17_SR,Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 over-capture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM17_EGR,Event Generation Register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Generate"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No update,Update"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((((per.w(ad:0x40014800+0x044))&0x300)==0x300)||(((per.w(ad:0x40014800+0x044))&0x300)==0x200))
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.w(ad:0x40014800)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if ((per.w(ad:0x40014800)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM17_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM17_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM17_ARR,Auto-Reload Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "TIM17_RCR,Repetition Counter Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM17_CCR1,Capture/Compare Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if (((per.w(ad:0x40014800+0x044))&0x300)==0x300)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x200)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40014800+0x044))&0x300)==0x300)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x200)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x100)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for Idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM17_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM17_CR1,TIM17_CR2,,TIM17_DIER,TIM17_SR,TIM17_EGR,TIM17_CMR1,,TIM17_CCER,TIM17_CNT,TIM17_PSC,TIM17_ARR,TIM17_RCR,TIM17_CCR1,,,,TIM17_BDTR,TIM17_DCR,TIM17_DMAR,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM17_CR1,TIM17_CR2,,TIM17_DIER,TIM17_SR,TIM17_EGR,TIM17_CMR1,,TIM17_CCER,TIM17_CNT,TIM17_PSC,TIM17_ARR,TIM17_RCR,TIM17_CCR1,,,,TIM17_BDTR,TIM17_DCR,TIM17_DMAR,?..."
|
|
endif
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM17_DMAR,DMA Address for Full Transfer"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"
|
|
tree "TIM19"
|
|
base ad:0x40015C00
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM19_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM19_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
width 13.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM19_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 13.
|
|
textline ""
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM19_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM19_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM19_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
textline ""
|
|
if (((per.w((ad:0x40015C00+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM19_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40015C00+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM19_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40015C00+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM19_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM19_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40015C00+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM19_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40015C00+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM19_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40015C00+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM19_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM19_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM19_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM19_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM19_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM19_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM19_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM19_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM19_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM19_CCR4,Capture/compare register 4"
|
|
width 13.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM19_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM19_CR1,TIM19_CR2,TIM19_SMCR,TIM19_DIER,TIM19_SR,TIM19_EGR,TIM19_CCMR1,TIM19_CCMR2,TIM19_CCER,TIM19_CNT,TIM19_PSC,TIM19_ARR,,TIM19_CCR1,TIM19_CCR2,TIM19_CCR3,TIM19_CCR4,,TIM19_DCR,TIM19_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM19_DMAR,DMA address for burst mode"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
else
|
|
tree "TIM2"
|
|
base ad:0x40000000
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
width 15.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM2_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM2_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIM2_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM2_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM2_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM2_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.l((ad:0x40000000+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000000+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000000+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.l((ad:0x40000000+0x1C)))&0x303)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000000+0x1C)))&0x3)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000000+0x1C)))&0x300)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
textline " "
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
if ((per.w(ad:0x40000000)&0x800)==0x0)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM2_CNT,Counter"
|
|
hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,Most significant part counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Least significant part of counter value"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM2_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--30. 1. " CNT[30:16] ,Most significant part counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM2_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM2_ARR,Auto-reload register"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "TIM2_CCR1,Capture/compare register 1"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TIM2_CCR2,Capture/compare register 2"
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TIM2_CCR3,Capture/compare register 3"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TIM2_CCR4,Capture/compare register 4"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM2_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,,TIM2_DCR,TIM2_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM2_DMAR,DMA address for full transfer"
|
|
width 0x0B
|
|
else
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM2_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM2_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
width 13.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM2_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 13.
|
|
textline ""
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM2_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM2_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM2_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
textline ""
|
|
if (((per.w((ad:0x40000000+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM2_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40000000+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000000+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM2_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM2_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM2_CNT,Counter"
|
|
hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,High counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Low counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM2_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM2_ARR,Auto-reload register"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "TIM2_CCR1,Capture/compare register 1"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TIM2_CCR2,Capture/compare register 2"
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TIM2_CCR3,Capture/compare register 3"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TIM2_CCR4,Capture/compare register 4"
|
|
width 13.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM2_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM2_CR1,TIM2_CR2,TIM2_SMCR,TIM2_DIER,TIM2_SR,TIM2_EGR,TIM2_CCMR1,TIM2_CCMR2,TIM2_CCER,TIM2_CNT,TIM2_PSC,TIM2_ARR,,TIM2_CCR1,TIM2_CCR2,TIM2_CCR3,TIM2_CCR4,,TIM2_DCR,TIM2_DMAR,TIM2_OR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM2_DMAR,DMA address for burst mode"
|
|
group.word 0x50++0x1
|
|
line.word 0x00 "TIM16_OR,TIM16 option register"
|
|
bitfld.word 0x00 10.--11. " TI1_RMP ,Internal trigger 1 remap" "TIM8_TRGOUT,PTP->TIM2_ITR1,OTG_FS_SOF->TIM2_ITR1,OTG_FS_SOF->TIM2_ITR1"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree "TIM3"
|
|
base ad:0x40000400
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
width 15.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM3_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM3_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIM3_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM3_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM3_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM3_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.l((ad:0x40000400+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000400+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000400+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.l((ad:0x40000400+0x1C)))&0x303)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000400+0x1C)))&0x3)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000400+0x1C)))&0x300)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
textline " "
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
if ((per.w(ad:0x40000400)&0x800)==0x0)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM3_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM3_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM3_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM3_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM3_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM3_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM3_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM3_CCR4,Capture/compare register 4"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM3_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM3_CR1,TIM3_CR2,TIM3_SMCR,TIM3_DIER,TIM3_SR,TIM3_EGR,TIM3_CCMR1,TIM3_CCMR2,TIM3_CCER,TIM3_CNT,TIM3_PSC,TIM3_ARR,,TIM3_CCR1,TIM3_CCR2,TIM3_CCR3,TIM3_CCR4,,TIM3_DCR,TIM3_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM3_DMAR,DMA address for full transfer"
|
|
width 0x0B
|
|
else
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM3_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM3_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
width 13.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM3_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 13.
|
|
textline ""
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM3_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM3_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM3_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
textline ""
|
|
if (((per.w((ad:0x40000400+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000400+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000400+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM3_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40000400+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000400+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000400+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM3_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM3_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM3_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM3_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM3_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM3_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM3_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM3_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM3_CCR4,Capture/compare register 4"
|
|
width 13.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM3_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM3_CR1,TIM3_CR2,TIM3_SMCR,TIM3_DIER,TIM3_SR,TIM3_EGR,TIM3_CCMR1,TIM3_CCMR2,TIM3_CCER,TIM3_CNT,TIM3_PSC,TIM3_ARR,,TIM3_CCR1,TIM3_CCR2,TIM3_CCR3,TIM3_CCR4,,TIM3_DCR,TIM3_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM3_DMAR,DMA address for burst mode"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
tree "TIM4"
|
|
base ad:0x40000800
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
width 15.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM4_CR1,Control register 1"
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM4_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "TIM4_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
textline " "
|
|
bitfld.long 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.long 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OCCS ,OCREF clear selection" "OCREF_CLR,ETRF"
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM4_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM4_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM4_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
if (((per.l((ad:0x40000800+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000800+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000800+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.l((ad:0x40000800+0x1C)))&0x303)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000800+0x1C)))&0x3)==0x0)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40000800+0x1C)))&0x300)==0x000)
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.long 0x00 12.--14. 24. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive,Retriggerable OPM1,Retriggerable OPM2,,,Combined PWM1,Combined PWM2,Asymmetric PWM1,Asymmetric PWM2"
|
|
textline " "
|
|
bitfld.long 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.long 0x1C++0x3
|
|
line.long 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.long 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
textline " "
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
if ((per.w(ad:0x40000800)&0x800)==0x0)
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM4_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM4_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM4_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM4_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM4_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM4_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM4_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM4_CCR4,Capture/compare register 4"
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM4_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM4_CR1,TIM4_CR2,TIM4_SMCR,TIM4_DIER,TIM4_SR,TIM4_EGR,TIM4_CCMR1,TIM4_CCMR2,TIM4_CCER,TIM4_CNT,TIM4_PSC,TIM4_ARR,,TIM4_CCR1,TIM4_CCR2,TIM4_CCR3,TIM4_CCR4,,TIM4_DCR,TIM4_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM4_DMAR,DMA address for full transfer"
|
|
width 0x0B
|
|
else
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM4_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM4_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
width 13.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM4_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 13.
|
|
textline ""
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM4_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM4_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM4_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
textline ""
|
|
if (((per.w((ad:0x40000800+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000800+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000800+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM4_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40000800+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000800+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000800+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM4_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM4_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM4_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM4_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM4_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM4_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM4_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM4_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM4_CCR4,Capture/compare register 4"
|
|
width 13.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM4_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM4_CR1,TIM4_CR2,TIM4_SMCR,TIM4_DIER,TIM4_SR,TIM4_EGR,TIM4_CCMR1,TIM4_CCMR2,TIM4_CCER,TIM4_CNT,TIM4_PSC,TIM4_ARR,,TIM4_CCR1,TIM4_CCR2,TIM4_CCR3,TIM4_CCR4,,TIM4_DCR,TIM4_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM4_DMAR,DMA address for burst mode"
|
|
width 0xB
|
|
endif
|
|
tree.end
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
tree "TIM5"
|
|
base ad:0x40000C00
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM5_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM5_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
width 13.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM5_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 13.
|
|
textline ""
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM5_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM5_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM5_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
textline ""
|
|
if (((per.w((ad:0x40000C00+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000C00+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000C00+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM5_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40000C00+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000C00+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40000C00+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM5_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM5_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM5_CNT,Counter"
|
|
hexmask.long.word 0x00 16.--31. 1. " CNT[31:16] ,High counter value"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Low counter value"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM5_PSC,Prescaler"
|
|
group.long 0x2C++0x3
|
|
line.long 0x00 "TIM5_ARR,Auto-reload register"
|
|
group.long 0x34++0x3
|
|
line.long 0x00 "TIM5_CCR1,Capture/compare register 1"
|
|
group.long 0x38++0x3
|
|
line.long 0x00 "TIM5_CCR2,Capture/compare register 2"
|
|
group.long 0x3C++0x3
|
|
line.long 0x00 "TIM5_CCR3,Capture/compare register 3"
|
|
group.long 0x40++0x3
|
|
line.long 0x00 "TIM5_CCR4,Capture/compare register 4"
|
|
width 13.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM5_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM5_CR1,TIM5_CR2,TIM5_SMCR,TIM5_DIER,TIM5_SR,TIM5_EGR,TIM5_CCMR1,TIM5_CCMR2,TIM5_CCER,TIM5_CNT,TIM5_PSC,TIM5_ARR,,TIM5_CCR1,TIM5_CCR2,TIM5_CCR3,TIM5_CCR4,,TIM5_DCR,TIM5_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM5_DMAR,DMA address for burst mode"
|
|
width 0xB
|
|
tree.end
|
|
tree "TIM12"
|
|
base ad:0x40001800
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM12_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM12_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM12_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM12_SR,Status register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM12_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "Not generated,Generated"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generated"
|
|
if (((per.w((ad:0x40001800+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40001800+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40001800+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM12_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
width 13.
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM12_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
width 13.
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM12_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM12_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM12_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM12_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM12_CCR2,Capture/compare register 2"
|
|
width 0xb
|
|
tree.end
|
|
tree "TIM13"
|
|
base ad:0x40001C00
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM13_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM13_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM13_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM13_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generated"
|
|
if (((per.w((ad:0x40001C00+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM13_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,?..."
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM13_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=8,fCK_INT|N=5,fCK_INT|N=6,fDTS/2|N=8,fDTS/2|N=5,fDTS/4|N=6,fDTS/4|N=8,?..."
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM13_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM13_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM13_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM13_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM13_CCR1,Capture/compare register 1"
|
|
width 0xb
|
|
tree.end
|
|
tree "TIM14"
|
|
base ad:0x40002000
|
|
width 12.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM14_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/UG set,Overflow"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM14_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM14_SR,Status register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM14_EGR,Event generation register"
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generated"
|
|
if (((per.w((ad:0x40002000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM14_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,?..."
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM14_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=8,fCK_INT|N=5,fCK_INT|N=6,fDTS/2|N=8,fDTS/2|N=5,fDTS/4|N=6,fDTS/4|N=8,?..."
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM14_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM14_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM14_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM14_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM14_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM14_OR,TIM14 option register 1"
|
|
bitfld.word 0x00 0.--1. " TI1_RMP ,Timer Input 1 remap" "TIM14_CH1->GPIO,RTC_CLK->TIM14_CH1,TIM14_CH1->HSE/32,TIM14_CH1->MCO"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
tree "TIM15"
|
|
base ad:0x40014000
|
|
width 15.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM15_CR1,Control register 1"
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "Not remapped,Remapped"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave update,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM15_CR2,Control register 2"
|
|
bitfld.word 0x00 10. " OIS2 ,Output idle state 2 (OC2 output)" "0,1"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1N output)" "0,1"
|
|
textline " "
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
textline " "
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 7. " TI1S ,TI1 selection" "TIM15_CH1,TIM15_CH1/CH2"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,?..."
|
|
bitfld.word 0x00 3. " CCDS ,Capture/compare DMA selection" "CCx event,Update"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/compare control update selection" "COMG bit,COMG bit/Rising edge"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CCPC ,Capture/compare preload control" "Not preloaded,Preloaded"
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIM15_SMCR,Slave mode control register"
|
|
bitfld.long 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.long 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,?..."
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. 16. " SMS ,Slave mode selection" "Disabled,,,,Reset,Gated,Trigger,External Clock,Reset + trigger,?..."
|
|
else
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM15_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI1FP2,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder mode 1,Encoder mode 2,Encoder mode 3,Reset,Gated,Trigger,External Clock"
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM15_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM15_SR,Status register"
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "Not updated,Updated"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM15_EGR,Event generation register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "Not generated,Generated"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "No action,Generated"
|
|
textline " "
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No update,Generated"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture|Compare/Capture"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture|Compare/Capture"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No action,Generated"
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l((ad:0x40014000+0x18)))&0x303)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM mode 1,PWM mode 2,,,,,Combined PWM mode 1,Combined PWM mode 2,?..."
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Inactive,Active,PWM mode 1,PWM mode 2,,,,,Combined PWM mode 1,Combined PWM mode 2,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40014000+0x18)))&0x3)==0x0)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Inactive,Active,PWM mode 1,PWM mode 2,,,,,Combined PWM mode 1,Combined PWM mode 2,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.l((ad:0x40014000+0x18)))&0x300)==0x000)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--14. 24. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Inactive,Active,PWM mode 1,PWM mode 2,,,,,Combined PWM mode 1,Combined PWM mode 2,?..."
|
|
bitfld.long 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.long 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014000+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM mode 1,PWM mode 2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM mode 1,PWM mode 2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM mode 1,PWM mode 2"
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM mode 1,PWM mode 2"
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM15_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " IC2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
endif
|
|
if (((per.w((ad:0x40014000+0x18)))&0x303)==0x000)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM15_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low"
|
|
textline " "
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On"
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x3)==0x0)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM15_CCER,Capture/compare enable register"
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/Rising edge,Inverted/Falling Edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low"
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Off,On"
|
|
elif (((per.w((ad:0x40014000+0x18)))&0x300)==0x000)
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM15_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 7. " CC2NP ,Capture/Compare 2 complementary output polarity" "Active high,Active low"
|
|
textline " "
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " CC2P ,Capture/Compare 2 output polarity" "Active high,Active low"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Off,On"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On"
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/Rising edge,Inverted/Falling Edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM15_CCER,Capture/compare enable register"
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 6. " CC2NE ,Capture/Compare 2 complementary output enable" "Off,On"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output polarity" "Non-inverted/Rising edge,Inverted/Falling Edge,,Non-inverted/Both edges"
|
|
bitfld.word 0x00 4. " CC2E ,Capture/Compare 2 output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Off,On"
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output polarity" "Non-inverted/Rising edge,Inverted/Falling Edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x24++0x3
|
|
line.long 0x00 "TIM15_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" "Not updated,Updated"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM15_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM15_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM15_ARR,Auto-reload register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "TIM15_RCR,Repetition counter register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM15_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM15_CCR2,Capture/compare register 2"
|
|
sif cpuis("STM32F334*")||cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpuis("STM32F328*8")||cpuis("STM32F358*C")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM15_BDTR,Break and Dead-time register"
|
|
bitfld.long 0x00 16.--19. " BKF[3:0] ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OSSI ,Off-state selection for Idle mode (OC/OCN)" "Disabled,Forced"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM15_BDTR,Break and Dead-time register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for Idle mode (OC/OCN)" "Disabled,Forced"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM15_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM15_CR1,TIM15_CR2,TIM15_SMCR,TIM15_DIER,TIM15_SR,TIM15_EGR,TIM15_CCMR1,,TIM15_CCER,TIM15_CNT,TIM15_PSC,TIM15_ARR,TIM15_RCR,TIM15_CCR1,TIM15_CCR2,,,TIM15_BDTR,TIM15_DCR,TIM15_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM15_DMAR,DMA address for full transfer"
|
|
width 0x0b
|
|
tree.end
|
|
tree "TIM16"
|
|
base ad:0x40014400
|
|
width 13.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM16_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.w(ad:0x40014400+0x044))&0x300)==0x300)||(((per.w(ad:0x40014400+0x044))&0x300)==0x200)||(((per.w(ad:0x40014400+0x044))&0x300)==0x100)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM16_CR2,Control Register 2"
|
|
rbitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
rbitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM16_CR2,Control Register 2"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM16_DIER,DMA/Interrupt Enable Register"
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&(!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE"))
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM16_SR,Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 over-capture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM16_EGR,Event Generation Register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Generate"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No update,Update"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM16_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((((per.w(ad:0x40014400+0x044))&0x300)==0x300)||(((per.w(ad:0x40014400+0x044))&0x300)==0x200))
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014400+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM16_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.w(ad:0x40014400)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if ((per.w(ad:0x40014400)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM16_CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM16_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM16_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM16_ARR,Auto-Reload Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "TIM16_RCR,Repetition Counter Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM16_CCR1,Capture/Compare Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if (((per.w(ad:0x40014400+0x044))&0x300)==0x300)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x200)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40014400+0x044))&0x300)==0x300)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x200)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014400+0x044))&0x300)==0x100)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM16_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for Idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM16_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM16_CR1,TIM16_CR2,,TIM16_DIER,TIM16_SR,TIM16_EGR,TIM16_CMR1,,TIM16_CCER,TIM16_CNT,TIM16_PSC,TIM16_ARR,TIM16_RCR,TIM16_CCR1,,,,TIM16_BDTR,TIM16_DCR,TIM16_DMAR,TIM16_OR,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM16_CR1,TIM16_CR2,,TIM16_DIER,TIM16_SR,TIM16_EGR,TIM16_CMR1,,TIM16_CCER,TIM16_CNT,TIM16_PSC,TIM16_ARR,TIM16_RCR,TIM16_CCR1,,,,TIM16_BDTR,TIM16_DCR,TIM16_DMAR,?..."
|
|
endif
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM16_DMAR,DMA Address for Full Transfer"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TIM16_OR,TIM16 Option Register"
|
|
bitfld.long 0x00 0.--1. " TI1_RMP ,Timer 16 input 1 connection" "GPIO,RTC_clock,HSE/32,MCO"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "TIM17"
|
|
base ad:0x40014800
|
|
width 13.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM17_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
if (((per.w(ad:0x40014800+0x044))&0x300)==0x300)||(((per.w(ad:0x40014800+0x044))&0x300)==0x200)||(((per.w(ad:0x40014800+0x044))&0x300)==0x100)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM17_CR2,Control Register 2"
|
|
rbitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
rbitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM17_CR2,Control Register 2"
|
|
bitfld.word 0x00 9. " OIS1N ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 8. " OIS1 ,Output idle state 1 (OC1 output)" "0,1"
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA selection" "Event,Update event"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CCUS ,Capture/Compare control update selection" "COMG,COMG/Rising"
|
|
bitfld.word 0x00 0. " CCPC ,Capture/Compare preloaded control" "Not preloaded,Preloaded"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM17_DIER,DMA/Interrupt Enable Register"
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 13. " COMDE ,COM DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " BIE ,Break interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F038?6"))&&(!cpuis("STM32F048?6"))&&(!cpuis("STM32F058?8"))&&(!cpuis("STM32F078?B"))&&(!cpuis("STM32F091?B"))&&(!cpuis("STM32F098?C")&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE"))
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIE ,COM interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM17_SR,Status Register"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 over-capture flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 7. " BIF ,Break interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt flag" "No trigger,Trigger"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMIF ,COM interrupt flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM17_EGR,Event Generation Register"
|
|
bitfld.word 0x00 7. " BG ,Break generation" "No action,Generate"
|
|
textline " "
|
|
sif !cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.word 0x00 6. " TG ,Trigger generation" "No action,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 5. " COMG ,Capture/Compare control update generation" "No update,Update"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 generation input/output" "No action,Generate"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No action,Generate"
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. 16. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive,?..."
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.long 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.long 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output compare 1 mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active/,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC1PE ,Output compare 1 preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output compare 1 fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x20)))&0x01)==0x01)
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
rbitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
else
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "TIM17_CCMR1,Capture/Compare Mode Register 1"
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input capture 1 filter" "No filter,fCK_INT N=2,fCK_INT N=4,fCK_INT N=8,fDTS/2 N=6,fDTS/2 N=8,fDTS/4 N=6,fDTS/4 N=8,fDTS/8 N=6,fDTS/8 N=8,fDTS/16 N=5,fDTS/16 N=6,fDTS/16 N=8,fDTS/32 N=5,fDTS/32 N=6,fDTS/32 N=8"
|
|
bitfld.word 0x00 2.--3. " IC1PSC ,Input capture 1 prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 selection" "Output,Input/IC1 mapped on TI1,Input/IC1 mapped on TI2,Input/IC1 mapped on TRC"
|
|
endif
|
|
endif
|
|
endif
|
|
if ((((per.w(ad:0x40014800+0x044))&0x300)==0x300)||(((per.w(ad:0x40014800+0x044))&0x300)==0x200))
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/Compare Enable Register"
|
|
rbitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w((ad:0x40014800+0x18)))&0x03)==0x00)
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/Compare Enable Register"
|
|
bitfld.word 0x00 3. " CC1NP ,Capture/Compare 1 complementary output polarity OC1N" "Active high,Active low"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CC1P ,Capture/Compare 1 output polarity output" "Active high,Active low"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "TIM17_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 2. " CC1NE ,Capture/Compare 1 complementary output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. 3. " CC1NP-CC1P ,The CC1NP/CC1P bits select the polarity of TI1FP1 and TI2FP1 for capture operation" "Non-inverted/Rising edge,Inverted/Falling edge,,Non-inverted/Both edges"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CC1E ,Capture/Compare 1 output enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.w(ad:0x40014800)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if ((per.w(ad:0x40014800)&0x800)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM17_CNT,Counter"
|
|
rbitfld.long 0x00 31. " UIFCPY ,UIF copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM17_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM17_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM17_ARR,Auto-Reload Register"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "TIM17_RCR,Repetition Counter Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " REP ,Repetition counter value"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "TIM17_CCR1,Capture/Compare Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if (((per.w(ad:0x40014800+0x044))&0x300)==0x300)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x200)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x100)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
bitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.long 0x00 16.--19. " BKF ,Break filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.long 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.long 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
rbitfld.long 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.long.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40014800+0x044))&0x300)==0x300)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x200)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
elif (((per.w(ad:0x40014800+0x044))&0x300)==0x100)
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
rbitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
else
|
|
group.word 0x44++0x01
|
|
line.word 0x00 "TIM17_BDTR,Break and Dead-Time Register"
|
|
bitfld.word 0x00 15. " MOE ,Main output enable (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " AOE ,Automatic output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " BKP ,Break polarity" "Active low,Active high"
|
|
textline " "
|
|
bitfld.word 0x00 12. " BKE ,Break enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " OSSR ,Off-state selection for Run mode (OC/OCN)" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OSSI ,Off-state selection for Idle mode (OC/OCN)" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " LOCK ,Lock configuration" "Disabled,LOCK Level 1,LOCK Level 2,LOCK Level 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " DTG ,Dead-time generator setup"
|
|
endif
|
|
endif
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "TIM17_DCR,DMA Control Register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA burst length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F398VE")
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM17_CR1,TIM17_CR2,,TIM17_DIER,TIM17_SR,TIM17_EGR,TIM17_CMR1,,TIM17_CCER,TIM17_CNT,TIM17_PSC,TIM17_ARR,TIM17_RCR,TIM17_CCR1,,,,TIM17_BDTR,TIM17_DCR,TIM17_DMAR,?..."
|
|
textline " "
|
|
else
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA base address" "TIM17_CR1,TIM17_CR2,,TIM17_DIER,TIM17_SR,TIM17_EGR,TIM17_CMR1,,TIM17_CCER,TIM17_CNT,TIM17_PSC,TIM17_ARR,TIM17_RCR,TIM17_CCR1,,,,TIM17_BDTR,TIM17_DCR,TIM17_DMAR,?..."
|
|
endif
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "TIM17_DMAR,DMA Address for Full Transfer"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
tree "TIM19"
|
|
base ad:0x40015C00
|
|
width 13.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM19_CR1,Control register 1"
|
|
bitfld.word 0x00 8.--9. " CKD ,Clock division" "tDTS=tCK_INT,tDTS=2*tCK_INT,tDTS=4*tCK_INT,?..."
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
textline " "
|
|
bitfld.word 0x00 5.--6. " CMS ,Center-aligned mode selection" "Edge,Center1,Center2,Center3"
|
|
bitfld.word 0x00 4. " DIR ,Direction" "Up,Down"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM19_CR2,Control register 2"
|
|
bitfld.word 0x00 7. " TI1S ,TI1 Selection" "CH1,CH1/CH2/CH3"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,Compare Pulse,Compare OC1REF,Compare OC2REF,Compare OC3REF,Compare OC4REF"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CCDS ,Capture/Compare DMA Selection" "CCx,Update"
|
|
width 13.
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "TIM19_SMCR,Slave mode control register"
|
|
bitfld.word 0x00 15. " ETP ,External trigger polarity" "Non-inverted/High/Rising,Inverted/Low/Falling"
|
|
bitfld.word 0x00 14. " ECE ,External clock enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12.--13. " ETPS ,External trigger prescaler" "Off,ETRP/2,ETRP/4,ETRP/8"
|
|
bitfld.word 0x00 8.--11. " ETF ,External trigger filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 7. " MSM ,Master/slave mode" "No action,Delayed"
|
|
bitfld.word 0x00 4.--6. " TS ,Trigger selection" "ITR0,ITR1,ITR2,ITR3,TI1F_ED,TI1FP1,TI2FP2,ETRF"
|
|
textline " "
|
|
bitfld.word 0x00 0.--2. " SMS ,Slave mode selection" "Disabled,Encoder 1,Encoder 2,Encoder 3,Reset,Gated,Trigger,External Clock"
|
|
width 13.
|
|
textline ""
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM19_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 14. " TDE ,Trigger DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CC4DE ,Capture/Compare 4 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CC3DE ,Capture/Compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " CC2DE ,Capture/Compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CC1DE ,Capture/Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIE ,Trigger interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CC4IE ,Capture/Compare 4 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IE ,Capture/Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " CC2IE ,Capture/Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IE ,Capture/Compare 1 interrupt enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
width 13.
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM19_SR,Status register"
|
|
bitfld.word 0x00 12. " CC4OF ,Capture/Compare 4 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 11. " CC3OF ,Capture/Compare 3 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 10. " CC2OF ,Capture/Compare 2 Overcapture Flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 9. " CC1OF ,Capture/Compare 1 Overcapture Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 6. " TIF ,Trigger interrupt Flag" "No trigger,Trigger"
|
|
bitfld.word 0x00 4. " CC4IF ,Capture/Compare 4 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3IF ,Capture/Compare 3 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 2. " CC2IF ,Capture/Compare 2 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1IF ,Capture/Compare 1 interrupt Flag input/output" "No input/No match,Captured/Matched"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM19_EGR,Event generation register"
|
|
bitfld.word 0x00 6. " TG ,Trigger Generation" "Not generated,Generated"
|
|
bitfld.word 0x00 4. " CC4G ,Capture/Compare 4 Generation input/output" "No action/No action,Capture 4/compare 4"
|
|
textline " "
|
|
bitfld.word 0x00 3. " CC3G ,Capture/Compare 3 Generation input/output" "No action/No action,Capture 3/compare 3"
|
|
bitfld.word 0x00 2. " CC2G ,Capture/Compare 2 Generation input/output" "No action/No action,Capture 2/compare 2"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CC1G ,Capture/Compare 1 Generation input/output" "No action/No action,Capture 1/compare 1"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
textline ""
|
|
if (((per.w((ad:0x40015C00+0x18)))&0x303)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM19_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40015C00+0x18)))&0x3)==0x0)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM19_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC1CE ,Output compare 1 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 1 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC1PE ,Output Compare 1 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC1FE ,Output Compare 1 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40015C00+0x18)))&0x300)==0x000)
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM19_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 15. " OC2CE ,Output compare 2 clear enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC2M ,Output Compare 2 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC2PE ,Output Compare 2 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC2FE ,Output Compare 2 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
else
|
|
group.word 0x18++0x1
|
|
line.word 0x00 "TIM19_CCMR1,Capture/compare mode register 1"
|
|
bitfld.word 0x00 12.--15. " IC2F ,Input Capture 2 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C2PSC ,Input Capture 2 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC2S ,Capture/Compare 2 Selection" "Output,Input mapped on TI2,Input mapped on TI1,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC1F ,Input Capture 1 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C1PSC ,Input Capture 1 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC1S ,Capture/Compare 1 Selection" "Output,Input mapped on TI1,Input mapped on TI2,Input mapped on TRC"
|
|
endif
|
|
if (((per.w((ad:0x40015C00+0x1C)))&0x303)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM19_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
textline " "
|
|
bitfld.word 0x00 4.--6. " OC3M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40015C00+0x1C)))&0x3)==0x0)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM19_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 7. " OC3CE ,Output Compare 3 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 4.--6. " OC1M ,Output Compare 3 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 3. " OC3PE ,Output Compare 3 Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " OC3FE ,Output Compare 3 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Inputmapped on TI4,Input mapped on TRC"
|
|
elif (((per.w((ad:0x40015C00+0x1C)))&0x300)==0x000)
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM19_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 15. " OC4CE ,Output Compare 4 Clear Enable" "Not affected,Cleared"
|
|
bitfld.word 0x00 12.--14. " OC4M ,Output Compare 4 Mode" "Frozen,Active,Inactive,Toggle,Force inactive,Force active,PWM1/active,PWM2/inactive"
|
|
textline " "
|
|
bitfld.word 0x00 11. " OC4PE ,Output Compare 4 Preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " OC4FE ,Output Compare 4 Fast enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
else
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "TIM19_CCMR2,Capture/compare mode register 2"
|
|
bitfld.word 0x00 12.--15. " IC4F ,Input Capture 4 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 10.--11. " C4PSC ,Input Capture 4 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " CC4S ,Capture/Compare 4 Selection" "Output,Input mapped on TI4,Input mapped on TI3,Input mapped on TRC"
|
|
textline " "
|
|
bitfld.word 0x00 4.--7. " IC3F ,Input Capture 3 Filter" "No filter,fCK_INT|N=2,fCK_INT|N=4,fCK_INT|N=8,fDTS/2|N=6,fDTS/2|N=8,fDTS/4|N=6,fDTS/4|N=8,fDTS/8|N=6,fDTS/8|N=8,fDTS/16|N=5,fDTS/16|N=6,fDTS/16|N=8,fDTS/32|N=5,fDTS/32|N=6,fDTS/32|N=8"
|
|
textline " "
|
|
bitfld.word 0x00 2.--3. " C3PSC ,Input Capture 3 Prescaler" "No prescaler,Every 2 events,Every 4 events,Every 8 events"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " CC3S ,Capture/Compare 3 Selection" "Output,Input mapped on TI3,Input mapped on TI4,Input mapped on TRC"
|
|
endif
|
|
group.word 0x20++0x1
|
|
line.word 0x00 "TIM19_CCER,Capture/compare enable register"
|
|
bitfld.word 0x00 13. 15. " CC4P ,Capture/Compare 4 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 12. " CC4E_NP ,Capture/Compare 4 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 9. 11. " CC3P ,Capture/Compare 3 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 8. " CC3E_NP ,Capture/Compare 3 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 5. 7. " CC2P ,Capture/Compare 2 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 4. " CC2E_NP ,Capture/Compare 2 output enable input/output" "Disabled/Off,Enabled/On"
|
|
textline " "
|
|
bitfld.word 0x00 1. 3. " CC1P ,Capture/Compare 1 output Polarity input/output" "Non-inverted|Rising/High,Inverted|Falling/Low,/High,Non-inverted|Both/Low"
|
|
bitfld.word 0x00 0. " CC1E_NP ,Capture/Compare 1 output enable input/output" "Disabled/Off,Enabled/On"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM19_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM19_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM19_ARR,Auto-reload register"
|
|
group.word 0x34++0x1
|
|
line.word 0x00 "TIM19_CCR1,Capture/compare register 1"
|
|
group.word 0x38++0x1
|
|
line.word 0x00 "TIM19_CCR2,Capture/compare register 2"
|
|
group.word 0x3C++0x1
|
|
line.word 0x00 "TIM19_CCR3,Capture/compare register 3"
|
|
group.word 0x40++0x1
|
|
line.word 0x00 "TIM19_CCR4,Capture/compare register 4"
|
|
width 13.
|
|
group.word 0x48++0x1
|
|
line.word 0x00 "TIM19_DCR,DMA control register"
|
|
bitfld.word 0x00 8.--12. " DBL ,DMA Burst Length" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,?..."
|
|
textline " "
|
|
bitfld.word 0x00 0.--4. " DBA ,DMA Base Address" "TIM19_CR1,TIM19_CR2,TIM19_SMCR,TIM19_DIER,TIM19_SR,TIM19_EGR,TIM19_CCMR1,TIM19_CCMR2,TIM19_CCER,TIM19_CNT,TIM19_PSC,TIM19_ARR,,TIM19_CCR1,TIM19_CCR2,TIM19_CCR3,TIM19_CCR4,,TIM19_DCR,TIM19_DMAR,?..."
|
|
group.word 0x4C++0x1
|
|
line.word 0x00 "TIM19_DMAR,DMA address for burst mode"
|
|
width 0xB
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
tree.open "BT (Basic Timers)"
|
|
sif (cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC"))||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
sif cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"
|
|
tree "TIM 6"
|
|
base ad:0x40001000
|
|
width 14.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM6_CR1,Control register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F30?D")||cpuis("STM32F302?E")
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM6_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM6_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM6_SR,Status register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM6_EGR,Event generation register"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Update"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
if ((per.w(ad:0x40001000)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM6_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM6_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM6_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM6_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM6_ARR,Auto-reload register"
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"&&!cpuis("STM32F302*6")&&!cpuis("STM32F302*8")&&!cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
tree "TIM 7"
|
|
base ad:0x40001400
|
|
width 14.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM7_CR1,Control register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F30?D")||cpuis("STM32F302?E")
|
|
bitfld.word 0x00 11. " UIFREMAP ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
textline " "
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F051T8")&&!cpuis("STM32F058T8")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM7_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM7_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM7_SR,Status register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM7_EGR,Event generation register"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "No effect,Update"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
if ((per.w(ad:0x40001400)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM7_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM7_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM7_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM7_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM7_ARR,Auto-reload register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
else
|
|
tree "TIM 6"
|
|
base ad:0x40001000
|
|
width 11.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM6_CR1,Control register 1"
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 11.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM6_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM6_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM6_SR,Status register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM6_EGR,Event generation register"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM6_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM6_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM6_ARR,Auto-reload register"
|
|
width 0xb
|
|
tree.end
|
|
tree "TIM 7"
|
|
base ad:0x40001400
|
|
width 11.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM7_CR1,Control register 1"
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 11.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM7_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM7_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM7_SR,Status register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM7_EGR,Event generation register"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM7_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM7_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM7_ARR,Auto-reload register"
|
|
width 0xb
|
|
tree.end
|
|
tree "TIM 18"
|
|
base ad:0x40009C00
|
|
width 11.
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "TIM18_CR1,Control register 1"
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
textline " "
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave/DMA request,Overflow/Underflow/DMA request"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
width 11.
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "TIM18_CR2,Control register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master Mode Selection" "Reset,Enable,Update,?..."
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "TIM18_DIER,DMA/Interrupt enable register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "TIM18_SR,Status register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt Flag" "No update,Update"
|
|
wgroup.word 0x14++0x1
|
|
line.word 0x00 "TIM18_EGR,Event generation register"
|
|
bitfld.word 0x00 0. " UG ,Update Generation" "Not generated,Generated"
|
|
group.word 0x24++0x1
|
|
line.word 0x00 "TIM18_CNT,Counter"
|
|
group.word 0x28++0x1
|
|
line.word 0x00 "TIM18_PSC,Prescaler"
|
|
group.word 0x2C++0x1
|
|
line.word 0x00 "TIM18_ARR,Auto-reload register"
|
|
width 0xb
|
|
tree.end
|
|
endif
|
|
else
|
|
tree "TIM 6"
|
|
base ad:0x40001000
|
|
width 11.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM6_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM6_CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM6_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM6_SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM6_EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.l(ad:0x40001000)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM6_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM6_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM6_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM6_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM6_ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302VB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F302VC")&&(cpu()!="STM32F302RB")&&(cpu()!="STM32F302RC")
|
|
tree "TIM 7"
|
|
base ad:0x40001400
|
|
width 11.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM7_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM7_CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM7_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM7_SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM7_EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.l(ad:0x40001400)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM7_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM7_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM7_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM7_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM7_ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
tree "TIM 18"
|
|
base ad:0x40009C00
|
|
width 11.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "TIM18_CR1,Control Register 1"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.word 0x00 11. " UIFREM ,UIF status bit remapping" "No remapping,Remapping"
|
|
textline " "
|
|
endif
|
|
bitfld.word 0x00 7. " ARPE ,Auto-reload preload enable" "Not buffered,Buffered"
|
|
bitfld.word 0x00 3. " OPM ,One pulse mode" "Not stopped,Stopped"
|
|
bitfld.word 0x00 2. " URS ,Update request source" "Overflow/Underflow/UG set/Slave,Overflow/Underflow"
|
|
textline " "
|
|
bitfld.word 0x00 1. " UDIS ,Update disable" "No,Yes"
|
|
bitfld.word 0x00 0. " CEN ,Counter enable" "Disabled,Enabled"
|
|
sif !cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070RB")
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "TIM18_CR2,Control Register 2"
|
|
bitfld.word 0x00 4.--6. " MMS ,Master mode selection" "Reset,Enable,Update,?..."
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "TIM18_DIER,DMA/Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " UDE ,Update DMA request enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " UIE ,Update interrupt enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "TIM18_SR,Status Register"
|
|
bitfld.word 0x00 0. " UIF ,Update interrupt flag" "No update,Update"
|
|
wgroup.word 0x14++0x01
|
|
line.word 0x00 "TIM18_EGR,Event Generation Register"
|
|
bitfld.word 0x00 0. " UG ,Update generation" "No effect,Generate"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
if ((per.l(ad:0x40009C00)&0x800)==0x000)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM18_CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "TIM18_CNT,Counter"
|
|
bitfld.long 0x00 31. " UIFCPY ,UIF Copy" ",Remapped"
|
|
hexmask.long.word 0x00 0.--15. 1. " CNT[15:0] ,Counter value"
|
|
endif
|
|
else
|
|
group.word 0x24++0x01
|
|
line.word 0x00 "TIM18_CNT,Counter"
|
|
endif
|
|
group.word 0x28++0x01
|
|
line.word 0x00 "TIM18_PSC,Prescaler"
|
|
group.word 0x2C++0x01
|
|
line.word 0x00 "TIM18_ARR,Auto-Reload Register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
tree.end
|
|
sif (cpuis("STM32F334*"))
|
|
tree "HRTIM (High-Resolution Timer)"
|
|
base ad:0x40017400
|
|
width 8.
|
|
tree "Master"
|
|
if (((per.l(ad:0x40017400)&0x8)==0x8))
|
|
if (((per.l(ad:0x40017400)&0xC0000000)==((0x00)||(0x40000000))))
|
|
if (((per.l(ad:0x40017400)&0x3E0000)!=0x00))
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "MCR,Master Timer Control Register"
|
|
bitfld.long 0x00 30.--31. " BRSTDMA ,Burst DMA update" "Independently from the DMA burst transfer completion,When the DMA burst transfer is completed,On master timer roll-over following a DMA burst transfer completion,?..."
|
|
textline " "
|
|
bitfld.long 0x00 29. " MREPU ,Master timer repetition update" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No DAC trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
bitfld.long 0x00 21. " TECEN ,Timer E counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TDCEN ,Timer D counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TCCEN ,Timer C counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TBCEN ,Timer B counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TACEN ,Timer A counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MCEN ,Master counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " SYNC_SRC ,Synchronization source" "Start,Compare 1 event,Timer A start/reset,Timer A compare 1 event"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " SYNC_OUT ,Synchronization output" "Disabled,,Positive,Negative"
|
|
bitfld.long 0x00 11. " SYNCSTRTM ,Synchronization starts master" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTM ,Synchronization resets master" "No effect,Reset"
|
|
bitfld.long 0x00 8.--9. " SYNC_IN ,Synchronization input" "Disabled,,Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RETRIG ,Master re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Master continuous mode" "Single-shot,Continuous"
|
|
bitfld.long 0x00 0.--2. " CK_PSC ,Clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "MCR,Master Timer Control Register"
|
|
bitfld.long 0x00 30.--31. " BRSTDMA ,Burst DMA update occur mode" "Independently from the DMA burst transfer completion,When the DMA burst transfer is completed,On master timer roll-over following a DMA burst transfer completion,?..."
|
|
textline " "
|
|
bitfld.long 0x00 29. " MREPU ,Master timer repetition update" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No DAC trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
bitfld.long 0x00 21. " TECEN ,Timer E counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TDCEN ,Timer D counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TCCEN ,Timer C counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TBCEN ,Timer B counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TACEN ,Timer A counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MCEN ,Master counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " SYNC_SRC ,Synchronization source" "Start,Compare 1 event,Timer A start/reset,Timer A compare 1 event"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SYNC_OUT ,Synchronization output" "Disabled,,Positive,Negative"
|
|
bitfld.long 0x00 11. " SYNCSTRTM ,Synchronization starts master" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTM ,Synchronization resets master" "No effect,Reset"
|
|
bitfld.long 0x00 8.--9. " SYNC_IN ,Synchronization input" "Disabled,,Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RETRIG ,Master re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Master continuous mode" "Single-shot,Continuous"
|
|
bitfld.long 0x00 0.--2. " CK_PSC ,Clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400)&0x3E0000)!=0x00))
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "MCR,Master Timer Control Register"
|
|
bitfld.long 0x00 30.--31. " BRSTDMA ,Burst DMA update occur mode" "Independently from the DMA burst transfer completion,When the DMA burst transfer is completed,On master timer roll-over following a DMA burst transfer completion,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 29. " MREPU ,Master timer repetition update" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No DAC trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
bitfld.long 0x00 21. " TECEN ,Timer E counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TDCEN ,Timer D counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TCCEN ,Timer C counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TBCEN ,Timer B counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TACEN ,Timer A counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MCEN ,Master counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " SYNC_SRC ,Synchronization source" "Start,Compare 1 event,Timer A start/reset,Timer A compare 1 event"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " SYNC_OUT ,Synchronization output" "Disabled,,Positive,Negative"
|
|
bitfld.long 0x00 11. " SYNCSTRTM ,Synchronization starts master" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTM ,Synchronization resets master" "No effect,Reset"
|
|
bitfld.long 0x00 8.--9. " SYNC_IN ,Synchronization input" "Disabled,,Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RETRIG ,Master re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Master continuous mode" "Single-shot,Continuous"
|
|
bitfld.long 0x00 0.--2. " CK_PSC ,Clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "MCR,Master Timer Control Register"
|
|
bitfld.long 0x00 30.--31. " BRSTDMA ,Burst DMA update occur mode" "Independently from the DMA burst transfer completion,When the DMA burst transfer is completed,On master timer roll-over following a DMA burst transfer completion,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 29. " MREPU ,Master timer repetition update" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No DAC trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
bitfld.long 0x00 21. " TECEN ,Timer E counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TDCEN ,Timer D counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TCCEN ,Timer C counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TBCEN ,Timer B counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TACEN ,Timer A counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MCEN ,Master counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " SYNC_SRC ,Synchronization source" "Start,Compare 1 event,Timer A start/reset,Timer A compare 1 event"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SYNC_OUT ,Synchronization output" "Disabled,,Positive,Negative"
|
|
bitfld.long 0x00 11. " SYNCSTRTM ,Synchronization starts master" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTM ,Synchronization resets master" "No effect,Reset"
|
|
bitfld.long 0x00 8.--9. " SYNC_IN ,Synchronization input" "Disabled,,Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RETRIG ,Master re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Master continuous mode" "Single-shot,Continuous"
|
|
bitfld.long 0x00 0.--2. " CK_PSC ,Clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400)&0xC0000000)==((0x00)||(0x40000000))))
|
|
if (((per.l(ad:0x40017400)&0x3E0000)!=0x00))
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "MCR,Master Timer Control Register"
|
|
bitfld.long 0x00 30.--31. " BRSTDMA ,Burst DMA update occur mode" "Independently from the DMA burst transfer completion,When the DMA burst transfer is completed,?..."
|
|
textline " "
|
|
bitfld.long 0x00 29. " MREPU ,Master timer repetition update" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No DAC trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
bitfld.long 0x00 21. " TECEN ,Timer E counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TDCEN ,Timer D counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TCCEN ,Timer C counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TBCEN ,Timer B counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TACEN ,Timer A counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MCEN ,Master counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " SYNC_SRC ,Synchronization source" "Start,Compare 1 event,Timer A start/reset,Timer A compare 1 event"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " SYNC_OUT ,Synchronization output" "Disabled,,Positive,Negative"
|
|
bitfld.long 0x00 11. " SYNCSTRTM ,Synchronization starts master" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTM ,Synchronization resets master" "No effect,Reset"
|
|
bitfld.long 0x00 8.--9. " SYNC_IN ,Synchronization input" "Disabled,,Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RETRIG ,Master re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Master continuous mode" "Single-shot,Continuous"
|
|
bitfld.long 0x00 0.--2. " CK_PSC ,Clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "MCR,Master Timer Control Register"
|
|
bitfld.long 0x00 30.--31. " BRSTDMA ,Burst DMA update occur mode" "Independently from the DMA burst transfer completion,When the DMA burst transfer is completed,?..."
|
|
textline " "
|
|
bitfld.long 0x00 29. " MREPU ,Master timer repetition update" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No DAC trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
bitfld.long 0x00 21. " TECEN ,Timer E counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TDCEN ,Timer D counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TCCEN ,Timer C counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TBCEN ,Timer B counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TACEN ,Timer A counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MCEN ,Master counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " SYNC_SRC ,Synchronization source" "Start,Compare 1 event,Timer A start/reset,Timer A compare 1 event"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SYNC_OUT ,Synchronization output" "Disabled,,Positive,Negative"
|
|
bitfld.long 0x00 11. " SYNCSTRTM ,Synchronization starts master" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTM ,Synchronization resets master" "No effect,Reset"
|
|
bitfld.long 0x00 8.--9. " SYNC_IN ,Synchronization input" "Disabled,,Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RETRIG ,Master re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Master continuous mode" "Single-shot,Continuous"
|
|
bitfld.long 0x00 0.--2. " CK_PSC ,Clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400)&0x3E0000)!=0x00))
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "MCR,Master Timer Control Register"
|
|
bitfld.long 0x00 30.--31. " BRSTDMA ,Burst DMA update occur mode" "Independently from the DMA burst transfer completion,When the DMA burst transfer is completed,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 29. " MREPU ,Master timer repetition update" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No DAC trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
bitfld.long 0x00 21. " TECEN ,Timer E counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TDCEN ,Timer D counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TCCEN ,Timer C counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TBCEN ,Timer B counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TACEN ,Timer A counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MCEN ,Master counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " SYNC_SRC ,Synchronization source" "Start,Compare 1 event,Timer A start/reset,Timer A compare 1 event"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " SYNC_OUT ,Synchronization output" "Disabled,,Positive,Negative"
|
|
bitfld.long 0x00 11. " SYNCSTRTM ,Synchronization starts master" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTM ,Synchronization resets master" "No effect,Reset"
|
|
bitfld.long 0x00 8.--9. " SYNC_IN ,Synchronization input" "Disabled,,Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RETRIG ,Master re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Master continuous mode" "Single-shot,Continuous"
|
|
bitfld.long 0x00 0.--2. " CK_PSC ,Clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
else
|
|
group.long 0x0++0x3
|
|
line.long 0x00 "MCR,Master Timer Control Register"
|
|
bitfld.long 0x00 30.--31. " BRSTDMA ,Burst DMA update occur mode" "Independently from the DMA burst transfer completion,When the DMA burst transfer is completed,?..."
|
|
textline " "
|
|
rbitfld.long 0x00 29. " MREPU ,Master timer repetition update" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No DAC trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
bitfld.long 0x00 21. " TECEN ,Timer E counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TDCEN ,Timer D counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TCCEN ,Timer C counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TBCEN ,Timer B counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " TACEN ,Timer A counter enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MCEN ,Master counter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14.--15. " SYNC_SRC ,Synchronization source" "Start,Compare 1 event,Timer A start/reset,Timer A compare 1 event"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " SYNC_OUT ,Synchronization output" "Disabled,,Positive,Negative"
|
|
bitfld.long 0x00 11. " SYNCSTRTM ,Synchronization starts master" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTM ,Synchronization resets master" "No effect,Reset"
|
|
bitfld.long 0x00 8.--9. " SYNC_IN ,Synchronization input" "Disabled,,Internal,External"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " RETRIG ,Master re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Master continuous mode" "Single-shot,Continuous"
|
|
bitfld.long 0x00 0.--2. " CK_PSC ,Clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
endif
|
|
endif
|
|
endif
|
|
textline " "
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x00 "MISR,Master Timer Interrupt Status Register"
|
|
bitfld.long 0x00 6. " MUPD ,Master update interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 5. " SYNC ,Sync input interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 4. " MREP ,Master repetition interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MCMP4 ,Master compare 4 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " MCMP3 ,Master compare 3 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 1. " MCMP2 ,Master compare 2 interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCMP1 ,Master compare 1 interrupt flag" "Not occurred,Occurred"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x00 "MICR,Master Timer Interrupt Clear Register"
|
|
bitfld.long 0x00 6. " MUPDC ,Master update interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " SYNCC ,Sync Input interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " MREPC ,Repetition interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MCMP4C ,Master compare 4 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " MCMP3C ,Master compare 3 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " MCMP2C ,Master compare 2 interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MCMP1C ,Master compare 1 interrupt flag clear" "No effect,Clear"
|
|
group.long 0xC++0x3
|
|
line.long 0x00 "MDIER,HRTIM Master Timer DMA / Interrupt Enable Register"
|
|
bitfld.long 0x00 22. " MUPDDE ,Master update DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " SYNCDE ,Sync input DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MREPDE ,Master repetition DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MCMP4DE ,Master compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MCMP3DE ,Master compare 3 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MCMP2DE ,Master compare 2 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MCMP1DE ,Master compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MUPDIE ,Master update interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYNCIE ,Sync input interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MREPIE ,Master repetition interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MCMP4IE ,Master compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MCMP3IE ,Master compare 3 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MCMP2IE ,Master compare 2 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MCMP1IE ,Master compare 1 interrupt enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40017400)&0x10000)==0x10000))
|
|
rgroup.long 0x10++0x3
|
|
line.long 0x00 "MCNTR,Master Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MCNT ,Counter value"
|
|
else
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "MCNTR,Master Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MCNT ,Counter value"
|
|
endif
|
|
group.long 0x14++0xB
|
|
line.long 0x00 "MPER,Master Timer Period Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MPER ,Master timer period value"
|
|
line.long 0x04 "MREP,Master Timer Repetition Register"
|
|
hexmask.long.byte 0x04 0.--7. 1. " MREP ,Master timer repetition counter value"
|
|
line.long 0x08 "MCMP1R,Master Timer Compare 1 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " MCMP1 ,Master timer compare 1 value"
|
|
group.long 0x24++0xB
|
|
line.long 0x00 "MCMP2R,Master Timer Compare 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " MCMP2 ,Master timer compare 2 value"
|
|
line.long 0x04 "MCMP3R,Master Timer Compare 3 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " MCMP3 ,Master timer compare 3 value"
|
|
line.long 0x08 "MCMP4R,Master Timer Compare 4 Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " MCMP4 ,Master timer compare 4 value"
|
|
tree.end
|
|
width 11.
|
|
tree "TIMA"
|
|
if (((per.l(ad:0x40017400)&0x20000)==0x20000))
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "TIMACR,Timer A Control Register"
|
|
bitfld.long 0x00 28.--31. " UPDGAT ,Update gating" "Independently from the DMA burst transfer,When the DMA burst transfer is completed,On the update event following the DMA burst transfer completion,On a rising edge of HRTIM update enable input 1,On a rising edge of HRTIM update enable input 2,On a rising edge of HRTIM update enable input 3,On the update event following a rising edge of HRTIM update enable input 1,On the update event following a rising edge of HRTIM update enable input 2,On the update event following a rising edge of HRTIM update enable input 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MSTU ,Master timer update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TEU ,Timer E update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TDU ,Timer D update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TCU ,Timer C update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TBU ,Timer B update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TARSTU ,Timer A reset update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TAREPU ,Timer A repetition update" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 14.--15. " DELCMP4 ,Delayed CMP4 mode" "Always active,Recomputed && active following capture 2 event,Recomputed && active following (capture 2||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DELCMP2 ,Delayed CMP2 mode" "Always active,Recomputed && active following capture 1 event,Recomputed && active following (capture 1||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " SYNCSTRTA ,Synchronization starts timer A" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTA ,Synchronization resets timer A" "No effect,Reset"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " PSHPLL ,Push-Pull mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RETRIG ,Re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Continuous mode" "Single-shot,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CK_PSCA ,HRTIM timer A clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
else
|
|
group.long 0x80++0x3
|
|
line.long 0x00 "TIMACR,Timer A Control Register"
|
|
bitfld.long 0x00 28.--31. " UPDGAT ,Update gating" "Independently from the DMA burst transfer,When the DMA burst transfer is completed,On the update event following the DMA burst transfer completion,On a rising edge of HRTIM update enable input 1,On a rising edge of HRTIM update enable input 2,On a rising edge of HRTIM update enable input 3,On the update event following a rising edge of HRTIM update enable input 1,On the update event following a rising edge of HRTIM update enable input 2,On the update event following a rising edge of HRTIM update enable input 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MSTU ,Master timer update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TEU ,Timer E update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TDU ,Timer D update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TCU ,Timer C update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TBU ,Timer B update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TARSTU ,Timer A reset update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TAREPU ,Timer A repetition update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DELCMP4 ,Delayed CMP4 mode" "Always active,Recomputed && active following capture 2 event,Recomputed && active following (capture 2||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DELCMP2 ,Delayed CMP2 mode" "Always active,Recomputed && active following capture 1 event,Recomputed && active following (capture 1||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNCSTRTA ,Synchronization starts timer A" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTA ,Synchronization resets timer A" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PSHPLL ,Push-Pull mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RETRIG ,Re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Continuous mode" "Single-shot,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CK_PSCA ,HRTIM timer A clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
endif
|
|
textline " "
|
|
rgroup.long (0x80+0x04)++0x3
|
|
line.long 0x00 "TIMAISR,Timer A Interrupt Status Register"
|
|
bitfld.long 0x00 21. " O2CPY ,Output 2 copy" "Inactive,Active"
|
|
bitfld.long 0x00 20. " O1CPY ,Output 1 copy" "Inactive,Active"
|
|
bitfld.long 0x00 19. " O2STAT ,Output 2 state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " O1STAT ,Output 1 state" "Inactive,Active"
|
|
bitfld.long 0x00 17. " IPPSTAT ,Idle push pull status" "Output 1 active/Output 2 inactive,Output 2 active/Output 1 inactive"
|
|
bitfld.long 0x00 16. " CPPSTAT ,Current push pull status" "Output 1 && 2 inactive,Output 2 && 1 inactive"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DLYPRT ,Delayed protection flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RST ,Reset and/or roll-over interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " RSTA2 ,Output 2 reset interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETA2 ,Output 2 set interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " RSTA1 ,Output 1 reset interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " SETx1 ,Output 1 set interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPT2 ,Capture2 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CPT1 ,Capture1 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " UPD ,Update interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REP ,Repetition interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CMP4 ,Compare 4 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CMP3 ,Compare 3 interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMP2 ,Compare 2 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CMP1 ,Compare 1 interrupt flag" "Not occurred,Occurred"
|
|
wgroup.long (0x80+0x08)++0x3
|
|
line.long 0x00 "TIMAICR,Timer A Interrupt Clear Register"
|
|
bitfld.long 0x00 14. " DLYPRTC ,Delayed protection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " RSTC ,Reset interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " RSTA2C ,Output 2 reset flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET2AC ,Output 2 set flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RSTA1C ,Output 1 reset flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " SET1AC ,Output 1 set flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPT2C ,Capture2 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " CPT1C ,Capture1 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " UPDC ,Update interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REPC ,Repetition interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CMP4C ,Compare 4 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CMP3C ,Compare 3 interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMP2C ,Compare 2 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CMP1C ,Compare 1 interrupt flag clear" "No effect,Clear"
|
|
group.long (0x80+0xC)++0x23
|
|
line.long 0x00 "TIMADIER,HRTIM Timer A DMA / Interrupt Enable Register"
|
|
bitfld.long 0x00 30. " DLYPRTDE ,Delayed protection DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RSTDE ,Reset/roll-over DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " RSTA2DE ,Output 2 reset DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SETA2DE ,Output 2 set DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RSTA1DE ,Output 1 reset DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SET1ADE ,Output 1 set DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " CPT2DE ,Capture 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CPT1DE ,Capture 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " UPDDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " REPDE ,Repetition DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMP4DE ,Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CMP3DE ,Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMP2DE ,Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CMP1DE ,Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DLYPRTIE ,Delayed protection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIE ,Reset/roll-over interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RSTA2IE ,Output 2 reset interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETA2IE ,Output 2 set interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RSTA1IE ,Output 1 reset interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SET1AIE ,Output 1 set interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CPT2IE ,Capture interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CPT1IE ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " UPDIE ,Update interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " REPIE ,Repetition interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CMP4IE ,Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CMP3IE ,Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CMP2IE ,Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP1IE ,Compare 1 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNTAR,Timer A Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CNTA ,Timer A counter value"
|
|
line.long 0x08 "PERAR,Timer A Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERA ,Timer A period value"
|
|
line.long 0x0C "REPAR,Timer A Repetition Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " REPA ,Timer A repetition counter value"
|
|
line.long 0x10 "CMP1AR,Timer A Compare 1 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " CMP1A ,Timer A compare 1 value"
|
|
line.long 0x14 "CMP1CAR,Timer A Compare 1 Compound_ Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. " REPA ,Timer A repetition value"
|
|
hexmask.long.word 0x14 0.--15. 1. " CMP1A ,Timer A compare 1 value"
|
|
line.long 0x18 "CMP2AR,Timer A Compare 2 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " CMP2A ,Timer A compare 2 value"
|
|
line.long 0x1C "CMP3AR,Timer A Compare 3 Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " CMP3A ,Timer A compare 3 value"
|
|
line.long 0x20 "CMP4AR,Timer A Compare 4 Register"
|
|
hexmask.long.word 0x20 0.--15. 1. " CMP4A ,Timer A compare 4 value"
|
|
rgroup.long (0x80+0x30)++0x7
|
|
line.long 0x00 "CPT1AR,Timer A Capture 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPT1A ,Timer A capture 1 value"
|
|
line.long 0x04 "CPT2AR,Timer A Capture 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CPT2A ,Timer A capture 2 value"
|
|
group.long (0x80+0x38)++0x2B
|
|
line.long 0x00 "DTAR,Timer A Deadtime Register"
|
|
bitfld.long 0x00 31. " DTFLKA ,Deadtime falling lock" "Writable,Read-only"
|
|
bitfld.long 0x00 30. " DTFSLKA ,Deadtime falling sign lock" "Writable,Read-only"
|
|
bitfld.long 0x00 25. " SDTFA ,Sign deadtime falling value" "Positive,Negative"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--24. 1. " DTFA ,Deadtime falling value"
|
|
bitfld.long 0x00 15. " DTRLKA ,Deadtime rising lock" "Writable,Read-only"
|
|
bitfld.long 0x00 14. " DTRSLKA ,Deadtime rising sign lock" "Writable,Read-only"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DTPRSC ,Deadtime prescaler" ",,,tHRTIM,tHRTIM*2,tHRTIM*4,tHRTIM*8,tHRTIM*16"
|
|
bitfld.long 0x00 9. " SDTRA ,Sign deadtime rising value" "Positive,Negative"
|
|
hexmask.long.word 0x00 0.--8. 1. " DTRA ,Deadtime rising value"
|
|
line.long 0x04 "SETA1R,Timer A Output1 Set Register"
|
|
bitfld.long 0x04 31. " UPDATE ,Registers update active state" "Not forced,Forced"
|
|
bitfld.long 0x04 30. " EXTEVNT10 ,External event 10 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 29. " EXTEVNT9 ,External event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 28. " EXTEVNT8 ,External event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 27. " EXTEVNT7 ,External event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 26. " EXTEVNT6 ,External event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 25. " EXTEVNT5 ,External event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 24. " EXTEVNT4 ,External event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 23. " EXTEVNT3 ,External event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 22. " EXTEVNT2 ,External event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 21. " EXTEVNT1 ,External event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 20. " TIMEVNT9 ,Timer event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 19. " TIMEVNT8 ,Timer event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 18. " TIMEVNT7 ,Timer event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 17. " TIMEVNT6 ,Timer event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 16. " TIMEVNT5 ,Timer event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 15. " TIMEVNT4 ,Timer event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 14. " TIMEVNT3 ,Timer event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TIMEVNT2 ,Timer event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 12. " TIMEVNT1 ,Timer event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 11. " MSTCMP4 ,Master compare 4 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MSTCMP3 ,Master compare 3 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 9. " MSTCMP2 ,Master compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 8. " MSTCMP1 ,Master compare 1 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSTPER ,Master period active state" "Not forced,Forced"
|
|
bitfld.long 0x04 6. " CMP4 ,Timer A compare 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 5. " CMP3 ,Timer A compare 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CMP2 ,Timer A compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 3. " CMP1 ,Timer A compare 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 2. " PER ,Timer A period active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RESYNC ,Timer A resynchronization active state" "Not forced,Forced"
|
|
bitfld.long 0x04 0. " SST ,Software set trigger active state" "Not forced,Forced"
|
|
line.long 0x08 "RSTA1R,Timer A Output1 Reset Register"
|
|
bitfld.long 0x08 31. " UPDATE ,Registers update inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 30. " EXTEVNT10 ,External event 10 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 29. " EXTEVNT9 ,External event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 28. " EXTEVNT8 ,External event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 27. " EXTEVNT7 ,External event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 26. " EXTEVNT6 ,External event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 25. " EXTEVNT5 ,External event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 24. " EXTEVNT4 ,External event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 23. " EXTEVNT3 ,External event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 22. " EXTEVNT2 ,External event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 21. " EXTEVNT1 ,External event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 20. " TIMEVNT9 ,Timer event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TIMEVNT8 ,Timer event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 18. " TIMEVNT7 ,Timer event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 17. " TIMEVNT6 ,Timer event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 16. " TIMEVNT5 ,Timer event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 15. " TIMEVNT4 ,Timer event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 14. " TIMEVNT3 ,Timer event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 13. " TIMEVNT2 ,Timer event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 12. " TIMEVNT1 ,Timer event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 11. " MSTCMP4 ,Master compare 4 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 10. " MSTCMP3 ,Master compare 3 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 9. " MSTCMP2 ,Master compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 8. " MSTCMP1 ,Master compare 1 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSTPER ,Master period inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 6. " CMP4 ,Timer A compare 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 5. " CMP3 ,Timer A compare 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CMP2 ,Timer A compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 3. " CMP1 ,Timer A compare 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 2. " PER ,Timer A period inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RESYNC ,Timer A resynchronizaton inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 0. " SRT ,Software set trigger inactive state" "Not forced,Forced"
|
|
line.long 0x0C "SETA2R,Timer A Output2 Set Register"
|
|
bitfld.long 0x0C 31. " UPDATE ,Registers update active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 30. " EXTEVNT10 ,External event 10 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 29. " EXTEVNT9 ,External event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " EXTEVNT8 ,External event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 27. " EXTEVNT7 ,External event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 26. " EXTEVNT6 ,External event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " EXTEVNT5 ,External event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 24. " EXTEVNT4 ,External event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 23. " EXTEVNT3 ,External event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " EXTEVNT2 ,External event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 21. " EXTEVNT1 ,External event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 20. " TIMEVNT9 ,Timer event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " TIMEVNT8 ,Timer event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 18. " TIMEVNT7 ,Timer event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 17. " TIMEVNT6 ,Timer event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " TIMEVNT5 ,Timer event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 15. " TIMEVNT4 ,Timer event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 14. " TIMEVNT3 ,Timer event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " TIMEVNT2 ,Timer event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 12. " TIMEVNT1 ,Timer event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 11. " MSTCMP4 ,Master compare 4 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " MSTCMP3 ,Master compare 3 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 9. " MSTCMP2 ,Master compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 8. " MSTCMP1 ,Master compare 1 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " MSTPER ,Master period active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 6. " CMP4 ,Timer A compare 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 5. " CMP3 ,Timer A compare 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMP2 ,Timer A compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 3. " CMP1 ,Timer A compare 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 2. " PER ,Timer A period active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " RESYNC ,Timer A resynchronizaton active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 0. " SST ,Software set trigger active state" "Not forced,Forced"
|
|
line.long 0x10 "RSTA2R,Timer A Output2 Reset Register"
|
|
bitfld.long 0x10 31. " UPDATE ,Registers update inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 30. " EXTEVNT10 ,External event 10 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 29. " EXTEVNT9 ,External event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 28. " EXTEVNT8 ,External event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 27. " EXTEVNT7 ,External event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 26. " EXTEVNT6 ,External event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EXTEVNT5 ,External event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 24. " EXTEVNT4 ,External event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 23. " EXTEVNT3 ,External event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 22. " EXTEVNT2 ,External event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 21. " EXTEVNT1 ,External event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 20. " TIMEVNT9 ,Timer event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 19. " TIMEVNT8 ,Timer event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 18. " TIMEVNT7 ,Timer event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 17. " TIMEVNT6 ,Timer event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 16. " TIMEVNT5 ,Timer event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 15. " TIMEVNT4 ,Timer event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 14. " TIMEVNT3 ,Timer event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 13. " TIMEVNT2 ,Timer event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 12. " TIMEVNT1 ,Timer event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 11. " MSTCMP4 ,Master compare 4 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 10. " MSTCMP3 ,Master compare 3 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 9. " MSTCMP2 ,Master compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 8. " MSTCMP1 ,Master compare 1 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 7. " MSTPER ,Master period inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 6. " CMP4 ,Timer A compare 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 5. " CMP3 ,Timer A compare 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 4. " CMP2 ,Timer A compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 3. " CMP1 ,Timer A compare 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 2. " PER ,Timer A period inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 1. " RESYNC ,Timer A resynchronizaton inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 0. " SRT ,Software set trigger inactive state" "Not forced,Forced"
|
|
textline " "
|
|
line.long 0x14 "EEFAR1,Timer A External Event Filtering Register 1"
|
|
bitfld.long 0x14 25.--28. " EE5FLTR ,External event 5 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 24. " EE5LTCH ,External event 5 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 19.--22. " EE4FLTR ,External event 4 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 18. " EE4LTCH ,External event 4 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 13.--16. " EE3FLTR ,External event 3 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 12. " EE3LTCH ,External event 3 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 7.--10. " EE2FLTR ,External event 2 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 6. " EE2LTCH ,External event 2 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 1.--4. " EE1FLTR ,External event 1 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 0. " EE1LTCH ,External event 1 latch" "Ignored,Latched"
|
|
line.long 0x18 "EEFAR2,Timer A External Event Filtering Register 2"
|
|
bitfld.long 0x18 25.--28. " EE10FLTR ,External event 10 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 24. " EE10LTCH ,External event 10 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 19.--22. " EE9FLTR ,External event 9 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 18. " EE9LTCH ,External event 9 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 13.--16. " EE8FLTR ,External event 8 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 12. " EE8LTCH ,External event 8 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 7.--10. " EE7FLTR ,External event 7 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 6. " EE7LTCH ,External event 7 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 1.--4. " EE6FLTR ,External event 6 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 0. " EE6LTCH ,External event 6 latch" "Ignored,Latched"
|
|
textline " "
|
|
line.long 0x1C "RSTAR,Timer A Reset Register"
|
|
bitfld.long 0x1C 30. " TIMECMP4 ,Timer E compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 29. " TIMECMP2 ,Timer E compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 28. " TIMECMP1 ,Timer E compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " TIMDCMP4 ,Timer D compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 26. " TIMDCMP2 ,Timer D compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 25. " TIMDCMP1 ,Timer D compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " TIMCCMP4 ,Timer C compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 23. " TIMCCMP2 ,Timer C compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 22. " TIMCCMP1 ,Timer C compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 21. " TIMBCMP4 ,Timer B compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 20. " TIMBCMP2 ,Timer B compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 19. " TIMBCMP1 ,Timer B compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 18. " EXTEVNT10 ,External event 10" "No reset,Reset"
|
|
bitfld.long 0x1C 17. " EXTEVNT9 ,External event 9" "No reset,Reset"
|
|
bitfld.long 0x1C 16. " EXTEVNT8 ,External event 8" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " EXTEVNT7 ,External event 7" "No reset,Reset"
|
|
bitfld.long 0x1C 14. " EXTEVNT6 ,External event 6" "No reset,Reset"
|
|
bitfld.long 0x1C 13. " EXTEVNT5 ,External event 5" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " EXTEVNT4 ,External event 4" "No reset,Reset"
|
|
bitfld.long 0x1C 11. " EXTEVNT3 ,External event 3" "No reset,Reset"
|
|
bitfld.long 0x1C 10. " EXTEVNT2 ,External event 2" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " EXTEVNT1 ,External event 1" "No reset,Reset"
|
|
bitfld.long 0x1C 8. " MSTCMP4 ,Master compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 7. " MSTCMP3 ,Master compare 3" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " MSTCMP2 ,Master compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 5. " MSTCMP1 ,Master compare 1" "No reset,Reset"
|
|
bitfld.long 0x1C 4. " MSTPER ,Master timer Period" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " CMP4 ,Timer A compare 4 reset" "No reset,Reset"
|
|
bitfld.long 0x1C 2. " CMP2 ,Timer A compare 2 reset" "No reset,Reset"
|
|
bitfld.long 0x1C 1. " UPDT ,Timer A update reset" "No reset,Reset"
|
|
line.long 0x20 "CHPAR,Timer A Chopper Register"
|
|
bitfld.long 0x20 7.--10. " STRTPW ,Timer A start pulsewidth" "40ns,80ns,120ns,160ns,200ns,240ns,280ns,320ns,360ns,400ns,440ns,480ns,520ns,560ns,600ns,640ns"
|
|
bitfld.long 0x20 4.--6. " CHPDTY ,Timer A chopper duty cycle value" "0/8,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
bitfld.long 0x20 0.--3. " CHPFRQ ,Timer A carrier frequency value" "fHRTIM/16,fHRTIM/32,fHRTIM/48,fHRTIM/64,fHRTIM/80,fHRTIM/96,fHRTIM/112,fHRTIM/128,fHRTIM/144,fHRTIM/160,fHRTIM/176,fHRTIM/192,fHRTIM/208,fHRTIM/224,fHRTIM/240,fHRTIM/256"
|
|
line.long 0x24 "CPT1ACR,Timer A Capture 2 Control Register"
|
|
bitfld.long 0x24 31. " TECMP2 ,Timer E compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 30. " TECMP1 ,Timer E compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 29. " TE1RST ,Timer E output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 28. " TE1SET ,Timer E output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 27. " TDCMP2 ,Timer D compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 26. " TDCMP1 ,Timer D compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 25. " TD1RST ,Timer D output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 24. " TD1SET ,Timer D output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 23. " TCCMP2 ,Timer C compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 22. " TCCMP1 ,Timer C compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 21. " TC1RST ,Timer C output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 20. " TC1SET ,Timer C output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 19. " TBCMP2 ,Timer B compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 18. " TBCMP1 ,Timer B compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 17. " TB1RST ,Timer B output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 16. " TB1SET ,Timer B output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 11. " EXEV10CPT ,External event 10 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 10. " EXEV9CPT ,External event 9 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 9. " EXEV8CPT ,External event 8 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 8. " EXEV7CPT ,External event 7 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 7. " EXEV6CPT ,External event 6 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 6. " EXEV5CPT ,External event 5 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 5. " EXEV4CPT ,External event 4 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 4. " EXEV3CPT ,External event 3 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 3. " EXEV2CPT ,External event 2 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 2. " EXEV1CPT ,External event 1 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 1. " UDPCPT ,Update capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 0. " SWCPT ,Software capture" "Not forced,Forced"
|
|
line.long 0x28 "CPT2ACR,HRTIM Timer A Capture 2 Control Register"
|
|
bitfld.long 0x28 31. " TECMP2 ,Timer E compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 30. " TECMP1 ,Timer E compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 29. " TE1RST ,Timer E output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 28. " TE1SET ,Timer E output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 27. " TDCMP2 ,Timer D compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 26. " TDCMP1 ,Timer D compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 25. " TD1RST ,Timer D output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 24. " TD1SET ,Timer D output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 23. " TCCMP2 ,Timer C compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 22. " TCCMP1 ,Timer C compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 21. " TC1RST ,Timer C output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 20. " TC1SET ,Timer C output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 19. " TBCMP2 ,Timer B compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 18. " TBCMP1 ,Timer B compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 17. " TB1RST ,Timer B output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 16. " TB1SET ,Timer B output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 11. " EXEV10CPT ,External event 10 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 10. " EXEV9CPT ,External event 9 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 9. " EXEV8CPT ,External event 8 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 8. " EXEV7CPT ,External event 7 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 7. " EXEV6CPT ,External event 6 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 6. " EXEV5CPT ,External event 5 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 5. " EXEV4CPT ,External event 4 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 4. " EXEV3CPT ,External event 3 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 3. " EXEV2CPT ,External event 2 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 2. " EXEV1CPT ,External event 1 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 1. " UDPCPT ,Update capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 0. " SWCPT ,Software capture" "Not forced,Forced"
|
|
textline " "
|
|
if (((per.l(ad:0x40017400)&0x20000)==0x20000))
|
|
if (((per.l(ad:0x40017400+0x80+0x64)&0x200)==0x200))
|
|
group.long (0x80+0x64)++0x3
|
|
line.long 0x00 "OUTAR,Timer A Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
rbitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 6,Output 2 delayed Idle on external event 6,Output 1 and output 2 delayed Idle on external event 6,Balanced Idle on external event 6,Output 1 delayed Idle on external event 7,Output 2 delayed Idle on external event 7,Output 1 and output 2 delayed Idle on external event 7,Balanced Idle on external event 7"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
else
|
|
group.long (0x80+0x64)++0x3
|
|
line.long 0x00 "OUTAR,Timer A Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 6,Output 2 delayed Idle on external event 6,Output 1 and output 2 delayed Idle on external event 6,Balanced Idle on external event 6,Output 1 delayed Idle on external event 7,Output 2 delayed Idle on external event 7,Output 1 and output 2 delayed Idle on external event 7,Balanced Idle on external event 7"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0x80+0x64)&0x200)==0x200))
|
|
group.long (0x80+0x64)++0x3
|
|
line.long 0x00 "OUTAR,Timer A Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
rbitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 6,Output 2 delayed Idle on external event 6,Output 1 and output 2 delayed Idle on external event 6,Balanced Idle on external event 6,Output 1 delayed Idle on external event 7,Output 2 delayed Idle on external event 7,Output 1 and output 2 delayed Idle on external event 7,Balanced Idle on external event 7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
else
|
|
group.long (0x80+0x64)++0x3
|
|
line.long 0x00 "OUTAR,Timer A Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 6,Output 2 delayed Idle on external event 6,Output 1 and output 2 delayed Idle on external event 6,Balanced Idle on external event 6,Output 1 delayed Idle on external event 7,Output 2 delayed Idle on external event 7,Output 1 and output 2 delayed Idle on external event 7,Balanced Idle on external event 7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
endif
|
|
endif
|
|
textline " "
|
|
group.long (0x80+0x68)++0x3
|
|
line.long 0x00 "FLTAR,Timer A Fault Register"
|
|
bitfld.long 0x00 31. " FLTLCK ,Fault sources lock" "FLT1EN..FLT5EN read/write,FLT1EN..FLT5EN read only"
|
|
bitfld.long 0x00 4. " FLT5EN ,Fault 5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FLT4EN ,Fault 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FLT3EN ,Fault 3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT2EN ,Fault 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FLT1EN ,Fault 1 enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TIMB"
|
|
if (((per.l(ad:0x40017400)&0x40000)==0x40000))
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "TIMBCR,Timer B Control Register"
|
|
bitfld.long 0x00 28.--31. " UPDGAT ,Update gating" "Independently from the DMA burst transfer,When the DMA burst transfer is completed,On the update event following the DMA burst transfer completion,On a rising edge of HRTIM update enable input 1,On a rising edge of HRTIM update enable input 2,On a rising edge of HRTIM update enable input 3,On the update event following a rising edge of HRTIM update enable input 1,On the update event following a rising edge of HRTIM update enable input 2,On the update event following a rising edge of HRTIM update enable input 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MSTU ,Master timer update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TEU ,Timer E update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TDU ,Timer D update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TCU ,Timer C update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TAU ,Timer A update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TBRSTU ,Timer B reset update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TBREPU ,Timer B repetition update" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 14.--15. " DELCMP4 ,Delayed CMP4 mode" "Always active,Recomputed && active following capture 2 event,Recomputed && active following (capture 2||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DELCMP2 ,Delayed CMP2 mode" "Always active,Recomputed && active following capture 1 event,Recomputed && active following (capture 1||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " SYNCSTRTB ,Synchronization starts timer B" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTB ,Synchronization resets timer B" "No effect,Reset"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " PSHPLL ,Push-Pull mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RETRIG ,Re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Continuous mode" "Single-shot,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CK_PSCB ,HRTIM timer B clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
else
|
|
group.long 0x100++0x3
|
|
line.long 0x00 "TIMBCR,Timer B Control Register"
|
|
bitfld.long 0x00 28.--31. " UPDGAT ,Update gating" "Independently from the DMA burst transfer,When the DMA burst transfer is completed,On the update event following the DMA burst transfer completion,On a rising edge of HRTIM update enable input 1,On a rising edge of HRTIM update enable input 2,On a rising edge of HRTIM update enable input 3,On the update event following a rising edge of HRTIM update enable input 1,On the update event following a rising edge of HRTIM update enable input 2,On the update event following a rising edge of HRTIM update enable input 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MSTU ,Master timer update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TEU ,Timer E update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TDU ,Timer D update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TCU ,Timer C update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TAU ,Timer A update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TBRSTU ,Timer B reset update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TBREPU ,Timer B repetition update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DELCMP4 ,Delayed CMP4 mode" "Always active,Recomputed && active following capture 2 event,Recomputed && active following (capture 2||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DELCMP2 ,Delayed CMP2 mode" "Always active,Recomputed && active following capture 1 event,Recomputed && active following (capture 1||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNCSTRTB ,Synchronization starts timer B" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTB ,Synchronization resets timer B" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PSHPLL ,Push-Pull mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RETRIG ,Re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Continuous mode" "Single-shot,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CK_PSCB ,HRTIM timer B clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
endif
|
|
textline " "
|
|
rgroup.long (0x100+0x04)++0x3
|
|
line.long 0x00 "TIMBISR,Timer B Interrupt Status Register"
|
|
bitfld.long 0x00 21. " O2CPY ,Output 2 copy" "Inactive,Active"
|
|
bitfld.long 0x00 20. " O1CPY ,Output 1 copy" "Inactive,Active"
|
|
bitfld.long 0x00 19. " O2STAT ,Output 2 state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " O1STAT ,Output 1 state" "Inactive,Active"
|
|
bitfld.long 0x00 17. " IPPSTAT ,Idle push pull status" "Output 1 active/Output 2 inactive,Output 2 active/Output 1 inactive"
|
|
bitfld.long 0x00 16. " CPPSTAT ,Current push pull status" "Output 1 && 2 inactive,Output 2 && 1 inactive"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DLYPRT ,Delayed protection flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RST ,Reset and/or roll-over interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " RSTB2 ,Output 2 reset interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETB2 ,Output 2 set interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " RSTB1 ,Output 1 reset interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " SETx1 ,Output 1 set interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPT2 ,Capture2 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CPT1 ,Capture1 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " UPD ,Update interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REP ,Repetition interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CMP4 ,Compare 4 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CMP3 ,Compare 3 interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMP2 ,Compare 2 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CMP1 ,Compare 1 interrupt flag" "Not occurred,Occurred"
|
|
wgroup.long (0x100+0x08)++0x3
|
|
line.long 0x00 "TIMBICR,Timer B Interrupt Clear Register"
|
|
bitfld.long 0x00 14. " DLYPRTC ,Delayed protection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " RSTC ,Reset interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " RSTB2C ,Output 2 reset flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET2BC ,Output 2 set flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RSTB1C ,Output 1 reset flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " SET1BC ,Output 1 set flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPT2C ,Capture2 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " CPT1C ,Capture1 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " UPDC ,Update interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REPC ,Repetition interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CMP4C ,Compare 4 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CMP3C ,Compare 3 interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMP2C ,Compare 2 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CMP1C ,Compare 1 interrupt flag clear" "No effect,Clear"
|
|
group.long (0x100+0xC)++0x23
|
|
line.long 0x00 "TIMBDIER,HRTIM Timer B DMA / Interrupt Enable Register"
|
|
bitfld.long 0x00 30. " DLYPRTDE ,Delayed protection DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RSTDE ,Reset/roll-over DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " RSTB2DE ,Output 2 reset DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SETB2DE ,Output 2 set DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RSTB1DE ,Output 1 reset DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SET1BDE ,Output 1 set DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " CPT2DE ,Capture 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CPT1DE ,Capture 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " UPDDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " REPDE ,Repetition DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMP4DE ,Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CMP3DE ,Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMP2DE ,Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CMP1DE ,Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DLYPRTIE ,Delayed protection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIE ,Reset/roll-over interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RSTB2IE ,Output 2 reset interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETB2IE ,Output 2 set interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RSTB1IE ,Output 1 reset interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SET1BIE ,Output 1 set interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CPT2IE ,Capture interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CPT1IE ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " UPDIE ,Update interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " REPIE ,Repetition interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CMP4IE ,Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CMP3IE ,Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CMP2IE ,Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP1IE ,Compare 1 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNTBR,Timer B Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CNTB ,Timer B counter value"
|
|
line.long 0x08 "PERBR,Timer B Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERB ,Timer B period value"
|
|
line.long 0x0C "REPBR,Timer B Repetition Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " REPB ,Timer B repetition counter value"
|
|
line.long 0x10 "CMP1BR,Timer B Compare 1 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " CMP1B ,Timer B compare 1 value"
|
|
line.long 0x14 "CMP1CBR,Timer B Compare 1 Compound_ Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. " REPB ,Timer B repetition value"
|
|
hexmask.long.word 0x14 0.--15. 1. " CMP1B ,Timer B compare 1 value"
|
|
line.long 0x18 "CMP2BR,Timer B Compare 2 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " CMP2B ,Timer B compare 2 value"
|
|
line.long 0x1C "CMP3BR,Timer B Compare 3 Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " CMP3B ,Timer B compare 3 value"
|
|
line.long 0x20 "CMP4BR,Timer B Compare 4 Register"
|
|
hexmask.long.word 0x20 0.--15. 1. " CMP4B ,Timer B compare 4 value"
|
|
rgroup.long (0x100+0x30)++0x7
|
|
line.long 0x00 "CPT1BR,Timer B Capture 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPT1B ,Timer B capture 1 value"
|
|
line.long 0x04 "CPT2BR,Timer B Capture 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CPT2B ,Timer B capture 2 value"
|
|
group.long (0x100+0x38)++0x2B
|
|
line.long 0x00 "DTBR,Timer B Deadtime Register"
|
|
bitfld.long 0x00 31. " DTFLKB ,Deadtime falling lock" "Writable,Read-only"
|
|
bitfld.long 0x00 30. " DTFSLKB ,Deadtime falling sign lock" "Writable,Read-only"
|
|
bitfld.long 0x00 25. " SDTFB ,Sign deadtime falling value" "Positive,Negative"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--24. 1. " DTFB ,Deadtime falling value"
|
|
bitfld.long 0x00 15. " DTRLKB ,Deadtime rising lock" "Writable,Read-only"
|
|
bitfld.long 0x00 14. " DTRSLKB ,Deadtime rising sign lock" "Writable,Read-only"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DTPRSC ,Deadtime prescaler" ",,,tHRTIM,tHRTIM*2,tHRTIM*4,tHRTIM*8,tHRTIM*16"
|
|
bitfld.long 0x00 9. " SDTRB ,Sign deadtime rising value" "Positive,Negative"
|
|
hexmask.long.word 0x00 0.--8. 1. " DTRB ,Deadtime rising value"
|
|
line.long 0x04 "SETB1R,Timer B Output1 Set Register"
|
|
bitfld.long 0x04 31. " UPDATE ,Registers update active state" "Not forced,Forced"
|
|
bitfld.long 0x04 30. " EXTEVNT10 ,External event 10 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 29. " EXTEVNT9 ,External event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 28. " EXTEVNT8 ,External event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 27. " EXTEVNT7 ,External event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 26. " EXTEVNT6 ,External event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 25. " EXTEVNT5 ,External event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 24. " EXTEVNT4 ,External event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 23. " EXTEVNT3 ,External event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 22. " EXTEVNT2 ,External event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 21. " EXTEVNT1 ,External event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 20. " TIMEVNT9 ,Timer event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 19. " TIMEVNT8 ,Timer event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 18. " TIMEVNT7 ,Timer event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 17. " TIMEVNT6 ,Timer event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 16. " TIMEVNT5 ,Timer event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 15. " TIMEVNT4 ,Timer event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 14. " TIMEVNT3 ,Timer event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TIMEVNT2 ,Timer event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 12. " TIMEVNT1 ,Timer event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 11. " MSTCMP4 ,Master compare 4 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MSTCMP3 ,Master compare 3 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 9. " MSTCMP2 ,Master compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 8. " MSTCMP1 ,Master compare 1 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSTPER ,Master period active state" "Not forced,Forced"
|
|
bitfld.long 0x04 6. " CMP4 ,Timer B compare 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 5. " CMP3 ,Timer B compare 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CMP2 ,Timer B compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 3. " CMP1 ,Timer B compare 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 2. " PER ,Timer B period active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RESYNC ,Timer B resynchronization active state" "Not forced,Forced"
|
|
bitfld.long 0x04 0. " SST ,Software set trigger active state" "Not forced,Forced"
|
|
line.long 0x08 "RSTB1R,Timer B Output1 Reset Register"
|
|
bitfld.long 0x08 31. " UPDATE ,Registers update inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 30. " EXTEVNT10 ,External event 10 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 29. " EXTEVNT9 ,External event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 28. " EXTEVNT8 ,External event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 27. " EXTEVNT7 ,External event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 26. " EXTEVNT6 ,External event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 25. " EXTEVNT5 ,External event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 24. " EXTEVNT4 ,External event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 23. " EXTEVNT3 ,External event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 22. " EXTEVNT2 ,External event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 21. " EXTEVNT1 ,External event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 20. " TIMEVNT9 ,Timer event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TIMEVNT8 ,Timer event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 18. " TIMEVNT7 ,Timer event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 17. " TIMEVNT6 ,Timer event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 16. " TIMEVNT5 ,Timer event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 15. " TIMEVNT4 ,Timer event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 14. " TIMEVNT3 ,Timer event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 13. " TIMEVNT2 ,Timer event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 12. " TIMEVNT1 ,Timer event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 11. " MSTCMP4 ,Master compare 4 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 10. " MSTCMP3 ,Master compare 3 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 9. " MSTCMP2 ,Master compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 8. " MSTCMP1 ,Master compare 1 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSTPER ,Master period inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 6. " CMP4 ,Timer B compare 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 5. " CMP3 ,Timer B compare 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CMP2 ,Timer B compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 3. " CMP1 ,Timer B compare 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 2. " PER ,Timer B period inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RESYNC ,Timer B resynchronizaton inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 0. " SRT ,Software set trigger inactive state" "Not forced,Forced"
|
|
line.long 0x0C "SETB2R,Timer B Output2 Set Register"
|
|
bitfld.long 0x0C 31. " UPDATE ,Registers update active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 30. " EXTEVNT10 ,External event 10 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 29. " EXTEVNT9 ,External event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " EXTEVNT8 ,External event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 27. " EXTEVNT7 ,External event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 26. " EXTEVNT6 ,External event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " EXTEVNT5 ,External event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 24. " EXTEVNT4 ,External event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 23. " EXTEVNT3 ,External event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " EXTEVNT2 ,External event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 21. " EXTEVNT1 ,External event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 20. " TIMEVNT9 ,Timer event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " TIMEVNT8 ,Timer event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 18. " TIMEVNT7 ,Timer event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 17. " TIMEVNT6 ,Timer event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " TIMEVNT5 ,Timer event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 15. " TIMEVNT4 ,Timer event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 14. " TIMEVNT3 ,Timer event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " TIMEVNT2 ,Timer event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 12. " TIMEVNT1 ,Timer event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 11. " MSTCMP4 ,Master compare 4 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " MSTCMP3 ,Master compare 3 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 9. " MSTCMP2 ,Master compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 8. " MSTCMP1 ,Master compare 1 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " MSTPER ,Master period active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 6. " CMP4 ,Timer B compare 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 5. " CMP3 ,Timer B compare 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMP2 ,Timer B compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 3. " CMP1 ,Timer B compare 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 2. " PER ,Timer B period active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " RESYNC ,Timer B resynchronizaton active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 0. " SST ,Software set trigger active state" "Not forced,Forced"
|
|
line.long 0x10 "RSTB2R,Timer B Output2 Reset Register"
|
|
bitfld.long 0x10 31. " UPDATE ,Registers update inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 30. " EXTEVNT10 ,External event 10 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 29. " EXTEVNT9 ,External event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 28. " EXTEVNT8 ,External event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 27. " EXTEVNT7 ,External event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 26. " EXTEVNT6 ,External event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EXTEVNT5 ,External event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 24. " EXTEVNT4 ,External event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 23. " EXTEVNT3 ,External event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 22. " EXTEVNT2 ,External event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 21. " EXTEVNT1 ,External event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 20. " TIMEVNT9 ,Timer event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 19. " TIMEVNT8 ,Timer event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 18. " TIMEVNT7 ,Timer event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 17. " TIMEVNT6 ,Timer event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 16. " TIMEVNT5 ,Timer event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 15. " TIMEVNT4 ,Timer event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 14. " TIMEVNT3 ,Timer event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 13. " TIMEVNT2 ,Timer event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 12. " TIMEVNT1 ,Timer event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 11. " MSTCMP4 ,Master compare 4 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 10. " MSTCMP3 ,Master compare 3 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 9. " MSTCMP2 ,Master compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 8. " MSTCMP1 ,Master compare 1 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 7. " MSTPER ,Master period inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 6. " CMP4 ,Timer B compare 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 5. " CMP3 ,Timer B compare 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 4. " CMP2 ,Timer B compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 3. " CMP1 ,Timer B compare 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 2. " PER ,Timer B period inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 1. " RESYNC ,Timer B resynchronizaton inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 0. " SRT ,Software set trigger inactive state" "Not forced,Forced"
|
|
textline " "
|
|
line.long 0x14 "EEFBR1,Timer B External Event Filtering Register 1"
|
|
bitfld.long 0x14 25.--28. " EE5FLTR ,External event 5 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 24. " EE5LTCH ,External event 5 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 19.--22. " EE4FLTR ,External event 4 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 18. " EE4LTCH ,External event 4 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 13.--16. " EE3FLTR ,External event 3 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 12. " EE3LTCH ,External event 3 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 7.--10. " EE2FLTR ,External event 2 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 6. " EE2LTCH ,External event 2 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 1.--4. " EE1FLTR ,External event 1 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 0. " EE1LTCH ,External event 1 latch" "Ignored,Latched"
|
|
line.long 0x18 "EEFBR2,Timer B External Event Filtering Register 2"
|
|
bitfld.long 0x18 25.--28. " EE10FLTR ,External event 10 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 24. " EE10LTCH ,External event 10 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 19.--22. " EE9FLTR ,External event 9 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 18. " EE9LTCH ,External event 9 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 13.--16. " EE8FLTR ,External event 8 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 12. " EE8LTCH ,External event 8 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 7.--10. " EE7FLTR ,External event 7 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 6. " EE7LTCH ,External event 7 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 1.--4. " EE6FLTR ,External event 6 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 0. " EE6LTCH ,External event 6 latch" "Ignored,Latched"
|
|
textline " "
|
|
line.long 0x1C "RSTBR,Timer B Reset Register"
|
|
bitfld.long 0x1C 30. " TIMECMP4 ,Timer E compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 29. " TIMECMP2 ,Timer E compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 28. " TIMECMP1 ,Timer E compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " TIMDCMP4 ,Timer D compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 26. " TIMDCMP2 ,Timer D compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 25. " TIMDCMP1 ,Timer D compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " TIMCCMP4 ,Timer C compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 23. " TIMCCMP2 ,Timer C compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 22. " TIMCCMP1 ,Timer C compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 21. " TIMACMP4 ,Timer A compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 20. " TIMACMP2 ,Timer A compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 19. " TIMACMP1 ,Timer A compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 18. " EXTEVNT10 ,External event 10" "No reset,Reset"
|
|
bitfld.long 0x1C 17. " EXTEVNT9 ,External event 9" "No reset,Reset"
|
|
bitfld.long 0x1C 16. " EXTEVNT8 ,External event 8" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " EXTEVNT7 ,External event 7" "No reset,Reset"
|
|
bitfld.long 0x1C 14. " EXTEVNT6 ,External event 6" "No reset,Reset"
|
|
bitfld.long 0x1C 13. " EXTEVNT5 ,External event 5" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " EXTEVNT4 ,External event 4" "No reset,Reset"
|
|
bitfld.long 0x1C 11. " EXTEVNT3 ,External event 3" "No reset,Reset"
|
|
bitfld.long 0x1C 10. " EXTEVNT2 ,External event 2" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " EXTEVNT1 ,External event 1" "No reset,Reset"
|
|
bitfld.long 0x1C 8. " MSTCMP4 ,Master compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 7. " MSTCMP3 ,Master compare 3" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " MSTCMP2 ,Master compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 5. " MSTCMP1 ,Master compare 1" "No reset,Reset"
|
|
bitfld.long 0x1C 4. " MSTPER ,Master timer Period" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " CMP4 ,Timer A compare 4 reset" "No reset,Reset"
|
|
bitfld.long 0x1C 2. " CMP2 ,Timer A compare 2 reset" "No reset,Reset"
|
|
bitfld.long 0x1C 1. " UPDT ,Timer A update reset" "No reset,Reset"
|
|
line.long 0x20 "CHPBR,Timer B Chopper Register"
|
|
bitfld.long 0x20 7.--10. " STRTPW ,Timer B start pulsewidth" "40ns,80ns,120ns,160ns,200ns,240ns,280ns,320ns,360ns,400ns,440ns,480ns,520ns,560ns,600ns,640ns"
|
|
bitfld.long 0x20 4.--6. " CHPDTY ,Timer B chopper duty cycle value" "0/8,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
bitfld.long 0x20 0.--3. " CHPFRQ ,Timer B carrier frequency value" "fHRTIM/16,fHRTIM/32,fHRTIM/48,fHRTIM/64,fHRTIM/80,fHRTIM/96,fHRTIM/112,fHRTIM/128,fHRTIM/144,fHRTIM/160,fHRTIM/176,fHRTIM/192,fHRTIM/208,fHRTIM/224,fHRTIM/240,fHRTIM/256"
|
|
line.long 0x24 "CPT1BCR,Timer B Capture 2 Control Register"
|
|
bitfld.long 0x24 31. " TECMP2 ,Timer E compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 30. " TECMP1 ,Timer E compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 29. " TE1RST ,Timer E output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 28. " TE1SET ,Timer E output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 27. " TDCMP2 ,Timer D compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 26. " TDCMP1 ,Timer D compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 25. " TD1RST ,Timer D output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 24. " TD1SET ,Timer D output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 23. " TCCMP2 ,Timer C compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 22. " TCCMP1 ,Timer C compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 21. " TC1RST ,Timer C output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 20. " TC1SET ,Timer C output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 15. " TACMP2 ,Timer A compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 14. " TACMP1 ,Timer A compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 13. " TA1RST ,Timer A output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 12. " TA1SET ,Timer A output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 11. " EXEV10CPT ,External event 10 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 10. " EXEV9CPT ,External event 9 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 9. " EXEV8CPT ,External event 8 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 8. " EXEV7CPT ,External event 7 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 7. " EXEV6CPT ,External event 6 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 6. " EXEV5CPT ,External event 5 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 5. " EXEV4CPT ,External event 4 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 4. " EXEV3CPT ,External event 3 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 3. " EXEV2CPT ,External event 2 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 2. " EXEV1CPT ,External event 1 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 1. " UDPCPT ,Update capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 0. " SWCPT ,Software capture" "Not forced,Forced"
|
|
line.long 0x28 "CPT2BCR,HRTIM Timer B Capture 2 Control Register"
|
|
bitfld.long 0x28 31. " TECMP2 ,Timer E compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 30. " TECMP1 ,Timer E compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 29. " TE1RST ,Timer E output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 28. " TE1SET ,Timer E output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 27. " TDCMP2 ,Timer D compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 26. " TDCMP1 ,Timer D compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 25. " TD1RST ,Timer D output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 24. " TD1SET ,Timer D output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 23. " TCCMP2 ,Timer C compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 22. " TCCMP1 ,Timer C compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 21. " TC1RST ,Timer C output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 20. " TC1SET ,Timer C output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 15. " TACMP2 ,Timer A compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 14. " TACMP1 ,Timer A compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 13. " TA1RST ,Timer A output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 12. " TA1SET ,Timer A output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 11. " EXEV10CPT ,External event 10 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 10. " EXEV9CPT ,External event 9 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 9. " EXEV8CPT ,External event 8 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 8. " EXEV7CPT ,External event 7 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 7. " EXEV6CPT ,External event 6 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 6. " EXEV5CPT ,External event 5 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 5. " EXEV4CPT ,External event 4 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 4. " EXEV3CPT ,External event 3 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 3. " EXEV2CPT ,External event 2 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 2. " EXEV1CPT ,External event 1 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 1. " UDPCPT ,Update capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 0. " SWCPT ,Software capture" "Not forced,Forced"
|
|
textline " "
|
|
if (((per.l(ad:0x40017400)&0x40000)==0x40000))
|
|
if (((per.l(ad:0x40017400+0x100+0x64)&0x200)==0x200))
|
|
group.long (0x100+0x64)++0x3
|
|
line.long 0x00 "OUTBR,Timer B Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
rbitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 6,Output 2 delayed Idle on external event 6,Output 1 and output 2 delayed Idle on external event 6,Balanced Idle on external event 6,Output 1 delayed Idle on external event 7,Output 2 delayed Idle on external event 7,Output 1 and output 2 delayed Idle on external event 7,Balanced Idle on external event 7"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
else
|
|
group.long (0x100+0x64)++0x3
|
|
line.long 0x00 "OUTBR,Timer B Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 6,Output 2 delayed Idle on external event 6,Output 1 and output 2 delayed Idle on external event 6,Balanced Idle on external event 6,Output 1 delayed Idle on external event 7,Output 2 delayed Idle on external event 7,Output 1 and output 2 delayed Idle on external event 7,Balanced Idle on external event 7"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0x100+0x64)&0x200)==0x200))
|
|
group.long (0x100+0x64)++0x3
|
|
line.long 0x00 "OUTBR,Timer B Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
rbitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 6,Output 2 delayed Idle on external event 6,Output 1 and output 2 delayed Idle on external event 6,Balanced Idle on external event 6,Output 1 delayed Idle on external event 7,Output 2 delayed Idle on external event 7,Output 1 and output 2 delayed Idle on external event 7,Balanced Idle on external event 7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
else
|
|
group.long (0x100+0x64)++0x3
|
|
line.long 0x00 "OUTBR,Timer B Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 6,Output 2 delayed Idle on external event 6,Output 1 and output 2 delayed Idle on external event 6,Balanced Idle on external event 6,Output 1 delayed Idle on external event 7,Output 2 delayed Idle on external event 7,Output 1 and output 2 delayed Idle on external event 7,Balanced Idle on external event 7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
endif
|
|
endif
|
|
textline " "
|
|
group.long (0x100+0x68)++0x3
|
|
line.long 0x00 "FLTBR,Timer B Fault Register"
|
|
bitfld.long 0x00 31. " FLTLCK ,Fault sources lock" "FLT1EN..FLT5EN read/write,FLT1EN..FLT5EN read only"
|
|
bitfld.long 0x00 4. " FLT5EN ,Fault 5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FLT4EN ,Fault 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FLT3EN ,Fault 3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT2EN ,Fault 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FLT1EN ,Fault 1 enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TIMC"
|
|
if (((per.l(ad:0x40017400)&0x80000)==0x80000))
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "TIMCCR,Timer C Control Register"
|
|
bitfld.long 0x00 28.--31. " UPDGAT ,Update gating" "Independently from the DMA burst transfer,When the DMA burst transfer is completed,On the update event following the DMA burst transfer completion,On a rising edge of HRTIM update enable input 1,On a rising edge of HRTIM update enable input 2,On a rising edge of HRTIM update enable input 3,On the update event following a rising edge of HRTIM update enable input 1,On the update event following a rising edge of HRTIM update enable input 2,On the update event following a rising edge of HRTIM update enable input 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MSTU ,Master timer update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TEU ,Timer E update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TDU ,Timer D update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TBU ,Timer B update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TAU ,Timer A update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TCRSTU ,Timer C reset update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TCREPU ,Timer C repetition update" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 14.--15. " DELCMP4 ,Delayed CMP4 mode" "Always active,Recomputed && active following capture 2 event,Recomputed && active following (capture 2||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DELCMP2 ,Delayed CMP2 mode" "Always active,Recomputed && active following capture 1 event,Recomputed && active following (capture 1||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " SYNCSTRTC ,Synchronization starts timer C" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTC ,Synchronization resets timer C" "No effect,Reset"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " PSHPLL ,Push-Pull mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RETRIG ,Re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Continuous mode" "Single-shot,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CK_PSCC ,HRTIM timer C clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
else
|
|
group.long 0x180++0x3
|
|
line.long 0x00 "TIMCCR,Timer C Control Register"
|
|
bitfld.long 0x00 28.--31. " UPDGAT ,Update gating" "Independently from the DMA burst transfer,When the DMA burst transfer is completed,On the update event following the DMA burst transfer completion,On a rising edge of HRTIM update enable input 1,On a rising edge of HRTIM update enable input 2,On a rising edge of HRTIM update enable input 3,On the update event following a rising edge of HRTIM update enable input 1,On the update event following a rising edge of HRTIM update enable input 2,On the update event following a rising edge of HRTIM update enable input 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MSTU ,Master timer update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TEU ,Timer E update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TDU ,Timer D update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TBU ,Timer B update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TAU ,Timer A update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TCRSTU ,Timer C reset update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TCREPU ,Timer C repetition update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DELCMP4 ,Delayed CMP4 mode" "Always active,Recomputed && active following capture 2 event,Recomputed && active following (capture 2||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DELCMP2 ,Delayed CMP2 mode" "Always active,Recomputed && active following capture 1 event,Recomputed && active following (capture 1||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNCSTRTC ,Synchronization starts timer C" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTC ,Synchronization resets timer C" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PSHPLL ,Push-Pull mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RETRIG ,Re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Continuous mode" "Single-shot,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CK_PSCC ,HRTIM timer C clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
endif
|
|
textline " "
|
|
rgroup.long (0x180+0x04)++0x3
|
|
line.long 0x00 "TIMCISR,Timer C Interrupt Status Register"
|
|
bitfld.long 0x00 21. " O2CPY ,Output 2 copy" "Inactive,Active"
|
|
bitfld.long 0x00 20. " O1CPY ,Output 1 copy" "Inactive,Active"
|
|
bitfld.long 0x00 19. " O2STAT ,Output 2 state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " O1STAT ,Output 1 state" "Inactive,Active"
|
|
bitfld.long 0x00 17. " IPPSTAT ,Idle push pull status" "Output 1 active/Output 2 inactive,Output 2 active/Output 1 inactive"
|
|
bitfld.long 0x00 16. " CPPSTAT ,Current push pull status" "Output 1 && 2 inactive,Output 2 && 1 inactive"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DLYPRT ,Delayed protection flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RST ,Reset and/or roll-over interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " RSTC2 ,Output 2 reset interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETC2 ,Output 2 set interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " RSTC1 ,Output 1 reset interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " SETx1 ,Output 1 set interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPT2 ,Capture2 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CPT1 ,Capture1 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " UPD ,Update interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REP ,Repetition interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CMP4 ,Compare 4 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CMP3 ,Compare 3 interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMP2 ,Compare 2 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CMP1 ,Compare 1 interrupt flag" "Not occurred,Occurred"
|
|
wgroup.long (0x180+0x08)++0x3
|
|
line.long 0x00 "TIMCICR,Timer C Interrupt Clear Register"
|
|
bitfld.long 0x00 14. " DLYPRTC ,Delayed protection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " RSTC ,Reset interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " RSTC2C ,Output 2 reset flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET2CC ,Output 2 set flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RSTC1C ,Output 1 reset flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " SET1CC ,Output 1 set flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPT2C ,Capture2 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " CPT1C ,Capture1 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " UPDC ,Update interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REPC ,Repetition interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CMP4C ,Compare 4 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CMP3C ,Compare 3 interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMP2C ,Compare 2 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CMP1C ,Compare 1 interrupt flag clear" "No effect,Clear"
|
|
group.long (0x180+0xC)++0x23
|
|
line.long 0x00 "TIMCDIER,HRTIM Timer C DMA / Interrupt Enable Register"
|
|
bitfld.long 0x00 30. " DLYPRTDE ,Delayed protection DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RSTDE ,Reset/roll-over DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " RSTC2DE ,Output 2 reset DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SETC2DE ,Output 2 set DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RSTC1DE ,Output 1 reset DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SET1CDE ,Output 1 set DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " CPT2DE ,Capture 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CPT1DE ,Capture 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " UPDDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " REPDE ,Repetition DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMP4DE ,Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CMP3DE ,Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMP2DE ,Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CMP1DE ,Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DLYPRTIE ,Delayed protection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIE ,Reset/roll-over interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RSTC2IE ,Output 2 reset interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETC2IE ,Output 2 set interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RSTC1IE ,Output 1 reset interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SET1CIE ,Output 1 set interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CPT2IE ,Capture interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CPT1IE ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " UPDIE ,Update interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " REPIE ,Repetition interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CMP4IE ,Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CMP3IE ,Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CMP2IE ,Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP1IE ,Compare 1 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNTCR,Timer C Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CNTC ,Timer C counter value"
|
|
line.long 0x08 "PERCR,Timer C Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERC ,Timer C period value"
|
|
line.long 0x0C "REPCR,Timer C Repetition Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " REPC ,Timer C repetition counter value"
|
|
line.long 0x10 "CMP1CR,Timer C Compare 1 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " CMP1C ,Timer C compare 1 value"
|
|
line.long 0x14 "CMP1CCR,Timer C Compare 1 Compound_ Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. " REPC ,Timer C repetition value"
|
|
hexmask.long.word 0x14 0.--15. 1. " CMP1C ,Timer C compare 1 value"
|
|
line.long 0x18 "CMP2CR,Timer C Compare 2 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " CMP2C ,Timer C compare 2 value"
|
|
line.long 0x1C "CMP3CR,Timer C Compare 3 Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " CMP3C ,Timer C compare 3 value"
|
|
line.long 0x20 "CMP4CR,Timer C Compare 4 Register"
|
|
hexmask.long.word 0x20 0.--15. 1. " CMP4C ,Timer C compare 4 value"
|
|
rgroup.long (0x180+0x30)++0x7
|
|
line.long 0x00 "CPT1CR,Timer C Capture 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPT1C ,Timer C capture 1 value"
|
|
line.long 0x04 "CPT2CR,Timer C Capture 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CPT2C ,Timer C capture 2 value"
|
|
group.long (0x180+0x38)++0x2B
|
|
line.long 0x00 "DTCR,Timer C Deadtime Register"
|
|
bitfld.long 0x00 31. " DTFLKC ,Deadtime falling lock" "Writable,Read-only"
|
|
bitfld.long 0x00 30. " DTFSLKC ,Deadtime falling sign lock" "Writable,Read-only"
|
|
bitfld.long 0x00 25. " SDTFC ,Sign deadtime falling value" "Positive,Negative"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--24. 1. " DTFC ,Deadtime falling value"
|
|
bitfld.long 0x00 15. " DTRLKC ,Deadtime rising lock" "Writable,Read-only"
|
|
bitfld.long 0x00 14. " DTRSLKC ,Deadtime rising sign lock" "Writable,Read-only"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DTPRSC ,Deadtime prescaler" ",,,tHRTIM,tHRTIM*2,tHRTIM*4,tHRTIM*8,tHRTIM*16"
|
|
bitfld.long 0x00 9. " SDTRC ,Sign deadtime rising value" "Positive,Negative"
|
|
hexmask.long.word 0x00 0.--8. 1. " DTRC ,Deadtime rising value"
|
|
line.long 0x04 "SETC1R,Timer C Output1 Set Register"
|
|
bitfld.long 0x04 31. " UPDATE ,Registers update active state" "Not forced,Forced"
|
|
bitfld.long 0x04 30. " EXTEVNT10 ,External event 10 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 29. " EXTEVNT9 ,External event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 28. " EXTEVNT8 ,External event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 27. " EXTEVNT7 ,External event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 26. " EXTEVNT6 ,External event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 25. " EXTEVNT5 ,External event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 24. " EXTEVNT4 ,External event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 23. " EXTEVNT3 ,External event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 22. " EXTEVNT2 ,External event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 21. " EXTEVNT1 ,External event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 20. " TIMEVNT9 ,Timer event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 19. " TIMEVNT8 ,Timer event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 18. " TIMEVNT7 ,Timer event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 17. " TIMEVNT6 ,Timer event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 16. " TIMEVNT5 ,Timer event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 15. " TIMEVNT4 ,Timer event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 14. " TIMEVNT3 ,Timer event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TIMEVNT2 ,Timer event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 12. " TIMEVNT1 ,Timer event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 11. " MSTCMP4 ,Master compare 4 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MSTCMP3 ,Master compare 3 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 9. " MSTCMP2 ,Master compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 8. " MSTCMP1 ,Master compare 1 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSTPER ,Master period active state" "Not forced,Forced"
|
|
bitfld.long 0x04 6. " CMP4 ,Timer C compare 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 5. " CMP3 ,Timer C compare 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CMP2 ,Timer C compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 3. " CMP1 ,Timer C compare 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 2. " PER ,Timer C period active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RESYNC ,Timer C resynchronization active state" "Not forced,Forced"
|
|
bitfld.long 0x04 0. " SST ,Software set trigger active state" "Not forced,Forced"
|
|
line.long 0x08 "RSTC1R,Timer C Output1 Reset Register"
|
|
bitfld.long 0x08 31. " UPDATE ,Registers update inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 30. " EXTEVNT10 ,External event 10 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 29. " EXTEVNT9 ,External event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 28. " EXTEVNT8 ,External event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 27. " EXTEVNT7 ,External event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 26. " EXTEVNT6 ,External event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 25. " EXTEVNT5 ,External event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 24. " EXTEVNT4 ,External event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 23. " EXTEVNT3 ,External event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 22. " EXTEVNT2 ,External event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 21. " EXTEVNT1 ,External event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 20. " TIMEVNT9 ,Timer event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TIMEVNT8 ,Timer event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 18. " TIMEVNT7 ,Timer event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 17. " TIMEVNT6 ,Timer event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 16. " TIMEVNT5 ,Timer event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 15. " TIMEVNT4 ,Timer event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 14. " TIMEVNT3 ,Timer event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 13. " TIMEVNT2 ,Timer event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 12. " TIMEVNT1 ,Timer event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 11. " MSTCMP4 ,Master compare 4 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 10. " MSTCMP3 ,Master compare 3 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 9. " MSTCMP2 ,Master compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 8. " MSTCMP1 ,Master compare 1 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSTPER ,Master period inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 6. " CMP4 ,Timer C compare 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 5. " CMP3 ,Timer C compare 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CMP2 ,Timer C compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 3. " CMP1 ,Timer C compare 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 2. " PER ,Timer C period inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RESYNC ,Timer C resynchronizaton inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 0. " SRT ,Software set trigger inactive state" "Not forced,Forced"
|
|
line.long 0x0C "SETC2R,Timer C Output2 Set Register"
|
|
bitfld.long 0x0C 31. " UPDATE ,Registers update active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 30. " EXTEVNT10 ,External event 10 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 29. " EXTEVNT9 ,External event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " EXTEVNT8 ,External event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 27. " EXTEVNT7 ,External event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 26. " EXTEVNT6 ,External event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " EXTEVNT5 ,External event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 24. " EXTEVNT4 ,External event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 23. " EXTEVNT3 ,External event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " EXTEVNT2 ,External event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 21. " EXTEVNT1 ,External event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 20. " TIMEVNT9 ,Timer event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " TIMEVNT8 ,Timer event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 18. " TIMEVNT7 ,Timer event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 17. " TIMEVNT6 ,Timer event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " TIMEVNT5 ,Timer event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 15. " TIMEVNT4 ,Timer event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 14. " TIMEVNT3 ,Timer event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " TIMEVNT2 ,Timer event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 12. " TIMEVNT1 ,Timer event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 11. " MSTCMP4 ,Master compare 4 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " MSTCMP3 ,Master compare 3 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 9. " MSTCMP2 ,Master compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 8. " MSTCMP1 ,Master compare 1 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " MSTPER ,Master period active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 6. " CMP4 ,Timer C compare 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 5. " CMP3 ,Timer C compare 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMP2 ,Timer C compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 3. " CMP1 ,Timer C compare 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 2. " PER ,Timer C period active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " RESYNC ,Timer C resynchronizaton active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 0. " SST ,Software set trigger active state" "Not forced,Forced"
|
|
line.long 0x10 "RSTC2R,Timer C Output2 Reset Register"
|
|
bitfld.long 0x10 31. " UPDATE ,Registers update inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 30. " EXTEVNT10 ,External event 10 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 29. " EXTEVNT9 ,External event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 28. " EXTEVNT8 ,External event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 27. " EXTEVNT7 ,External event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 26. " EXTEVNT6 ,External event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EXTEVNT5 ,External event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 24. " EXTEVNT4 ,External event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 23. " EXTEVNT3 ,External event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 22. " EXTEVNT2 ,External event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 21. " EXTEVNT1 ,External event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 20. " TIMEVNT9 ,Timer event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 19. " TIMEVNT8 ,Timer event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 18. " TIMEVNT7 ,Timer event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 17. " TIMEVNT6 ,Timer event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 16. " TIMEVNT5 ,Timer event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 15. " TIMEVNT4 ,Timer event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 14. " TIMEVNT3 ,Timer event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 13. " TIMEVNT2 ,Timer event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 12. " TIMEVNT1 ,Timer event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 11. " MSTCMP4 ,Master compare 4 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 10. " MSTCMP3 ,Master compare 3 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 9. " MSTCMP2 ,Master compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 8. " MSTCMP1 ,Master compare 1 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 7. " MSTPER ,Master period inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 6. " CMP4 ,Timer C compare 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 5. " CMP3 ,Timer C compare 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 4. " CMP2 ,Timer C compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 3. " CMP1 ,Timer C compare 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 2. " PER ,Timer C period inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 1. " RESYNC ,Timer C resynchronizaton inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 0. " SRT ,Software set trigger inactive state" "Not forced,Forced"
|
|
textline " "
|
|
line.long 0x14 "EEFCR1,Timer C External Event Filtering Register 1"
|
|
bitfld.long 0x14 25.--28. " EE5FLTR ,External event 5 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 24. " EE5LTCH ,External event 5 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 19.--22. " EE4FLTR ,External event 4 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 18. " EE4LTCH ,External event 4 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 13.--16. " EE3FLTR ,External event 3 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 12. " EE3LTCH ,External event 3 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 7.--10. " EE2FLTR ,External event 2 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 6. " EE2LTCH ,External event 2 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 1.--4. " EE1FLTR ,External event 1 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 0. " EE1LTCH ,External event 1 latch" "Ignored,Latched"
|
|
line.long 0x18 "EEFCR2,Timer C External Event Filtering Register 2"
|
|
bitfld.long 0x18 25.--28. " EE10FLTR ,External event 10 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 24. " EE10LTCH ,External event 10 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 19.--22. " EE9FLTR ,External event 9 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 18. " EE9LTCH ,External event 9 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 13.--16. " EE8FLTR ,External event 8 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 12. " EE8LTCH ,External event 8 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 7.--10. " EE7FLTR ,External event 7 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 6. " EE7LTCH ,External event 7 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 1.--4. " EE6FLTR ,External event 6 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 0. " EE6LTCH ,External event 6 latch" "Ignored,Latched"
|
|
textline " "
|
|
line.long 0x1C "RSTCR,Timer C Reset Register"
|
|
bitfld.long 0x1C 30. " TIMECMP4 ,Timer E compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 29. " TIMECMP2 ,Timer E compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 28. " TIMECMP1 ,Timer E compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " TIMDCMP4 ,Timer D compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 26. " TIMDCMP2 ,Timer D compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 25. " TIMDCMP1 ,Timer D compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " TIMBCMP4 ,Timer B compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 23. " TIMBCMP2 ,Timer B compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 22. " TIMBCMP1 ,Timer B compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 21. " TIMACMP4 ,Timer A compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 20. " TIMACMP2 ,Timer A compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 19. " TIMACMP1 ,Timer A compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 18. " EXTEVNT10 ,External event 10" "No reset,Reset"
|
|
bitfld.long 0x1C 17. " EXTEVNT9 ,External event 9" "No reset,Reset"
|
|
bitfld.long 0x1C 16. " EXTEVNT8 ,External event 8" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " EXTEVNT7 ,External event 7" "No reset,Reset"
|
|
bitfld.long 0x1C 14. " EXTEVNT6 ,External event 6" "No reset,Reset"
|
|
bitfld.long 0x1C 13. " EXTEVNT5 ,External event 5" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " EXTEVNT4 ,External event 4" "No reset,Reset"
|
|
bitfld.long 0x1C 11. " EXTEVNT3 ,External event 3" "No reset,Reset"
|
|
bitfld.long 0x1C 10. " EXTEVNT2 ,External event 2" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " EXTEVNT1 ,External event 1" "No reset,Reset"
|
|
bitfld.long 0x1C 8. " MSTCMP4 ,Master compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 7. " MSTCMP3 ,Master compare 3" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " MSTCMP2 ,Master compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 5. " MSTCMP1 ,Master compare 1" "No reset,Reset"
|
|
bitfld.long 0x1C 4. " MSTPER ,Master timer Period" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " CMP4 ,Timer A compare 4 reset" "No reset,Reset"
|
|
bitfld.long 0x1C 2. " CMP2 ,Timer A compare 2 reset" "No reset,Reset"
|
|
bitfld.long 0x1C 1. " UPDT ,Timer A update reset" "No reset,Reset"
|
|
line.long 0x20 "CHPCR,Timer C Chopper Register"
|
|
bitfld.long 0x20 7.--10. " STRTPW ,Timer C start pulsewidth" "40ns,80ns,120ns,160ns,200ns,240ns,280ns,320ns,360ns,400ns,440ns,480ns,520ns,560ns,600ns,640ns"
|
|
bitfld.long 0x20 4.--6. " CHPDTY ,Timer C chopper duty cycle value" "0/8,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
bitfld.long 0x20 0.--3. " CHPFRQ ,Timer C carrier frequency value" "fHRTIM/16,fHRTIM/32,fHRTIM/48,fHRTIM/64,fHRTIM/80,fHRTIM/96,fHRTIM/112,fHRTIM/128,fHRTIM/144,fHRTIM/160,fHRTIM/176,fHRTIM/192,fHRTIM/208,fHRTIM/224,fHRTIM/240,fHRTIM/256"
|
|
line.long 0x24 "CPT1CCR,Timer C Capture 2 Control Register"
|
|
bitfld.long 0x24 31. " TECMP2 ,Timer E compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 30. " TECMP1 ,Timer E compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 29. " TE1RST ,Timer E output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 28. " TE1SET ,Timer E output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 27. " TDCMP2 ,Timer D compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 26. " TDCMP1 ,Timer D compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 25. " TD1RST ,Timer D output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 24. " TD1SET ,Timer D output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 19. " TBCMP2 ,Timer B compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 18. " TBCMP1 ,Timer B compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 17. " TB1RST ,Timer B output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 16. " TB1SET ,Timer B output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 15. " TACMP2 ,Timer A compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 14. " TACMP1 ,Timer A compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 13. " TA1RST ,Timer A output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 12. " TA1SET ,Timer A output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 11. " EXEV10CPT ,External event 10 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 10. " EXEV9CPT ,External event 9 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 9. " EXEV8CPT ,External event 8 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 8. " EXEV7CPT ,External event 7 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 7. " EXEV6CPT ,External event 6 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 6. " EXEV5CPT ,External event 5 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 5. " EXEV4CPT ,External event 4 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 4. " EXEV3CPT ,External event 3 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 3. " EXEV2CPT ,External event 2 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 2. " EXEV1CPT ,External event 1 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 1. " UDPCPT ,Update capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 0. " SWCPT ,Software capture" "Not forced,Forced"
|
|
line.long 0x28 "CPT2CCR,HRTIM Timer C Capture 2 Control Register"
|
|
bitfld.long 0x28 31. " TECMP2 ,Timer E compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 30. " TECMP1 ,Timer E compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 29. " TE1RST ,Timer E output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 28. " TE1SET ,Timer E output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 27. " TDCMP2 ,Timer D compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 26. " TDCMP1 ,Timer D compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 25. " TD1RST ,Timer D output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 24. " TD1SET ,Timer D output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 19. " TBCMP2 ,Timer B compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 18. " TBCMP1 ,Timer B compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 17. " TB1RST ,Timer B output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 16. " TB1SET ,Timer B output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 15. " TACMP2 ,Timer A compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 14. " TACMP1 ,Timer A compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 13. " TA1RST ,Timer A output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 12. " TA1SET ,Timer A output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 11. " EXEV10CPT ,External event 10 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 10. " EXEV9CPT ,External event 9 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 9. " EXEV8CPT ,External event 8 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 8. " EXEV7CPT ,External event 7 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 7. " EXEV6CPT ,External event 6 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 6. " EXEV5CPT ,External event 5 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 5. " EXEV4CPT ,External event 4 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 4. " EXEV3CPT ,External event 3 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 3. " EXEV2CPT ,External event 2 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 2. " EXEV1CPT ,External event 1 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 1. " UDPCPT ,Update capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 0. " SWCPT ,Software capture" "Not forced,Forced"
|
|
textline " "
|
|
if (((per.l(ad:0x40017400)&0x80000)==0x80000))
|
|
if (((per.l(ad:0x40017400+0x180+0x64)&0x200)==0x200))
|
|
group.long (0x180+0x64)++0x3
|
|
line.long 0x00 "OUTCR,Timer C Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
rbitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 6,Output 2 delayed Idle on external event 6,Output 1 and output 2 delayed Idle on external event 6,Balanced Idle on external event 6,Output 1 delayed Idle on external event 7,Output 2 delayed Idle on external event 7,Output 1 and output 2 delayed Idle on external event 7,Balanced Idle on external event 7"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
else
|
|
group.long (0x180+0x64)++0x3
|
|
line.long 0x00 "OUTCR,Timer C Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 6,Output 2 delayed Idle on external event 6,Output 1 and output 2 delayed Idle on external event 6,Balanced Idle on external event 6,Output 1 delayed Idle on external event 7,Output 2 delayed Idle on external event 7,Output 1 and output 2 delayed Idle on external event 7,Balanced Idle on external event 7"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0x180+0x64)&0x200)==0x200))
|
|
group.long (0x180+0x64)++0x3
|
|
line.long 0x00 "OUTCR,Timer C Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
rbitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 6,Output 2 delayed Idle on external event 6,Output 1 and output 2 delayed Idle on external event 6,Balanced Idle on external event 6,Output 1 delayed Idle on external event 7,Output 2 delayed Idle on external event 7,Output 1 and output 2 delayed Idle on external event 7,Balanced Idle on external event 7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
else
|
|
group.long (0x180+0x64)++0x3
|
|
line.long 0x00 "OUTCR,Timer C Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 6,Output 2 delayed Idle on external event 6,Output 1 and output 2 delayed Idle on external event 6,Balanced Idle on external event 6,Output 1 delayed Idle on external event 7,Output 2 delayed Idle on external event 7,Output 1 and output 2 delayed Idle on external event 7,Balanced Idle on external event 7"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
endif
|
|
endif
|
|
textline " "
|
|
group.long (0x180+0x68)++0x3
|
|
line.long 0x00 "FLTCR,Timer C Fault Register"
|
|
bitfld.long 0x00 31. " FLTLCK ,Fault sources lock" "FLT1EN..FLT5EN read/write,FLT1EN..FLT5EN read only"
|
|
bitfld.long 0x00 4. " FLT5EN ,Fault 5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FLT4EN ,Fault 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FLT3EN ,Fault 3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT2EN ,Fault 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FLT1EN ,Fault 1 enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TIMD"
|
|
if (((per.l(ad:0x40017400)&0x100000)==0x100000))
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "TIMDCR,Timer D Control Register"
|
|
bitfld.long 0x00 28.--31. " UPDGAT ,Update gating" "Independently from the DMA burst transfer,When the DMA burst transfer is completed,On the update event following the DMA burst transfer completion,On a rising edge of HRTIM update enable input 1,On a rising edge of HRTIM update enable input 2,On a rising edge of HRTIM update enable input 3,On the update event following a rising edge of HRTIM update enable input 1,On the update event following a rising edge of HRTIM update enable input 2,On the update event following a rising edge of HRTIM update enable input 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MSTU ,Master timer update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TEU ,Timer E update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TCU ,Timer C update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TBU ,Timer B update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TAU ,Timer A update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TDRSTU ,Timer D reset update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TDREPU ,Timer D repetition update" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 14.--15. " DELCMP4 ,Delayed CMP4 mode" "Always active,Recomputed && active following capture 2 event,Recomputed && active following (capture 2||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DELCMP2 ,Delayed CMP2 mode" "Always active,Recomputed && active following capture 1 event,Recomputed && active following (capture 1||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " SYNCSTRTD ,Synchronization starts timer D" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTD ,Synchronization resets timer D" "No effect,Reset"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " PSHPLL ,Push-Pull mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RETRIG ,Re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Continuous mode" "Single-shot,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CK_PSCD ,HRTIM timer D clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
else
|
|
group.long 0x200++0x3
|
|
line.long 0x00 "TIMDCR,Timer D Control Register"
|
|
bitfld.long 0x00 28.--31. " UPDGAT ,Update gating" "Independently from the DMA burst transfer,When the DMA burst transfer is completed,On the update event following the DMA burst transfer completion,On a rising edge of HRTIM update enable input 1,On a rising edge of HRTIM update enable input 2,On a rising edge of HRTIM update enable input 3,On the update event following a rising edge of HRTIM update enable input 1,On the update event following a rising edge of HRTIM update enable input 2,On the update event following a rising edge of HRTIM update enable input 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MSTU ,Master timer update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " TEU ,Timer E update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TCU ,Timer C update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TBU ,Timer B update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TAU ,Timer A update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TDRSTU ,Timer D reset update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TDREPU ,Timer D repetition update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DELCMP4 ,Delayed CMP4 mode" "Always active,Recomputed && active following capture 2 event,Recomputed && active following (capture 2||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DELCMP2 ,Delayed CMP2 mode" "Always active,Recomputed && active following capture 1 event,Recomputed && active following (capture 1||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNCSTRTD ,Synchronization starts timer D" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTD ,Synchronization resets timer D" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PSHPLL ,Push-Pull mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RETRIG ,Re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Continuous mode" "Single-shot,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CK_PSCD ,HRTIM timer D clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
endif
|
|
textline " "
|
|
rgroup.long (0x200+0x04)++0x3
|
|
line.long 0x00 "TIMDISR,Timer D Interrupt Status Register"
|
|
bitfld.long 0x00 21. " O2CPY ,Output 2 copy" "Inactive,Active"
|
|
bitfld.long 0x00 20. " O1CPY ,Output 1 copy" "Inactive,Active"
|
|
bitfld.long 0x00 19. " O2STAT ,Output 2 state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " O1STAT ,Output 1 state" "Inactive,Active"
|
|
bitfld.long 0x00 17. " IPPSTAT ,Idle push pull status" "Output 1 active/Output 2 inactive,Output 2 active/Output 1 inactive"
|
|
bitfld.long 0x00 16. " CPPSTAT ,Current push pull status" "Output 1 && 2 inactive,Output 2 && 1 inactive"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DLYPRT ,Delayed protection flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RST ,Reset and/or roll-over interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " RSTD2 ,Output 2 reset interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETD2 ,Output 2 set interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " RSTD1 ,Output 1 reset interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " SETx1 ,Output 1 set interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPT2 ,Capture2 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CPT1 ,Capture1 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " UPD ,Update interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REP ,Repetition interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CMP4 ,Compare 4 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CMP3 ,Compare 3 interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMP2 ,Compare 2 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CMP1 ,Compare 1 interrupt flag" "Not occurred,Occurred"
|
|
wgroup.long (0x200+0x08)++0x3
|
|
line.long 0x00 "TIMDICR,Timer D Interrupt Clear Register"
|
|
bitfld.long 0x00 14. " DLYPRTC ,Delayed protection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " RSTC ,Reset interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " RSTD2C ,Output 2 reset flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET2DC ,Output 2 set flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RSTD1C ,Output 1 reset flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " SET1DC ,Output 1 set flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPT2C ,Capture2 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " CPT1C ,Capture1 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " UPDC ,Update interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REPC ,Repetition interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CMP4C ,Compare 4 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CMP3C ,Compare 3 interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMP2C ,Compare 2 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CMP1C ,Compare 1 interrupt flag clear" "No effect,Clear"
|
|
group.long (0x200+0xC)++0x23
|
|
line.long 0x00 "TIMDDIER,HRTIM Timer D DMA / Interrupt Enable Register"
|
|
bitfld.long 0x00 30. " DLYPRTDE ,Delayed protection DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RSTDE ,Reset/roll-over DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " RSTD2DE ,Output 2 reset DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SETD2DE ,Output 2 set DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RSTD1DE ,Output 1 reset DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SET1DDE ,Output 1 set DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " CPT2DE ,Capture 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CPT1DE ,Capture 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " UPDDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " REPDE ,Repetition DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMP4DE ,Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CMP3DE ,Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMP2DE ,Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CMP1DE ,Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DLYPRTIE ,Delayed protection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIE ,Reset/roll-over interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RSTD2IE ,Output 2 reset interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETD2IE ,Output 2 set interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RSTD1IE ,Output 1 reset interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SET1DIE ,Output 1 set interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CPT2IE ,Capture interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CPT1IE ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " UPDIE ,Update interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " REPIE ,Repetition interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CMP4IE ,Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CMP3IE ,Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CMP2IE ,Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP1IE ,Compare 1 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNTDR,Timer D Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CNTD ,Timer D counter value"
|
|
line.long 0x08 "PERDR,Timer D Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERD ,Timer D period value"
|
|
line.long 0x0C "REPDR,Timer D Repetition Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " REPD ,Timer D repetition counter value"
|
|
line.long 0x10 "CMP1DR,Timer D Compare 1 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " CMP1D ,Timer D compare 1 value"
|
|
line.long 0x14 "CMP1CDR,Timer D Compare 1 Compound_ Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. " REPD ,Timer D repetition value"
|
|
hexmask.long.word 0x14 0.--15. 1. " CMP1D ,Timer D compare 1 value"
|
|
line.long 0x18 "CMP2DR,Timer D Compare 2 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " CMP2D ,Timer D compare 2 value"
|
|
line.long 0x1C "CMP3DR,Timer D Compare 3 Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " CMP3D ,Timer D compare 3 value"
|
|
line.long 0x20 "CMP4DR,Timer D Compare 4 Register"
|
|
hexmask.long.word 0x20 0.--15. 1. " CMP4D ,Timer D compare 4 value"
|
|
rgroup.long (0x200+0x30)++0x7
|
|
line.long 0x00 "CPT1DR,Timer D Capture 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPT1D ,Timer D capture 1 value"
|
|
line.long 0x04 "CPT2DR,Timer D Capture 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CPT2D ,Timer D capture 2 value"
|
|
group.long (0x200+0x38)++0x2B
|
|
line.long 0x00 "DTDR,Timer D Deadtime Register"
|
|
bitfld.long 0x00 31. " DTFLKD ,Deadtime falling lock" "Writable,Read-only"
|
|
bitfld.long 0x00 30. " DTFSLKD ,Deadtime falling sign lock" "Writable,Read-only"
|
|
bitfld.long 0x00 25. " SDTFD ,Sign deadtime falling value" "Positive,Negative"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--24. 1. " DTFD ,Deadtime falling value"
|
|
bitfld.long 0x00 15. " DTRLKD ,Deadtime rising lock" "Writable,Read-only"
|
|
bitfld.long 0x00 14. " DTRSLKD ,Deadtime rising sign lock" "Writable,Read-only"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DTPRSC ,Deadtime prescaler" ",,,tHRTIM,tHRTIM*2,tHRTIM*4,tHRTIM*8,tHRTIM*16"
|
|
bitfld.long 0x00 9. " SDTRD ,Sign deadtime rising value" "Positive,Negative"
|
|
hexmask.long.word 0x00 0.--8. 1. " DTRD ,Deadtime rising value"
|
|
line.long 0x04 "SETD1R,Timer D Output1 Set Register"
|
|
bitfld.long 0x04 31. " UPDATE ,Registers update active state" "Not forced,Forced"
|
|
bitfld.long 0x04 30. " EXTEVNT10 ,External event 10 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 29. " EXTEVNT9 ,External event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 28. " EXTEVNT8 ,External event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 27. " EXTEVNT7 ,External event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 26. " EXTEVNT6 ,External event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 25. " EXTEVNT5 ,External event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 24. " EXTEVNT4 ,External event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 23. " EXTEVNT3 ,External event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 22. " EXTEVNT2 ,External event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 21. " EXTEVNT1 ,External event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 20. " TIMEVNT9 ,Timer event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 19. " TIMEVNT8 ,Timer event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 18. " TIMEVNT7 ,Timer event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 17. " TIMEVNT6 ,Timer event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 16. " TIMEVNT5 ,Timer event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 15. " TIMEVNT4 ,Timer event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 14. " TIMEVNT3 ,Timer event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TIMEVNT2 ,Timer event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 12. " TIMEVNT1 ,Timer event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 11. " MSTCMP4 ,Master compare 4 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MSTCMP3 ,Master compare 3 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 9. " MSTCMP2 ,Master compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 8. " MSTCMP1 ,Master compare 1 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSTPER ,Master period active state" "Not forced,Forced"
|
|
bitfld.long 0x04 6. " CMP4 ,Timer D compare 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 5. " CMP3 ,Timer D compare 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CMP2 ,Timer D compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 3. " CMP1 ,Timer D compare 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 2. " PER ,Timer D period active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RESYNC ,Timer D resynchronization active state" "Not forced,Forced"
|
|
bitfld.long 0x04 0. " SST ,Software set trigger active state" "Not forced,Forced"
|
|
line.long 0x08 "RSTD1R,Timer D Output1 Reset Register"
|
|
bitfld.long 0x08 31. " UPDATE ,Registers update inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 30. " EXTEVNT10 ,External event 10 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 29. " EXTEVNT9 ,External event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 28. " EXTEVNT8 ,External event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 27. " EXTEVNT7 ,External event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 26. " EXTEVNT6 ,External event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 25. " EXTEVNT5 ,External event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 24. " EXTEVNT4 ,External event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 23. " EXTEVNT3 ,External event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 22. " EXTEVNT2 ,External event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 21. " EXTEVNT1 ,External event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 20. " TIMEVNT9 ,Timer event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TIMEVNT8 ,Timer event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 18. " TIMEVNT7 ,Timer event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 17. " TIMEVNT6 ,Timer event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 16. " TIMEVNT5 ,Timer event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 15. " TIMEVNT4 ,Timer event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 14. " TIMEVNT3 ,Timer event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 13. " TIMEVNT2 ,Timer event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 12. " TIMEVNT1 ,Timer event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 11. " MSTCMP4 ,Master compare 4 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 10. " MSTCMP3 ,Master compare 3 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 9. " MSTCMP2 ,Master compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 8. " MSTCMP1 ,Master compare 1 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSTPER ,Master period inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 6. " CMP4 ,Timer D compare 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 5. " CMP3 ,Timer D compare 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CMP2 ,Timer D compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 3. " CMP1 ,Timer D compare 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 2. " PER ,Timer D period inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RESYNC ,Timer D resynchronizaton inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 0. " SRT ,Software set trigger inactive state" "Not forced,Forced"
|
|
line.long 0x0C "SETD2R,Timer D Output2 Set Register"
|
|
bitfld.long 0x0C 31. " UPDATE ,Registers update active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 30. " EXTEVNT10 ,External event 10 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 29. " EXTEVNT9 ,External event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " EXTEVNT8 ,External event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 27. " EXTEVNT7 ,External event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 26. " EXTEVNT6 ,External event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " EXTEVNT5 ,External event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 24. " EXTEVNT4 ,External event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 23. " EXTEVNT3 ,External event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " EXTEVNT2 ,External event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 21. " EXTEVNT1 ,External event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 20. " TIMEVNT9 ,Timer event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " TIMEVNT8 ,Timer event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 18. " TIMEVNT7 ,Timer event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 17. " TIMEVNT6 ,Timer event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " TIMEVNT5 ,Timer event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 15. " TIMEVNT4 ,Timer event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 14. " TIMEVNT3 ,Timer event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " TIMEVNT2 ,Timer event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 12. " TIMEVNT1 ,Timer event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 11. " MSTCMP4 ,Master compare 4 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " MSTCMP3 ,Master compare 3 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 9. " MSTCMP2 ,Master compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 8. " MSTCMP1 ,Master compare 1 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " MSTPER ,Master period active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 6. " CMP4 ,Timer D compare 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 5. " CMP3 ,Timer D compare 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMP2 ,Timer D compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 3. " CMP1 ,Timer D compare 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 2. " PER ,Timer D period active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " RESYNC ,Timer D resynchronizaton active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 0. " SST ,Software set trigger active state" "Not forced,Forced"
|
|
line.long 0x10 "RSTD2R,Timer D Output2 Reset Register"
|
|
bitfld.long 0x10 31. " UPDATE ,Registers update inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 30. " EXTEVNT10 ,External event 10 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 29. " EXTEVNT9 ,External event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 28. " EXTEVNT8 ,External event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 27. " EXTEVNT7 ,External event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 26. " EXTEVNT6 ,External event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EXTEVNT5 ,External event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 24. " EXTEVNT4 ,External event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 23. " EXTEVNT3 ,External event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 22. " EXTEVNT2 ,External event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 21. " EXTEVNT1 ,External event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 20. " TIMEVNT9 ,Timer event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 19. " TIMEVNT8 ,Timer event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 18. " TIMEVNT7 ,Timer event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 17. " TIMEVNT6 ,Timer event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 16. " TIMEVNT5 ,Timer event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 15. " TIMEVNT4 ,Timer event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 14. " TIMEVNT3 ,Timer event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 13. " TIMEVNT2 ,Timer event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 12. " TIMEVNT1 ,Timer event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 11. " MSTCMP4 ,Master compare 4 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 10. " MSTCMP3 ,Master compare 3 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 9. " MSTCMP2 ,Master compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 8. " MSTCMP1 ,Master compare 1 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 7. " MSTPER ,Master period inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 6. " CMP4 ,Timer D compare 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 5. " CMP3 ,Timer D compare 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 4. " CMP2 ,Timer D compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 3. " CMP1 ,Timer D compare 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 2. " PER ,Timer D period inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 1. " RESYNC ,Timer D resynchronizaton inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 0. " SRT ,Software set trigger inactive state" "Not forced,Forced"
|
|
textline " "
|
|
line.long 0x14 "EEFDR1,Timer D External Event Filtering Register 1"
|
|
bitfld.long 0x14 25.--28. " EE5FLTR ,External event 5 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 24. " EE5LTCH ,External event 5 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 19.--22. " EE4FLTR ,External event 4 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 18. " EE4LTCH ,External event 4 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 13.--16. " EE3FLTR ,External event 3 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 12. " EE3LTCH ,External event 3 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 7.--10. " EE2FLTR ,External event 2 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 6. " EE2LTCH ,External event 2 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 1.--4. " EE1FLTR ,External event 1 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 0. " EE1LTCH ,External event 1 latch" "Ignored,Latched"
|
|
line.long 0x18 "EEFDR2,Timer D External Event Filtering Register 2"
|
|
bitfld.long 0x18 25.--28. " EE10FLTR ,External event 10 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 24. " EE10LTCH ,External event 10 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 19.--22. " EE9FLTR ,External event 9 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 18. " EE9LTCH ,External event 9 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 13.--16. " EE8FLTR ,External event 8 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 12. " EE8LTCH ,External event 8 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 7.--10. " EE7FLTR ,External event 7 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 6. " EE7LTCH ,External event 7 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 1.--4. " EE6FLTR ,External event 6 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 0. " EE6LTCH ,External event 6 latch" "Ignored,Latched"
|
|
textline " "
|
|
line.long 0x1C "RSTDR,Timer D Reset Register"
|
|
bitfld.long 0x1C 30. " TIMECMP4 ,Timer E compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 29. " TIMECMP2 ,Timer E compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 28. " TIMECMP1 ,Timer E compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " TIMCCMP4 ,Timer C compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 26. " TIMCCMP2 ,Timer C compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 25. " TIMCCMP1 ,Timer C compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " TIMBCMP4 ,Timer B compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 23. " TIMBCMP2 ,Timer B compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 22. " TIMBCMP1 ,Timer B compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 21. " TIMACMP4 ,Timer A compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 20. " TIMACMP2 ,Timer A compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 19. " TIMACMP1 ,Timer A compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 18. " EXTEVNT10 ,External event 10" "No reset,Reset"
|
|
bitfld.long 0x1C 17. " EXTEVNT9 ,External event 9" "No reset,Reset"
|
|
bitfld.long 0x1C 16. " EXTEVNT8 ,External event 8" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " EXTEVNT7 ,External event 7" "No reset,Reset"
|
|
bitfld.long 0x1C 14. " EXTEVNT6 ,External event 6" "No reset,Reset"
|
|
bitfld.long 0x1C 13. " EXTEVNT5 ,External event 5" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " EXTEVNT4 ,External event 4" "No reset,Reset"
|
|
bitfld.long 0x1C 11. " EXTEVNT3 ,External event 3" "No reset,Reset"
|
|
bitfld.long 0x1C 10. " EXTEVNT2 ,External event 2" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " EXTEVNT1 ,External event 1" "No reset,Reset"
|
|
bitfld.long 0x1C 8. " MSTCMP4 ,Master compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 7. " MSTCMP3 ,Master compare 3" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " MSTCMP2 ,Master compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 5. " MSTCMP1 ,Master compare 1" "No reset,Reset"
|
|
bitfld.long 0x1C 4. " MSTPER ,Master timer Period" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " CMP4 ,Timer A compare 4 reset" "No reset,Reset"
|
|
bitfld.long 0x1C 2. " CMP2 ,Timer A compare 2 reset" "No reset,Reset"
|
|
bitfld.long 0x1C 1. " UPDT ,Timer A update reset" "No reset,Reset"
|
|
line.long 0x20 "CHPDR,Timer D Chopper Register"
|
|
bitfld.long 0x20 7.--10. " STRTPW ,Timer D start pulsewidth" "40ns,80ns,120ns,160ns,200ns,240ns,280ns,320ns,360ns,400ns,440ns,480ns,520ns,560ns,600ns,640ns"
|
|
bitfld.long 0x20 4.--6. " CHPDTY ,Timer D chopper duty cycle value" "0/8,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
bitfld.long 0x20 0.--3. " CHPFRQ ,Timer D carrier frequency value" "fHRTIM/16,fHRTIM/32,fHRTIM/48,fHRTIM/64,fHRTIM/80,fHRTIM/96,fHRTIM/112,fHRTIM/128,fHRTIM/144,fHRTIM/160,fHRTIM/176,fHRTIM/192,fHRTIM/208,fHRTIM/224,fHRTIM/240,fHRTIM/256"
|
|
line.long 0x24 "CPT1DCR,Timer D Capture 2 Control Register"
|
|
bitfld.long 0x24 31. " TECMP2 ,Timer E compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 30. " TECMP1 ,Timer E compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 29. " TE1RST ,Timer E output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 28. " TE1SET ,Timer E output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 23. " TCCMP2 ,Timer C compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 22. " TCCMP1 ,Timer C compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 21. " TC1RST ,Timer C output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 20. " TC1SET ,Timer C output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 19. " TBCMP2 ,Timer B compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 18. " TBCMP1 ,Timer B compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 17. " TB1RST ,Timer B output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 16. " TB1SET ,Timer B output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 15. " TACMP2 ,Timer A compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 14. " TACMP1 ,Timer A compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 13. " TA1RST ,Timer A output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 12. " TA1SET ,Timer A output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 11. " EXEV10CPT ,External event 10 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 10. " EXEV9CPT ,External event 9 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 9. " EXEV8CPT ,External event 8 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 8. " EXEV7CPT ,External event 7 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 7. " EXEV6CPT ,External event 6 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 6. " EXEV5CPT ,External event 5 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 5. " EXEV4CPT ,External event 4 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 4. " EXEV3CPT ,External event 3 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 3. " EXEV2CPT ,External event 2 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 2. " EXEV1CPT ,External event 1 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 1. " UDPCPT ,Update capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 0. " SWCPT ,Software capture" "Not forced,Forced"
|
|
line.long 0x28 "CPT2DCR,HRTIM Timer D Capture 2 Control Register"
|
|
bitfld.long 0x28 31. " TECMP2 ,Timer E compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 30. " TECMP1 ,Timer E compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 29. " TE1RST ,Timer E output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 28. " TE1SET ,Timer E output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 23. " TCCMP2 ,Timer C compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 22. " TCCMP1 ,Timer C compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 21. " TC1RST ,Timer C output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 20. " TC1SET ,Timer C output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 19. " TBCMP2 ,Timer B compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 18. " TBCMP1 ,Timer B compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 17. " TB1RST ,Timer B output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 16. " TB1SET ,Timer B output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 15. " TACMP2 ,Timer A compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 14. " TACMP1 ,Timer A compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 13. " TA1RST ,Timer A output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 12. " TA1SET ,Timer A output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 11. " EXEV10CPT ,External event 10 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 10. " EXEV9CPT ,External event 9 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 9. " EXEV8CPT ,External event 8 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 8. " EXEV7CPT ,External event 7 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 7. " EXEV6CPT ,External event 6 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 6. " EXEV5CPT ,External event 5 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 5. " EXEV4CPT ,External event 4 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 4. " EXEV3CPT ,External event 3 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 3. " EXEV2CPT ,External event 2 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 2. " EXEV1CPT ,External event 1 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 1. " UDPCPT ,Update capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 0. " SWCPT ,Software capture" "Not forced,Forced"
|
|
textline " "
|
|
if (((per.l(ad:0x40017400)&0x100000)==0x100000))
|
|
if (((per.l(ad:0x40017400+0x200+0x64)&0x200)==0x200))
|
|
group.long (0x200+0x64)++0x3
|
|
line.long 0x00 "OUTDR,Timer D Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
rbitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 8,Output 2 delayed Idle on external event 8,Output 1 and output 2 delayed Idle on external event 8,Balanced Idle on external event 8,Output 1 delayed Idle on external event 9,Output 2 delayed Idle on external event 9,Output 1 and output 2 delayed Idle on external event 9,Balanced Idle on external event 9"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
else
|
|
group.long (0x200+0x64)++0x3
|
|
line.long 0x00 "OUTDR,Timer D Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 8,Output 2 delayed Idle on external event 8,Output 1 and output 2 delayed Idle on external event 8,Balanced Idle on external event 8,Output 1 delayed Idle on external event 9,Output 2 delayed Idle on external event 9,Output 1 and output 2 delayed Idle on external event 9,Balanced Idle on external event 9"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0x200+0x64)&0x200)==0x200))
|
|
group.long (0x200+0x64)++0x3
|
|
line.long 0x00 "OUTDR,Timer D Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
rbitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 8,Output 2 delayed Idle on external event 8,Output 1 and output 2 delayed Idle on external event 8,Balanced Idle on external event 8,Output 1 delayed Idle on external event 9,Output 2 delayed Idle on external event 9,Output 1 and output 2 delayed Idle on external event 9,Balanced Idle on external event 9"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
else
|
|
group.long (0x200+0x64)++0x3
|
|
line.long 0x00 "OUTDR,Timer D Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 8,Output 2 delayed Idle on external event 8,Output 1 and output 2 delayed Idle on external event 8,Balanced Idle on external event 8,Output 1 delayed Idle on external event 9,Output 2 delayed Idle on external event 9,Output 1 and output 2 delayed Idle on external event 9,Balanced Idle on external event 9"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
endif
|
|
endif
|
|
textline " "
|
|
group.long (0x200+0x68)++0x3
|
|
line.long 0x00 "FLTDR,Timer D Fault Register"
|
|
bitfld.long 0x00 31. " FLTLCK ,Fault sources lock" "FLT1EN..FLT5EN read/write,FLT1EN..FLT5EN read only"
|
|
bitfld.long 0x00 4. " FLT5EN ,Fault 5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FLT4EN ,Fault 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FLT3EN ,Fault 3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT2EN ,Fault 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FLT1EN ,Fault 1 enable" "Disabled,Enabled"
|
|
tree.end
|
|
tree "TIME"
|
|
if (((per.l(ad:0x40017400)&0x200000)==0x200000))
|
|
group.long 0x280++0x3
|
|
line.long 0x00 "TIMECR,Timer E Control Register"
|
|
bitfld.long 0x00 28.--31. " UPDGAT ,Update gating" "Independently from the DMA burst transfer,When the DMA burst transfer is completed,On the update event following the DMA burst transfer completion,On a rising edge of HRTIM update enable input 1,On a rising edge of HRTIM update enable input 2,On a rising edge of HRTIM update enable input 3,On the update event following a rising edge of HRTIM update enable input 1,On the update event following a rising edge of HRTIM update enable input 2,On the update event following a rising edge of HRTIM update enable input 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MSTU ,Master timer update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TDU ,Timer D update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TCU ,Timer C update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TBU ,Timer B update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TAU ,Timer A update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TERSTU ,Timer E reset update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TEREPU ,Timer E repetition update" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 14.--15. " DELCMP4 ,Delayed CMP4 mode" "Always active,Recomputed && active following capture 2 event,Recomputed && active following (capture 2||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " DELCMP2 ,Delayed CMP2 mode" "Always active,Recomputed && active following capture 1 event,Recomputed && active following (capture 1||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " SYNCSTRTE ,Synchronization starts timer E" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTE ,Synchronization resets timer E" "No effect,Reset"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " PSHPLL ,Push-Pull mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RETRIG ,Re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Continuous mode" "Single-shot,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CK_PSCE ,HRTIM timer E clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
else
|
|
group.long 0x280++0x3
|
|
line.long 0x00 "TIMECR,Timer E Control Register"
|
|
bitfld.long 0x00 28.--31. " UPDGAT ,Update gating" "Independently from the DMA burst transfer,When the DMA burst transfer is completed,On the update event following the DMA burst transfer completion,On a rising edge of HRTIM update enable input 1,On a rising edge of HRTIM update enable input 2,On a rising edge of HRTIM update enable input 3,On the update event following a rising edge of HRTIM update enable input 1,On the update event following a rising edge of HRTIM update enable input 2,On the update event following a rising edge of HRTIM update enable input 3,?..."
|
|
textline " "
|
|
bitfld.long 0x00 27. " PREEN ,Preload enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25.--26. " DACSYNC ,DAC synchronization" "No trigger,Hrtim_dac_trg1,Hrtim_dac_trg2,Hrtim_dac_trg3"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MSTU ,Master timer update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TDU ,Timer D update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " TCU ,Timer C update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " TBU ,Timer B update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TAU ,Timer A update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " TERSTU ,Timer E reset update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TEREPU ,Timer E repetition update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14.--15. " DELCMP4 ,Delayed CMP4 mode" "Always active,Recomputed && active following capture 2 event,Recomputed && active following (capture 2||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " DELCMP2 ,Delayed CMP2 mode" "Always active,Recomputed && active following capture 1 event,Recomputed && active following (capture 1||compare 1 match) event,Recomputed && active following (capture ||compare 3 match) event"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SYNCSTRTE ,Synchronization starts timer E" "No effect,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " SYNCRSTE ,Synchronization resets timer E" "No effect,Reset"
|
|
textline " "
|
|
bitfld.long 0x00 6. " PSHPLL ,Push-Pull mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " HALF ,Half mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " RETRIG ,Re-triggerable mode" "Not re-triggerable,Re-triggerable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CONT ,Continuous mode" "Single-shot,Continuous"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " CK_PSCE ,HRTIM timer E clock prescaler" ",,,,,fHRTIM,fHRTIM/2,fHRTIM/4"
|
|
endif
|
|
textline " "
|
|
rgroup.long (0x280+0x04)++0x3
|
|
line.long 0x00 "TIMEISR,Timer E Interrupt Status Register"
|
|
bitfld.long 0x00 21. " O2CPY ,Output 2 copy" "Inactive,Active"
|
|
bitfld.long 0x00 20. " O1CPY ,Output 1 copy" "Inactive,Active"
|
|
bitfld.long 0x00 19. " O2STAT ,Output 2 state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " O1STAT ,Output 1 state" "Inactive,Active"
|
|
bitfld.long 0x00 17. " IPPSTAT ,Idle push pull status" "Output 1 active/Output 2 inactive,Output 2 active/Output 1 inactive"
|
|
bitfld.long 0x00 16. " CPPSTAT ,Current push pull status" "Output 1 && 2 inactive,Output 2 && 1 inactive"
|
|
textline " "
|
|
bitfld.long 0x00 14. " DLYPRT ,Delayed protection flag" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " RST ,Reset and/or roll-over interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 12. " RSTE2 ,Output 2 reset interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SETE2 ,Output 2 set interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " RSTE1 ,Output 1 reset interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 9. " SETx1 ,Output 1 set interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPT2 ,Capture2 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 7. " CPT1 ,Capture1 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 6. " UPD ,Update interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REP ,Repetition interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 3. " CMP4 ,Compare 4 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 2. " CMP3 ,Compare 3 interrupt flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMP2 ,Compare 2 interrupt flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 0. " CMP1 ,Compare 1 interrupt flag" "Not occurred,Occurred"
|
|
wgroup.long (0x280+0x08)++0x3
|
|
line.long 0x00 "TIMEICR,Timer E Interrupt Clear Register"
|
|
bitfld.long 0x00 14. " DLYPRTC ,Delayed protection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 13. " RSTC ,Reset interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " RSTE2C ,Output 2 reset flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SET2EC ,Output 2 set flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " RSTE1C ,Output 1 reset flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " SET1EC ,Output 1 set flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CPT2C ,Capture2 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 7. " CPT1C ,Capture1 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 6. " UPDC ,Update interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " REPC ,Repetition interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CMP4C ,Compare 4 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " CMP3C ,Compare 3 interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " CMP2C ,Compare 2 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CMP1C ,Compare 1 interrupt flag clear" "No effect,Clear"
|
|
group.long (0x280+0xC)++0x23
|
|
line.long 0x00 "TIMEDIER,HRTIM Timer E DMA / Interrupt Enable Register"
|
|
bitfld.long 0x00 30. " DLYPRTDE ,Delayed protection DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " RSTDE ,Reset/roll-over DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " RSTE2DE ,Output 2 reset DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 27. " SETE2DE ,Output 2 set DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " RSTE1DE ,Output 1 reset DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " SET1EDE ,Output 1 set DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " CPT2DE ,Capture 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " CPT1DE ,Capture 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " UPDDE ,Update DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " REPDE ,Repetition DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CMP4DE ,Compare 4 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CMP3DE ,Compare 3 DMA request enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMP2DE ,Compare 2 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " CMP1DE ,Compare 1 DMA request enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DLYPRTIE ,Delayed protection interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " RSTIE ,Reset/roll-over interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " RSTE2IE ,Output 2 reset interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SETE2IE ,Output 2 set interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " RSTE1IE ,Output 1 reset interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SET1EIE ,Output 1 set interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " CPT2IE ,Capture interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CPT1IE ,Capture interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " UPDIE ,Update interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " REPIE ,Repetition interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " CMP4IE ,Compare 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CMP3IE ,Compare 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CMP2IE ,Compare 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CMP1IE ,Compare 1 interrupt enable" "Disabled,Enabled"
|
|
line.long 0x04 "CNTER,Timer E Counter Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CNTE ,Timer E counter value"
|
|
line.long 0x08 "PERER,Timer E Period Register"
|
|
hexmask.long.word 0x08 0.--15. 1. " PERE ,Timer E period value"
|
|
line.long 0x0C "REPER,Timer E Repetition Register"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " REPE ,Timer E repetition counter value"
|
|
line.long 0x10 "CMP1ER,Timer E Compare 1 Register"
|
|
hexmask.long.word 0x10 0.--15. 1. " CMP1E ,Timer E compare 1 value"
|
|
line.long 0x14 "CMP1CER,Timer E Compare 1 Compound_ Register"
|
|
hexmask.long.byte 0x14 16.--23. 1. " REPE ,Timer E repetition value"
|
|
hexmask.long.word 0x14 0.--15. 1. " CMP1E ,Timer E compare 1 value"
|
|
line.long 0x18 "CMP2ER,Timer E Compare 2 Register"
|
|
hexmask.long.word 0x18 0.--15. 1. " CMP2E ,Timer E compare 2 value"
|
|
line.long 0x1C "CMP3ER,Timer E Compare 3 Register"
|
|
hexmask.long.word 0x1C 0.--15. 1. " CMP3E ,Timer E compare 3 value"
|
|
line.long 0x20 "CMP4ER,Timer E Compare 4 Register"
|
|
hexmask.long.word 0x20 0.--15. 1. " CMP4E ,Timer E compare 4 value"
|
|
rgroup.long (0x280+0x30)++0x7
|
|
line.long 0x00 "CPT1ER,Timer E Capture 1 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " CPT1E ,Timer E capture 1 value"
|
|
line.long 0x04 "CPT2ER,Timer E Capture 2 Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " CPT2E ,Timer E capture 2 value"
|
|
group.long (0x280+0x38)++0x2B
|
|
line.long 0x00 "DTER,Timer E Deadtime Register"
|
|
bitfld.long 0x00 31. " DTFLKE ,Deadtime falling lock" "Writable,Read-only"
|
|
bitfld.long 0x00 30. " DTFSLKE ,Deadtime falling sign lock" "Writable,Read-only"
|
|
bitfld.long 0x00 25. " SDTFE ,Sign deadtime falling value" "Positive,Negative"
|
|
textline " "
|
|
hexmask.long.word 0x00 16.--24. 1. " DTFE ,Deadtime falling value"
|
|
bitfld.long 0x00 15. " DTRLKE ,Deadtime rising lock" "Writable,Read-only"
|
|
bitfld.long 0x00 14. " DTRSLKE ,Deadtime rising sign lock" "Writable,Read-only"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DTPRSC ,Deadtime prescaler" ",,,tHRTIM,tHRTIM*2,tHRTIM*4,tHRTIM*8,tHRTIM*16"
|
|
bitfld.long 0x00 9. " SDTRE ,Sign deadtime rising value" "Positive,Negative"
|
|
hexmask.long.word 0x00 0.--8. 1. " DTRE ,Deadtime rising value"
|
|
line.long 0x04 "SETE1R,Timer E Output1 Set Register"
|
|
bitfld.long 0x04 31. " UPDATE ,Registers update active state" "Not forced,Forced"
|
|
bitfld.long 0x04 30. " EXTEVNT10 ,External event 10 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 29. " EXTEVNT9 ,External event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 28. " EXTEVNT8 ,External event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 27. " EXTEVNT7 ,External event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 26. " EXTEVNT6 ,External event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 25. " EXTEVNT5 ,External event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 24. " EXTEVNT4 ,External event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 23. " EXTEVNT3 ,External event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 22. " EXTEVNT2 ,External event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 21. " EXTEVNT1 ,External event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 20. " TIMEVNT9 ,Timer event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 19. " TIMEVNT8 ,Timer event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 18. " TIMEVNT7 ,Timer event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 17. " TIMEVNT6 ,Timer event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 16. " TIMEVNT5 ,Timer event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 15. " TIMEVNT4 ,Timer event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 14. " TIMEVNT3 ,Timer event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 13. " TIMEVNT2 ,Timer event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 12. " TIMEVNT1 ,Timer event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 11. " MSTCMP4 ,Master compare 4 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 10. " MSTCMP3 ,Master compare 3 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 9. " MSTCMP2 ,Master compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 8. " MSTCMP1 ,Master compare 1 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 7. " MSTPER ,Master period active state" "Not forced,Forced"
|
|
bitfld.long 0x04 6. " CMP4 ,Timer E compare 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 5. " CMP3 ,Timer E compare 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 4. " CMP2 ,Timer E compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 3. " CMP1 ,Timer E compare 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x04 2. " PER ,Timer E period active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x04 1. " RESYNC ,Timer E resynchronization active state" "Not forced,Forced"
|
|
bitfld.long 0x04 0. " SST ,Software set trigger active state" "Not forced,Forced"
|
|
line.long 0x08 "RSTE1R,Timer E Output1 Reset Register"
|
|
bitfld.long 0x08 31. " UPDATE ,Registers update inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 30. " EXTEVNT10 ,External event 10 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 29. " EXTEVNT9 ,External event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 28. " EXTEVNT8 ,External event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 27. " EXTEVNT7 ,External event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 26. " EXTEVNT6 ,External event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 25. " EXTEVNT5 ,External event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 24. " EXTEVNT4 ,External event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 23. " EXTEVNT3 ,External event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 22. " EXTEVNT2 ,External event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 21. " EXTEVNT1 ,External event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 20. " TIMEVNT9 ,Timer event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 19. " TIMEVNT8 ,Timer event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 18. " TIMEVNT7 ,Timer event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 17. " TIMEVNT6 ,Timer event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 16. " TIMEVNT5 ,Timer event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 15. " TIMEVNT4 ,Timer event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 14. " TIMEVNT3 ,Timer event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 13. " TIMEVNT2 ,Timer event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 12. " TIMEVNT1 ,Timer event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 11. " MSTCMP4 ,Master compare 4 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 10. " MSTCMP3 ,Master compare 3 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 9. " MSTCMP2 ,Master compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 8. " MSTCMP1 ,Master compare 1 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MSTPER ,Master period inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 6. " CMP4 ,Timer E compare 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 5. " CMP3 ,Timer E compare 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 4. " CMP2 ,Timer E compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 3. " CMP1 ,Timer E compare 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 2. " PER ,Timer E period inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x08 1. " RESYNC ,Timer E resynchronizaton inactive state" "Not forced,Forced"
|
|
bitfld.long 0x08 0. " SRT ,Software set trigger inactive state" "Not forced,Forced"
|
|
line.long 0x0C "SETE2R,Timer E Output2 Set Register"
|
|
bitfld.long 0x0C 31. " UPDATE ,Registers update active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 30. " EXTEVNT10 ,External event 10 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 29. " EXTEVNT9 ,External event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " EXTEVNT8 ,External event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 27. " EXTEVNT7 ,External event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 26. " EXTEVNT6 ,External event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " EXTEVNT5 ,External event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 24. " EXTEVNT4 ,External event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 23. " EXTEVNT3 ,External event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " EXTEVNT2 ,External event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 21. " EXTEVNT1 ,External event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 20. " TIMEVNT9 ,Timer event 9 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " TIMEVNT8 ,Timer event 8 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 18. " TIMEVNT7 ,Timer event 7 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 17. " TIMEVNT6 ,Timer event 6 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " TIMEVNT5 ,Timer event 5 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 15. " TIMEVNT4 ,Timer event 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 14. " TIMEVNT3 ,Timer event 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " TIMEVNT2 ,Timer event 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 12. " TIMEVNT1 ,Timer event 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 11. " MSTCMP4 ,Master compare 4 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " MSTCMP3 ,Master compare 3 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 9. " MSTCMP2 ,Master compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 8. " MSTCMP1 ,Master compare 1 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " MSTPER ,Master period active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 6. " CMP4 ,Timer E compare 4 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 5. " CMP3 ,Timer E compare 3 active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " CMP2 ,Timer E compare 2 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 3. " CMP1 ,Timer E compare 1 active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 2. " PER ,Timer E period active state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " RESYNC ,Timer E resynchronizaton active state" "Not forced,Forced"
|
|
bitfld.long 0x0C 0. " SST ,Software set trigger active state" "Not forced,Forced"
|
|
line.long 0x10 "RSTE2R,Timer E Output2 Reset Register"
|
|
bitfld.long 0x10 31. " UPDATE ,Registers update inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 30. " EXTEVNT10 ,External event 10 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 29. " EXTEVNT9 ,External event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 28. " EXTEVNT8 ,External event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 27. " EXTEVNT7 ,External event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 26. " EXTEVNT6 ,External event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 25. " EXTEVNT5 ,External event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 24. " EXTEVNT4 ,External event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 23. " EXTEVNT3 ,External event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 22. " EXTEVNT2 ,External event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 21. " EXTEVNT1 ,External event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 20. " TIMEVNT9 ,Timer event 9 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 19. " TIMEVNT8 ,Timer event 8 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 18. " TIMEVNT7 ,Timer event 7 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 17. " TIMEVNT6 ,Timer event 6 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 16. " TIMEVNT5 ,Timer event 5 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 15. " TIMEVNT4 ,Timer event 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 14. " TIMEVNT3 ,Timer event 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 13. " TIMEVNT2 ,Timer event 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 12. " TIMEVNT1 ,Timer event 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 11. " MSTCMP4 ,Master compare 4 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 10. " MSTCMP3 ,Master compare 3 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 9. " MSTCMP2 ,Master compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 8. " MSTCMP1 ,Master compare 1 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 7. " MSTPER ,Master period inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 6. " CMP4 ,Timer E compare 4 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 5. " CMP3 ,Timer E compare 3 inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 4. " CMP2 ,Timer E compare 2 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 3. " CMP1 ,Timer E compare 1 inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 2. " PER ,Timer E period inactive state" "Not forced,Forced"
|
|
textline " "
|
|
bitfld.long 0x10 1. " RESYNC ,Timer E resynchronizaton inactive state" "Not forced,Forced"
|
|
bitfld.long 0x10 0. " SRT ,Software set trigger inactive state" "Not forced,Forced"
|
|
textline " "
|
|
line.long 0x14 "EEFER1,Timer E External Event Filtering Register 1"
|
|
bitfld.long 0x14 25.--28. " EE5FLTR ,External event 5 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 24. " EE5LTCH ,External event 5 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 19.--22. " EE4FLTR ,External event 4 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 18. " EE4LTCH ,External event 4 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 13.--16. " EE3FLTR ,External event 3 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 12. " EE3LTCH ,External event 3 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 7.--10. " EE2FLTR ,External event 2 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 6. " EE2LTCH ,External event 2 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x14 1.--4. " EE1FLTR ,External event 1 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x14 0. " EE1LTCH ,External event 1 latch" "Ignored,Latched"
|
|
line.long 0x18 "EEFER2,Timer E External Event Filtering Register 2"
|
|
bitfld.long 0x18 25.--28. " EE10FLTR ,External event 10 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 24. " EE10LTCH ,External event 10 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 19.--22. " EE9FLTR ,External event 9 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 18. " EE9LTCH ,External event 9 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 13.--16. " EE8FLTR ,External event 8 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 12. " EE8LTCH ,External event 8 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 7.--10. " EE7FLTR ,External event 7 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 6. " EE7LTCH ,External event 7 latch" "Ignored,Latched"
|
|
textline " "
|
|
bitfld.long 0x18 1.--4. " EE6FLTR ,External event 6 filter" "No filtering,Blanking from counter reset/roll-over to compare 1,Blanking from counter reset/roll-over to compare 2,Blanking from counter reset/roll-over to compare 3,Blanking from counter reset/roll-over to compare 4,TIMFLTR1 source,TIMFLTR2 source,TIMFLTR3 source,TIMFLTR4 source,TIMFLTR5 source,TIMFLTR6 source,TIMFLTR7 source,TIMFLTR8 source,Windowing from counter reset/roll-over to compare 2,Windowing from counter reset/roll-over to compare 3,TIMWIN source"
|
|
bitfld.long 0x18 0. " EE6LTCH ,External event 6 latch" "Ignored,Latched"
|
|
textline " "
|
|
line.long 0x1C "RSTER,Timer E Reset Register"
|
|
bitfld.long 0x1C 30. " TIMDCMP4 ,Timer D compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 29. " TIMDCMP2 ,Timer D compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 28. " TIMDCMP1 ,Timer D compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 27. " TIMCCMP4 ,Timer C compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 26. " TIMCCMP2 ,Timer C compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 25. " TIMCCMP1 ,Timer C compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 24. " TIMBCMP4 ,Timer B compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 23. " TIMBCMP2 ,Timer B compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 22. " TIMBCMP1 ,Timer B compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 21. " TIMACMP4 ,Timer A compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 20. " TIMACMP2 ,Timer A compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 19. " TIMACMP1 ,Timer A compare 1" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 18. " EXTEVNT10 ,External event 10" "No reset,Reset"
|
|
bitfld.long 0x1C 17. " EXTEVNT9 ,External event 9" "No reset,Reset"
|
|
bitfld.long 0x1C 16. " EXTEVNT8 ,External event 8" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 15. " EXTEVNT7 ,External event 7" "No reset,Reset"
|
|
bitfld.long 0x1C 14. " EXTEVNT6 ,External event 6" "No reset,Reset"
|
|
bitfld.long 0x1C 13. " EXTEVNT5 ,External event 5" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 12. " EXTEVNT4 ,External event 4" "No reset,Reset"
|
|
bitfld.long 0x1C 11. " EXTEVNT3 ,External event 3" "No reset,Reset"
|
|
bitfld.long 0x1C 10. " EXTEVNT2 ,External event 2" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 9. " EXTEVNT1 ,External event 1" "No reset,Reset"
|
|
bitfld.long 0x1C 8. " MSTCMP4 ,Master compare 4" "No reset,Reset"
|
|
bitfld.long 0x1C 7. " MSTCMP3 ,Master compare 3" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 6. " MSTCMP2 ,Master compare 2" "No reset,Reset"
|
|
bitfld.long 0x1C 5. " MSTCMP1 ,Master compare 1" "No reset,Reset"
|
|
bitfld.long 0x1C 4. " MSTPER ,Master timer Period" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x1C 3. " CMP4 ,Timer A compare 4 reset" "No reset,Reset"
|
|
bitfld.long 0x1C 2. " CMP2 ,Timer A compare 2 reset" "No reset,Reset"
|
|
bitfld.long 0x1C 1. " UPDT ,Timer A update reset" "No reset,Reset"
|
|
line.long 0x20 "CHPER,Timer E Chopper Register"
|
|
bitfld.long 0x20 7.--10. " STRTPW ,Timer E start pulsewidth" "40ns,80ns,120ns,160ns,200ns,240ns,280ns,320ns,360ns,400ns,440ns,480ns,520ns,560ns,600ns,640ns"
|
|
bitfld.long 0x20 4.--6. " CHPDTY ,Timer E chopper duty cycle value" "0/8,1/8,2/8,3/8,4/8,5/8,6/8,7/8"
|
|
bitfld.long 0x20 0.--3. " CHPFRQ ,Timer E carrier frequency value" "fHRTIM/16,fHRTIM/32,fHRTIM/48,fHRTIM/64,fHRTIM/80,fHRTIM/96,fHRTIM/112,fHRTIM/128,fHRTIM/144,fHRTIM/160,fHRTIM/176,fHRTIM/192,fHRTIM/208,fHRTIM/224,fHRTIM/240,fHRTIM/256"
|
|
line.long 0x24 "CPT1ECR,Timer E Capture 2 Control Register"
|
|
bitfld.long 0x24 27. " TDCMP2 ,Timer D compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 26. " TDCMP1 ,Timer D compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 25. " TD1RST ,Timer D output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 24. " TD1SET ,Timer D output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 23. " TCCMP2 ,Timer C compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 22. " TCCMP1 ,Timer C compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 21. " TC1RST ,Timer C output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 20. " TC1SET ,Timer C output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 19. " TBCMP2 ,Timer B compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 18. " TBCMP1 ,Timer B compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 17. " TB1RST ,Timer B output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 16. " TB1SET ,Timer B output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 15. " TACMP2 ,Timer A compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 14. " TACMP1 ,Timer A compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x24 13. " TA1RST ,Timer A output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 12. " TA1SET ,Timer A output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 11. " EXEV10CPT ,External event 10 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 10. " EXEV9CPT ,External event 9 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 9. " EXEV8CPT ,External event 8 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 8. " EXEV7CPT ,External event 7 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 7. " EXEV6CPT ,External event 6 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 6. " EXEV5CPT ,External event 5 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 5. " EXEV4CPT ,External event 4 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 4. " EXEV3CPT ,External event 3 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 3. " EXEV2CPT ,External event 2 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x24 2. " EXEV1CPT ,External event 1 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 1. " UDPCPT ,Update capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x24 0. " SWCPT ,Software capture" "Not forced,Forced"
|
|
line.long 0x28 "CPT2ECR,HRTIM Timer E Capture 2 Control Register"
|
|
bitfld.long 0x28 27. " TDCMP2 ,Timer D compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 26. " TDCMP1 ,Timer D compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 25. " TD1RST ,Timer D output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 24. " TD1SET ,Timer D output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 23. " TCCMP2 ,Timer C compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 22. " TCCMP1 ,Timer C compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 21. " TC1RST ,Timer C output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 20. " TC1SET ,Timer C output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 19. " TBCMP2 ,Timer B compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 18. " TBCMP1 ,Timer B compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 17. " TB1RST ,Timer B output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 16. " TB1SET ,Timer B output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 15. " TACMP2 ,Timer A compare 2 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 14. " TACMP1 ,Timer A compare 1 triggers capture 2" "Not triggered,Triggered"
|
|
bitfld.long 0x28 13. " TA1RST ,Timer A output 1 reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 12. " TA1SET ,Timer A output 1 set" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 11. " EXEV10CPT ,External event 10 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 10. " EXEV9CPT ,External event 9 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 9. " EXEV8CPT ,External event 8 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 8. " EXEV7CPT ,External event 7 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 7. " EXEV6CPT ,External event 6 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 6. " EXEV5CPT ,External event 5 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 5. " EXEV4CPT ,External event 4 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 4. " EXEV3CPT ,External event 3 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 3. " EXEV2CPT ,External event 2 capture trigger" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x28 2. " EXEV1CPT ,External event 1 capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 1. " UDPCPT ,Update capture trigger" "Not triggered,Triggered"
|
|
bitfld.long 0x28 0. " SWCPT ,Software capture" "Not forced,Forced"
|
|
textline " "
|
|
if (((per.l(ad:0x40017400)&0x200000)==0x200000))
|
|
if (((per.l(ad:0x40017400+0x280+0x64)&0x200)==0x200))
|
|
group.long (0x280+0x64)++0x3
|
|
line.long 0x00 "OUTER,Timer E Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
rbitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 8,Output 2 delayed Idle on external event 8,Output 1 and output 2 delayed Idle on external event 8,Balanced Idle on external event 8,Output 1 delayed Idle on external event 9,Output 2 delayed Idle on external event 9,Output 1 and output 2 delayed Idle on external event 9,Balanced Idle on external event 9"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
else
|
|
group.long (0x280+0x64)++0x3
|
|
line.long 0x00 "OUTER,Timer E Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 8,Output 2 delayed Idle on external event 8,Output 1 and output 2 delayed Idle on external event 8,Balanced Idle on external event 8,Output 1 delayed Idle on external event 9,Output 2 delayed Idle on external event 9,Output 1 and output 2 delayed Idle on external event 9,Balanced Idle on external event 9"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
rbitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
rbitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
endif
|
|
else
|
|
if (((per.l(ad:0x40017400+0x280+0x64)&0x200)==0x200))
|
|
group.long (0x280+0x64)++0x3
|
|
line.long 0x00 "OUTER,Timer E Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
rbitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 8,Output 2 delayed Idle on external event 8,Output 1 and output 2 delayed Idle on external event 8,Balanced Idle on external event 8,Output 1 delayed Idle on external event 9,Output 2 delayed Idle on external event 9,Output 1 and output 2 delayed Idle on external event 9,Balanced Idle on external event 9"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
else
|
|
group.long (0x280+0x64)++0x3
|
|
line.long 0x00 "OUTER,Timer E Output Register"
|
|
bitfld.long 0x00 23. " DIDL2 ,Output 2 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " CHP2 ,Output 2 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20.--21. " FAULT2 ,Output 2 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 19. " IDLES2 ,Output 2 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 18. " IDLEM2 ,Output 2 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 17. " POL2 ,Output 2 polarity" "Positive,Negative"
|
|
textline " "
|
|
bitfld.long 0x00 10.--12. " DLYPRT ,Delayed protection" "Output 1 delayed Idle on external event 8,Output 2 delayed Idle on external event 8,Output 1 and output 2 delayed Idle on external event 8,Balanced Idle on external event 8,Output 1 delayed Idle on external event 9,Output 2 delayed Idle on external event 9,Output 1 and output 2 delayed Idle on external event 9,Balanced Idle on external event 9"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DLYPRTEN ,Delayed protection enable" "No action,Enabled"
|
|
bitfld.long 0x00 8. " DTEN ,Deadtime enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DIDL1 ,Output 1 Deadtime upon burst mode idle entry" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " CHP1 ,Output 1 chopper enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " FAULT1 ,Output 1 fault state" "No action,Active,Inactive,High-Z"
|
|
bitfld.long 0x00 3. " IDLES1 ,Output 1 idle state" "Inactive,Active"
|
|
textline " "
|
|
bitfld.long 0x00 2. " IDLEM1 ,Output 1 idle mode" "No action,Idle"
|
|
bitfld.long 0x00 1. " POL1 ,Output 1 polarity" "Positive,Negative"
|
|
endif
|
|
endif
|
|
textline " "
|
|
group.long (0x280+0x68)++0x3
|
|
line.long 0x00 "FLTER,Timer E Fault Register"
|
|
bitfld.long 0x00 31. " FLTLCK ,Fault sources lock" "FLT1EN..FLT5EN read/write,FLT1EN..FLT5EN read only"
|
|
bitfld.long 0x00 4. " FLT5EN ,Fault 5 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FLT4EN ,Fault 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FLT3EN ,Fault 3 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT2EN ,Fault 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " FLT1EN ,Fault 1 enable" "Disabled,Enabled"
|
|
tree.end
|
|
width 9.
|
|
tree "Common"
|
|
group.long 0x380++0x7
|
|
line.long 0x00 "CR1,Control Register 1"
|
|
bitfld.long 0x00 25.--27. " AD4USRC ,ADC trigger 4 update source" "Master timer,Timer A,Timer B,Timer C,Timer D,Timer E,?..."
|
|
bitfld.long 0x00 22.--24. " AD3USRC ,ADC trigger 3 update source" "Master timer,Timer A,Timer B,Timer C,Timer D,Timer E,?..."
|
|
bitfld.long 0x00 19.--21. " AD2USRC ,ADC trigger 2 update source" "Master timer,Timer A,Timer B,Timer C,Timer D,Timer E,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--18. " AD1USRC ,ADC trigger 1 update source" "Master timer,Timer A,Timer B,Timer C,Timer D,Timer E,?..."
|
|
bitfld.long 0x00 5. " TEUDIS ,Timer E update disable" "No,Yes"
|
|
bitfld.long 0x00 4. " TDUDIS ,Timer D update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TCUDIS ,Timer C update disable" "No,Yes"
|
|
bitfld.long 0x00 2. " TBUDIS ,Timer B update disable" "No,Yes"
|
|
bitfld.long 0x00 1. " TAUDIS ,Timer A update disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MUDIS ,Master update disable" "No,Yes"
|
|
line.long 0x04 "CR2,Control Register 2"
|
|
bitfld.long 0x04 13. " TERST ,Timer E counter software reset" "No reset,Reset"
|
|
bitfld.long 0x04 12. " TDRST ,Timer D counter software reset" "No reset,Reset"
|
|
bitfld.long 0x04 11. " TCRST ,Timer C counter software reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 10. " TBRST ,Timer B counter software reset" "No reset,Reset"
|
|
bitfld.long 0x04 9. " TARST ,Timer A counter software reset" "No reset,Reset"
|
|
bitfld.long 0x04 8. " MRST ,Master counter software reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.long 0x04 5. " TESWU ,Timer E software update" "Disabled,Enabled"
|
|
bitfld.long 0x04 4. " TDSWU ,Timer D software update" "Disabled,Enabled"
|
|
bitfld.long 0x04 3. " TCSWU ,Timer C software update" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x04 2. " TBSWU ,Timer B software update" "Disabled,Enabled"
|
|
bitfld.long 0x04 1. " TASWU ,Timer A software update" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " MSWU ,Master timer software update" "Disabled,Enabled"
|
|
rgroup.long 0x388++0x03
|
|
line.long 0x00 "ISR,Interrupt Status Register"
|
|
sif (cpuis("STM32F334*"))
|
|
bitfld.long 0x00 17. " BMPER ,Burst mode period interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 16. " DLLRDY ,DLL ready interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " SYSFLT ,System fault interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FLT5 ,Fault 5 interrupt flag" "No interrupt,Interrupt"
|
|
else
|
|
bitfld.long 0x00 17. " BMPER ,Burst mode period interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 5. " SYSFLT ,System fault interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 4. " FLT5 ,Fault 5 interrupt flag" "No interrupt,Interrupt"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " FLT4 ,Fault 4 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 2. " FLT3 ,Fault 3 interrupt flag" "No interrupt,Interrupt"
|
|
bitfld.long 0x00 1. " FLT2 ,Fault 2 interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FLT1 ,Fault 1 interrupt flag" "No interrupt,Interrupt"
|
|
wgroup.long 0x38C++0x03
|
|
line.long 0x00 "ICR,Interrupt Clear Register"
|
|
sif (cpuis("STM32F334*"))
|
|
bitfld.long 0x00 17. " BMPER ,Burst mode period interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 16. " DLLRDY ,DLL ready interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " SYSFLT ,System fault interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FLT5 ,Fault 5 interrupt flag clear" "No effect,Clear"
|
|
else
|
|
bitfld.long 0x00 17. " BMPER ,Burst mode period interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 5. " SYSFLT ,System fault interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " FLT5 ,Fault 5 interrupt flag clear" "No effect,Clear"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " FLT4 ,Fault 4 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 2. " FLT3 ,Fault 3 interrupt flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 1. " FLT2 ,Fault 2 interrupt flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FLT1 ,Fault 1 interrupt flag clear" "No effect,Clear"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
sif (cpuis("STM32F334*"))
|
|
bitfld.long 0x00 17. " BMPER ,Burst mode period interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DLLRDY ,DLL ready interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYSFLT ,System fault interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FLT5 ,Fault 5 interrupt enable" "Disabled,Enabled"
|
|
else
|
|
bitfld.long 0x00 17. " BMPER ,Burst mode period interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " SYSFLT ,System fault interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " FLT5 ,Fault 5 interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x00 3. " FLT4 ,Fault 4 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " FLT3 ,Fault 3 interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " FLT2 ,Fault 2 interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FLT1 ,Fault 1 interrupt enable" "Disabled,Enabled"
|
|
sif (cpuis("STM32F334*"))
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "OENR,Output Enable Register"
|
|
bitfld.long 0x00 9. " TE2OEN ,Timer E output 2 enable" "No effect,Enable"
|
|
bitfld.long 0x00 8. " TE1OEN ,Timer E output 1 enable" "No effect,Enable"
|
|
bitfld.long 0x00 7. " TD2OEN ,Timer D output 2 enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TD1OEN ,Timer D output 1 enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " TC2OEN ,Timer C output 2 enable" "No effect,Enable"
|
|
bitfld.long 0x00 4. " TC1OEN ,Timer C output 1 enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TB2OEN ,Timer B output 2 enable" "No effect,Enable"
|
|
bitfld.long 0x00 2. " TB1OEN ,Timer B output 1 enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " TA2OEN ,Timer A output 2 enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TA1OEN ,Timer A output 1 enable" "No effect,Enable"
|
|
else
|
|
wgroup.long 0x394++0x03
|
|
line.long 0x00 "OENR,Output Enable Register"
|
|
bitfld.long 0x00 9. " TE2OEN ,Timer E output 2 enable" "No effect,Enable"
|
|
bitfld.long 0x00 8. " TE1OEN ,Timer E output 1 enable" "No effect,Enable"
|
|
bitfld.long 0x00 7. " TD2OEN ,Timer D output 2 enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TD1OEN ,Timer D output 1 enable" "No effect,Enable"
|
|
bitfld.long 0x00 5. " TC2OEN ,Timer C output 2 enable" "No effect,Enable"
|
|
bitfld.long 0x00 4. " TC1OEN ,Timer C output 1 enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TB2OEN ,Timer B output 2 enable" "No effect,Enable"
|
|
bitfld.long 0x00 2. " TB1OEN ,Timer B output 1 enable" "No effect,Enable"
|
|
bitfld.long 0x00 1. " TA2OEN ,Timer A output 2 enable" "No effect,Enable"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TA1OEN ,Timer A output 1 enable" "No effect,Enable"
|
|
endif
|
|
wgroup.long 0x398++0x03
|
|
line.long 0x00 "DISR,Output Disable Register"
|
|
bitfld.long 0x00 9. " TE2ODIS ,Timer E output 2 disable" "No,Yes"
|
|
bitfld.long 0x00 8. " TE1ODIS ,Timer E output 1 disable" "No,Yes"
|
|
bitfld.long 0x00 7. " TD2ODIS ,Timer D output 2 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TD1ODIS ,Timer D output 1 disable" "No,Yes"
|
|
bitfld.long 0x00 5. " TC2ODIS ,Timer C output 2 disable" "No,Yes"
|
|
bitfld.long 0x00 4. " TC1ODIS ,Timer C output 1 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TB2ODIS ,Timer B output 2 disable" "No,Yes"
|
|
bitfld.long 0x00 2. " TB1ODIS ,Timer B output 1 disable" "No,Yes"
|
|
bitfld.long 0x00 1. " TA2ODIS ,Timer A output 2 disable" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TA1ODIS ,Timer A output 1 disable" "No,Yes"
|
|
rgroup.long 0x39C++0x3
|
|
line.long 0x00 "ODSR,Output Disable Status Register"
|
|
bitfld.long 0x00 9. " TE2ODS ,Timer E output 2 disable status" "Idle,Failure"
|
|
bitfld.long 0x00 8. " TE1ODS ,Timer E output 1 disable status" "Idle,Failure"
|
|
bitfld.long 0x00 7. " TD2ODS ,Timer D output 2 disable status" "Idle,Failure"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TD1ODS ,Timer D output 1 disable status" "Idle,Failure"
|
|
bitfld.long 0x00 5. " TC2ODS ,Timer C output 2 disable status" "Idle,Failure"
|
|
bitfld.long 0x00 4. " TC1ODS ,Timer C output 1 disable status" "Idle,Failure"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TB2ODS ,Timer B output 2 disable status" "Idle,Failure"
|
|
bitfld.long 0x00 2. " TB1ODS ,Timer B output 1 disable status" "Idle,Failure"
|
|
bitfld.long 0x00 1. " TA2ODS ,Timer A output 2 disable status" "Idle,Failure"
|
|
textline " "
|
|
bitfld.long 0x00 0. " TA1ODS ,Timer A output 1 disable status" "Idle,Failure"
|
|
group.long 0x3A0++0x3
|
|
line.long 0x00 "BMCR,Burst Mode Control Register"
|
|
bitfld.long 0x00 31. " BMSTAT ,Burst mode status" "Normal op,Burst op"
|
|
bitfld.long 0x00 21. " TEBM ,Timer E burst mode" "Normal op,Op stopped"
|
|
bitfld.long 0x00 20. " TDBM ,Timer D burst mode" "Normal op,Op stopped"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TCBM ,Timer C burst mode" "Normal op,Op stopped"
|
|
bitfld.long 0x00 18. " TBBM ,Timer B burst mode" "Normal op,Op stopped"
|
|
bitfld.long 0x00 17. " TABM ,Timer A burst mode" "Normal op,Op stopped"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MTBM ,Master timer burst mode" "Normal op,Op stopped"
|
|
bitfld.long 0x00 10. " BMPREN ,Burst mode preload enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6.--9. " BMPRSC ,Burst mode prescaler" "Not divided,/2,/4,/8,/16,/32,/64,/128,/256,/512,/1024,/2048,/4096,/8192,/16384,/32768"
|
|
textline " "
|
|
bitfld.long 0x00 2.--5. " BMCLK ,Burst mode clock source" "Master,Timer A,Timer B,Timer C,Timer D,Timer E,On-chip event 1,On-chip event 2,On-chip event 3,On-chip event 4,Prescaled clock,?..."
|
|
bitfld.long 0x00 1. " BMOM ,Burst mode operating mode" "Single-shot,Continuous"
|
|
bitfld.long 0x00 0. " BME ,Burst mode enable" "Disabled,Enabled"
|
|
if (((per.l(ad:0x40017400+0x3A0)&0x01)==0x01))
|
|
group.long 0x3A4++0x3
|
|
line.long 0x00 "BMTRG,Burst Mode Trigger Register"
|
|
bitfld.long 0x00 31. " OCHPEV ,On-chip event" "Not triggered,Triggered"
|
|
bitfld.long 0x00 30. " EEV8 ,External event 8 conditioned by TIMD filters started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 29. " EEV7 ,External event 7 conditioned by TIMA filters started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TDEEV8 ,Timer D period following external event 8 started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 27. " TAEEV7 ,Timer A period following external event 7 started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 26. " TECMP2 ,Timer E compare 2 event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TECMP1 ,Timer E compare 1 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 24. " TEREP ,Timer E repetition event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 23. " TERST ,Timer E reset or roll-over event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TDCMP2 ,Timer D compare 2 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 21. " TDCMP1 ,Timer D compare 1 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 20. " TDREP ,Timer D repetition event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TDRST ,Timer D reset or roll-over event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 18. " TCCMP2 ,Timer C compare 2 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 17. " TCCMP1 ,Timer C compare 1 event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TCREP ,Timer C repetition event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 15. " TCRST ,Timer C reset or roll-over event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 14. " TBCMP2 ,Timer B compare 2 event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TBCMP1 ,Timer B compare 1 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 12. " TBREP ,Timer B repetition event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 11. " TBRST ,Timer B reset or roll-over event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TACMP2 ,Timer A compare 2 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 9. " TACMP1 ,Timer A compare 1 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 8. " TAREP ,Timer A repetition event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TARST ,Timer A reset or roll-over event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 6. " MSTCMP4 ,Master timer compare 4 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 5. " MSTCMP3 ,Master timer compare 3 event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MSTCMP2 ,Master timer compare 2 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 3. " MSTCMP1 ,Master timer compare 1 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 2. " MSTREP ,Master timer repetition event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTRST ,Master timer reset and roll-over event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 0. " SW ,Software start" "Not started,Started"
|
|
else
|
|
group.long 0x3A4++0x3
|
|
line.long 0x00 "BMTRG,Burst Mode Trigger Register"
|
|
bitfld.long 0x00 31. " OCHPEV ,On-chip event" "Not triggered,Triggered"
|
|
bitfld.long 0x00 30. " EEV8 ,External event 8 conditioned by TIMD filters started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 29. " EEV7 ,External event 7 conditioned by TIMA filters started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 28. " TDEEV8 ,Timer D period following external event 8 started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 27. " TAEEV7 ,Timer A period following external event 7 started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 26. " TECMP2 ,Timer E compare 2 event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 25. " TECMP1 ,Timer E compare 1 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 24. " TEREP ,Timer E repetition event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 23. " TERST ,Timer E reset or roll-over event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 22. " TDCMP2 ,Timer D compare 2 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 21. " TDCMP1 ,Timer D compare 1 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 20. " TDREP ,Timer D repetition event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 19. " TDRST ,Timer D reset or roll-over event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 18. " TCCMP2 ,Timer C compare 2 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 17. " TCCMP1 ,Timer C compare 1 event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 16. " TCREP ,Timer C repetition event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 15. " TCRST ,Timer C reset or roll-over event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 14. " TBCMP2 ,Timer B compare 2 event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 13. " TBCMP1 ,Timer B compare 1 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 12. " TBREP ,Timer B repetition event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 11. " TBRST ,Timer B reset or roll-over event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 10. " TACMP2 ,Timer A compare 2 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 9. " TACMP1 ,Timer A compare 1 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 8. " TAREP ,Timer A repetition event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TARST ,Timer A reset or roll-over event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 6. " MSTCMP4 ,Master timer compare 4 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 5. " MSTCMP3 ,Master timer compare 3 event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MSTCMP2 ,Master timer compare 2 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 3. " MSTCMP1 ,Master timer compare 1 event started burst mode" "Not started,Started"
|
|
bitfld.long 0x00 2. " MSTREP ,Master timer repetition event started burst mode" "Not started,Started"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MSTRST ,Master timer reset and roll-over event started burst mode" "Not started,Started"
|
|
endif
|
|
group.long 0x3A8++0x7
|
|
line.long 0x00 "BMCMPR,Burst Mode Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " BMCMP ,Burst mode compare value"
|
|
line.long 0x04 "BMPER,Burst Mode Period Register"
|
|
hexmask.long.word 0x04 0.--15. 1. " BMPER ,Burst mode Period"
|
|
group.long 0x3B0++0x1B
|
|
line.long 0x00 "EECR1,Timer External Event Control Register 1"
|
|
bitfld.long 0x00 29. " EE5FAST ,External event 5 fast mode" "Re-synchronized,Asynchronously"
|
|
bitfld.long 0x00 27.--28. " EE5SNS ,External event 5 sensitivity" "Active level,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 26. " EE5POL ,External event 5 polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 24.--25. " EE5SRC ,External event 5 source" "Hrtim_evt11,Hrtim_evt12,Hrtim_evt13,Hrtim_evt14"
|
|
bitfld.long 0x00 23. " EE4FAST ,External event 4 fast mode" "Re-synchronized,Asynchronously"
|
|
bitfld.long 0x00 21.--22. " EE4SNS ,External event 4 sensitivity" "Active level,Rising edge,Falling edge,Both edges"
|
|
textline " "
|
|
bitfld.long 0x00 20. " EE4POL ,External event 4 polarity" "High,Low"
|
|
bitfld.long 0x00 18.--19. " EE4SRC ,External Event 4 source" "Hrtim_evt11,Hrtim_evt12,Hrtim_evt13,Hrtim_evt14"
|
|
bitfld.long 0x00 17. " EE3FAST ,External event 3 fast mode" "Re-synchronized,Asynchronously"
|
|
textline " "
|
|
bitfld.long 0x00 15.--16. " EE3SNS ,External event 3 sensitivity" "Active level,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 14. " EE3POL ,External event 3 polarity" "High,Low"
|
|
bitfld.long 0x00 12.--13. " EE3SRC ,External event 3 source" "Hrtim_evt11,Hrtim_evt12,Hrtim_evt13,Hrtim_evt14"
|
|
textline " "
|
|
bitfld.long 0x00 11. " EE2FAST ,External event 2 fast mode" "Re-synchronized,Asynchronously"
|
|
bitfld.long 0x00 9.--10. " EE2SNS ,External event 2 sensitivity" "Active level,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x00 8. " EE2POL ,External event 2 polarity" "High,Low"
|
|
textline " "
|
|
bitfld.long 0x00 6.--7. " EE2SRC ,External event 2 source" "Hrtim_evt11,Hrtim_evt12,Hrtim_evt13,Hrtim_evt14"
|
|
bitfld.long 0x00 5. " EE1FAST ,External event 1 fast mode" "Re-synchronized,Asynchronously"
|
|
bitfld.long 0x00 3.--4. " EE1SNS ,External event 1 sensitivity" "Active level,Rising edge,Falling edge,Both edges"
|
|
textline " "
|
|
bitfld.long 0x00 2. " EE1POL ,External event 1 polarity" "High,Low"
|
|
bitfld.long 0x00 0.--1. " EE1SRC ,External event 1 source" "Hrtim_evt11,Hrtim_evt12,Hrtim_evt13,Hrtim_evt14"
|
|
line.long 0x04 "EECR2,Timer External Event Control Register 2"
|
|
bitfld.long 0x04 27.--28. " EE10SNS ,External event 10 sensitivity" "Active level,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x04 26. " EE10POL ,External event 10 polarity" "High,Low"
|
|
bitfld.long 0x04 24.--25. " EE10SRC ,External event 10 source" "Hrtim_evt11,Hrtim_evt12,Hrtim_evt13,Hrtim_evt14"
|
|
textline " "
|
|
bitfld.long 0x04 21.--22. " EE9SNS ,External event 9 sensitivity" "Active level,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x04 20. " EE9POL ,External event 9 polarity" "High,Low"
|
|
bitfld.long 0x04 18.--19. " EE9SRC ,External event 9 source" "Hrtim_evt11,Hrtim_evt12,Hrtim_evt13,Hrtim_evt14"
|
|
textline " "
|
|
bitfld.long 0x04 15.--16. " EE8SNS ,External event 8 sensitivity" "Active level,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x04 14. " EE8POL ,External event 8 polarity" "High,Low"
|
|
bitfld.long 0x04 12.--13. " EE8SRC ,External event 8 source" "Hrtim_evt11,Hrtim_evt12,Hrtim_evt13,Hrtim_evt14"
|
|
textline " "
|
|
bitfld.long 0x04 9.--10. " EE7SNS ,External event 7 sensitivity" "Active level,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x04 8. " EE7POL ,External event 7 polarity" "High,Low"
|
|
bitfld.long 0x04 6.--7. " EE7SRC ,External event 7 source" "Hrtim_evt11,Hrtim_evt12,Hrtim_evt13,Hrtim_evt14"
|
|
textline " "
|
|
bitfld.long 0x04 3.--4. " EE6SNS ,External event 6 sensitivity" "Active level,Rising edge,Falling edge,Both edges"
|
|
bitfld.long 0x04 2. " EE6POL ,External event 6 polarity" "High,Low"
|
|
bitfld.long 0x04 0.--1. " EE6SRC ,External event 6 source" "Hrtim_evt11,Hrtim_evt12,Hrtim_evt13,Hrtim_evt14"
|
|
line.long 0x08 "EECR3,Timer External Event Control Register 3"
|
|
bitfld.long 0x08 30.--31. " EEVSD ,External event sampling clock division" "fHRTIM,fHRTIM/2,fHRTIM/4,fHRTIM/8"
|
|
bitfld.long 0x08 24.--27. " EE10F ,External event 10 filter" "Disabled,fHRTIM N=2,fHRTIM N=4,fHRTIM N=8,fEEVS/2 N=6,fEEVS/2 N=8,fEEVS/4 N=6,fEEVS/4 N=8,fEEVS/8 N=6,fEEVS/8 N=8,fEEVS/16 N=5,fEEVS/16 N=6,fEEVS/16 N=8,fEEVS/32 N=5,fEEVS/32 N=6,fEEVS/32 N=8"
|
|
bitfld.long 0x08 18.--21. " EE9F ,External event 9 filter" "Disabled,fHRTIM N=2,fHRTIM N=4,fHRTIM N=8,fEEVS/2 N=6,fEEVS/2 N=8,fEEVS/4 N=6,fEEVS/4 N=8,fEEVS/8 N=6,fEEVS/8 N=8,fEEVS/16 N=5,fEEVS/16 N=6,fEEVS/16 N=8,fEEVS/32 N=5,fEEVS/32 N=6,fEEVS/32 N=8"
|
|
textline " "
|
|
bitfld.long 0x08 12.--15. " EE8F ,External event 8 filter" "Disabled,fHRTIM N=2,fHRTIM N=4,fHRTIM N=8,fEEVS/2 N=6,fEEVS/2 N=8,fEEVS/4 N=6,fEEVS/4 N=8,fEEVS/8 N=6,fEEVS/8 N=8,fEEVS/16 N=5,fEEVS/16 N=6,fEEVS/16 N=8,fEEVS/32 N=5,fEEVS/32 N=6,fEEVS/32 N=8"
|
|
bitfld.long 0x08 6.--9. " EE7F ,External event 7 filter" "Disabled,fHRTIM N=2,fHRTIM N=4,fHRTIM N=8,fEEVS/2 N=6,fEEVS/2 N=8,fEEVS/4 N=6,fEEVS/4 N=8,fEEVS/8 N=6,fEEVS/8 N=8,fEEVS/16 N=5,fEEVS/16 N=6,fEEVS/16 N=8,fEEVS/32 N=5,fEEVS/32 N=6,fEEVS/32 N=8"
|
|
bitfld.long 0x08 0.--3. " EE6F ,External event 6 filter" "Disabled,fHRTIM N=2,fHRTIM N=4,fHRTIM N=8,fEEVS/2 N=6,fEEVS/2 N=8,fEEVS/4 N=6,fEEVS/4 N=8,fEEVS/8 N=6,fEEVS/8 N=8,fEEVS/16 N=5,fEEVS/16 N=6,fEEVS/16 N=8,fEEVS/32 N=5,fEEVS/32 N=6,fEEVS/32 N=8"
|
|
line.long 0x0C "ADC1R,ADC Trigger 1 Register"
|
|
bitfld.long 0x0C 31. " AD1TEPER ,ADC trigger 1 on timer E period" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 30. " AD1TEC4 ,ADC trigger 1 on timer E compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 29. " AD1TEC3 ,ADC trigger 1 on timer E compare 3" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x0C 28. " AD1TEC2 ,ADC trigger 1 on timer E compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 27. " AD1TDPER ,ADC trigger 1 on timer D period" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 26. " AD1TDC4 ,ADC trigger 1 on timer D compare 4" "0,1"
|
|
textline " "
|
|
bitfld.long 0x0C 25. " AD1TDC3 ,ADC trigger 1 on timer D compare 3" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 24. " AD1TDC2 ,ADC trigger 1 on timer D compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 23. " AD1TCPER ,ADC trigger 1 on timer C period" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x0C 22. " AD1TCC4 ,ADC trigger 1 on timer C compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 21. " AD1TCC3 ,ADC trigger 1 on timer C compare 3" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 20. " AD1TCC2 ,ADC trigger 1 on timer C compare 2" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x0C 19. " AD1TBRST ,ADC trigger 1 on timer B reset" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 18. " AD1TBPER ,ADC trigger 1 on timer B period" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 17. " AD1TBC4 ,ADC trigger 1 on timer B compare 4" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x0C 16. " AD1TBC3 ,ADC trigger 1 on timer B compare 3" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 15. " AD1TBC2 ,ADC trigger 1 on timer B compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 14. " AD1TARST ,ADC trigger 1 on timer A reset" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x0C 13. " AD1TAPER ,ADC trigger 1 on timer A period" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 12. " AD1TAC4 ,ADC trigger 1 on timer A compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 11. " AD1TAC3 ,ADC trigger 1 on timer A compare 3" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x0C 10. " AD1TAC2 ,ADC trigger 1 on timer A compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 9. " AD1EEV5 ,ADC trigger 1 on external event 5" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 8. " AD1EEV4 ,ADC trigger 1 on external event 4" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x0C 7. " AD1EEV3 ,ADC trigger 1 on external event 3" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 6. " AD1EEV2 ,ADC trigger 1 on external event 2" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 5. " AD1EEV1 ,ADC trigger 1 on external event 1" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x0C 4. " AD1MPER ,ADC trigger 1 on master period" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 3. " AD1MC4 ,ADC trigger 1 on master compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 2. " AD1MC3 ,ADC trigger 1 on master compare 3" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x0C 1. " AD1MC2 ,ADC trigger 1 on master compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x0C 0. " AD1MC1 ,ADC trigger 1 on master compare 1" "Not triggered,Triggered"
|
|
line.long 0x10 "ADC2R,ADC Trigger 2 Register"
|
|
bitfld.long 0x10 31. " AD2TERST ,ADC trigger 2 on timer E reset" "Not triggered,Triggered"
|
|
bitfld.long 0x10 30. " AD2TEC4 ,ADC trigger 2 on timer E compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x10 29. " AD2TEC3 ,ADC trigger 2 on timer E compare 3" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x10 28. " AD2TEC2 ,ADC trigger 2 on timer E compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x10 27. " AD2TDRST ,ADC trigger 2 on timer D reset" "Not triggered,Triggered"
|
|
bitfld.long 0x10 26. " AD2TDPER ,ADC trigger 2 on timer D period" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x10 25. " AD2TDC4 ,ADC trigger 2 on timer D compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x10 24. " AD2TDC3 ,ADC trigger 2 on timer D compare 3" "Not triggered,Triggered"
|
|
bitfld.long 0x10 23. " AD2TDC2 ,ADC trigger 2 on timer D compare 2" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x10 22. " AD2TCRST ,ADC trigger 2 on timer C reset" "Not triggered,Triggered"
|
|
bitfld.long 0x10 21. " AD2TCPER ,ADC trigger 2 on timer C period" "Not triggered,Triggered"
|
|
bitfld.long 0x10 20. " AD2TCC4 ,ADC trigger 2 on timer C compare 4" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x10 19. " AD2TCC3 ,ADC trigger 2 on timer C compare 3" "Not triggered,Triggered"
|
|
bitfld.long 0x10 18. " AD2TCC2 ,ADC trigger 2 on timer C compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x10 17. " AD2TBPER ,ADC trigger 2 on timer B period" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x10 16. " AD2TBC4 ,ADC trigger 2 on timer B compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x10 15. " AD2TBC3 ,ADC trigger 2 on timer B compare 3" "Not triggered,Triggered"
|
|
bitfld.long 0x10 14. " AD2TBC2 ,ADC trigger 2 on timer B compare 2" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x10 13. " AD2TAPER ,ADC trigger 2 on timer A period" "Not triggered,Triggered"
|
|
bitfld.long 0x10 12. " AD2TAC4 ,ADC trigger 2 on timer A compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x10 11. " AD2TAC3 ,ADC trigger 2 on timer A compare 3" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x10 10. " AD2TAC2 ,ADC trigger 2 on timer A compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x10 9. " AD2EEV10 ,ADC trigger 2 on external event 10" "Not triggered,Triggered"
|
|
bitfld.long 0x10 8. " AD2EEV9 ,ADC trigger 2 on external event 9" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x10 7. " AD2EEV8 ,ADC trigger 2 on external event 8" "Not triggered,Triggered"
|
|
bitfld.long 0x10 6. " AD2EEV7 ,ADC trigger 2 on external event 7" "Not triggered,Triggered"
|
|
bitfld.long 0x10 5. " AD2EEV6 ,ADC trigger 2 on external event 6" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x10 4. " AD2MPER ,ADC trigger 2 on master period" "Not triggered,Triggered"
|
|
bitfld.long 0x10 3. " AD2MC4 ,ADC trigger 2 on master compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x10 2. " AD2MC3 ,ADC trigger 2 on master compare 3" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x10 1. " AD2MC2 ,ADC trigger 2 on master compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x10 0. " AD2MC1 ,ADC trigger 2 on master compare 1" "Not triggered,Triggered"
|
|
line.long 0x14 "ADC3R,ADC Trigger 3 Register"
|
|
bitfld.long 0x14 31. " ADC3TEPER ,ADC trigger 3 on timer E period" "Not triggered,Triggered"
|
|
bitfld.long 0x14 30. " ADC3TEC4 ,ADC trigger 3 on timer E compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x14 29. " ADC3TEC3 ,ADC trigger 3 on timer E compare 3" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x14 28. " ADC3TEC2 ,ADC trigger 3 on timer E compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x14 27. " ADC3TDPER ,ADC trigger 3 on timer D period" "Not triggered,Triggered"
|
|
bitfld.long 0x14 26. " ADC3TDC4 ,ADC trigger 3 on timer D compare 4" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ADC3TDC3 ,ADC trigger 3 on timer D compare 3" "Not triggered,Triggered"
|
|
bitfld.long 0x14 24. " ADC3TDC2 ,ADC trigger 3 on timer D compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x14 23. " ADC3TCPER ,ADC trigger 3 on timer C period" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x14 22. " ADC3TCC4 ,ADC trigger 3 on timer C compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x14 21. " ADC3TCC3 ,ADC trigger 3 on timer C compare 3" "Not triggered,Triggered"
|
|
bitfld.long 0x14 20. " ADC3TCC2 ,ADC trigger 3 on timer C compare 2" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ADC3TBRST ,ADC trigger 3 on timer B reset and counter roll-over" "Not triggered,Triggered"
|
|
bitfld.long 0x14 18. " ADC3TBPER ,ADC trigger 3 on timer B period" "Not triggered,Triggered"
|
|
bitfld.long 0x14 17. " ADC3TBC4 ,ADC trigger 3 on timer B compare 4" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x14 16. " ADC3TBC3 ,ADC trigger 3 on timer B compare 3" "Not triggered,Triggered"
|
|
bitfld.long 0x14 15. " ADC3TBC2 ,ADC trigger 3 on timer B compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x14 14. " ADC3TARST ,ADC trigger 3 on timer A reset and counter roll-over" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ADC3TAPER ,ADC trigger 3 on timer A period" "Not triggered,Triggered"
|
|
bitfld.long 0x14 12. " ADC3TAC4 ,ADC trigger 3 on timer A compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x14 11. " ADC3TAC3 ,ADC trigger 3 on timer A compare 3" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x14 10. " ADC3TAC2 ,ADC trigger 3 on timer A compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x14 9. " ADC3EEV5 ,ADC trigger 3 on external event 5" "Not triggered,Triggered"
|
|
bitfld.long 0x14 8. " ADC3EEV4 ,ADC trigger 3 on external event 4" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ADC3EEV3 ,ADC trigger 3 on external event 3" "Not triggered,Triggered"
|
|
bitfld.long 0x14 6. " ADC3EEV2 ,ADC trigger 3 on external event 2" "Not triggered,Triggered"
|
|
bitfld.long 0x14 5. " ADC3EEV1 ,ADC trigger 3 on external event 1" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x14 4. " ADC3MPER ,ADC trigger 3 on master period" "Not triggered,Triggered"
|
|
bitfld.long 0x14 3. " ADC3MC4 ,ADC trigger 3 on master compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x14 2. " ADC3MC3 ,ADC trigger 3 on master compare 3" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ADC3MC2 ,ADC trigger 3 on master compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x14 0. " ADC3MC1 ,ADC trigger 3 on master compare 1" "Not triggered,Triggered"
|
|
line.long 0x18 "ADC4R,ADC Trigger 4 Register"
|
|
bitfld.long 0x18 31. " ADC4TERST ,ADC trigger 4 on timer E Reset and counter roll-over" "Not triggered,Triggered"
|
|
bitfld.long 0x18 30. " ADC4TEC4 ,ADC trigger 4 on timer E compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x18 29. " ADC4TEC3 ,ADC trigger 4 on timer E compare 3" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x18 28. " ADC4TEC2 ,ADC trigger 4 on timer E compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x18 27. " ADC4TDRST ,ADC trigger 4 on timer D reset and counter roll-over" "Not triggered,Triggered"
|
|
bitfld.long 0x18 26. " ADC4TDPER ,ADC trigger 4 on timer D period" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ADC4TDC4 ,ADC trigger 4 on timer D compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x18 24. " ADC4TDC3 ,ADC trigger 4 on Timer D Compare 3" "Not triggered,Triggered"
|
|
bitfld.long 0x18 23. " ADC4TDC2 ,ADC trigger 2 on timer D compare 2" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x18 22. " ADC4TCRST ,ADC trigger 4 on timer C reset and counter roll-over" "Not triggered,Triggered"
|
|
bitfld.long 0x18 21. " ADC4TCPER ,ADC trigger 4 on timer C period" "Not triggered,Triggered"
|
|
bitfld.long 0x18 20. " ADC4TCC4 ,ADC trigger 4 on timer C compare 4" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ADC4TCC3 ,ADC trigger 4 on timer C compare 3" "Not triggered,Triggered"
|
|
bitfld.long 0x18 18. " ADC4TCC2 ,ADC trigger 4 on timer C compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x18 17. " ADC4TBPER ,ADC trigger 4 on timer B period" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x18 16. " ADC4TBC4 ,ADC trigger 4 on timer B compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x18 15. " ADC4TBC3 ,ADC trigger 4 on timer B compare 3" "Not triggered,Triggered"
|
|
bitfld.long 0x18 14. " ADC4TBC2 ,ADC trigger 4 on timer B compare 2" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ADC4TAPER ,ADC trigger 4 on timer A period" "Not triggered,Triggered"
|
|
bitfld.long 0x18 12. " ADC4TAC4 ,ADC trigger 4 on timer A compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x18 11. " ADC4TAC3 ,ADC trigger 4 on timer A compare 3" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x18 10. " ADC4TAC2 ,ADC trigger 4 on timer A compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x18 9. " ADC4EEV10 ,ADC trigger 4 on external event 10" "Not triggered,Triggered"
|
|
bitfld.long 0x18 8. " ADC4EEV9 ,ADC trigger 4 on external event 9" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ADC4EEV8 ,ADC trigger 4 on external event 8" "Not triggered,Triggered"
|
|
bitfld.long 0x18 6. " ADC4EEV7 ,ADC trigger 4 on external event 7" "Not triggered,Triggered"
|
|
bitfld.long 0x18 5. " ADC4EEV6 ,ADC trigger 4 on external event 6" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x18 4. " ADC4MPER ,ADC trigger 4 on master period" "Not triggered,Triggered"
|
|
bitfld.long 0x18 3. " ADC4MC4 ,ADC trigger 4 on master compare 4" "Not triggered,Triggered"
|
|
bitfld.long 0x18 2. " ADC4MC3 ,ADC trigger 4 on master compare 3" "Not triggered,Triggered"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ADC4MC2 ,ADC trigger 4 on master compare 2" "Not triggered,Triggered"
|
|
bitfld.long 0x18 0. " ADC4MC1 ,ADC trigger 4 on master compare 1" "Not triggered,Triggered"
|
|
sif (cpuis("STM32F334*"))
|
|
group.long 0x3CC++0x3
|
|
line.long 0x00 "DLLCR,HRTIM DLL Control Register"
|
|
bitfld.long 0x00 2.--3. " CALRTE ,DLL calibration rate" "7.3 ms,910 us,114 us,14 us"
|
|
bitfld.long 0x00 1. " CALEN ,DLL calibration enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " CAL ,DLL calibration start" "No effect,Start"
|
|
endif
|
|
group.long 0x3D0++0xB
|
|
line.long 0x00 "FLTINR1,HRTIM Fault Input Register 1"
|
|
bitfld.long 0x00 31. " FLT4LCK ,Fault 4 lock" "Read/write,Read-only"
|
|
bitfld.long 0x00 27.--30. " FLT4F ,Fault 4 filter" "Disabled,fHRTIM N=2,fHRTIM N=4,fHRTIM N=8,fEEVS/2 N=6,fEEVS/2 N=8,fEEVS/4 N=6,fEEVS/4 N=8,fEEVS/8 N=6,fEEVS/8 N=8,fEEVS/16 N=5,fEEVS/16 N=6,fEEVS/16 N=8,fEEVS/32 N=5,fEEVS/32 N=6,fEEVS/32 N=8"
|
|
bitfld.long 0x00 26. " FLT4SRC ,Fault 4 source" "PB3,NC"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FLT4P ,Fault 5 polarity" "Low,High"
|
|
bitfld.long 0x00 24. " FLT4E ,Fault 4 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " FLT3LCK ,Fault 3 lock" "Read/write,Read-only"
|
|
textline " "
|
|
bitfld.long 0x00 19.--22. " FLT3F ,Fault 3 filter" "Disabled,fHRTIM N=2,fHRTIM N=4,fHRTIM N=8,fEEVS/2 N=6,fEEVS/2 N=8,fEEVS/4 N=6,fEEVS/4 N=8,fEEVS/8 N=6,fEEVS/8 N=8,fEEVS/16 N=5,fEEVS/16 N=6,fEEVS/16 N=8,fEEVS/32 N=5,fEEVS/32 N=6,fEEVS/32 N=8"
|
|
bitfld.long 0x00 18. " FLT3SRC ,Fault 3 source" "PD4,NC"
|
|
bitfld.long 0x00 17. " FLT3P ,Fault 3 polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " FLT3E ,Fault 3 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " FLT2LCK ,Fault 2 lock" "Read/write,Read-only"
|
|
bitfld.long 0x00 11.--14. " FLT2F ,Fault 2 filter" "Disabled,fHRTIM N=2,fHRTIM N=4,fHRTIM N=8,fEEVS/2 N=6,fEEVS/2 N=8,fEEVS/4 N=6,fEEVS/4 N=8,fEEVS/8 N=6,fEEVS/8 N=8,fEEVS/16 N=5,fEEVS/16 N=6,fEEVS/16 N=8,fEEVS/32 N=5,fEEVS/32 N=6,fEEVS/32 N=8"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FLT2SRC ,Fault 2 source" "PC11,COMP2"
|
|
bitfld.long 0x00 9. " FLT2P ,Fault 2 polarity" "Low,High"
|
|
bitfld.long 0x00 8. " FLT2E ,Fault 2 enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FLT1LCK ,Fault 1 lock" "Read/write,Read-only"
|
|
bitfld.long 0x00 3.--6. " FLT1F ,Fault 1 filter" "Disabled,fHRTIM N=2,fHRTIM N=4,fHRTIM N=8,fEEVS/2 N=6,fEEVS/2 N=8,fEEVS/4 N=6,fEEVS/4 N=8,fEEVS/8 N=6,fEEVS/8 N=8,fEEVS/16 N=5,fEEVS/16 N=6,fEEVS/16 N=8,fEEVS/32 N=5,fEEVS/32 N=6,fEEVS/32 N=8"
|
|
bitfld.long 0x00 2. " FLT1SRC ,Fault 1 source" "PA15,COMP1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FLT1P ,Fault 1 polarity" "Low,High"
|
|
bitfld.long 0x00 0. " FLT1E ,Fault 1 enable" "Disabled,Enabled"
|
|
line.long 0x04 "FLTINR2,HRTIM Fault Input Register 2"
|
|
bitfld.long 0x04 24.--25. " FLTSD ,Fault sampling clock division" "fHRTIM,fHRTIM/2,fHRTIM/4,fHRTIM/8"
|
|
bitfld.long 0x04 7. " FLT5LCK ,Fault 5 lock" "Read/write,Read-only"
|
|
bitfld.long 0x04 3.--6. " FLT5F ,Fault 5 filter" "Disabled,fHRTIM N=2,fHRTIM N=4,fHRTIM N=8,fEEVS/2 N=6,fEEVS/2 N=8,fEEVS/4 N=6,fEEVS/4 N=8,fEEVS/8 N=6,fEEVS/8 N=8,fEEVS/16 N=5,fEEVS/16 N=6,fEEVS/16 N=8,fEEVS/32 N=5,fEEVS/32 N=6,fEEVS/32 N=8"
|
|
textline " "
|
|
bitfld.long 0x04 2. " FLT5SRC ,Fault 5 source" "PG10,NC"
|
|
bitfld.long 0x04 1. " FLT5P ,Fault 5 polarity" "Low,High"
|
|
bitfld.long 0x04 0. " FLT5E ,Fault 5 enable" "Disabled,Enabled"
|
|
line.long 0x08 "BDMUPDR,HRTIM Burst DMA Master Timer Update Register"
|
|
bitfld.long 0x08 9. " MCMP4 ,MCMP4R register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 8. " MCMP3 ,MCMP3R register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 7. " MCMP2 ,MCMP2R register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 6. " MCMP1 ,MCMP1R register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 5. " MREP ,MREP register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 4. " MPER ,MPER register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 3. " MCNT ,MCNTR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 2. " MDIER ,MDIER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 1. " MICR ,MICR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x08 0. " MCR ,MCR register update enable" "Disabled,Enabled"
|
|
group.long 0x3DC++0x03
|
|
line.long 0x00 "BDTAUPR,Burst DMA Timer A Update Register"
|
|
bitfld.long 0x00 20. " TIMAFLTR ,HRTIM_FLTAR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TIMAOUTR ,HRTIM_OUTAR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TIMACHPR ,HRTIM_CHPAR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TIMARSTR ,HRTIM_RSTAR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TIMAEEFR2 ,HRTIM_EEFAR2 register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TIMAEEFR1 ,HRTIM_EEFAR1 register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TIMARST2R ,HRTIM_RST2AR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TIMASET2R ,HRTIM_SET2AR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIMARST1R ,HRTIM_RST1AR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TIMASET1R ,HRTIM_SET1AR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIMA_DTR ,HRTIM_DTAR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIMACMP4 ,HRTIM_CMP4AR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMACMP3 ,HRTIM_CMP3AR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TIMACMP2 ,HRTIM_CMP2AR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TIMACMP1 ,HRTIM_CMP1AR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIMAREP ,HRTIM_REPAR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TIMAPER ,HRTIM_PERAR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIMACNT ,HRTIM_CNTAR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIMADIER ,HRTIM_TIMADIER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMAICR ,HRTIM_TIMAICR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TIMACR ,HRTIM_TIMACR register update enable" "Disabled,Enabled"
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "BDTBUPR,Burst DMA Timer B Update Register"
|
|
bitfld.long 0x00 20. " TIMBFLTR ,HRTIM_FLTBR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TIMBOUTR ,HRTIM_OUTBR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TIMBCHPR ,HRTIM_CHPBR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TIMBRSTR ,HRTIM_RSTBR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TIMBEEFR2 ,HRTIM_EEFBR2 register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TIMBEEFR1 ,HRTIM_EEFBR1 register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TIMBRST2R ,HRTIM_RST2BR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TIMBSET2R ,HRTIM_SET2BR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIMBRST1R ,HRTIM_RST1BR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TIMBSET1R ,HRTIM_SET1BR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIMB_DTR ,HRTIM_DTBR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIMBCMP4 ,HRTIM_CMP4BR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMBCMP3 ,HRTIM_CMP3BR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TIMBCMP2 ,HRTIM_CMP2BR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TIMBCMP1 ,HRTIM_CMP1BR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIMBREP ,HRTIM_REPBR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TIMBPER ,HRTIM_PERBR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIMBCNT ,HRTIM_CNTBR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIMBDIER ,HRTIM_TIMBDIER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMBICR ,HRTIM_TIMBICR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TIMBCR ,HRTIM_TIMBCR register update enable" "Disabled,Enabled"
|
|
group.long 0x3E4++0x03
|
|
line.long 0x00 "BDTCUPR,Burst DMA Timer C Update Register"
|
|
bitfld.long 0x00 20. " TIMCFLTR ,HRTIM_FLTCR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TIMCOUTR ,HRTIM_OUTCR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TIMCCHPR ,HRTIM_CHPCR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TIMCRSTR ,HRTIM_RSTCR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TIMCEEFR2 ,HRTIM_EEFCR2 register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TIMCEEFR1 ,HRTIM_EEFCR1 register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TIMCRST2R ,HRTIM_RST2CR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TIMCSET2R ,HRTIM_SET2CR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIMCRST1R ,HRTIM_RST1CR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TIMCSET1R ,HRTIM_SET1CR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIMC_DTR ,HRTIM_DTCR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIMCCMP4 ,HRTIM_CMP4CR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMCCMP3 ,HRTIM_CMP3CR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TIMCCMP2 ,HRTIM_CMP2CR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TIMCCMP1 ,HRTIM_CMP1CR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIMCREP ,HRTIM_REPCR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TIMCPER ,HRTIM_PERCR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIMCCNT ,HRTIM_CNTCR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIMCDIER ,HRTIM_TIMCDIER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMCICR ,HRTIM_TIMCICR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TIMCCR ,HRTIM_TIMCCR register update enable" "Disabled,Enabled"
|
|
group.long 0x3E8++0x03
|
|
line.long 0x00 "BDTDUPR,Burst DMA Timer D Update Register"
|
|
bitfld.long 0x00 20. " TIMDFLTR ,HRTIM_FLTDR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TIMDOUTR ,HRTIM_OUTDR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TIMDCHPR ,HRTIM_CHPDR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TIMDRSTR ,HRTIM_RSTDR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TIMDEEFR2 ,HRTIM_EEFDR2 register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TIMDEEFR1 ,HRTIM_EEFDR1 register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TIMDRST2R ,HRTIM_RST2DR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TIMDSET2R ,HRTIM_SET2DR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIMDRST1R ,HRTIM_RST1DR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TIMDSET1R ,HRTIM_SET1DR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIMD_DTR ,HRTIM_DTDR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIMDCMP4 ,HRTIM_CMP4DR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMDCMP3 ,HRTIM_CMP3DR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TIMDCMP2 ,HRTIM_CMP2DR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TIMDCMP1 ,HRTIM_CMP1DR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIMDREP ,HRTIM_REPDR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TIMDPER ,HRTIM_PERDR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIMDCNT ,HRTIM_CNTDR register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIMDDIER ,HRTIM_TIMDDIER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMDICR ,HRTIM_TIMDICR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TIMDCR ,HRTIM_TIMDCR register update enable" "Disabled,Enabled"
|
|
group.long 0x3EC++0x03
|
|
line.long 0x00 "BDTEUPR,Burst DMA Timer E Update Register"
|
|
bitfld.long 0x00 20. " TIMEFLTR ,HRTIM_FLTER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " TIMEOUTR ,HRTIM_OUTER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " TIMECHPR ,HRTIM_CHPER register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " TIMERSTR ,HRTIM_RSTER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " TIMEEEFR2 ,HRTIM_EEFER2 register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " TIMEEEFR1 ,HRTIM_EEFER1 register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TIMERST2R ,HRTIM_RST2ER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " TIMESET2R ,HRTIM_SET2ER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIMERST1R ,HRTIM_RST1ER register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " TIMESET1R ,HRTIM_SET1ER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TIME_DTR ,HRTIM_DTER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TIMECMP4 ,HRTIM_CMP4ER register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TIMECMP3 ,HRTIM_CMP3ER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " TIMECMP2 ,HRTIM_CMP2ER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TIMECMP1 ,HRTIM_CMP1ER register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TIMEREP ,HRTIM_REPER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " TIMEPER ,HRTIM_PERER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TIMECNT ,HRTIM_CNTER register update enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " TIMEDIER ,HRTIM_TIMEDIER register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TIMEICR ,HRTIM_TIMEICR register update enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " TIMECR ,HRTIM_TIMECR register update enable" "Disabled,Enabled"
|
|
wgroup.long 0x3F0++0x3
|
|
line.long 0x00 "BDMADR,Burst DMA Data Register"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
tree "IWDG (Independent watchdog)"
|
|
base ad:0x40003000
|
|
width 11.
|
|
wgroup.long 0x00++0x3
|
|
line.long 0x00 "IWDG_KR,Key register"
|
|
hexmask.long.word 0x00 0.--15. 1. " KEY ,Key value"
|
|
group.long 0x04++0x7
|
|
line.long 0x00 "IWDG_PR,Prescaler register"
|
|
bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256"
|
|
line.long 0x04 "IWDG_RLR,Reload register"
|
|
hexmask.long.word 0x04 0.--11. 1. " RL ,Watchdog counter reload value"
|
|
rgroup.long 0x0C++0x3
|
|
line.long 0x00 "IWDG_SR,Status register"
|
|
bitfld.long 0x00 2. " WVU ,Watchdog counter window value update" "Completed,Running"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RVU ,Watchdog counter reload value update" "Completed,Running"
|
|
bitfld.long 0x00 0. " PVU ,Watchdog prescaler value update" "Completed,Running"
|
|
group.long 0x10++0x3
|
|
line.long 0x00 "IWDG_WINR,Window register"
|
|
hexmask.long.word 0x00 0.--11. 1. " WIN[11:0] ,Watchdog counter window value"
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "IWDG (Independent watchdog)"
|
|
base ad:0x40003000
|
|
width 11.
|
|
wgroup.long 0x00++0x03
|
|
line.long 0x00 "IWDG_KR,Key Register"
|
|
hexmask.long.word 0x00 0.--15. 1. " KEY ,Key value"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "IWDG_PR,Prescaler Register"
|
|
bitfld.long 0x00 0.--2. " PR ,Prescaler divider" "/4,/8,/16,/32,/64,/128,/256,/256"
|
|
line.long 0x04 "IWDG_RLR,Reload Register"
|
|
hexmask.long.word 0x04 0.--11. 1. " RL ,Watchdog counter reload value"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "IWDG_SR,Status Register"
|
|
sif ((cpu()=="STM32F050C4")||(cpu()=="STM32F050C6")||(cpu()=="STM32F050K4")||(cpu()=="STM32F050K6")||(cpu()=="STM32F051C4")||(cpu()=="STM32F051C6")||(cpu()=="STM32F051C8")||(cpu()=="STM32F051K4")||(cpu()=="STM32F051K6")||(cpu()=="STM32F051K8")||(cpu()=="STM32F051R4")||(cpu()=="STM32F051R6")||(cpu()=="STM32F051R8")||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpuis("STM32F7*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB"))
|
|
bitfld.long 0x00 2. " WVU ,Watchdog counter window value update" "Completed,Running"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " RVU ,Watchdog counter reload value update" "Completed,Running"
|
|
bitfld.long 0x00 0. " PVU ,Watchdog prescaler value update" "Completed,Running"
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8"||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||(cpuis("STM32F7*"))||cpuis("STM32F038?6")||cpuis("STM32F048?6")||cpuis("STM32F058?8")||cpuis("STM32F078?B")||cpuis("STM32F091*")||cpuis("STM32F098*")||cpuis("STM32F031E6")||cpuis("STM32F038E6")||cpuis("STM32F051T8")||cpuis("STM32F058T8")||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB"))
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IWDG_WINR,Window Register"
|
|
hexmask.long.word 0x00 0.--11. 1. " WIN ,Watchdog counter window value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "WWDG (System window watchdog)"
|
|
base ad:0x40002C00
|
|
width 10.
|
|
group.long 0x00++0x0B
|
|
line.long 0x00 "WWDG_CR,Control Register"
|
|
bitfld.long 0x00 7. " WDGA ,Activation bit" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " T ,7-bit counter"
|
|
line.long 0x04 "WWDG_CFR,Configuration Register"
|
|
bitfld.long 0x04 9. " EWI ,Early wakeup interrupt" "No interrupt,Interrupt"
|
|
bitfld.long 0x04 7.--8. " WDGTB ,Timer base" "Div by 1,Div by 2,Div by 4,Div by 8"
|
|
textline " "
|
|
hexmask.long.byte 0x04 0.--6. 1. " W ,7-bit window value"
|
|
line.long 0x08 "WWDG_SR,Status Register"
|
|
bitfld.long 0x08 0. " EWIF ,Early wakeup interrupt flag" "No interrupt,Interrupt"
|
|
width 0x0B
|
|
tree.end
|
|
tree "RTC (Real-time clock)"
|
|
base ad:0x40002800
|
|
width 14.
|
|
if (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800)&0x300000)!=0x200000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_TR,RTC time register"
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800)&0x300000)==0x200000))
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_TR,RTC time register"
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
elif ((per.l(ad:0x40002800)&0x300000)==0x100000)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_TR,RTC time register"
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "RTC_TR,RTC time register"
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 20.--21. " HT ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
endif
|
|
if (((per.l(ad:0x40002800+0x04)&0x30)==0x30)&&((per.l(ad:0x40002800+0x04)&0x1000)==0x1000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_DR,RTC date register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. " DU ,Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12. " MT ,Month tens in BCD format" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MU ,Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 20.--23. " YT ,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 16.--19. " YT ,Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
elif (((per.l(ad:0x40002800+0x04)&0x30)==0x30)&&((per.l(ad:0x40002800+0x04)&0x1000)==0x0))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_DR,RTC date register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. " DU ,Date units in BCD format" "0,1,-,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12. " MT ,Month tens in BCD format" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MU ,Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
bitfld.long 0x00 20.--23. " YT ,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 16.--19. " YT ,Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
elif (((per.l(ad:0x40002800+0x04)&0x30)!=0x30)&&((per.l(ad:0x40002800+0x04)&0x1000)==0x1000))
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_DR,RTC date register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
bitfld.long 0x00 12. " MT ,Month tens in BCD format" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MU ,Month units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 20.--23. " YT ,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 16.--19. " YT ,Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RTC_DR,RTC date register"
|
|
bitfld.long 0x00 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x00 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 0.--3. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
bitfld.long 0x00 12. " MT ,Month tens in BCD format" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MU ,Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
bitfld.long 0x00 20.--23. " YT ,Year tens in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,-,?..."
|
|
bitfld.long 0x00 16.--19. " YT ,Year units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,-,?..."
|
|
endif
|
|
textline " "
|
|
if (((per.l(ad:0x40002800+0x0C))&0x04)==0x04)&&(((per.l(ad:0x40002800+0x08))&0x400)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_CR,RTC Control Register"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,Alarm A,Alarm B,Wakeup"
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
textline " "
|
|
bitfld.long 0x00 18. " BKP ,Backup" "Not performed,Performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted"
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added"
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TSE ,Time stamp enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FMT ,Hour format" "24 hour/day,AM/PM"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 4. " REFCKON ,RTC_REFIN reference clock detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,CK_SPRE,CK_SPRE,CK_SPRE/WUT+2^16,CK_SPRE/WUT+2^16"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "RTC_CR,RTC Control Register"
|
|
bitfld.long 0x00 23. " COE ,Calibration output enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 21.--22. " OSEL ,Output selection" "Disabled,Alarm A,Alarm B,Wakeup"
|
|
bitfld.long 0x00 20. " POL ,Output polarity" "High,Low"
|
|
bitfld.long 0x00 19. " COSEL ,Calibration output selection" "512Hz,1Hz"
|
|
textline " "
|
|
bitfld.long 0x00 18. " BKP ,Backup" "Not performed,Performed"
|
|
bitfld.long 0x00 17. " SUB1H ,Subtract 1 hour (winter time change)" "No effect,Subtracted"
|
|
bitfld.long 0x00 16. " ADD1H ,Add 1 hour (summer time change)" "No effect,Added"
|
|
bitfld.long 0x00 15. " TSIE ,Time-stamp interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " WUTIE ,Wakeup timer interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ALRBIE ,Alarm B interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ALRAIE ,Alarm A interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TSE ,Time stamp enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " WUTE ,Wakeup timer enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBE ,Alarm B enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ALRAE ,Alarm A enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " FMT ,Hour format" "24 hour/day,AM/PM"
|
|
textline " "
|
|
bitfld.long 0x00 5. " BYPSHAD ,Bypass the shadow registers" "Not bypassed,Bypassed"
|
|
bitfld.long 0x00 4. " REFCKON ,RTC_REFIN reference clock detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " TSEDGE ,Time-stamp event active edge" "Rising edge,Falling edge"
|
|
rbitfld.long 0x00 0.--2. " WUCKSEL ,Wakeup clock selection" "RTC/16,RTC/8,RTC/4,RTC/2,CK_SPRE,CK_SPRE,CK_SPRE/WUT+2^16,CK_SPRE/WUT+2^16"
|
|
endif
|
|
if (((per.l(ad:0x40002800+0x0C))&0x04)==0x04)&&(((per.l(ad:0x40002800+0x08))&0x400)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RTC_ISR,RTC Initialization And Status Register"
|
|
bitfld.long 0x00 16. " RECALPF ,Recalibration pending flag" "Not detected,Detected"
|
|
bitfld.long 0x00 15. " TAMP3F ,RTC_TAMP3 detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " TAMP2F ,RTC_TAMP2 detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " TAMP1F ,RTC_TAMP1 detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TSOVF ,Time-stamp overflow flag" "Not overflowed,Overflowed"
|
|
bitfld.long 0x00 11. " TSF ,Time-stamp flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " WUTF ,Wakeup timer flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBF ,Alarm B flag enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ALRAF ,Alarm A flag enable" "Diasbled,Enabled"
|
|
bitfld.long 0x00 7. " INIT ,Initialization mode" "Free running,Enabled"
|
|
rbitfld.long 0x00 6. " INITF ,Initialization flag" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " RSF ,Registers synchronization flag" "Not synchronized,Synchronized"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " INITS ,Initialization status flag" "Not initialized,Initialized"
|
|
rbitfld.long 0x00 3. " SHPF ,Shift operation pending" "Not pending,Pending"
|
|
bitfld.long 0x00 2. " WUTWF ,Wakeup timer write flag" "Not allowed,Allowed"
|
|
rbitfld.long 0x00 1. " ALRBWF ,Alarm B write flag" "Not allowed,Allowed"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " ALRAWF ,Alarm A write flag" "Not allowed,Allowed"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RTC_ISR,RTC Initialization And Status Register"
|
|
bitfld.long 0x00 16. " RECALPF ,Recalibration pending flag" "Not detected,Detected"
|
|
bitfld.long 0x00 15. " TAMP3F ,RTC_TAMP3 detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 14. " TAMP2F ,RTC_TAMP2 detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 13. " TAMP1F ,RTC_TAMP1 detection flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 12. " TSOVF ,Time-stamp overflow flag" "Not overflowed,Overflowed"
|
|
bitfld.long 0x00 11. " TSF ,Time-stamp flag" "Not occurred,Occurred"
|
|
bitfld.long 0x00 10. " WUTF ,Wakeup timer flag enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ALRBF ,Alarm B flag enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " ALRAF ,Alarm A flag enable" "Diasbled,Enabled"
|
|
bitfld.long 0x00 7. " INIT ,Initialization mode" "Free running,Enabled"
|
|
rbitfld.long 0x00 6. " INITF ,Initialization flag" "Not allowed,Allowed"
|
|
bitfld.long 0x00 5. " RSF ,Registers synchronization flag" "Not synchronized,Synchronized"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " INITS ,Initialization status flag" "Not initialized,Initialized"
|
|
rbitfld.long 0x00 3. " SHPF ,Shift operation pending" "Not pending,Pending"
|
|
rbitfld.long 0x00 2. " WUTWF ,Wakeup timer write flag" "Not allowed,Allowed"
|
|
rbitfld.long 0x00 1. " ALRBWF ,Alarm B write flag" "Not allowed,Allowed"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " ALRAWF ,Alarm A write flag" "Not allowed,Allowed"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RTC_PRER,RTC Prescaler Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. " PREDIV_A ,Asynchronous prescaler factor"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--14. 1. " PREDIV_S ,Synchronous prescaler factor"
|
|
if (((per.l(ad:0x40002800+0x0C))&0x04)==0x04)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WUT ,Wakeup auto-reload value bits"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "RTC_WUTR,RTC wakeup timer register"
|
|
hexmask.long.word 0x00 0.--15. 1. " WUT ,Wakeup auto-reload value bits"
|
|
endif
|
|
textline " "
|
|
if (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,PM,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x1C)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)!=0x00))
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Day unit,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x1C)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x81)==0x00))
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Day unit,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
elif ((per.l(ad:0x40002800+0x0C)&0x81)!=0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Day unit,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
else
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "RTC_ALRMAR,RTC alarm A register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Day unit,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm A date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm A hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm A minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm A seconds mask" "Not masked,Masked"
|
|
endif
|
|
if (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00))
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)!=0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00))
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00))
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x8)&0x40)==0x0)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x200000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00))
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x300000)==0x100000)&&((per.l(ad:0x40002800+0x20)&0x40000000)==0x40000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00))
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,-,-,-,-,-,-,-,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Date units,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)!=0x00))
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Day unit,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif (((per.l(ad:0x40002800+0x20)&0x40000000)==0x00000000)&&((per.l(ad:0x40002800+0x0C)&0x82)==0x00))
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 28.--29. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x00 24.--27. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Day unit,Week day"
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
elif ((per.l(ad:0x40002800+0x0C)&0x82)!=0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Day unit,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
else
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "RTC_ALRMBR,RTC alarm B register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
textline " "
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
bitfld.long 0x00 24.--27. " DAY ,Week day" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday,?..."
|
|
bitfld.long 0x00 30. " WDSEL ,Week day selection" "Day unit,Week day"
|
|
textline " "
|
|
bitfld.long 0x00 31. " MSK4 ,Alarm B date mask" "Not masked,Masked"
|
|
bitfld.long 0x00 23. " MSK3 ,Alarm B hours mask" "Not masked,Masked"
|
|
bitfld.long 0x00 15. " MSK2 ,Alarm B minutes mask" "Not masked,Masked"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MSK1 ,Alarm B seconds mask" "Not masked,Masked"
|
|
endif
|
|
wgroup.long 0x24++0x03
|
|
line.long 0x00 "RTC_WPR,RTC write protection register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " KEY ,Write protection key"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "RTC_SSR,RTC sub second register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SS ,Sub second value"
|
|
textline " "
|
|
wgroup.long 0x2C++0x03
|
|
line.long 0x00 "RTC_SHIFTR,RTC shift control register"
|
|
bitfld.long 0x00 31. " ADD1S ,Add one second" "No effect,Added to the clock/calendar"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--14. 1. " SUBFS ,Subtract a fraction of a second"
|
|
if (((per.l(ad:0x40002800+0x0C))&0x800)==0x00)
|
|
hgroup.long 0x30++0x07
|
|
hide.long 0x00 "RTC_TSTR,RTC time stamp time register"
|
|
hide.long 0x04 "RTC_TSDR,RTC time stamp date register"
|
|
elif (((per.l(ad:0x40002800+0xC))&0x800)==0x800)&&(((per.l(ad:0x40002800+0x8))&0x40)==0x0)
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "RTC_TSTR,RTC time stamp time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,2,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "24h,PM"
|
|
line.long 0x04 "RTC_TSDR,RTC time stamp date register"
|
|
bitfld.long 0x04 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x04 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x04 12. " MT ,Month tens in BCD format" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " MU ,Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
else
|
|
rgroup.long 0x30++0x07
|
|
line.long 0x00 "RTC_TSTR,RTC time stamp time register"
|
|
bitfld.long 0x00 20.--21. " HOUR ,Hour tens in BCD format" "0,1,-,-"
|
|
bitfld.long 0x00 16.--19. " HU ,Hour units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 12.--14. " MNT ,Minute tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 8.--11. " MNU ,Minute units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--6. " ST ,Second tens in BCD format" "0,1,2,3,4,5,-,-"
|
|
bitfld.long 0x00 0.--3. " SU ,Second units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x00 22. " PM ,AM/PM notation" "AM,PM"
|
|
line.long 0x04 "RTC_TSDR,RTC time stamp date register"
|
|
bitfld.long 0x04 13.--15. " WDU ,Week day units" "-,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,Sunday"
|
|
bitfld.long 0x04 4.--5. " DATE ,Date tens in BCD format" "0,1,2,3"
|
|
bitfld.long 0x04 0.--3. " DU ,Date units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
bitfld.long 0x04 12. " MT ,Month tens in BCD format" "0,1"
|
|
textline " "
|
|
bitfld.long 0x04 8.--11. " MU ,Month units in BCD format" "0,1,2,3,4,5,6,7,8,9,-,?..."
|
|
endif
|
|
if (((per.l(ad:0x40002800+0xC))&0x800)==0x800)
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "RTC_TSSSR,RTC timestamp sub second register"
|
|
hexmask.long.word 0x00 0.--15. 1. " SS ,Sub second value"
|
|
else
|
|
hgroup.long 0x38++0x03
|
|
hide.long 0x00 "RTC_TSSSR,RTC timestamp sub second register"
|
|
endif
|
|
textline " "
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "RTC_CALR,RTC calibration register"
|
|
bitfld.long 0x00 15. " CALP ,Increase frequency of RTC by 488.5 ppm" "No RTCCLK,One RTCCLK"
|
|
bitfld.long 0x00 14. " CALW8 ,Use an 8-second calibration cycle period" "Not selected,Selected"
|
|
textline " "
|
|
bitfld.long 0x00 13. " CALW16 ,Use a 16-second calibration cycle period" "Not selected,Selected"
|
|
hexmask.long.word 0x00 0.--8. 1. " CALM ,Calibration minus"
|
|
if (((per.l(ad:0x40002800+0x40))&0x1800)!=0x00)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RTC_TAFCR,RTC tamper and alternate function configuration register"
|
|
bitfld.long 0x00 23. " PC15MODE ,PC15 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 22. " PC15VALUE ,PC15 value" "0,1"
|
|
bitfld.long 0x00 21. " PC14MODE ,PC14 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 20. " PC14VALUE ,PC14 value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PC13MODE ,PC13 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 18. " PC13VALUE ,RTC_ALARM output type/PC13 value" "Open-drain,Push-pull"
|
|
bitfld.long 0x00 15. " TAMPPUDIS ,Rtc_tampx pull-up disable" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " TAMPPRCH ,Rtc_tampx precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " TAMPFLT ,Rtc_tampx filter count" "On edge,After 2 samples,After 4 samples,After 8 samples"
|
|
bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512,RTCCLK/256"
|
|
bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Timestamp not saved,Timestamp saved"
|
|
bitfld.long 0x00 6. " TAMP3TRG ,Active level for RTC_TAMP3 input" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMP3E ,RTC_TAMP3 detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Low,High"
|
|
bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 input detection enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "RTC_TAFCR,RTC tamper and alternate function configuration register"
|
|
bitfld.long 0x00 23. " PC15MODE ,PC15 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 22. " PC15VALUE ,PC15 value" "0,1"
|
|
bitfld.long 0x00 21. " PC14MODE ,PC14 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 20. " PC14VALUE ,PC14 value" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " PC13MODE ,PC13 mode" "Standby mode,Push-pull"
|
|
bitfld.long 0x00 18. " PC13VALUE ,RTC_ALARM output type/PC13 value" "Open-drain,Push-pull"
|
|
bitfld.long 0x00 15. " TAMPPUDIS ,Rtc_tampx pull-up disable" "No,Yes"
|
|
bitfld.long 0x00 13.--14. " TAMPPRCH ,Rtc_tampx precharge duration" "1 RTCCLK cycle,2 RTCCLK cycles,4 RTCCLK cycles,8 RTCCLK cycles"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " TAMPFLT ,Rtc_tampx filter count" "On edge,After 2 samples,After 4 samples,After 8 samples"
|
|
bitfld.long 0x00 8.--10. " TAMPFREQ ,Tamper sampling frequency" "RTCCLK/32768,RTCCLK/16384,RTCCLK/8192,RTCCLK/4096,RTCCLK/2048,RTCCLK/1024,RTCCLK/512,RTCCLK/256"
|
|
bitfld.long 0x00 7. " TAMPTS ,Activate timestamp on tamper detection event" "Timestamp not saved,Timestamp saved"
|
|
bitfld.long 0x00 6. " TAMP3TRG ,Active level for RTC_TAMP3 input" "Rising edge,Falling edge"
|
|
textline " "
|
|
bitfld.long 0x00 5. " TAMP3E ,RTC_TAMP3 detection enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " TAMPIE ,Tamper interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TAMP1TRG ,Active level for RTC_TAMP1 input" "Rising edge,Falling edge"
|
|
bitfld.long 0x00 0. " TAMP1E ,RTC_TAMP1 input detection enable" "Disabled,Enabled"
|
|
endif
|
|
if ((per.l(ad:0x40002800+0x0C)&0x81)!=0x00)
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared"
|
|
hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value"
|
|
else
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "RTC_ALRMASSR,RTC alarm A sub second register"
|
|
bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared"
|
|
hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value"
|
|
endif
|
|
if ((per.l(ad:0x40002800+0x0C)&0x82)!=0x00)
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RTC_ALRMBSSR,RTC alarm B sub second register"
|
|
bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared"
|
|
hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value"
|
|
else
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "RTC_ALRMBSSR,RTC alarm B sub second register"
|
|
bitfld.long 0x00 24.--27. " MASKSS ,Mask the most-significant bits starting at this bit" "No comparison,SS[0] compared,SS[1:0] compared,SS[2:0] compared,SS[3:0] compared,SS[4:0] compared,SS[5:0] compared,SS[6:0] compared,SS[7:0] compared,SS[8:0] compared,SS[9:0] compared,SS[10:0] compared,SS[11:0] compared,SS[12:0] compared,SS[13:0] compared,All bits compared"
|
|
hexmask.long.word 0x00 0.--14. 1. " SS ,Sub seconds value"
|
|
endif
|
|
tree "RTC backup registers"
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
group.long 0x50++0x7F
|
|
line.long 0x0 "RTC_BKP0R,RTC backup register 0"
|
|
line.long 0x4 "RTC_BKP1R,RTC backup register 1"
|
|
line.long 0x8 "RTC_BKP2R,RTC backup register 2"
|
|
line.long 0xC "RTC_BKP3R,RTC backup register 3"
|
|
line.long 0x10 "RTC_BKP4R,RTC backup register 4"
|
|
line.long 0x14 "RTC_BKP5R,RTC backup register 5"
|
|
line.long 0x18 "RTC_BKP6R,RTC backup register 6"
|
|
line.long 0x1C "RTC_BKP7R,RTC backup register 7"
|
|
line.long 0x20 "RTC_BKP8R,RTC backup register 8"
|
|
line.long 0x24 "RTC_BKP9R,RTC backup register 9"
|
|
line.long 0x28 "RTC_BKP10R,RTC backup register 10"
|
|
line.long 0x2C "RTC_BKP11R,RTC backup register 11"
|
|
line.long 0x30 "RTC_BKP12R,RTC backup register 12"
|
|
line.long 0x34 "RTC_BKP13R,RTC backup register 13"
|
|
line.long 0x38 "RTC_BKP14R,RTC backup register 14"
|
|
line.long 0x3C "RTC_BKP15R,RTC backup register 15"
|
|
line.long 0x40 "RTC_BKP16R,RTC backup register 16"
|
|
line.long 0x44 "RTC_BKP17R,RTC backup register 17"
|
|
line.long 0x48 "RTC_BKP18R,RTC backup register 18"
|
|
line.long 0x4C "RTC_BKP19R,RTC backup register 19"
|
|
line.long 0x50 "RTC_BKP20R,RTC backup register 20"
|
|
line.long 0x54 "RTC_BKP21R,RTC backup register 21"
|
|
line.long 0x58 "RTC_BKP22R,RTC backup register 22"
|
|
line.long 0x5C "RTC_BKP23R,RTC backup register 23"
|
|
line.long 0x60 "RTC_BKP24R,RTC backup register 24"
|
|
line.long 0x64 "RTC_BKP25R,RTC backup register 25"
|
|
line.long 0x68 "RTC_BKP26R,RTC backup register 26"
|
|
line.long 0x6C "RTC_BKP27R,RTC backup register 27"
|
|
line.long 0x70 "RTC_BKP28R,RTC backup register 28"
|
|
line.long 0x74 "RTC_BKP29R,RTC backup register 29"
|
|
line.long 0x78 "RTC_BKP30R,RTC backup register 30"
|
|
line.long 0x7C "RTC_BKP31R,RTC backup register 31"
|
|
elif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F398VE")
|
|
group.long 0x50++0x3B
|
|
line.long 0x0 "RTC_BKP0R,RTC backup register 0"
|
|
line.long 0x4 "RTC_BKP1R,RTC backup register 1"
|
|
line.long 0x8 "RTC_BKP2R,RTC backup register 2"
|
|
line.long 0xC "RTC_BKP3R,RTC backup register 3"
|
|
line.long 0x10 "RTC_BKP4R,RTC backup register 4"
|
|
line.long 0x14 "RTC_BKP5R,RTC backup register 5"
|
|
line.long 0x18 "RTC_BKP6R,RTC backup register 6"
|
|
line.long 0x1C "RTC_BKP7R,RTC backup register 7"
|
|
line.long 0x20 "RTC_BKP8R,RTC backup register 8"
|
|
line.long 0x24 "RTC_BKP9R,RTC backup register 9"
|
|
line.long 0x28 "RTC_BKP10R,RTC backup register 10"
|
|
line.long 0x2C "RTC_BKP11R,RTC backup register 11"
|
|
line.long 0x30 "RTC_BKP12R,RTC backup register 12"
|
|
line.long 0x34 "RTC_BKP13R,RTC backup register 13"
|
|
line.long 0x38 "RTC_BKP14R,RTC backup register 14"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
tree.open "I2C (Inter-integrated circuit)"
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
width 18.
|
|
if ((per.l(ad:0x40005400+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005400+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C1_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005400+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005400+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C1_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005400+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005400+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C1_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005400+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005400+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C1_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40005400+0x04)&0x800)==0x00)&&((per.l(ad:0x40005400)&0x10000)==0x00))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005400+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
elif (((per.l(ad:0x40005400+0x04)&0x800)==0x00)&&((per.l(ad:0x40005400)&0x10000)==0x10000))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005400+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
elif (((per.l(ad:0x40005400+0x04)&0x800)==0x800)&&((per.l(ad:0x40005400)&0x10000)==0x00))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005400+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
endif
|
|
else
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005400+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40005400+0x08)&0x8000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C1_OAR1,Own address 1 register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C1_OAR1,Own address 1 register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
endif
|
|
if ((per.l(ad:0x40005400+0x0C)&0x8000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C1_OAR2,Own address 2 register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2[7:1] ,Interface address"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C1_OAR2,Own address 2 register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2[7:1] ,Interface address"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C1_TIMINGR,Timing register"
|
|
bitfld.long 0x00 28.--31. " PRESC[3:0] ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL[3:0] ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SDADEL[3:0] ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH[7:0] ,SCL high period"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL[7:0] ,SCL low period"
|
|
if ((per.l(ad:0x40005400+0x14)&0x8000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C1_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB[11:0] ,Bus timeout B"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA[11:0] ,Bus Timeout A"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C1_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB[11:0] ,Bus timeout B"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA[11:0] ,Bus Timeout A"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C1_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x00 17.--23. 1. " ADDCODE[6:0] ,Address match code"
|
|
rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy"
|
|
rbitfld.long 0x00 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 11. " PECERR ,PEC Error in reception" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " BERR ,Bus error" "No error,Error"
|
|
rbitfld.long 0x00 7. " TCR ,Transfer Complete Reload" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " TC ,Transfer Complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " NACKF ,Not Acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
eventfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "I2C1_ICR,Interrupt clear register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PECCF ,PEC Error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear " "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C1_PECR,PEC register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC[7:0] ,Packet error checking register"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "I2C1_RXDR,Receive data register"
|
|
in
|
|
if ((per.l(ad:0x40005400+0x18)&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C1_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA[7:0] ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "I2C1_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA[7:0] ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("STM32F334?4")&&!cpuis("STM32F334?6")&&!cpuis("STM32F334?8")&&!cpuis("STM32F303*6")&&!cpuis("STM32F303*8")&&!cpuis("STM32F328*8")
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
width 18.
|
|
if ((per.l(ad:0x40005800+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005800+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C2_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005800+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005800+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C2_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005800+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005800+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C2_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005800+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005800+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C2_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40005800+0x04)&0x800)==0x00)&&((per.l(ad:0x40005800)&0x10000)==0x00))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
elif (((per.l(ad:0x40005800+0x04)&0x800)==0x00)&&((per.l(ad:0x40005800)&0x10000)==0x10000))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
elif (((per.l(ad:0x40005800+0x04)&0x800)==0x800)&&((per.l(ad:0x40005800)&0x10000)==0x00))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
endif
|
|
else
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40005800+0x08)&0x8000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C2_OAR1,Own address 1 register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C2_OAR1,Own address 1 register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
endif
|
|
if ((per.l(ad:0x40005800+0x0C)&0x8000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C2_OAR2,Own address 2 register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2[7:1] ,Interface address"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C2_OAR2,Own address 2 register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2[7:1] ,Interface address"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C2_TIMINGR,Timing register"
|
|
bitfld.long 0x00 28.--31. " PRESC[3:0] ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL[3:0] ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SDADEL[3:0] ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH[7:0] ,SCL high period"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL[7:0] ,SCL low period"
|
|
if ((per.l(ad:0x40005800+0x14)&0x8000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C2_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB[11:0] ,Bus timeout B"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA[11:0] ,Bus Timeout A"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C2_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB[11:0] ,Bus timeout B"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA[11:0] ,Bus Timeout A"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C2_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x00 17.--23. 1. " ADDCODE[6:0] ,Address match code"
|
|
rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy"
|
|
rbitfld.long 0x00 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 11. " PECERR ,PEC Error in reception" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " BERR ,Bus error" "No error,Error"
|
|
rbitfld.long 0x00 7. " TCR ,Transfer Complete Reload" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " TC ,Transfer Complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " NACKF ,Not Acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
eventfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "I2C2_ICR,Interrupt clear register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PECCF ,PEC Error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear " "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C2_PECR,PEC register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC[7:0] ,Packet error checking register"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "I2C2_RXDR,Receive data register"
|
|
in
|
|
if ((per.l(ad:0x40005800+0x18)&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C2_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA[7:0] ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "I2C2_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA[7:0] ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")
|
|
tree "I2C3"
|
|
base ad:0x40007800
|
|
width 18.
|
|
if ((per.l(ad:0x40007800+0x00)&0x100000)==0x00)&&((per.l(ad:0x40007800+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C3_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007800+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40007800+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C3_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007800+0x00)&0x100000)==0x00)&&((per.l(ad:0x40007800+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C3_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007800+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40007800+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C3_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40007800+0x04)&0x800)==0x00)&&((per.l(ad:0x40007800)&0x10000)==0x00))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40007800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
elif (((per.l(ad:0x40007800+0x04)&0x800)==0x00)&&((per.l(ad:0x40007800)&0x10000)==0x10000))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40007800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
elif (((per.l(ad:0x40007800+0x04)&0x800)==0x800)&&((per.l(ad:0x40007800)&0x10000)==0x00))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40007800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
endif
|
|
else
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40007800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40007800+0x08)&0x8000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C3_OAR1,Own address 1 register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C3_OAR1,Own address 1 register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
endif
|
|
if ((per.l(ad:0x40007800+0x0C)&0x8000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C3_OAR2,Own address 2 register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2[7:1] ,Interface address"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C3_OAR2,Own address 2 register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2[7:1] ,Interface address"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C3_TIMINGR,Timing register"
|
|
bitfld.long 0x00 28.--31. " PRESC[3:0] ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL[3:0] ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SDADEL[3:0] ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH[7:0] ,SCL high period"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL[7:0] ,SCL low period"
|
|
if ((per.l(ad:0x40007800+0x14)&0x8000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C3_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB[11:0] ,Bus timeout B"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA[11:0] ,Bus Timeout A"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C3_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB[11:0] ,Bus timeout B"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA[11:0] ,Bus Timeout A"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C3_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x00 17.--23. 1. " ADDCODE[6:0] ,Address match code"
|
|
rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy"
|
|
rbitfld.long 0x00 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 11. " PECERR ,PEC Error in reception" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " BERR ,Bus error" "No error,Error"
|
|
rbitfld.long 0x00 7. " TCR ,Transfer Complete Reload" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " TC ,Transfer Complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " NACKF ,Not Acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
eventfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "I2C3_ICR,Interrupt clear register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PECCF ,PEC Error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear " "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C3_PECR,PEC register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC[7:0] ,Packet error checking register"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "I2C3_RXDR,Receive data register"
|
|
in
|
|
if ((per.l(ad:0x40007800+0x18)&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C3_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA[7:0] ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "I2C3_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA[7:0] ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
elif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
width 18.
|
|
if ((per.l(ad:0x40005400+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005400+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C1_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005400+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005400+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C1_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005400+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005400+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C1_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005400+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005400+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C1_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40005400+0x04)&0x800)==0x00)&&((per.l(ad:0x40005400)&0x10000)==0x00))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005400+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
elif (((per.l(ad:0x40005400+0x04)&0x800)==0x00)&&((per.l(ad:0x40005400)&0x10000)==0x10000))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005400+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
elif (((per.l(ad:0x40005400+0x04)&0x800)==0x800)&&((per.l(ad:0x40005400)&0x10000)==0x00))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005400+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
endif
|
|
else
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005400+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40005400+0x08)&0x8000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C1_OAR1,Own address 1 register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C1_OAR1,Own address 1 register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
endif
|
|
if ((per.l(ad:0x40005400+0x0C)&0x8000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C1_OAR2,Own address 2 register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2[7:1] ,Interface address"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C1_OAR2,Own address 2 register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2[7:1] ,Interface address"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C1_TIMINGR,Timing register"
|
|
bitfld.long 0x00 28.--31. " PRESC[3:0] ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL[3:0] ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SDADEL[3:0] ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH[7:0] ,SCL high period"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL[7:0] ,SCL low period"
|
|
if ((per.l(ad:0x40005400+0x14)&0x8000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C1_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB[11:0] ,Bus timeout B"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA[11:0] ,Bus Timeout A"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C1_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB[11:0] ,Bus timeout B"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA[11:0] ,Bus Timeout A"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C1_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x00 17.--23. 1. " ADDCODE[6:0] ,Address match code"
|
|
rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy"
|
|
rbitfld.long 0x00 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 11. " PECERR ,PEC Error in reception" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " BERR ,Bus error" "No error,Error"
|
|
rbitfld.long 0x00 7. " TCR ,Transfer Complete Reload" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " TC ,Transfer Complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " NACKF ,Not Acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
eventfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "I2C1_ICR,Interrupt clear register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PECCF ,PEC Error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear " "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C1_PECR,PEC register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC[7:0] ,Packet error checking register"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "I2C1_RXDR,Receive data register"
|
|
in
|
|
if ((per.l(ad:0x40005400+0x18)&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C1_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA[7:0] ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "I2C1_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA[7:0] ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
width 18.
|
|
if ((per.l(ad:0x40005800+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005800+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C2_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005800+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005800+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C2_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005800+0x00)&0x100000)==0x00)&&((per.l(ad:0x40005800+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C2_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40005800+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40005800+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C2_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40005800+0x04)&0x800)==0x00)&&((per.l(ad:0x40005800)&0x10000)==0x00))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
elif (((per.l(ad:0x40005800+0x04)&0x800)==0x00)&&((per.l(ad:0x40005800)&0x10000)==0x10000))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
elif (((per.l(ad:0x40005800+0x04)&0x800)==0x800)&&((per.l(ad:0x40005800)&0x10000)==0x00))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
endif
|
|
else
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40005800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40005800+0x08)&0x8000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C2_OAR1,Own address 1 register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C2_OAR1,Own address 1 register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
endif
|
|
if ((per.l(ad:0x40005800+0x0C)&0x8000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C2_OAR2,Own address 2 register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2[7:1] ,Interface address"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C2_OAR2,Own address 2 register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2[7:1] ,Interface address"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C2_TIMINGR,Timing register"
|
|
bitfld.long 0x00 28.--31. " PRESC[3:0] ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL[3:0] ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SDADEL[3:0] ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH[7:0] ,SCL high period"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL[7:0] ,SCL low period"
|
|
if ((per.l(ad:0x40005800+0x14)&0x8000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C2_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB[11:0] ,Bus timeout B"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA[11:0] ,Bus Timeout A"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C2_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB[11:0] ,Bus timeout B"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA[11:0] ,Bus Timeout A"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C2_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x00 17.--23. 1. " ADDCODE[6:0] ,Address match code"
|
|
rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy"
|
|
rbitfld.long 0x00 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 11. " PECERR ,PEC Error in reception" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " BERR ,Bus error" "No error,Error"
|
|
rbitfld.long 0x00 7. " TCR ,Transfer Complete Reload" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " TC ,Transfer Complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " NACKF ,Not Acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
eventfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "I2C2_ICR,Interrupt clear register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PECCF ,PEC Error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear " "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C2_PECR,PEC register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC[7:0] ,Packet error checking register"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "I2C2_RXDR,Receive data register"
|
|
in
|
|
if ((per.l(ad:0x40005800+0x18)&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C2_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA[7:0] ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "I2C2_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA[7:0] ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C3"
|
|
base ad:0x40007800
|
|
width 18.
|
|
if ((per.l(ad:0x40007800+0x00)&0x100000)==0x00)&&((per.l(ad:0x40007800+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C3_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007800+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40007800+0x00)&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C3_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007800+0x00)&0x100000)==0x00)&&((per.l(ad:0x40007800+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C3_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
elif ((per.l(ad:0x40007800+0x00)&0x100000)==0x100000)&&((per.l(ad:0x40007800+0x00)&0x01)==0x01)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "I2C3_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert support" "Not supported,Supported"
|
|
textline " "
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (!cpuis("STM32F7*"))
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--11. " DNF[3:0] ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 tI2CCLK,12 tI2CCLK,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l(ad:0x40007800+0x04)&0x800)==0x00)&&((per.l(ad:0x40007800)&0x10000)==0x00))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40007800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
elif (((per.l(ad:0x40007800+0x04)&0x800)==0x00)&&((per.l(ad:0x40007800)&0x10000)==0x10000))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40007800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " SADD[7:1] ,Slave address bit 7:1"
|
|
endif
|
|
elif (((per.l(ad:0x40007800+0x04)&0x800)==0x800)&&((per.l(ad:0x40007800)&0x10000)==0x00))
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40007800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x00 14. " STOP ,Stop generation" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0 "
|
|
endif
|
|
else
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
if (((per.l(ad:0x40007800+0x04))&0x2000)==0x2000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
rbitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
rbitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
endif
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "I2C3_CR2,Control register 2"
|
|
bitfld.long 0x00 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
bitfld.long 0x00 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RELOAD ,NBYTES reload mode" "Stop,Reload"
|
|
hexmask.long.byte 0x00 16.--23. 1. " NBYTES[7:0] ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x00 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
textline " "
|
|
bitfld.long 0x00 13. " START ,Start generation" "No effect,Start/Restart"
|
|
bitfld.long 0x00 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x00 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--9. 1. " SADD[9:0] ,Slave address bit 9:0"
|
|
endif
|
|
endif
|
|
if ((per.l(ad:0x40007800+0x08)&0x8000)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C3_OAR1,Own address 1 register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
textline " "
|
|
bitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
textline " "
|
|
bitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "I2C3_OAR1,Own address 1 register"
|
|
bitfld.long 0x00 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
textline " "
|
|
rbitfld.long 0x00 8.--9. " OA1[9:8] ,Interface address" "0,1,2,3"
|
|
hexmask.long.byte 0x00 1.--7. 0x02 " OA1[7:1] ,Interface address"
|
|
textline " "
|
|
rbitfld.long 0x00 0. " OA1[0] ,Interface address" "0,1"
|
|
endif
|
|
if ((per.l(ad:0x40007800+0x0C)&0x8000)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C3_OAR2,Own address 2 register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2[7:1] ,Interface address"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "I2C3_OAR2,Own address 2 register"
|
|
bitfld.long 0x00 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8.--10. " OA2MSK[2:0] ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
textline " "
|
|
hexmask.long.byte 0x00 1.--7. 1. " OA2[7:1] ,Interface address"
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "I2C3_TIMINGR,Timing register"
|
|
bitfld.long 0x00 28.--31. " PRESC[3:0] ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 20.--23. " SCLDEL[3:0] ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " SDADEL[3:0] ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.byte 0x00 8.--15. 1. " SCLH[7:0] ,SCL high period"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--7. 1. " SCLL[7:0] ,SCL low period"
|
|
if ((per.l(ad:0x40007800+0x14)&0x8000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C3_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB[11:0] ,Bus timeout B"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA[11:0] ,Bus Timeout A"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "I2C3_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x00 31. " TEXTEN ,Extended clock timeout enable" "Disabled,Enabled"
|
|
hexmask.long.word 0x00 16.--27. 1. " TIMEOUTB[11:0] ,Bus timeout B"
|
|
textline " "
|
|
bitfld.long 0x00 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " TIMEOUTA[11:0] ,Bus Timeout A"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "I2C3_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x00 17.--23. 1. " ADDCODE[6:0] ,Address match code"
|
|
rbitfld.long 0x00 16. " DIR ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " BUSY ,Bus busy" "Not busy,Busy"
|
|
rbitfld.long 0x00 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 11. " PECERR ,PEC Error in reception" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x00 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x00 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x00 8. " BERR ,Bus error" "No error,Error"
|
|
rbitfld.long 0x00 7. " TCR ,Transfer Complete Reload" "Not completed,Completed"
|
|
textline " "
|
|
rbitfld.long 0x00 6. " TC ,Transfer Complete" "Not completed,Completed"
|
|
rbitfld.long 0x00 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x00 4. " NACKF ,Not Acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x00 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
textline " "
|
|
rbitfld.long 0x00 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
eventfld.long 0x00 1. " TXIS ,Transmit interrupt status" "Not empty,Empty"
|
|
textline " "
|
|
eventfld.long 0x00 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "I2C3_ICR,Interrupt clear register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " PECCF ,PEC Error flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear " "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C3_PECR,PEC register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC[7:0] ,Packet error checking register"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "I2C3_RXDR,Receive data register"
|
|
in
|
|
if ((per.l(ad:0x40007800+0x18)&0x01)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C3_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA[7:0] ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "I2C3_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA[7:0] ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
else
|
|
tree "I2C1"
|
|
base ad:0x40005400
|
|
width 18.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "I2C1_CR1,Control register 1"
|
|
bitfld.long 0x00 23. " PECEN ,PEC enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " ALERTEN ,SMBus alert enable (Device mode/Host mode)" "Disabled/Not supported,Enabled/Supported"
|
|
bitfld.long 0x00 21. " SMBDEN ,SMBus Device Default address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 20. " SMBHEN ,SMBus Host address enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 18. " WUPEN ,Wakeup from STOP enable" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302VB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F302VC")&&(cpu()!="STM32F302RB")&&(cpu()!="STM32F302RC")&&(cpu()!="STM32F303RB")&&(cpu()!="STM32F303RC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303VB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F303VC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F313RC")&&(cpu()!="STM32F313VC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373VC")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373V8")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F373VB")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")&&(cpu()!="STM32F383VC")&&!CPUIS("STM32F058T8")&&!CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 13. " SWRST ,Software reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 ti2cclk,12 ti2cclk,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
line.long 0x04 "I2C1_CR2,Control register 2"
|
|
bitfld.long 0x04 26. " PECBYTE ,Packet error checking byte" "No PEC,PEC"
|
|
textline " "
|
|
bitfld.long 0x04 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x04 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed"
|
|
hexmask.long.byte 0x04 16.--23. 1. " NBYTES ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x04 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x04 14. " STOP ,Stop generation" "No stop,Stop"
|
|
bitfld.long 0x04 13. " START ,Start generation" "No start,Start/Restart"
|
|
textline " "
|
|
bitfld.long 0x04 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x04 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x04 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " SADD ,Slave address bit 9:8" "0,1,2,3"
|
|
hexmask.long.byte 0x04 1.--7. 1. " SADD ,Slave address bit 7:1"
|
|
bitfld.long 0x04 0. " SADD0 ,Slave address bit 0" "0,1"
|
|
line.long 0x08 "I2C1_OAR1,Own address 1 register"
|
|
bitfld.long 0x08 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
bitfld.long 0x08 8.--9. " OA1 ,Interface address" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x08 1.--7. 1. " OA1[7:1] ,Interface address"
|
|
bitfld.long 0x08 0. " OA1[0] ,Interface address" "0,1"
|
|
line.long 0x0C "I2C1_OAR2,Own address 2 register"
|
|
bitfld.long 0x0C 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8.--10. " OA2MSK ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x0C 1.--7. 1. " OA2 ,Interface address"
|
|
line.long 0x10 "I2C1_TIMINGR,Timing register"
|
|
bitfld.long 0x10 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " SCLH ,SCL high period"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SCLL ,SCL low period"
|
|
line.long 0x14 "I2C1_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x14 31. " TEXTEN ,Extended clock timeout enable" "Disalbed,Enabled"
|
|
hexmask.long.word 0x14 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x14 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
hexmask.long.word 0x14 0.--11. 1. " TIMEOUTA ,Bus Timeout A"
|
|
line.long 0x18 "I2C1_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. " ADDCODE ,Address match code"
|
|
rbitfld.long 0x18 16. " DIR ,Transfer direction" "Write,Read"
|
|
rbitfld.long 0x18 15. " BUSY ,Bus busy" "Not busy,Busy"
|
|
textline " "
|
|
rbitfld.long 0x18 13. " ALERT ,SMBus alert" "Not detected,Detected"
|
|
rbitfld.long 0x18 12. " TIMEOUT ,Timeout or tLOW detection flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 11. " PECERR ,PEC Error in reception" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x18 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 8. " BERR ,Bus error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x18 7. " TCR ,Transfer Complete Reload" "Not completed,Completed"
|
|
rbitfld.long 0x18 6. " TC ,Transfer Complete" "Not completed,Completed"
|
|
rbitfld.long 0x18 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x18 4. " NACKF ,Not Acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x18 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
rbitfld.long 0x18 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TXIS ,Transmit interrupt status" "Not empty,Empty"
|
|
bitfld.long 0x18 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "I2C1_ICR,Interrupt clear register"
|
|
bitfld.long 0x00 13. " ALERTCF ,Alert flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 12. " TIMOUTCF ,Timeout detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 11. " PECCF ,PEC Error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear" "No effect,Clear"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "I2C1_PECR,PEC register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PEC ,Packet error checking register"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "I2C1_RXDR,Receive data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data"
|
|
if (((per.l(ad:0x40005400))&0x01)==0x01)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C1_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "I2C1_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "I2C2"
|
|
base ad:0x40005800
|
|
width 18.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "I2C2_CR1,Control register 1"
|
|
bitfld.long 0x00 19. " GCEN ,General call enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif !CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
endif
|
|
bitfld.long 0x00 17. " NOSTRETCH ,Clock stretching disable" "No,Yes"
|
|
bitfld.long 0x00 16. " SBC ,Slave byte control" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " RXDMAEN ,DMA reception requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 14. " TXDMAEN ,DMA transmission requests enable" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302VB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F302VC")&&(cpu()!="STM32F302RB")&&(cpu()!="STM32F302RC")&&(cpu()!="STM32F303RB")&&(cpu()!="STM32F303RC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303VB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F303VC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F313RC")&&(cpu()!="STM32F313VC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372V8")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372VB")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F372VC")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373VC")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373V8")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F373VB")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")&&(cpu()!="STM32F383VC")&&!CPUIS("STM32F058T8")&&!CPUIS("STM32F030CC")&&!CPUIS("STM32F030RC")&&!CPUIS("STM32F070C6")&&!CPUIS("STM32F070CB")&&!CPUIS("STM32F070F6")&&!CPUIS("STM32F070RB")
|
|
bitfld.long 0x00 13. " SWRST ,Software reset" "No reset,Reset"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " ANFOFF ,Analog noise filter OFF" "Disabled,Enabled"
|
|
bitfld.long 0x00 8.--11. " DNF ,Digital noise filter" "Disabled,1 tI2CCLK,2 tI2CCLK,3 tI2CCLK,4 tI2CCLK,5 tI2CCLK,6 tI2CCLK,7 tI2CCLK,8 tI2CCLK,9 tI2CCLK,10 ti2cclk,12 ti2cclk,12 tI2CCLK,13 tI2CCLK,14 tI2CCLK,15 tI2CCLK"
|
|
bitfld.long 0x00 7. " ERRIE ,Error interrupts enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCIE ,Transfer Complete interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " STOPIE ,STOP detection Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACKIE ,Not acknowledge received Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ADDRIE ,Address match Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXIE ,RX Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " TXIE ,TX Interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PE ,Peripheral enable" "Disabled,Enabled"
|
|
line.long 0x04 "I2C2_CR2,Control register 2"
|
|
bitfld.long 0x04 25. " AUTOEND ,Automatic end mode" "Software mode,Automatic mode"
|
|
bitfld.long 0x04 24. " RELOAD ,NBYTES reload mode" "Completed,Not completed"
|
|
hexmask.long.byte 0x04 16.--23. 1. " NBYTES ,Number of bytes"
|
|
textline " "
|
|
bitfld.long 0x04 15. " NACK ,NACK generation" "ACK sent,NACK sent"
|
|
bitfld.long 0x04 14. " STOP ,Stop generation" "No stop,Stop"
|
|
bitfld.long 0x04 13. " START ,Start generation" "No start,Start/Restart"
|
|
textline " "
|
|
bitfld.long 0x04 12. " HEAD10R ,10-bit address header only read direction" "10 bits,7 bits"
|
|
bitfld.long 0x04 11. " ADD10 ,10-bit addressing mode" "7-bit,10-bit"
|
|
bitfld.long 0x04 10. " RD_WRN ,Transfer direction" "Write,Read"
|
|
textline " "
|
|
bitfld.long 0x04 8.--9. " SADD ,Slave address bit 9:8" "0,1,2,3"
|
|
hexmask.long.byte 0x04 1.--7. 1. " SADD ,Slave address bit 7:1"
|
|
bitfld.long 0x04 0. " SADD0 ,Slave address bit 0" "0,1"
|
|
line.long 0x08 "I2C2_OAR1,Own address 1 register"
|
|
bitfld.long 0x08 15. " OA1EN ,Own Address 1 enable" "Disabled,Enabled"
|
|
bitfld.long 0x08 10. " OA1MODE ,Own Address 1 10-bit mode" "7-bit,10-bit"
|
|
bitfld.long 0x08 8.--9. " OA1 ,Interface address" "0,1,2,3"
|
|
textline " "
|
|
hexmask.long.byte 0x08 1.--7. 1. " OA1[7:1] ,Interface address"
|
|
bitfld.long 0x08 0. " OA1[0] ,Interface address" "0,1"
|
|
line.long 0x0C "I2C2_OAR2,Own address 2 register"
|
|
bitfld.long 0x0C 15. " OA2EN ,Own Address 2 enable" "Disabled,Enabled"
|
|
bitfld.long 0x0C 8.--10. " OA2MSK ,Own Address 2 masks" "No mask,OA2[7:2] compared,OA2[7:3] compared,OA2[7:4] compared,OA2[7:5] compared,OA2[7:6] compared,OA2[7] compared,No comparison"
|
|
hexmask.long.byte 0x0C 1.--7. 1. " OA2 ,Interface address"
|
|
line.long 0x10 "I2C2_TIMINGR,Timing register"
|
|
bitfld.long 0x10 28.--31. " PRESC ,Timing prescaler" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 20.--23. " SCLDEL ,Data setup time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x10 16.--19. " SDADEL ,Data hold time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.byte 0x10 8.--15. 1. " SCLH ,SCL high period"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SCLL ,SCL low period"
|
|
line.long 0x14 "I2C2_TIMEOUTR,Timeout register"
|
|
bitfld.long 0x14 31. " TEXTEN ,Extended clock timeout enable" "Disalbed,Enabled"
|
|
hexmask.long.word 0x14 16.--27. 1. " TIMEOUTB ,Bus timeout B"
|
|
bitfld.long 0x14 15. " TIMOUTEN ,Clock timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 12. " TIDLE ,Idle clock timeout detection" "Low timeout,High timeout"
|
|
hexmask.long.word 0x14 0.--11. 1. " TIMEOUTA ,Bus Timeout A"
|
|
line.long 0x18 "I2C2_ISR,Interrupt and Status register"
|
|
hexmask.long.byte 0x18 17.--23. 1. " ADDCODE ,Address match code"
|
|
rbitfld.long 0x18 16. " DIR ,Transfer direction" "Write,Read"
|
|
rbitfld.long 0x18 15. " BUSY ,Bus busy" "Not busy,Busy"
|
|
textline " "
|
|
rbitfld.long 0x18 10. " OVR ,Overrun/Underrun" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 9. " ARLO ,Arbitration lost" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 8. " BERR ,Bus error" "No error,Error"
|
|
textline " "
|
|
rbitfld.long 0x18 7. " TCR ,Transfer Complete Reload" "Not completed,Completed"
|
|
rbitfld.long 0x18 6. " TC ,Transfer Complete" "Not completed,Completed"
|
|
rbitfld.long 0x18 5. " STOPF ,Stop detection flag" "Not detected,Detected"
|
|
textline " "
|
|
rbitfld.long 0x18 4. " NACKF ,Not Acknowledge received flag" "Not received,Received"
|
|
rbitfld.long 0x18 3. " ADDR ,Address matched" "Not matched,Matched"
|
|
rbitfld.long 0x18 2. " RXNE ,Receive data register not empty" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x18 1. " TXIS ,Transmit interrupt status" "Not empty,Empty"
|
|
bitfld.long 0x18 0. " TXE ,Transmit data register empty" "Not empty,Empty"
|
|
wgroup.long 0x1C++0x03
|
|
line.long 0x00 "I2C2_ICR,Interrupt clear register"
|
|
bitfld.long 0x00 10. " OVRCF ,Overrun/Underrun flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 9. " ARLOCF ,Arbitration Lost flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 8. " BERRCF ,Bus error flag clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 5. " STOPCF ,Stop detection flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 4. " NACKCF ,Not Acknowledge flag clear" "No effect,Clear"
|
|
bitfld.long 0x00 3. " ADDRCF ,Address Matched flag clear" "No effect,Clear"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "I2C2_RXDR,Receive data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " RXDATA ,8-bit receive data"
|
|
if (((per.l(ad:0x40005800))&0x01)==0x01)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "I2C2_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
else
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "I2C2_TXDR,Transmit data register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXDATA ,8-bit transmit data"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "USART (Universal synchronous asynchronous receiver transmitter)"
|
|
tree "USART 1"
|
|
base ad:0x40013800
|
|
width 12.
|
|
if (((per.l((ad:0x40013800+0x0)))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif !cpuis("STM32F37*")
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif !cpuis("STM32F37*")
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l((ad:0x40013800+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40013800+0x0)))&0x04)==0x04)&&(((per.l((ad:0x40013800+0x4)))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40013800+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40013800+0x0)))&0x04)==0x04)&&(((per.l((ad:0x40013800+0x4)))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40013800+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40013800+0x0)))&0x04)==0x00)&&(((per.l((ad:0x40013800+0x4)))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40013800+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40013800+0x0)))&0x04)==0x00)&&(((per.l((ad:0x40013800+0x4)))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l((ad:0x40013800+0x0)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control register 3"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control register 3"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l((ad:0x40013800+0x0)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40013800+0x0)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40013800+0x0)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x40013800+0x08)))&0x20)==0x00)&&(((per.l((ad:0x40013800+0x0)))&0x1)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value (IrDA)"
|
|
elif (((per.l((ad:0x40013800+0x08)))&0x20)==0x00)&&(((per.l((ad:0x40013800+0x0)))&0x1)==0x01)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value (IrDA)"
|
|
elif (((per.l((ad:0x40013800+0x08)))&0x20)==0x20)&&(((per.l((ad:0x40013800+0x0)))&0x1)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value (Smartcard)" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value (Smartcard)" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block Length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request register"
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & status register"
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Not set,Set"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "No end,End"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt flag clear register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive data register"
|
|
in
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 2"
|
|
base ad:0x40004400
|
|
width 12.
|
|
if (((per.l((ad:0x40004400+0x0)))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif !cpuis("STM32F37*")
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif !cpuis("STM32F37*")
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l((ad:0x40004400+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40004400+0x0)))&0x04)==0x04)&&(((per.l((ad:0x40004400+0x4)))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40004400+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40004400+0x0)))&0x04)==0x04)&&(((per.l((ad:0x40004400+0x4)))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40004400+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40004400+0x0)))&0x04)==0x00)&&(((per.l((ad:0x40004400+0x4)))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40004400+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40004400+0x0)))&0x04)==0x00)&&(((per.l((ad:0x40004400+0x4)))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l((ad:0x40004400+0x0)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control register 3"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control register 3"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l((ad:0x40004400+0x0)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004400+0x0)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004400+0x0)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x40004400+0x08)))&0x20)==0x00)&&(((per.l((ad:0x40004400+0x0)))&0x1)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value (IrDA)"
|
|
elif (((per.l((ad:0x40004400+0x08)))&0x20)==0x00)&&(((per.l((ad:0x40004400+0x0)))&0x1)==0x01)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value (IrDA)"
|
|
elif (((per.l((ad:0x40004400+0x08)))&0x20)==0x20)&&(((per.l((ad:0x40004400+0x0)))&0x1)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value (Smartcard)" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value (Smartcard)" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block Length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request register"
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & status register"
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Not set,Set"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "No end,End"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt flag clear register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive data register"
|
|
in
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "USART 3"
|
|
base ad:0x40004800
|
|
width 12.
|
|
if (((per.l((ad:0x40004800+0x0)))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif !cpuis("STM32F37*")
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif !cpuis("STM32F37*")
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 27. " EOBIE ,End of Block interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 21.--25. " DEAT ,Driver Enable assertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 16.--20. " DEDT ,Driver Enable deassertion time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l((ad:0x40004800+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40004800+0x0)))&0x04)==0x04)&&(((per.l((ad:0x40004800+0x4)))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40004800+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40004800+0x0)))&0x04)==0x04)&&(((per.l((ad:0x40004800+0x4)))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40004800+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40004800+0x0)))&0x04)==0x00)&&(((per.l((ad:0x40004800+0x4)))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40004800+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40004800+0x0)))&0x04)==0x00)&&(((per.l((ad:0x40004800+0x4)))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
rbitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21.--22. " ABRMOD ,Auto baud rate mode" "Start bit,Falling edge,0x7F frame,0x55 frame"
|
|
bitfld.long 0x00 20. " ABREN ,Auto baud rate enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 11. " CLKEN ,Clock enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CPOL ,Clock polarity" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CPHA ,Clock phase" "First,Second"
|
|
bitfld.long 0x00 8. " LBCL ,Last bit clock pulse" "Not output,Output"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l((ad:0x40004800+0x0)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control register 3"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
textline " "
|
|
bitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
bitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control register 3"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
textline " "
|
|
rbitfld.long 0x00 17.--19. " SCARCNT ,Smartcard auto-retry count" "0,1,2,3,4,5,6,7"
|
|
rbitfld.long 0x00 15. " DEP ,Driver enable polarity selection" "High,Low"
|
|
rbitfld.long 0x00 14. " DEM ,Driver enable mode" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CTSIE ,CTS interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 9. " CTSE ,CTS enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 8. " RTSE ,RTS enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " SCEN ,Smartcard mode enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 4. " NACK ,Smartcard NACK enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l((ad:0x40004800+0x0)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004800+0x0)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004800+0x0)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x40004800+0x08)))&0x20)==0x00)&&(((per.l((ad:0x40004800+0x0)))&0x1)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value (IrDA)"
|
|
elif (((per.l((ad:0x40004800+0x08)))&0x20)==0x00)&&(((per.l((ad:0x40004800+0x0)))&0x1)==0x01)
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value (IrDA)"
|
|
elif (((per.l((ad:0x40004800+0x08)))&0x20)==0x20)&&(((per.l((ad:0x40004800+0x0)))&0x1)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value (Smartcard)" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " GT ,Guard time value"
|
|
bitfld.long 0x00 0.--4. " PSC ,Prescaler value (Smartcard)" ",2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,44,46,48,50,52,54,56,58,60,62"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block Length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request register"
|
|
bitfld.long 0x00 4. " TXFRQ ,Transmit data flush request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ABRRQ ,Auto baud rate request" "Not requested,Requested"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & status register"
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ABRF ,Auto baud rate flag" "Not set,Set"
|
|
bitfld.long 0x00 14. " ABRE ,Auto baud rate error" "No error,Error"
|
|
bitfld.long 0x00 12. " EOBF ,End of block flag" "No end,End"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 10. " CTS ,CTS flag" "Set,Reset"
|
|
bitfld.long 0x00 9. " CTSIF ,CTS interrupt flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt flag clear register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOBCF ,End of timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 9. " CTSCF ,CTS clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive data register"
|
|
in
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32F302*B")||cpuis("STM32F302*C")||cpuis("STM32F303*B")||cpuis("STM32F303*C")||cpuis("STM32F303*B")||cpuis("STM32F358*C")||cpu()=="STM32F313CC"||cpu()=="STM32F313RC"||cpu()=="STM32F313VC"||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
tree "UART 4"
|
|
base ad:0x40004C00
|
|
width 12.
|
|
if (((per.l((ad:0x40004C00+0x0)))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif !cpuis("STM32F37*")
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif !cpuis("STM32F37*")
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l((ad:0x40004C00+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40004C00+0x0)))&0x04)==0x04)&&(((per.l((ad:0x40004C00+0x4)))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40004C00+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40004C00+0x0)))&0x04)==0x04)&&(((per.l((ad:0x40004C00+0x4)))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40004C00+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40004C00+0x0)))&0x04)==0x00)&&(((per.l((ad:0x40004C00+0x4)))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40004C00+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40004C00+0x0)))&0x04)==0x00)&&(((per.l((ad:0x40004C00+0x4)))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l((ad:0x40004C00+0x0)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control register 3"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control register 3"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l((ad:0x40004C00+0x0)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004C00+0x0)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40004C00+0x0)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x40004C00+0x0)))&0x1)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value (IrDA)"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value (IrDA)"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block Length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request register"
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & status register"
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt flag clear register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive data register"
|
|
in
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "UART 5"
|
|
base ad:0x40005000
|
|
width 12.
|
|
if (((per.l((ad:0x40005000+0x0)))&0x01)==0x00)
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif !cpuis("STM32F37*")
|
|
bitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,?..."
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
bitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "USART_CR1,Control register 1"
|
|
sif !cpuis("STM32F37*")
|
|
rbitfld.long 0x00 12. 28. " M ,Word length" "8 bits,9 bits,7 bits,"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 26. " RTOIE ,Receiver timeout interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 15. " OVER8 ,Oversampling mode" "By 16,By 8"
|
|
bitfld.long 0x00 14. " CMIE ,Character match interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MME ,Mute mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 11. " WAKE ,Receiver wakeup method" "Idle line,Address mark"
|
|
rbitfld.long 0x00 10. " PCE ,Parity control enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 9. " PS ,Parity selection" "Even,Odd"
|
|
bitfld.long 0x00 8. " PEIE ,PE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TXEIE ,TXE Interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " TCIE ,Transmission complete interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNEIE ,RXNE interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " IDLEIE ,IDLE interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " TE ,Transmitter enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RE ,Receiver enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " UESM ,USART enable in Stop mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " UE ,USART enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l((ad:0x40005000+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40005000+0x0)))&0x04)==0x04)&&(((per.l((ad:0x40005000+0x4)))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40005000+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40005000+0x0)))&0x04)==0x04)&&(((per.l((ad:0x40005000+0x4)))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
rbitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40005000+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40005000+0x0)))&0x04)==0x00)&&(((per.l((ad:0x40005000+0x4)))&0x100000)==0x100000)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
elif (((per.l((ad:0x40005000+0x0)))&0x01)==0x01)&&(((per.l((ad:0x40005000+0x0)))&0x04)==0x00)&&(((per.l((ad:0x40005000+0x4)))&0x100000)==0x00)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
rbitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
rbitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
rbitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
rbitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
rbitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
else
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USART_CR2,Control register 2"
|
|
bitfld.long 0x00 28.--31. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. " ADD ,Address of the USART node" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. " RTOEN ,Receiver timeout enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MSBFIRST ,Most significant bit first" "0 bit,MSB"
|
|
bitfld.long 0x00 18. " DATAINV ,Binary data inversion" "Positive/direct logic,Negative/inverse logic"
|
|
bitfld.long 0x00 17. " TXINV ,TX pin active level inversion" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.long 0x00 16. " RXINV ,RX pin active level inversion" "Not inverted,Inverted"
|
|
bitfld.long 0x00 15. " SWAP ,Swap TX/RX pins" "Not swapped,Swapped"
|
|
bitfld.long 0x00 14. " LINEN ,LIN mode enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12.--13. " STOP ,STOP bits" "1 stop bit,,2 stop bits,1.5 stop bit"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBDIE ,LIN break detection interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBDL ,LIN break detection length" "10-bit,11-bit"
|
|
bitfld.long 0x00 4. " ADDM7 ,7-bit Address Detection/4-bit Address Detection" "4-bit,7-bit"
|
|
endif
|
|
if (((per.l((ad:0x40005000+0x0)))&0x01)==0x00)
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control register 3"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
textline " "
|
|
bitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
bitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
bitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
bitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "USART_CR3,Control register 3"
|
|
bitfld.long 0x00 22. " WUFIE ,Wakeup from Stop mode interrupt enable" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20.--21. " WUS ,Wakeup from Stop mode interrupt flag selection" "Address match,,Start bit,RXNE"
|
|
textline " "
|
|
rbitfld.long 0x00 13. " DDRE ,DMA Disable on Reception Error" "No,Yes"
|
|
rbitfld.long 0x00 12. " OVRDIS ,Overrun Disable" "No,Yes"
|
|
rbitfld.long 0x00 11. " ONEBIT ,One sample bit method enable" "Three sample,One sample"
|
|
textline " "
|
|
bitfld.long 0x00 7. " DMAT ,DMA enable transmitter" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " DMAR ,DMA enable receiver" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.long 0x00 3. " HDSEL ,Half-duplex selection" "Not selected,Selected"
|
|
rbitfld.long 0x00 2. " IRLP ,IrDA low-power" "Normal mode,Low-power mode"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " IREN ,IrDA mode enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " EIE ,Error interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.l((ad:0x40005000+0x0)))&0x8001)==0x8000)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40005000+0x0)))&0x8001)==0x8001)
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--2. " BRR ,BRR[2:0] = USARTDIV[3:0] shifted 1 bit to the right" "0,1,2,3,4,5,6,7"
|
|
elif (((per.l((ad:0x40005000+0x0)))&0x8001)==0x00)
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[3:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "USART_BRR,Baud rate register"
|
|
hexmask.long.word 0x00 4.--15. 1. " BRR ,BRR[15:4] = USARTDIV[15:4]"
|
|
bitfld.long 0x00 0.--3. " BRR ,BRR[2:0] = USARTDIV[3:0]" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
if (((per.l((ad:0x40005000+0x0)))&0x1)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value (IrDA)"
|
|
else
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "USART_GTPR,Guard time and prescaler register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PSC ,Prescaler value (IrDA)"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USART_RTOR,Receiver timeout register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " BLEN ,Block Length"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " RTO ,Receiver timeout value"
|
|
wgroup.long 0x18++0x03
|
|
line.long 0x00 "USART_RQR,Request register"
|
|
bitfld.long 0x00 3. " RXFRQ ,Receive data flush request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 2. " MMRQ ,Mute mode request" "Not requested,Requested"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SBKRQ ,Send break request" "Not requested,Requested"
|
|
textline " "
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "USART_ISR,Interrupt & status register"
|
|
bitfld.long 0x00 22. " REACK ,Receive enable acknowledge flag " "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 21. " TEACK ,Transmit enable acknowledge flag" "Not acknowledged,Acknowledged"
|
|
bitfld.long 0x00 20. " WUF ,Wakeup from Stop mode flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 19. " RWU ,Receiver wakeup from Mute mode" "Active mode,Mute mode"
|
|
bitfld.long 0x00 18. " SBKF ,Send break flag" "No break,Break"
|
|
bitfld.long 0x00 17. " CMF ,Character match flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.long 0x00 16. " BUSY ,Busy flag" "Idle,Busy"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RTOF ,Receiver timeout" "No timeout,Timeout"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBDF ,LIN break detection flag" "Not detected,Detected"
|
|
bitfld.long 0x00 7. " TXE ,Transmit data register empty" "Not transferred,Transferred"
|
|
bitfld.long 0x00 6. " TC ,Transmission complete" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 5. " RXNE ,Read data register not empty" "No,Yes"
|
|
bitfld.long 0x00 4. " IDLE ,Idle line detected" "Not detected,Detected"
|
|
bitfld.long 0x00 3. " ORE ,Overrun error" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NF ,Noise detected flag" "Not detected,Detected"
|
|
bitfld.long 0x00 1. " FE ,Framing error" "No error,Error"
|
|
bitfld.long 0x00 0. " PE ,Parity error" "No error,Error"
|
|
wgroup.long 0x20++0x03
|
|
line.long 0x00 "USART_ICR,Interrupt flag clear register"
|
|
bitfld.long 0x00 20. " WUCF ,Wakeup from Stop mode clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 17. " CMCF ,Character match clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 11. " RTOCF ,Receiver timeout clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 8. " LBDCF ,LIN break detection clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 6. " TCCF ,Transmission complete clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IDLECF ,Idle line detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ORECF ,Overrun error clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " NCF ,Noise detected clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FECF ,Framing error clear flag" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PECF ,Parity error clear flag" "No effect,Clear"
|
|
hgroup.long 0x24++0x03
|
|
hide.long 0x00 "USART_RDR,Receive data register"
|
|
in
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "USART_TDR,Transmit data register"
|
|
hexmask.long.word 0x00 0.--8. 1. " TDR ,Transmit data value"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree.open "SPI/I2S (Serial peripheral interface/inter-IC sound)"
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
sif cpu()!="STM32F378CC"&&cpu()!="STM32F378RC"&&cpu()!="STM32F378VC"&&!cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
width 13.
|
|
if (((per.w(ad:0x40013000+0x04))&0x10)==0x10)
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data"
|
|
endif
|
|
endif
|
|
if (((per.w(ad:0x40013000+0x04))&0x10)==0x10)
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 11.--12. " FTLVL ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
width 0x0B
|
|
else
|
|
width 13.
|
|
if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x10))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x10))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x04++0x1
|
|
hide.word 0x00 "SPI_CR2,SPI Control Register 2"
|
|
endif
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI Status Register"
|
|
bitfld.word 0x00 11.--12. " FTLVL ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI Data Register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC Polynomial Register"
|
|
if (((per.w((ad:0x40013000+0x1C)))&0x800)==0x000)
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC Register"
|
|
hexmask.word 0x00 0.--15. 1. " RXCRC ,Rx CRC Register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x00 0.--15. 1. " TxCRC ,Tx CRC Register"
|
|
endif
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPIx_I2S Configuration Register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif !cpuis("STM32F334?4")&&!cpuis("STM32F334?6")&&!cpuis("STM32F334?8")
|
|
tree "SPI2/I2S2"
|
|
base ad:0x40003800
|
|
width 13.
|
|
if ((((per.w(ad:0x40003800+0x1C))&0x800)==0x00)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x10))
|
|
if (((per.w(ad:0x40003800))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40003800))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
endif
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40003800+0x1C))&0x800)==0x00)&&(((per.w((ad:0x40003800+0x04)))&0x10)==0x10))
|
|
if (((per.w(ad:0x40003800))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40003800))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " UDR ,Under-run flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SPI_DR,SPI SATA register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
if (((per.w(ad:0x40003800+0x1C))&0x800)==0x00)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,?..."
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
hgroup.word 0x20++0x01
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI3/I2S3"
|
|
base ad:0x40003C00
|
|
width 13.
|
|
if ((((per.w(ad:0x40003C00+0x1C))&0x800)==0x00)&&(((per.w(ad:0x40003C00+0x04))&0x10)==0x10))
|
|
if (((per.w(ad:0x40003C00))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
elif (((per.w(ad:0x40003C00+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40003C00))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
endif
|
|
elif (((per.w(ad:0x40003C00+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40003C00+0x1C))&0x800)==0x00)&&(((per.w((ad:0x40003C00+0x04)))&0x10)==0x10))
|
|
if (((per.w(ad:0x40003C00))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40003C00+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40003C00))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40003C00+0x1C))&0x800)==0x800)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " UDR ,Under-run flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SPI_DR,SPI SATA register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
if (((per.w(ad:0x40003C00+0x1C))&0x800)==0x00)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((per.w(ad:0x40003C00+0x1C))&0x800)==0x800)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,?..."
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
hgroup.word 0x20++0x01
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
tree "SPI4"
|
|
base ad:0x40013C00
|
|
width 13.
|
|
if (((per.w(ad:0x40013C00+0x04))&0x10)==0x10)
|
|
if (((per.w(ad:0x40013C00))&0x40)==0x40)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40013C00))&0x40)==0x40)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data"
|
|
else
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data"
|
|
endif
|
|
endif
|
|
if (((per.w(ad:0x40013C00+0x04))&0x10)==0x10)
|
|
if (((per.w(ad:0x40013C00))&0x40)==0x40)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40013C00))&0x40)==0x40)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
rbitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
rbitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 11.--12. " FTLVL ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI data register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
endif
|
|
else
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
tree "SPI1/I2S1"
|
|
base ad:0x40013000
|
|
width 13.
|
|
if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x00)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x10))
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
endif
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x00)&&(((per.w((ad:0x40013000+0x04)))&0x10)==0x10))
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40013000))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " UDR ,Under-run flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SPI_DR,SPI SATA register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x00)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,?..."
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
hgroup.word 0x20++0x01
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif (cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")
|
|
tree "SPI1"
|
|
base ad:0x40013000
|
|
width 13.
|
|
if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x10))
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)
|
|
group.word 0x00++0x1
|
|
line.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame Format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud Rate Control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master Selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock Polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock Phase" "First clock,First data"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x1
|
|
hide.word 0x00 "SPI_CR1,SPI Control Register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40013000+0x1C))&0x800)==0x000)&&(((per.w(ad:0x40013000+0x04))&0x10)==0x10))
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x000)
|
|
group.word 0x04++0x1
|
|
line.word 0x00 "SPI_CR2,SPI Control Register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX , Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40013000+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x04++0x1
|
|
hide.word 0x00 "SPI_CR2,SPI Control Register 2"
|
|
endif
|
|
group.word 0x08++0x1
|
|
line.word 0x00 "SPI_SR,SPI Status Register"
|
|
bitfld.word 0x00 11.--12. " FTLVL ,FIFO Transmission Level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
group.word 0x0C++0x1
|
|
line.word 0x00 "SPI_DR,SPI Data Register"
|
|
group.word 0x10++0x1
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC Polynomial Register"
|
|
if (((per.w((ad:0x40013000+0x1C)))&0x800)==0x000)
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC Register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC Register"
|
|
else
|
|
rgroup.word 0x14++0x1
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC Register"
|
|
hexmask.word 0x00 0.--15. 1. " RXCRC ,Rx CRC Register"
|
|
rgroup.word 0x18++0x1
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
hexmask.word 0x00 0.--15. 1. " TxCRC ,Tx CRC Register"
|
|
endif
|
|
group.word 0x1C++0x1
|
|
line.word 0x00 "SPI_I2SCFGR,SPIx_I2S Configuration Register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "SPI2/I2S2"
|
|
base ad:0x40003800
|
|
width 13.
|
|
if ((((per.w(ad:0x40003800+0x1C))&0x800)==0x00)&&(((per.w(ad:0x40003800+0x04))&0x10)==0x10))
|
|
if (((per.w(ad:0x40003800))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40003800))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
endif
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40003800+0x1C))&0x800)==0x00)&&(((per.w((ad:0x40003800+0x04)))&0x10)==0x10))
|
|
if (((per.w(ad:0x40003800))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40003800))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " UDR ,Under-run flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SPI_DR,SPI SATA register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
if (((per.w(ad:0x40003800+0x1C))&0x800)==0x00)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((per.w(ad:0x40003800+0x1C))&0x800)==0x800)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,?..."
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
hgroup.word 0x20++0x01
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI3/I2S3"
|
|
base ad:0x40003C00
|
|
width 13.
|
|
if ((((per.w(ad:0x40003C00+0x1C))&0x800)==0x00)&&(((per.w(ad:0x40003C00+0x04))&0x10)==0x10))
|
|
if (((per.w(ad:0x40003C00))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
textline " "
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
endif
|
|
elif (((per.w(ad:0x40003C00+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40003C00))&0x40)==0x40)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
rbitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
rbitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SPI_CR1,SPI control register 1"
|
|
bitfld.word 0x00 15. " BIDIMODE ,Bidirectional data mode enable" "Uni-directional,Bidirectional"
|
|
bitfld.word 0x00 14. " BIDIOE ,Output enable in bidirectional mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CRCEN ,Hardware CRC calculation enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 12. " CRCNEXT ,Transmit CRC next" "Tx buffer,Tx CRC register"
|
|
textline " "
|
|
bitfld.word 0x00 11. " CRCL ,CRC length" "8-bit,16-bit"
|
|
bitfld.word 0x00 10. " RXONLY ,Receive only" "Full duplex,Receive only"
|
|
bitfld.word 0x00 9. " SSM ,Software slave management" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SSI ,Internal slave select" "0 to NSS pin,1 to NSS pin"
|
|
textline " "
|
|
bitfld.word 0x00 7. " LSBFIRST ,Frame format" "MSB,LSB"
|
|
bitfld.word 0x00 6. " SPE ,SPI enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 3.--5. " BR ,Baud rate control" "fPCLK/2,fPCLK/4,fPCLK/8,fPCLK/16,fPCLK/32,fPCLK/64,fPCLK/128,fPCLK/256"
|
|
bitfld.word 0x00 2. " MSTR ,Master selection" "Slave,Master"
|
|
textline " "
|
|
bitfld.word 0x00 1. " CPOL ,Clock polarity" "0,1"
|
|
bitfld.word 0x00 0. " CPHA ,Clock phase" "First clock,First data"
|
|
endif
|
|
elif (((per.w(ad:0x40003C00+0x1C))&0x800)==0x800)
|
|
hgroup.word 0x00++0x01
|
|
hide.word 0x00 "SPI_CR1,SPI control register 1"
|
|
endif
|
|
if ((((per.w(ad:0x40003C00+0x1C))&0x800)==0x00)&&(((per.w((ad:0x40003C00+0x04)))&0x10)==0x10))
|
|
if (((per.w(ad:0x40003C00))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40003C00+0x1C))&0x800)==0x00)
|
|
if (((per.w(ad:0x40003C00))&0x40)==0x40)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
rbitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
rbitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
else
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 14. " LDMA_TX ,Last DMA transfer for transmission" "Even,Odd"
|
|
bitfld.word 0x00 13. " LDMA_RX ,Last DMA transfer for reception" "Even,Odd"
|
|
bitfld.word 0x00 12. " FRXTH ,FIFO reception threshold" "16-bit,8-bit"
|
|
bitfld.word 0x00 8.--11. " DS ,Data size" ",,,4-bit,5-bit,6-bit,7-bit,8-bit,9-bit,10-bit,11-bit,12-bit,13-bit,14-bit,15-bit,16-bit"
|
|
textline " "
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 4. " FRF ,Frame format" "Motorola mode,TI mode"
|
|
textline " "
|
|
bitfld.word 0x00 3. " NSSP ,NSS pulse management" "No pulse,Generated"
|
|
bitfld.word 0x00 2. " SSOE ,SS output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
rbitfld.word 0x00 11.--12. " FTLVL ,FIFO transmission level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 9.--10. " FRLVL ,FIFO reception level" "Empty,1/4,1/2,Full"
|
|
rbitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
rbitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
rbitfld.word 0x00 5. " MODF ,Mode fault" "Not occurred,Occurred"
|
|
bitfld.word 0x00 4. " CRCERR ,CRC error flag" "Matched,Not matched"
|
|
rbitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
elif (((per.w(ad:0x40003C00+0x1C))&0x800)==0x800)
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPI_CR2,SPI control register 2"
|
|
bitfld.word 0x00 7. " TXEIE ,Tx buffer empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 6. " RXNEIE ,RX buffer not empty interrupt enable" "Masked,Not masked"
|
|
bitfld.word 0x00 5. " ERRIE ,Error interrupt enable" "Masked,Enabled"
|
|
bitfld.word 0x00 1. " TXDMAEN ,Tx buffer DMA enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " RXDMAEN ,Rx buffer DMA enable" "Disabled,Enabled"
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "SPI_SR,SPI status register"
|
|
bitfld.word 0x00 8. " FRE ,Frame format error" "No error,Error"
|
|
bitfld.word 0x00 7. " BSY ,Busy flag" "Not busy,Busy/Tx buffer is not empty"
|
|
bitfld.word 0x00 6. " OVR ,Overrun flag" "Not occurred,Occurred"
|
|
bitfld.word 0x00 3. " UDR ,Under-run flag" "Not occurred,Occurred"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CHSIDE ,Channel side" "Left,Right"
|
|
bitfld.word 0x00 1. " TXE ,Transmit buffer empty" "Not empty,Empty"
|
|
bitfld.word 0x00 0. " RXNE ,Receive buffer not empty" "Empty,Not empty"
|
|
endif
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SPI_DR,SPI SATA register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPI_CRCPR,SPI CRC polynomial register"
|
|
if (((per.w(ad:0x40003C00+0x1C))&0x800)==0x00)
|
|
rgroup.word 0x14++0x01
|
|
line.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
else
|
|
hgroup.word 0x14++0x01
|
|
hide.word 0x00 "SPI_RXCRCR,SPI Rx CRC register"
|
|
hgroup.word 0x18++0x01
|
|
hide.word 0x00 "SPI_TXCRCR,SPI Tx CRC register"
|
|
endif
|
|
if (((per.w(ad:0x40003C00+0x1C))&0x800)==0x800)
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
bitfld.word 0x00 10. " I2SE ,I2S enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8.--9. " I2SCFG ,I2S configuration mode" "Slave - transmit,Slave - receive,Master - transmit,Master - receive"
|
|
bitfld.word 0x00 7. " PCMSYNC ,PCM frame synchronization" "Short,Long"
|
|
textline " "
|
|
bitfld.word 0x00 4.--5. " I2SSTD ,I2S standard selection" "Philips,MSB,LSB,PCM"
|
|
bitfld.word 0x00 3. " CKPOL ,Steady state clock polarity" "Low,High"
|
|
bitfld.word 0x00 1.--2. " DATLEN ,Data length to be transferred" "16-bit,24-bit,32-bit,?..."
|
|
bitfld.word 0x00 0. " CHLEN ,Channel length" "16-bit,32-bit"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
bitfld.word 0x00 9. " MCKOE ,Master clock output enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " ODD ,Odd factor for the prescaler" "I2SDIV *2,I2SDIV * 2+1"
|
|
textline " "
|
|
hexmask.word.byte 0x00 0.--7. 1. " I2SDIV ,I2S linear prescaler"
|
|
else
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "SPI_I2SCFGR,SPI_I2S configuration register"
|
|
bitfld.word 0x00 11. " I2SMOD ,I2S mode selection" "SPI,I2S"
|
|
hgroup.word 0x20++0x01
|
|
hide.word 0x00 "SPI_I2SPR,SPI_I2S prescaler register"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&!cpuis("STM32F302*6")&&!cpuis("STM32F302*8")&&!cpuis("STM32F303*6")&&!cpuis("STM32F303*8")&&cpu()!="STM32F328C8"&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"&&!cpuis("STM32F334*4")&&!cpuis("STM32F334*6")&&!cpuis("STM32F334*8")&&(cpu()!="STM32F358CC")&&(cpu()!="STM32F358RC")&&(cpu()!="STM32F358VC")&&(cpu()!="STM32F378CC")&&(cpu()!="STM32F378RC")&&(cpu()!="STM32F378VC")&&!cpuis("STM32F302*")&&!cpuis("STM32F303*")&&!cpuis("STM32F398VE")
|
|
tree "TSC (Touch sensing controller)"
|
|
base ad:0x40024000
|
|
width 12.
|
|
group.long 0x00++0x13
|
|
line.long 0x00 "TSC_CR,TSC control register"
|
|
bitfld.long 0x00 28.--31. " CTPH[3:0] ,Charge transfer pulse high" "1x t PGCLK,2x t PGCLK,3x t PGCLK,4x t PGCLK,5x t PGCLK,6x t PGCLK,7x t PGCLK,8x t PGCLK,9x t PGCLK,10x t PGCLK,11x t PGCLK,12x t PGCLK,13x t PGCLK,14x t PGCLK,15x t PGCLK,16x t PGCLK"
|
|
bitfld.long 0x00 24.--27. " CTPL[3:0] ,Charge transfer pulse low" "1x t PGCLK,2x t PGCLK,3x t PGCLK,4x t PGCLK,5x t PGCLK,6x t PGCLK,7x t PGCLK,8x t PGCLK,9x t PGCLK,10x t PGCLK,11x t PGCLK,12x t PGCLK,13x t PGCLK,14x t PGCLK,15x t PGCLK,16x t PGCLK"
|
|
hexmask.long.byte 0x00 17.--23. 1. " SSD[6:0] ,Spread spectrum deviation"
|
|
bitfld.long 0x00 16. " SSE ,Spread spectrum enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SSPSC ,Spread spectrum prescaler" "Fhclk,Fhclk /2"
|
|
bitfld.long 0x00 12.--14. " PGPSC[2:0] ,Pulse generator prescaler" "Fhclk,Fhclk /2,Fhclk /4,Fhclk /8,Fhclk /16,Fhclk /32,Fhclk /64,Fhclk /128"
|
|
bitfld.long 0x00 5.--7. " MCV[2:0] ,Max count value" "255,511,1023,2047,4095,8191,16383,?..."
|
|
bitfld.long 0x00 4. " IODEF ,I/O Default mode" "Output push-pull low,Input floating"
|
|
textline " "
|
|
bitfld.long 0x00 3. " SYNCPOL ,Synchronization pin polarity" "Falling edge,Rising edge and high level"
|
|
bitfld.long 0x00 2. " AM ,Acquisition mode" "Normal,Synchronized"
|
|
bitfld.long 0x00 1. " START ,Start a new acquisition" "Not started,Started"
|
|
bitfld.long 0x00 0. " TSCE ,Touch sensing controller enable" "Disabled,Enabled"
|
|
line.long 0x04 "TSC_IER,TSC interrupt enable register"
|
|
bitfld.long 0x04 1. " MCEIE ,Max count error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x04 0. " EOAIE ,End of acquisition interrupt enable" "Disabled,Enabled"
|
|
line.long 0x08 "TSC_ICR,TSC interrupt clear register"
|
|
bitfld.long 0x08 1. " MCEIC ,Max count error interrupt clear" "No effect,Cleared"
|
|
bitfld.long 0x08 0. " EOAIC ,End of acquisition interrupt clear" "No effect,Cleared"
|
|
line.long 0x0C "TSC_ISR,TSC interrupt status register"
|
|
bitfld.long 0x0C 1. " MCEF ,Max count error flag" "Not detected,Detected"
|
|
bitfld.long 0x0C 0. " EOAF ,End of acquisition flag" "Not occurred,Occurred"
|
|
line.long 0x10 "TSC_IOHCR,TSC I/O hysteresis control register"
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x10 31. " G8_IO4 ,G8_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 30. " G8_IO3 ,G8_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 29. " G8_IO2 ,G8_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 28. " G8_IO1 ,G8_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 27. " G7_IO4 ,G7_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 26. " G7_IO3 ,G7_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 25. " G7_IO2 ,G7_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 24. " G7_IO1 ,G7_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&!CPUIS("STM32F050*")&&!CPUIS("STM32F042*"))
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")
|
|
bitfld.long 0x10 23. " G6_IO4 ,G6_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 22. " G6_IO3 ,G6_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 21. " G6_IO2 ,G6_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 20. " G6_IO1 ,G6_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 19. " G5_IO4 ,G5_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 18. " G5_IO3 ,G5_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 17. " G5_IO2 ,G5_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 16. " G5_IO1 ,G5_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 15. " G4_IO4 ,G4_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 14. " G4_IO3 ,G4_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 13. " G4_IO2 ,G4_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 12. " G4_IO1 ,G4_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x10 11. " G3_IO4 ,G3_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x10 10. " G3_IO3 ,G3_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 9. " G3_IO2 ,G3_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
sif !CPUIS("STM32F050*")&&!CPUIS("STM32F042*")
|
|
bitfld.long 0x10 8. " G3_IO1 ,G3_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x10 7. " G2_IO4 ,G2_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x10 6. " G2_IO3 ,G2_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 5. " G2_IO2 ,G2_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 4. " G2_IO1 ,G2_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 3. " G1_IO4 ,G1_IO4 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x10 2. " G1_IO3 ,G1_IO3 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 1. " G1_IO2 ,G1_IO2 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
bitfld.long 0x10 0. " G1_IO1 ,G1_IO1 Schmitt trigger hysteresis mode" "Disabled,Enabled"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TSC_IOASCR,TSC I/O analog switch control register"
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&!CPUIS("STM32F050*")&&!CPUIS("STM32F042*"))
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
sif !CPUIS("STM32F050*")&&!CPUIS("STM32F042*")
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 analog switch enable" "Opened,Closed"
|
|
textline " "
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 analog switch enable" "Opened,Closed"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 analog switch enable" "Opened,Closed"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TSC_IOSCR,TSC I/O sampling control register"
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&!CPUIS("STM32F050*")&&!CPUIS("STM32F042*"))
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 sampling mode" "Unused,Used"
|
|
textline " "
|
|
sif !CPUIS("STM32F050*")&&!CPUIS("STM32F042*")
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 sampling mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 sampling mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 sampling mode" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 sampling mode" "Unused,Used"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TSC_IOCCR,TSC I/O channel control register"
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 31. " G8_IO4 ,G8_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 30. " G8_IO3 ,G8_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 29. " G8_IO2 ,G8_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 28. " G8_IO1 ,G8_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 27. " G7_IO4 ,G7_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 26. " G7_IO3 ,G7_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 25. " G7_IO2 ,G7_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 24. " G7_IO1 ,G7_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&!CPUIS("STM32F050*")&&!CPUIS("STM32F042*"))
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372RC")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372R8")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F372RB")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373RB")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373RC")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F373R8")&&(cpu()!="STM32F383CC")&&(cpu()!="STM32F383RC")
|
|
bitfld.long 0x00 23. " G6_IO4 ,G6_IO4 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 22. " G6_IO3 ,G6_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 21. " G6_IO2 ,G6_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 20. " G6_IO1 ,G6_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " G5_IO4 ,G5_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 18. " G5_IO3 ,G5_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 17. " G5_IO2 ,G5_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 16. " G5_IO1 ,G5_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 15. " G4_IO4 ,G4_IO4 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 14. " G4_IO3 ,G4_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 13. " G4_IO2 ,G4_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 12. " G4_IO1 ,G4_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
sif (cpu()!="STM32F302CB")&&(cpu()!="STM32F302CC")&&(cpu()!="STM32F303CB")&&(cpu()!="STM32F303CC")&&(cpu()!="STM32F313CC")&&(cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 11. " G3_IO4 ,G3_IO4 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 10. " G3_IO3 ,G3_IO3 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 9. " G3_IO2 ,G3_IO2 channel mode" "Unused,Used"
|
|
textline " "
|
|
sif !CPUIS("STM32F050*")&&!CPUIS("STM32F042*")
|
|
bitfld.long 0x00 8. " G3_IO1 ,G3_IO1 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
sif (cpu()!="STM32F372CB")&&(cpu()!="STM32F372CC")&&(cpu()!="STM32F372C8")&&(cpu()!="STM32F373C8")&&(cpu()!="STM32F373CB")&&(cpu()!="STM32F373CC")&&(cpu()!="STM32F383CC")
|
|
bitfld.long 0x00 7. " G2_IO4 ,G2_IO4 channel mode" "Unused,Used"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 6. " G2_IO3 ,G2_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 5. " G2_IO2 ,G2_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 4. " G2_IO1 ,G2_IO1 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 3. " G1_IO4 ,G1_IO4 channel mode" "Unused,Used"
|
|
textline " "
|
|
bitfld.long 0x00 2. " G1_IO3 ,G1_IO3 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 1. " G1_IO2 ,G1_IO2 channel mode" "Unused,Used"
|
|
bitfld.long 0x00 0. " G1_IO1 ,G1_IO1 channel mode" "Unused,Used"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TSC_IOGCSR,TSC I/O group control status register"
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 23. " G8S ,Analog I/O group 8 status" "Not started,Completed"
|
|
bitfld.long 0x00 22. " G7S ,Analog I/O group 7 status" "Not started,Completed"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&!CPUIS("STM32F050*")&&!CPUIS("STM32F042*"))
|
|
bitfld.long 0x00 21. " G6S ,Analog I/O group 6 status" "Not started,Completed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 20. " G5S ,Analog I/O group 5 status" "Not started,Completed"
|
|
bitfld.long 0x00 19. " G4S ,Analog I/O group 4 status" "Not started,Completed"
|
|
bitfld.long 0x00 18. " G3S ,Analog I/O group 3 status" "Not started,Completed"
|
|
bitfld.long 0x00 17. " G2S ,Analog I/O group 2 status" "Not started,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 16. " G1S ,Analog I/O group 1 status" "Not started,Completed"
|
|
textline " "
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x00 7. " G8E ,Analog I/O group 8 status" "Not started,Completed"
|
|
bitfld.long 0x00 6. " G7E ,Analog I/O group 7 status" "Not started,Completed"
|
|
textline " "
|
|
endif
|
|
sif (CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&!CPUIS("STM32F050*")&&!CPUIS("STM32F042*"))
|
|
bitfld.long 0x00 5. " G6E ,Analog I/O group 6 status" "Not started,Completed"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " G5E ,Analog I/O group 5 status" "Not started,Completed"
|
|
bitfld.long 0x00 3. " G4E ,Analog I/O group 4 status" "Not started,Completed"
|
|
bitfld.long 0x00 2. " G3E ,Analog I/O group 3 status" "Not started,Completed"
|
|
bitfld.long 0x00 1. " G2E ,Analog I/O group 2 status" "Not started,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 0. " G1E ,Analog I/O group 1 status" "Not started,Completed"
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
rgroup.long 0x34++0x1B
|
|
else
|
|
group.long 0x34++0x1B
|
|
endif
|
|
line.long 0x0 "TSC_IOG1CR,TSC I/O group 1 counter register"
|
|
hexmask.long.word 0x0 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
line.long 0x4 "TSC_IOG2CR,TSC I/O group 2 counter register"
|
|
hexmask.long.word 0x4 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
line.long 0x8 "TSC_IOG3CR,TSC I/O group 3 counter register"
|
|
hexmask.long.word 0x8 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
line.long 0xC "TSC_IOG4CR,TSC I/O group 4 counter register"
|
|
hexmask.long.word 0xC 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
line.long 0x10 "TSC_IOG5CR,TSC I/O group 5 counter register"
|
|
hexmask.long.word 0x10 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
line.long 0x14 "TSC_IOG6CR,TSC I/O group 6 counter register"
|
|
hexmask.long.word 0x14 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
sif (cpu()=="STM32F302VB")||(cpu()=="STM32F302VC")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383VC")
|
|
rgroup.long 0x4C++0x1B
|
|
line.long 0x0 "TSC_IOG7CR,TSC I/O group 7 counter register"
|
|
hexmask.long.word 0x0 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
line.long 0x4 "TSC_IOG8CR,TSC I/O group 8 counter register"
|
|
hexmask.long.word 0x4 0.--13. 1. " CNT[13:0] ,Counter value"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif !cpuis("STM32F301*6")&&!cpuis("STM32F301*8")&&cpu()!="STM32F318C8"&&cpu()!="STM32F318K8"
|
|
tree "CAN (Controller Area Network)"
|
|
base ad:0x40006400
|
|
width 11.
|
|
group.long 0x00++0x1F
|
|
line.long 0x00 "CAN_MCR,CAN Master Control Register"
|
|
bitfld.long 0x00 16. " DBF ,Debug freeze" "Not frozen,Frozen"
|
|
bitfld.long 0x00 15. " RESET ,bxCAN software master reset" "No reset,Reset"
|
|
bitfld.long 0x00 7. " TTCM ,Time Triggered Communication Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " ABOM ,Automatic Bus-Off Management" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " AWUM ,Automatic Wake-Up Mode" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " NART ,No Automatic Retransmission" "Retransmitted,Transmitted once"
|
|
bitfld.long 0x00 3. " RFLM ,Receive FIFO Locked Mode" "Not locked,Locked"
|
|
bitfld.long 0x00 2. " TXFP ,Transmit FIFO Priority" "Identifier,Request order"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEP ,SLEEP Mode Request" "Normal mode,Sleep mode"
|
|
bitfld.long 0x00 0. " INRQ ,Initialization Request" "No effect,Initialize"
|
|
line.long 0x04 "CAN_MSR,CAN Master Status Register"
|
|
rbitfld.long 0x04 11. " RX ,CAN Rx Signal" "0,1"
|
|
rbitfld.long 0x04 10. " SAMP ,Last Sample Point" "0,1"
|
|
rbitfld.long 0x04 9. " RXM ,Receive Mode" "Not receiving,Receiving"
|
|
rbitfld.long 0x04 8. " TXM ,Transmit Mode" "Not transmitting,Transmitting"
|
|
textline " "
|
|
eventfld.long 0x04 4. " SLAKI ,SLEEP Acknowledge Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 3. " WKUI ,Wake-Up Interrupt" "No interrupt,Interrupt"
|
|
eventfld.long 0x04 2. " ERRI ,Error Interrupt" "No interrupt,Interrupt"
|
|
rbitfld.long 0x04 1. " SLAK ,SLEEP Acknowledge" "No sleep,Sleep"
|
|
textline " "
|
|
rbitfld.long 0x04 0. " INAK ,Initialization Acknowledge" "No initialization,Initialization"
|
|
line.long 0x08 "CAN_TSR,CAN Transmit Status Register"
|
|
rbitfld.long 0x08 31. " LOW2 ,Lowest Priority Flag for Mailbox 2" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 30. " LOW1 ,Lowest Priority Flag for Mailbox 1" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 29. " LOW0 ,Lowest Priority Flag for Mailbox 0" "Not lowest,Lowest"
|
|
rbitfld.long 0x08 28. " TME2 ,Transmit Mailbox 2 Empty" "Not empty,Empty"
|
|
textline " "
|
|
rbitfld.long 0x08 27. " TME1 ,Transmit Mailbox 1 Empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 26. " TME0 ,Transmit Mailbox 0 Empty" "Not empty,Empty"
|
|
rbitfld.long 0x08 24.--25. " CODE ,Mailbox Code" "0,1,2,3"
|
|
bitfld.long 0x08 23. " ABRQ2 ,Abort Request for Mailbox 2" "No effect,Abort"
|
|
textline " "
|
|
eventfld.long 0x08 19. " TERR2 ,Transmission Error of Mailbox 2" "No error,Error"
|
|
eventfld.long 0x08 18. " ALST2 ,Arbitration Lost for Mailbox 2" "Not lost,Lost"
|
|
eventfld.long 0x08 17. " TXOK2 ,Transmission OK of Mailbox 2" "Failed,Successful"
|
|
eventfld.long 0x08 16. " RQCP2 ,Request Completed Mailbox 2" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x08 15. " ABRQ1 ,Abort Request for Mailbox 1" "No effect,Abort"
|
|
eventfld.long 0x08 11. " TERR1 ,Transmission Error of Mailbox 1" "No error,Error"
|
|
eventfld.long 0x08 10. " ALST1 ,Arbitration Lost for Mailbox 1" "Not lost,Lost"
|
|
eventfld.long 0x08 9. " TXOK1 ,Transmission OK of Mailbox 1" "Failed,Successful"
|
|
textline " "
|
|
eventfld.long 0x08 8. " RQCP1 ,Request Completed Mailbox 1" "Not completed,Completed"
|
|
bitfld.long 0x08 7. " ABRQ0 ,Abort Request for Mailbox 0" "No effect,Abort"
|
|
eventfld.long 0x08 3. " TERR0 ,Transmission Error of Mailbox 0" "No error,Error"
|
|
eventfld.long 0x08 2. " ALST0 ,Arbitration Lost for Mailbox 0" "Not lost,Lost"
|
|
textline " "
|
|
eventfld.long 0x08 1. " TXOK0 ,Transmission OK of Mailbox 0" "Failed,Successful"
|
|
eventfld.long 0x08 0. " RQCP0 ,Request Completed Mailbox 0" "Not completed,Completed"
|
|
line.long 0x0C "CAN_RF0R,CAN Receive FIFO 0 Register"
|
|
bitfld.long 0x0C 5. " RFOM0 ,Release FIFO 0 Output Mailbox" "No effect,Release"
|
|
eventfld.long 0x0C 4. " FOVR0 ,FIFO 0 Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x0C 3. " FULL0 ,FIFO 0 Full" "Not full,Full"
|
|
rbitfld.long 0x0C 0.--1. " FMP0 ,FIFO 0 Message Pending" "0,1,2,3"
|
|
line.long 0x10 "CAN_RF1R,CAN Receive FIFO 1 Register"
|
|
bitfld.long 0x10 5. " RFOM1 ,Release FIFO 1 Output Mailbox" "No effect,Release"
|
|
eventfld.long 0x10 4. " FOVR1 ,FIFO 1 Overrun" "No overrun,Overrun"
|
|
eventfld.long 0x10 3. " FULL1 ,FIFO 1 Full" "Not full,Full"
|
|
rbitfld.long 0x10 0.--1. " FMP1 ,FIFO 1 Message Pending" "0,1,2,3"
|
|
line.long 0x14 "CAN_IER,CAN Interrupt Enable Register"
|
|
bitfld.long 0x14 17. " SLKIE ,SLEEP Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 16. " WKUIE ,Wake-Up Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 15. " ERRIE ,Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 11. " LECIE ,Last Error Code Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 10. " BOFIE ,Bus-Off Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 9. " EPVIE ,Error Passive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 8. " EWGIE ,Error Warning Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 6. " FOVIE1 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 5. " FFIE1 ,FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 4. " FMPIE1 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 3. " FOVIE0 ,FIFO Overrun Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 2. " FFIE0 ,FIFO Full Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x14 1. " FMPIE0 ,FIFO Message Pending Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.long 0x14 0. " TMEIE ,Transmit Mailbox Empty Interrupt Enable" "Disabled,Enabled"
|
|
line.long 0x18 "CAN_ESR,CAN Error Status Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " REC ,Receive Error Counter"
|
|
hexmask.long.byte 0x18 16.--23. 1. " TEC ,Least significant byte of the 9-bit Transmit Error Counter"
|
|
bitfld.long 0x18 4.--6. " LEC ,Last Error Code" "No error,Stuff,Form,Acknowledgement,Bit recessive,Bit dominant,CRC,Set by software"
|
|
rbitfld.long 0x18 2. " BOFF ,Bus-Off Flag" "Not occurred,Occurred"
|
|
textline " "
|
|
rbitfld.long 0x18 1. " EPVF ,Error Passive Flag" "Not occurred,Occurred"
|
|
rbitfld.long 0x18 0. " EWGF ,Error Warning Flag" "Not occurred,Occurred"
|
|
line.long 0x1C "CAN_BTR,CAN Bit Timing Register"
|
|
bitfld.long 0x1C 31. " SILM ,Silent Mode" "Normal,Silent"
|
|
bitfld.long 0x1C 30. " LBKM ,Loop Back Mode" "Disabled,Enabled"
|
|
bitfld.long 0x1C 24.--25. " SJW ,Resynchronization Jump Width" "0,1,2,3"
|
|
bitfld.long 0x1C 20.--22. " TS2 ,Time Segment 2" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x1C 16.--19. " TS1 ,Time Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x1C 0.--9. 1. " BRP ,Baud Rate Prescaler"
|
|
tree "T0 Mailbox"
|
|
if (((per.l((ad:0x40006400+0x180)))&0x4)==0x4)
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "CAN_TI0R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x180+0x04)++0x0B
|
|
line.long 0x00 "CAN_TDT0R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_TDL0R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_TDH0R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "T1 Mailbox"
|
|
if (((per.l((ad:0x40006400+0x190)))&0x4)==0x4)
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "CAN_TI1R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x190+0x04)++0x0B
|
|
line.long 0x00 "CAN_TDT1R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_TDL1R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_TDH1R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "T2 Mailbox"
|
|
if (((per.l((ad:0x40006400+0x1A0)))&0x4)==0x4)
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
else
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "CAN_TI2R,TX Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
bitfld.long 0x00 0. " TXRQ ,Transmit Mailbox Request" "Not requested,Requested"
|
|
endif
|
|
group.long (0x1A0+0x04)++0x0B
|
|
line.long 0x00 "CAN_TDT2R,Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
bitfld.long 0x00 8. " TGT ,Transmit Global Time" "Not sent,Sent"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_TDL2R,Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_TDH2R,Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "FIFO 0"
|
|
if (((per.l((ad:0x40006400+0x1B0)))&0x4)==0x4)
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "CAN_RI0R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1B0+0x04)++0x0B
|
|
line.long 0x00 "CAN_RDT0R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_RDL0R,Receive FIFO Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_RDH0R,Receive FIFO Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "FIFO 1"
|
|
if (((per.l((ad:0x40006400+0x1C0)))&0x4)==0x4)
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long 0x00 3.--31. 1. " EXID ,Extended Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
else
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "CAN_RI1R,Rx FIFO Mailbox Identifier Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " STID ,Standard Identifier"
|
|
bitfld.long 0x00 2. " IDE ,Extended Identifier" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 1. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
endif
|
|
rgroup.long (0x1C0+0x04)++0x0B
|
|
line.long 0x00 "CAN_RDT1R,Receive FIFO Mailbox Data Length Control And Time Stamp Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " TIME ,Message Time Stamp"
|
|
hexmask.long.byte 0x00 8.--15. 1. " FMI ,Filter Match Index"
|
|
textline " "
|
|
bitfld.long 0x00 0.--3. " DLC ,Data Length Code" "0,1,2,3,4,5,6,7,8,?..."
|
|
line.long 0x04 "CAN_RDL1R,Receive FIFO Mailbox Data Low Register"
|
|
hexmask.long.byte 0x04 24.--31. 1. " DATA3 ,Data Byte 3"
|
|
hexmask.long.byte 0x04 16.--23. 1. " DATA2 ,Data Byte 2"
|
|
hexmask.long.byte 0x04 8.--15. 1. " DATA1 ,Data Byte 1"
|
|
hexmask.long.byte 0x04 0.--7. 1. " DATA0 ,Data Byte 0"
|
|
line.long 0x08 "CAN_RDH1R,Receive FIFO Mailbox Data High Register"
|
|
hexmask.long.byte 0x08 24.--31. 1. " DATA7 ,Data Byte 7"
|
|
hexmask.long.byte 0x08 16.--23. 1. " DATA6 ,Data Byte 6"
|
|
hexmask.long.byte 0x08 8.--15. 1. " DATA5 ,Data Byte 5"
|
|
hexmask.long.byte 0x08 0.--7. 1. " DATA4 ,Data Byte 4"
|
|
tree.end
|
|
tree "Filter Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "CAN_FMR,CAN Filter Master Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*")&&!cpuis("STM32F446*")&&!cpuis("STM32F412*")&&!cpuis("STM32F469*")&&!cpuis("STM32F479*")&&!cpuis("STM32F413*")&&!cpuis("STM32F423?H")||cpuis("STM32F103TB")||cpuis("STM32F7*"))
|
|
hexmask.long.byte 0x00 8.--13. 1. " CAN2SB ,CAN2 start bank"
|
|
bitfld.long 0x00 0. " FINIT ,Filter Init Mode" "Active mode,Initialization"
|
|
else
|
|
sif (cpu()=="STM32F372CB")||(cpuis("STM32F446*"))||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F412*")||cpuis("STM32F469*")||cpuis("STM32F479*")||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
hexmask.long.byte 0x00 8.--13. 1. " CANSB ,CAN start bank"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " FINIT ,Filter Init Mode" "Active,Initialization"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "CAN_FM1R,CAN Filter Mode Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FBM27 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 26. " FBM26 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 25. " FBM25 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FBM24 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 23. " FBM23 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 22. " FBM22 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FBM21 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 20. " FBM20 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 19. " FBM19 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FBM18 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 17. " FBM17 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 16. " FBM16 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FBM15 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 14. " FBM14 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FBM13 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 12. " FBM12 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 11. " FBM11 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FBM10 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 9. " FBM9 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 8. " FBM8 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FBM7 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 6. " FBM6 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 5. " FBM5 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FBM4 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 3. " FBM3 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 2. " FBM2 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FBM1 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 0. " FBM0 ,Filter Mode" "Mask,List"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "CAN_FS1R,CAN Filter Scale Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FSC27 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 26. " FSC26 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 25. " FSC25 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FSC24 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 23. " FSC23 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 22. " FSC22 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FSC21 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 20. " FSC20 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 19. " FSC19 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FSC18 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 17. " FSC17 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 16. " FSC16 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FSC15 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 14. " FSC14 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FSC13 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 12. " FSC12 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 11. " FSC11 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSC10 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 9. " FSC9 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 8. " FSC8 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FSC7 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 6. " FSC6 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 5. " FSC5 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FSC4 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 3. " FSC3 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 2. " FSC2 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSC1 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 0. " FSC0 ,Filter Scale Configuration" "Dual,Single"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "CAN_FFA1R,CAN Filter FIFO Assignment Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FFA27 ,Filter FIFO Assignment for Filter 27" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 26. " FFA26 ,Filter FIFO Assignment for Filter 26" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 25. " FFA25 ,Filter FIFO Assignment for Filter 25" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FFA24 ,Filter FIFO Assignment for Filter 24" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 23. " FFA23 ,Filter FIFO Assignment for Filter 23" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 22. " FFA22 ,Filter FIFO Assignment for Filter 22" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FFA21 ,Filter FIFO Assignment for Filter 21" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 20. " FFA20 ,Filter FIFO Assignment for Filter 20" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 19. " FFA19 ,Filter FIFO Assignment for Filter 19" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FFA18 ,Filter FIFO Assignment for Filter 18" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 17. " FFA17 ,Filter FIFO Assignment for Filter 17" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 16. " FFA16 ,Filter FIFO Assignment for Filter 16" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FFA15 ,Filter FIFO Assignment for Filter 15" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 14. " FFA14 ,Filter FIFO Assignment for Filter 14" "FIFO0,FIFO1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FFA13 ,Filter FIFO Assignment for Filter 13" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 12. " FFA12 ,Filter FIFO Assignment for Filter 12" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 11. " FFA11 ,Filter FIFO Assignment for Filter 11" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FFA10 ,Filter FIFO Assignment for Filter 10" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 9. " FFA9 ,Filter FIFO Assignment for Filter 9" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 8. " FFA8 ,Filter FIFO Assignment for Filter 8" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FFA7 ,Filter FIFO Assignment for Filter 7" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 6. " FFA6 ,Filter FIFO Assignment for Filter 6" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 5. " FFA5 ,Filter FIFO Assignment for Filter 5" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FFA4 ,Filter FIFO Assignment for Filter 4" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 3. " FFA3 ,Filter FIFO Assignment for Filter 3" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 2. " FFA2 ,Filter FIFO Assignment for Filter 2" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FFA1 ,Filter FIFO Assignment for Filter 1" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 0. " FFA0 ,Filter FIFO Assignment for Filter 0" "FIFO0,FIFO1"
|
|
else
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "CAN_FM1R,CAN Filter Mode Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FBM27 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 26. " FBM26 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 25. " FBM25 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FBM24 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 23. " FBM23 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 22. " FBM22 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FBM21 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 20. " FBM20 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 19. " FBM19 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FBM18 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 17. " FBM17 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 16. " FBM16 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FBM15 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 14. " FBM14 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FBM13 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 12. " FBM12 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 11. " FBM11 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FBM10 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 9. " FBM9 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 8. " FBM8 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FBM7 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 6. " FBM6 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 5. " FBM5 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FBM4 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 3. " FBM3 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 2. " FBM2 ,Filter Mode" "Mask,List"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FBM1 ,Filter Mode" "Mask,List"
|
|
bitfld.long 0x00 0. " FBM0 ,Filter Mode" "Mask,List"
|
|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "CAN_FS1R,CAN Filter Scale Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FSC27 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 26. " FSC26 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 25. " FSC25 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FSC24 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 23. " FSC23 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 22. " FSC22 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FSC21 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 20. " FSC20 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 19. " FSC19 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FSC18 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 17. " FSC17 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 16. " FSC16 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FSC15 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
bitfld.long 0x00 14. " FSC14 ,Filter Scale Configuration" "2 x 16-bit,1 x 32-bit"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FSC13 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 12. " FSC12 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 11. " FSC11 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FSC10 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 9. " FSC9 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 8. " FSC8 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FSC7 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 6. " FSC6 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 5. " FSC5 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FSC4 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 3. " FSC3 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 2. " FSC2 ,Filter Scale Configuration" "Dual,Single"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FSC1 ,Filter Scale Configuration" "Dual,Single"
|
|
bitfld.long 0x00 0. " FSC0 ,Filter Scale Configuration" "Dual,Single"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "CAN_FFA1R,CAN Filter FIFO Assignment Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FFA27 ,Filter FIFO Assignment for Filter 27" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 26. " FFA26 ,Filter FIFO Assignment for Filter 26" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 25. " FFA25 ,Filter FIFO Assignment for Filter 25" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 24. " FFA24 ,Filter FIFO Assignment for Filter 24" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 23. " FFA23 ,Filter FIFO Assignment for Filter 23" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 22. " FFA22 ,Filter FIFO Assignment for Filter 22" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FFA21 ,Filter FIFO Assignment for Filter 21" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 20. " FFA20 ,Filter FIFO Assignment for Filter 20" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 19. " FFA19 ,Filter FIFO Assignment for Filter 19" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " FFA18 ,Filter FIFO Assignment for Filter 18" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 17. " FFA17 ,Filter FIFO Assignment for Filter 17" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 16. " FFA16 ,Filter FIFO Assignment for Filter 16" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FFA15 ,Filter FIFO Assignment for Filter 15" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 14. " FFA14 ,Filter FIFO Assignment for Filter 14" "FIFO0,FIFO1"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FFA13 ,Filter FIFO Assignment for Filter 13" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 12. " FFA12 ,Filter FIFO Assignment for Filter 12" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 11. " FFA11 ,Filter FIFO Assignment for Filter 11" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 10. " FFA10 ,Filter FIFO Assignment for Filter 10" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 9. " FFA9 ,Filter FIFO Assignment for Filter 9" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 8. " FFA8 ,Filter FIFO Assignment for Filter 8" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FFA7 ,Filter FIFO Assignment for Filter 7" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 6. " FFA6 ,Filter FIFO Assignment for Filter 6" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 5. " FFA5 ,Filter FIFO Assignment for Filter 5" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 4. " FFA4 ,Filter FIFO Assignment for Filter 4" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 3. " FFA3 ,Filter FIFO Assignment for Filter 3" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 2. " FFA2 ,Filter FIFO Assignment for Filter 2" "FIFO0,FIFO1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FFA1 ,Filter FIFO Assignment for Filter 1" "FIFO0,FIFO1"
|
|
bitfld.long 0x00 0. " FFA0 ,Filter FIFO Assignment for Filter 0" "FIFO0,FIFO1"
|
|
endif
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "CAN_FA1R,CAN Filter Activation Register"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
bitfld.long 0x00 27. " FACT27 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 26. " FACT26 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FACT25 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 24. " FACT24 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FACT23 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 22. " FACT22 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FACT21 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 20. " FACT20 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FACT19 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 18. " FACT18 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FACT17 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 16. " FACT16 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FACT15 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 14. " FACT14 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 13. " FACT13 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 12. " FACT12 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FACT11 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 10. " FACT10 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FACT9 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 8. " FACT8 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FACT7 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 6. " FACT6 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FACT5 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 4. " FACT4 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FACT3 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 2. " FACT2 ,Filter Active" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FACT1 ,Filter Active" "Not active,Active"
|
|
bitfld.long 0x00 0. " FACT0 ,Filter Active" "Not active,Active"
|
|
tree "Filter Bank Registers"
|
|
sif (cpuis("STM32F105*")||cpuis("STM32F107*")||cpuis("STM32F2*")||cpuis("STM32F4*"))||((cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpuis("STM32F7*"))
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<0.))==0x00)
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "CAN_F0R1,Filter Bank 0_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "CAN_F0R1,Filter Bank 0_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<0.))==0x00)
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "CAN_F0R2,Filter Bank 0_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x244++0x03
|
|
line.long 0x00 "CAN_F0R2,Filter Bank 0_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<1.))==0x00)
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "CAN_F1R1,Filter Bank 1_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x248++0x03
|
|
line.long 0x00 "CAN_F1R1,Filter Bank 1_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<1.))==0x00)
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "CAN_F1R2,Filter Bank 1_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x24C++0x03
|
|
line.long 0x00 "CAN_F1R2,Filter Bank 1_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<2.))==0x00)
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "CAN_F2R1,Filter Bank 2_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x250++0x03
|
|
line.long 0x00 "CAN_F2R1,Filter Bank 2_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<2.))==0x00)
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "CAN_F2R2,Filter Bank 2_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x254++0x03
|
|
line.long 0x00 "CAN_F2R2,Filter Bank 2_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<3.))==0x00)
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "CAN_F3R1,Filter Bank 3_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x258++0x03
|
|
line.long 0x00 "CAN_F3R1,Filter Bank 3_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<3.))==0x00)
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "CAN_F3R2,Filter Bank 3_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "CAN_F3R2,Filter Bank 3_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<4.))==0x00)
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "CAN_F4R1,Filter Bank 4_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x260++0x03
|
|
line.long 0x00 "CAN_F4R1,Filter Bank 4_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<4.))==0x00)
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "CAN_F4R2,Filter Bank 4_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x264++0x03
|
|
line.long 0x00 "CAN_F4R2,Filter Bank 4_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<5.))==0x00)
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "CAN_F5R1,Filter Bank 5_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x268++0x03
|
|
line.long 0x00 "CAN_F5R1,Filter Bank 5_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<5.))==0x00)
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "CAN_F5R2,Filter Bank 5_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x26C++0x03
|
|
line.long 0x00 "CAN_F5R2,Filter Bank 5_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<6.))==0x00)
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "CAN_F6R1,Filter Bank 6_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x270++0x03
|
|
line.long 0x00 "CAN_F6R1,Filter Bank 6_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<6.))==0x00)
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "CAN_F6R2,Filter Bank 6_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x274++0x03
|
|
line.long 0x00 "CAN_F6R2,Filter Bank 6_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<7.))==0x00)
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "CAN_F7R1,Filter Bank 7_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x278++0x03
|
|
line.long 0x00 "CAN_F7R1,Filter Bank 7_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<7.))==0x00)
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "CAN_F7R2,Filter Bank 7_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x27C++0x03
|
|
line.long 0x00 "CAN_F7R2,Filter Bank 7_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<8.))==0x00)
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "CAN_F8R1,Filter Bank 8_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x280++0x03
|
|
line.long 0x00 "CAN_F8R1,Filter Bank 8_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<8.))==0x00)
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "CAN_F8R2,Filter Bank 8_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "CAN_F8R2,Filter Bank 8_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<9.))==0x00)
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "CAN_F9R1,Filter Bank 9_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "CAN_F9R1,Filter Bank 9_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<9.))==0x00)
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "CAN_F9R2,Filter Bank 9_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x28C++0x03
|
|
line.long 0x00 "CAN_F9R2,Filter Bank 9_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<10.))==0x00)
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "CAN_F10R1,Filter Bank 10_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x290++0x03
|
|
line.long 0x00 "CAN_F10R1,Filter Bank 10_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<10.))==0x00)
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "CAN_F10R2,Filter Bank 10_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "CAN_F10R2,Filter Bank 10_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<11.))==0x00)
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "CAN_F11R1,Filter Bank 11_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "CAN_F11R1,Filter Bank 11_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<11.))==0x00)
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "CAN_F11R2,Filter Bank 11_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x29C++0x03
|
|
line.long 0x00 "CAN_F11R2,Filter Bank 11_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<12.))==0x00)
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "CAN_F12R1,Filter Bank 12_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2A0++0x03
|
|
line.long 0x00 "CAN_F12R1,Filter Bank 12_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<12.))==0x00)
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "CAN_F12R2,Filter Bank 12_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2A4++0x03
|
|
line.long 0x00 "CAN_F12R2,Filter Bank 12_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<13.))==0x00)
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "CAN_F13R1,Filter Bank 13_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2A8++0x03
|
|
line.long 0x00 "CAN_F13R1,Filter Bank 13_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<13.))==0x00)
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "CAN_F13R2,Filter Bank 13_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2AC++0x03
|
|
line.long 0x00 "CAN_F13R2,Filter Bank 13_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<14.))==0x00)
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "CAN_F14R1,Filter Bank 14_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2B0++0x03
|
|
line.long 0x00 "CAN_F14R1,Filter Bank 14_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<14.))==0x00)
|
|
group.long 0x2B4++0x03
|
|
line.long 0x00 "CAN_F14R2,Filter Bank 14_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2B4++0x03
|
|
line.long 0x00 "CAN_F14R2,Filter Bank 14_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<15.))==0x00)
|
|
group.long 0x2B8++0x03
|
|
line.long 0x00 "CAN_F15R1,Filter Bank 15_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2B8++0x03
|
|
line.long 0x00 "CAN_F15R1,Filter Bank 15_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<15.))==0x00)
|
|
group.long 0x2BC++0x03
|
|
line.long 0x00 "CAN_F15R2,Filter Bank 15_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2BC++0x03
|
|
line.long 0x00 "CAN_F15R2,Filter Bank 15_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<16.))==0x00)
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "CAN_F16R1,Filter Bank 16_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2C0++0x03
|
|
line.long 0x00 "CAN_F16R1,Filter Bank 16_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<16.))==0x00)
|
|
group.long 0x2C4++0x03
|
|
line.long 0x00 "CAN_F16R2,Filter Bank 16_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2C4++0x03
|
|
line.long 0x00 "CAN_F16R2,Filter Bank 16_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<17.))==0x00)
|
|
group.long 0x2C8++0x03
|
|
line.long 0x00 "CAN_F17R1,Filter Bank 17_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2C8++0x03
|
|
line.long 0x00 "CAN_F17R1,Filter Bank 17_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<17.))==0x00)
|
|
group.long 0x2CC++0x03
|
|
line.long 0x00 "CAN_F17R2,Filter Bank 17_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2CC++0x03
|
|
line.long 0x00 "CAN_F17R2,Filter Bank 17_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<18.))==0x00)
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "CAN_F18R1,Filter Bank 18_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2D0++0x03
|
|
line.long 0x00 "CAN_F18R1,Filter Bank 18_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<18.))==0x00)
|
|
group.long 0x2D4++0x03
|
|
line.long 0x00 "CAN_F18R2,Filter Bank 18_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2D4++0x03
|
|
line.long 0x00 "CAN_F18R2,Filter Bank 18_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<19.))==0x00)
|
|
group.long 0x2D8++0x03
|
|
line.long 0x00 "CAN_F19R1,Filter Bank 19_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2D8++0x03
|
|
line.long 0x00 "CAN_F19R1,Filter Bank 19_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<19.))==0x00)
|
|
group.long 0x2DC++0x03
|
|
line.long 0x00 "CAN_F19R2,Filter Bank 19_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2DC++0x03
|
|
line.long 0x00 "CAN_F19R2,Filter Bank 19_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<20.))==0x00)
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "CAN_F20R1,Filter Bank 20_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2E0++0x03
|
|
line.long 0x00 "CAN_F20R1,Filter Bank 20_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<20.))==0x00)
|
|
group.long 0x2E4++0x03
|
|
line.long 0x00 "CAN_F20R2,Filter Bank 20_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2E4++0x03
|
|
line.long 0x00 "CAN_F20R2,Filter Bank 20_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<21.))==0x00)
|
|
group.long 0x2E8++0x03
|
|
line.long 0x00 "CAN_F21R1,Filter Bank 21_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2E8++0x03
|
|
line.long 0x00 "CAN_F21R1,Filter Bank 21_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<21.))==0x00)
|
|
group.long 0x2EC++0x03
|
|
line.long 0x00 "CAN_F21R2,Filter Bank 21_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2EC++0x03
|
|
line.long 0x00 "CAN_F21R2,Filter Bank 21_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<22.))==0x00)
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "CAN_F22R1,Filter Bank 22_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2F0++0x03
|
|
line.long 0x00 "CAN_F22R1,Filter Bank 22_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<22.))==0x00)
|
|
group.long 0x2F4++0x03
|
|
line.long 0x00 "CAN_F22R2,Filter Bank 22_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2F4++0x03
|
|
line.long 0x00 "CAN_F22R2,Filter Bank 22_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<23.))==0x00)
|
|
group.long 0x2F8++0x03
|
|
line.long 0x00 "CAN_F23R1,Filter Bank 23_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2F8++0x03
|
|
line.long 0x00 "CAN_F23R1,Filter Bank 23_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<23.))==0x00)
|
|
group.long 0x2FC++0x03
|
|
line.long 0x00 "CAN_F23R2,Filter Bank 23_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x2FC++0x03
|
|
line.long 0x00 "CAN_F23R2,Filter Bank 23_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<24.))==0x00)
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "CAN_F24R1,Filter Bank 24_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "CAN_F24R1,Filter Bank 24_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<24.))==0x00)
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "CAN_F24R2,Filter Bank 24_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "CAN_F24R2,Filter Bank 24_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<25.))==0x00)
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "CAN_F25R1,Filter Bank 25_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "CAN_F25R1,Filter Bank 25_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<25.))==0x00)
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "CAN_F25R2,Filter Bank 25_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "CAN_F25R2,Filter Bank 25_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<26.))==0x00)
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "CAN_F26R1,Filter Bank 26_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "CAN_F26R1,Filter Bank 26_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<26.))==0x00)
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "CAN_F26R2,Filter Bank 26_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "CAN_F26R2,Filter Bank 26_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<27.))==0x00)
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "CAN_F27R1,Filter Bank 27_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "CAN_F27R1,Filter Bank 27_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if (((per.l(ad:0x40006400+0x200))&0x01)==0x01)||(((per.l(ad:0x40006400+0x21C))&(0x01<<27.))==0x00)
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "CAN_F27R2,Filter Bank 27_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "CAN_F27R2,Filter Bank 27_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
elif cpuis("STM32F103*")
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<0.))==0x00))
|
|
;
|
|
group.long 0x240++0x07
|
|
line.long 0x00 "CAN_F0R0,Filter Bank 0_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F0R1,Filter Bank 0_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x240++0x07
|
|
line.long 0x00 "CAN_F0R0,Filter Bank 0_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F0R1,Filter Bank 0_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<1.))==0x00))
|
|
;
|
|
group.long 0x244++0x07
|
|
line.long 0x00 "CAN_F1R0,Filter Bank 1_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F1R1,Filter Bank 1_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x244++0x07
|
|
line.long 0x00 "CAN_F1R0,Filter Bank 1_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F1R1,Filter Bank 1_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<2.))==0x00))
|
|
;
|
|
group.long 0x248++0x07
|
|
line.long 0x00 "CAN_F2R0,Filter Bank 2_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F2R1,Filter Bank 2_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x248++0x07
|
|
line.long 0x00 "CAN_F2R0,Filter Bank 2_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F2R1,Filter Bank 2_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<3.))==0x00))
|
|
;
|
|
group.long 0x24C++0x07
|
|
line.long 0x00 "CAN_F3R0,Filter Bank 3_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F3R1,Filter Bank 3_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x24C++0x07
|
|
line.long 0x00 "CAN_F3R0,Filter Bank 3_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F3R1,Filter Bank 3_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<4.))==0x00))
|
|
;
|
|
group.long 0x250++0x07
|
|
line.long 0x00 "CAN_F4R0,Filter Bank 4_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F4R1,Filter Bank 4_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x250++0x07
|
|
line.long 0x00 "CAN_F4R0,Filter Bank 4_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F4R1,Filter Bank 4_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<5.))==0x00))
|
|
;
|
|
group.long 0x254++0x07
|
|
line.long 0x00 "CAN_F5R0,Filter Bank 5_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F5R1,Filter Bank 5_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x254++0x07
|
|
line.long 0x00 "CAN_F5R0,Filter Bank 5_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F5R1,Filter Bank 5_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<6.))==0x00))
|
|
;
|
|
group.long 0x258++0x07
|
|
line.long 0x00 "CAN_F6R0,Filter Bank 6_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F6R1,Filter Bank 6_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x258++0x07
|
|
line.long 0x00 "CAN_F6R0,Filter Bank 6_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F6R1,Filter Bank 6_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<7.))==0x00))
|
|
;
|
|
group.long 0x25C++0x07
|
|
line.long 0x00 "CAN_F7R0,Filter Bank 7_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F7R1,Filter Bank 7_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x25C++0x07
|
|
line.long 0x00 "CAN_F7R0,Filter Bank 7_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F7R1,Filter Bank 7_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<8.))==0x00))
|
|
;
|
|
group.long 0x260++0x07
|
|
line.long 0x00 "CAN_F8R0,Filter Bank 8_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F8R1,Filter Bank 8_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x260++0x07
|
|
line.long 0x00 "CAN_F8R0,Filter Bank 8_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F8R1,Filter Bank 8_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<9.))==0x00))
|
|
;
|
|
group.long 0x264++0x07
|
|
line.long 0x00 "CAN_F9R0,Filter Bank 9_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F9R1,Filter Bank 9_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x264++0x07
|
|
line.long 0x00 "CAN_F9R0,Filter Bank 9_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F9R1,Filter Bank 9_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<10.))==0x00))
|
|
;
|
|
group.long 0x268++0x07
|
|
line.long 0x00 "CAN_F10R0,Filter Bank 10_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F10R1,Filter Bank 10_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x268++0x07
|
|
line.long 0x00 "CAN_F10R0,Filter Bank 10_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F10R1,Filter Bank 10_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<11.))==0x00))
|
|
;
|
|
group.long 0x26C++0x07
|
|
line.long 0x00 "CAN_F11R0,Filter Bank 11_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F11R1,Filter Bank 11_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x26C++0x07
|
|
line.long 0x00 "CAN_F11R0,Filter Bank 11_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F11R1,Filter Bank 11_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<12.))==0x00))
|
|
;
|
|
group.long 0x270++0x07
|
|
line.long 0x00 "CAN_F12R0,Filter Bank 12_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F12R1,Filter Bank 12_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x270++0x07
|
|
line.long 0x00 "CAN_F12R0,Filter Bank 12_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F12R1,Filter Bank 12_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
if ((((per.l(ad:0x40006400+0x200))&0x01)==0x01)&&(((per.l(ad:0x40006400+0x21C))&(0x01<<13.))==0x00))
|
|
;
|
|
group.long 0x274++0x07
|
|
line.long 0x00 "CAN_F13R0,Filter Bank 13_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F13R1,Filter Bank 13_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
else
|
|
rgroup.long 0x274++0x07
|
|
line.long 0x00 "CAN_F13R0,Filter Bank 13_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
line.long 0x04 "CAN_F13R1,Filter Bank 13_$3 Registers (Identifier/Mask)"
|
|
bitfld.long 0x04 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x04 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x04 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
else
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "CAN_F0R1,Filter Bank 0_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "CAN_F0R2,Filter Bank 0_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "CAN_F1R1,Filter Bank 1_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "CAN_F1R2,Filter Bank 1_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "CAN_F2R1,Filter Bank 2_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "CAN_F2R2,Filter Bank 2_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "CAN_F3R1,Filter Bank 3_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "CAN_F3R2,Filter Bank 3_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "CAN_F4R1,Filter Bank 4_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "CAN_F4R2,Filter Bank 4_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "CAN_F5R1,Filter Bank 5_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "CAN_F5R2,Filter Bank 5_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "CAN_F6R1,Filter Bank 6_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "CAN_F6R2,Filter Bank 6_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "CAN_F7R1,Filter Bank 7_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "CAN_F7R2,Filter Bank 7_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "CAN_F8R1,Filter Bank 8_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x284++0x03
|
|
line.long 0x00 "CAN_F8R2,Filter Bank 8_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x288++0x03
|
|
line.long 0x00 "CAN_F9R1,Filter Bank 9_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x28C++0x03
|
|
line.long 0x00 "CAN_F9R2,Filter Bank 9_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "CAN_F10R1,Filter Bank 10_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x294++0x03
|
|
line.long 0x00 "CAN_F10R2,Filter Bank 10_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x298++0x03
|
|
line.long 0x00 "CAN_F11R1,Filter Bank 11_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x29C++0x03
|
|
line.long 0x00 "CAN_F11R2,Filter Bank 11_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "CAN_F12R1,Filter Bank 12_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2A4++0x03
|
|
line.long 0x00 "CAN_F12R2,Filter Bank 12_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2A8++0x03
|
|
line.long 0x00 "CAN_F13R1,Filter Bank 13_1 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
group.long 0x2AC++0x03
|
|
line.long 0x00 "CAN_F13R2,Filter Bank 13_2 Registers (Identifier/Mask)"
|
|
bitfld.long 0x00 31. " FB31 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 30. " FB30 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 29. " FB29 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 28. " FB28 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 27. " FB27 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 26. " FB26 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 25. " FB25 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 24. " FB24 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 23. " FB23 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 22. " FB22 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FB21 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 20. " FB20 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 19. " FB19 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 18. " FB18 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 17. " FB17 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 16. " FB16 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 15. " FB15 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 14. " FB14 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 13. " FB13 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 12. " FB12 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 11. " FB11 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 10. " FB10 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 9. " FB9 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 8. " FB8 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 7. " FB7 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 6. " FB6 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 5. " FB5 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 4. " FB4 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 3. " FB3 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 2. " FB2 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
textline " "
|
|
bitfld.long 0x00 1. " FB1 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
bitfld.long 0x00 0. " FB0 ,Filter Bits" "Dominant/Not used,Recessive/Matched"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif cpuis("STM32F37??")||cpuis("STM32F303?B")||cpuis("STM32F303?C")||cpuis("STM32F302?B")||cpuis("STM32F302?C")||cpuis("STM32F302?6")||cpuis("STM32F302?8")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
tree "USB (USB Full Speed Device)"
|
|
base ad:0x40005C00
|
|
width 12.
|
|
tree "Common"
|
|
group.long 0x40++0x07
|
|
line.long 0x00 "USB_CNTR,USB Control Register"
|
|
bitfld.long 0x00 15. " CTRM ,Correct transfer interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PMAOVRM ,Packet memory area over/underrun interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ERRM ,Error interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " WKUPM ,Wake-up interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " SUSPM ,Suspend mode interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " RESETM ,USB reset interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SOFM ,Start of frame interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ESOFM ,Expected start of frame interrupt mask" "Disabled,Enabled"
|
|
textline " "
|
|
sif cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x00 7. " L1REQM ,LPM L1 state request interrupt mask" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " L1RESUME ,LPM L1 resume request" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " RESUME ,Resume request" "No effect,Requested"
|
|
bitfld.long 0x00 3. " FSUSP ,Force suspend" "No effect,Forced"
|
|
bitfld.long 0x00 2. " LP_MODE ,Low-power mode" "No Low-power,Low-power"
|
|
bitfld.long 0x00 1. " PDWN ,Power down" "Not powered down,Powered down"
|
|
textline " "
|
|
bitfld.long 0x00 0. " FRES ,Force USB reset" "Cleared,Reset"
|
|
line.long 0x04 "USB_ISTR,USB Interrupt Status Register"
|
|
rbitfld.long 0x04 15. " CTR ,Correct transfer" "No effect,Correct"
|
|
bitfld.long 0x04 14. " PMAOVR ,Packet memory area over/underrun" "No over/underrun,Over/underrun"
|
|
bitfld.long 0x04 13. " ERR ,Error" "No error,Error"
|
|
bitfld.long 0x04 12. " WKUP ,Wakeup" "No wakeup,Wakeup"
|
|
textline " "
|
|
bitfld.long 0x04 11. " SUSP ,Suspend mode request" "Not requested,Requested"
|
|
bitfld.long 0x04 10. " RESET ,USB RESET request" "No reset,Reset"
|
|
bitfld.long 0x04 9. " SOF ,Start of frame" "No effect,Packet arrived"
|
|
bitfld.long 0x04 8. " ESOF ,Expected start of frame" "No effect,Packet expected"
|
|
textline " "
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
bitfld.long 0x04 7. " L1REQ ,LPM L1 state request" "Not requested,Requested"
|
|
textline " "
|
|
endif
|
|
rbitfld.long 0x04 4. " DIR ,Direction of transaction" "IN,OUT/2 pending transactions"
|
|
rbitfld.long 0x04 0.--3. " EP_ID ,Endpoint identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x48++0x13
|
|
line.long 0x00 "USB_FNR,USB Frame Number Register"
|
|
bitfld.long 0x00 15. " RXDP ,Receive data + line status" "No data,Data"
|
|
bitfld.long 0x00 14. " RXDM ,Receive data - line status" "No data,Data"
|
|
bitfld.long 0x00 13. " LCK ,Locked" "Unlocked,Locked"
|
|
textline " "
|
|
bitfld.long 0x00 11.--12. " LSOF ,Lost SOF" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--10. 1. " FN ,Frame number"
|
|
group.long 0x4C++0x07
|
|
line.long 0x00 "USB_DADDR,USB Device Address"
|
|
bitfld.long 0x00 7. " EF ,Enable function" "Disabled,Enabled"
|
|
hexmask.long.byte 0x00 0.--6. 1. " ADD ,Device address"
|
|
line.long 0x04 "USB_BTABLE,Buffer Table Address"
|
|
hexmask.long.word 0x04 3.--15. 0x08 " BTABLE ,Buffer table"
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "USB_LPMCSR,LPM Control And Status Register"
|
|
rbitfld.long 0x00 4.--7. " BESL ,BESL value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 3. " REMWAKE ,Bremotewake value" "0,1"
|
|
bitfld.long 0x00 1. " LPMACK ,LPM token acknowledge enable" "NYET,ACK"
|
|
bitfld.long 0x00 0. " LPMEN ,LPM support enable" "Disabled,Enabled"
|
|
endif
|
|
tree.end
|
|
tree "Endpoint-specific Registers"
|
|
width 11.
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "USB_EP0R,USB Endpoint 0 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "USB_EP1R,USB Endpoint 1 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "USB_EP2R,USB Endpoint 2 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "USB_EP3R,USB Endpoint 3 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "USB_EP4R,USB Endpoint 4 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "USB_EP5R,USB Endpoint 5 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "USB_EP6R,USB Endpoint 6 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "USB_EP7R,USB Endpoint 7 Register"
|
|
bitfld.long 0x00 15. " CTR_RX ,Correct transfer for reception" "No action,Correct transfer"
|
|
bitfld.long 0x00 14. " DTOG_RX ,Data toggle for reception transfers" "DATA0,DATA1"
|
|
bitfld.long 0x00 12.--13. " STAT_RX ,Status bits for reception transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 11. " SETUP ,Setup transaction completed" "No action,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 9.--10. " EP_TYPE ,Endpoint type" "Bulk,Control,Iso,Interrupt"
|
|
bitfld.long 0x00 8. " EP_KIND ,Endpoint kind" "DBL_BUF,STATUS_OUT"
|
|
bitfld.long 0x00 7. " CTR_TX ,Correct transfer for transmission" "No action,Completed"
|
|
bitfld.long 0x00 6. " DTOG_TX ,Data toggle for transmission transfers" "DATA0,DATA1"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " STAT_TX ,Status bits for transmission transfers" "Disabled,Stall,Nak,Valid"
|
|
bitfld.long 0x00 0.--3. " EA ,Endpoint address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
tree.end
|
|
width 16.
|
|
base ad:((per.l((ad:0x40005C00+0x50))&0xFFF8))
|
|
tree "Buffer Descriptor Table"
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "USB_ADDR0_TX,Transmission Buffer Address 0"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR0_TX ,Transmission buffer address"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "USB_COUNT0_TX,Transmission Byte Count 0"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT0_TX ,Transmission byte count"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "USB_ADDR0_RX,Reception Buffer Address 0"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR0_RX ,Reception buffer address"
|
|
textline " "
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "USB_COUNT0_RX,Reception Byte Count 0"
|
|
bitfld.long 0x00 15. " BL_SIZE ,Block size" "2 byte,32 byte"
|
|
bitfld.long 0x00 10.--14. " NUM_BLOCK ,Number of blocks" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT0_RX ,Reception byte count"
|
|
textline " "
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "USB_ADDR1_TX,Transmission Buffer Address 1"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR1_TX ,Transmission buffer address"
|
|
group.long (0x10+0x04)++0x03
|
|
line.long 0x00 "USB_COUNT1_TX,Transmission Byte Count 1"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT1_TX_0 ,Transmission byte count 0"
|
|
group.word (0x10+0x08)++0x01
|
|
line.word 0x00 "USB_ADDR1_RX,Reception Buffer Address 1"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR1_RX ,Reception buffer address"
|
|
textline " "
|
|
group.long (0x10+0x0C)++0x03
|
|
line.long 0x00 "USB_COUNT1_RX,Reception Byte Count 1"
|
|
bitfld.long 0x00 15. " BL_SIZE_0 ,Block size 0" "2 byte,32 byte"
|
|
bitfld.long 0x00 10.--14. " NUM_BLOCK_0 ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT1_RX_0 ,Reception byte count 0"
|
|
group.word 0x20++0x01
|
|
line.word 0x00 "USB_ADDR2_TX,Transmission Buffer Address 2"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR2_TX ,Transmission buffer address"
|
|
group.long (0x20+0x04)++0x03
|
|
line.long 0x00 "USB_COUNT2_TX,Transmission Byte Count 2"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT2_TX_0 ,Transmission byte count 0"
|
|
group.word (0x20+0x08)++0x01
|
|
line.word 0x00 "USB_ADDR2_RX,Reception Buffer Address 2"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR2_RX ,Reception buffer address"
|
|
textline " "
|
|
group.long (0x20+0x0C)++0x03
|
|
line.long 0x00 "USB_COUNT2_RX,Reception Byte Count 2"
|
|
bitfld.long 0x00 15. " BL_SIZE_0 ,Block size 0" "2 byte,32 byte"
|
|
bitfld.long 0x00 10.--14. " NUM_BLOCK_0 ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT2_RX_0 ,Reception byte count 0"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "USB_ADDR3_TX,Transmission Buffer Address 3"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR3_TX ,Transmission buffer address"
|
|
group.long (0x30+0x04)++0x03
|
|
line.long 0x00 "USB_COUNT3_TX,Transmission Byte Count 3"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT3_TX_0 ,Transmission byte count 0"
|
|
group.word (0x30+0x08)++0x01
|
|
line.word 0x00 "USB_ADDR3_RX,Reception Buffer Address 3"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR3_RX ,Reception buffer address"
|
|
textline " "
|
|
group.long (0x30+0x0C)++0x03
|
|
line.long 0x00 "USB_COUNT3_RX,Reception Byte Count 3"
|
|
bitfld.long 0x00 15. " BL_SIZE_0 ,Block size 0" "2 byte,32 byte"
|
|
bitfld.long 0x00 10.--14. " NUM_BLOCK_0 ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT3_RX_0 ,Reception byte count 0"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "USB_ADDR4_TX,Transmission Buffer Address 4"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR4_TX ,Transmission buffer address"
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "USB_COUNT4_TX,Transmission Byte Count 4"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT4_TX_0 ,Transmission byte count 0"
|
|
group.word (0x40+0x08)++0x01
|
|
line.word 0x00 "USB_ADDR4_RX,Reception Buffer Address 4"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR4_RX ,Reception buffer address"
|
|
textline " "
|
|
group.long (0x40+0x0C)++0x03
|
|
line.long 0x00 "USB_COUNT4_RX,Reception Byte Count 4"
|
|
bitfld.long 0x00 15. " BL_SIZE_0 ,Block size 0" "2 byte,32 byte"
|
|
bitfld.long 0x00 10.--14. " NUM_BLOCK_0 ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT4_RX_0 ,Reception byte count 0"
|
|
group.word 0x50++0x01
|
|
line.word 0x00 "USB_ADDR5_TX,Transmission Buffer Address 5"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR5_TX ,Transmission buffer address"
|
|
group.long (0x50+0x04)++0x03
|
|
line.long 0x00 "USB_COUNT5_TX,Transmission Byte Count 5"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT5_TX_0 ,Transmission byte count 0"
|
|
group.word (0x50+0x08)++0x01
|
|
line.word 0x00 "USB_ADDR5_RX,Reception Buffer Address 5"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR5_RX ,Reception buffer address"
|
|
textline " "
|
|
group.long (0x50+0x0C)++0x03
|
|
line.long 0x00 "USB_COUNT5_RX,Reception Byte Count 5"
|
|
bitfld.long 0x00 15. " BL_SIZE_0 ,Block size 0" "2 byte,32 byte"
|
|
bitfld.long 0x00 10.--14. " NUM_BLOCK_0 ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT5_RX_0 ,Reception byte count 0"
|
|
group.word 0x60++0x01
|
|
line.word 0x00 "USB_ADDR6_TX,Transmission Buffer Address 6"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR6_TX ,Transmission buffer address"
|
|
group.long (0x60+0x04)++0x03
|
|
line.long 0x00 "USB_COUNT6_TX,Transmission Byte Count 6"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT6_TX_0 ,Transmission byte count 0"
|
|
group.word (0x60+0x08)++0x01
|
|
line.word 0x00 "USB_ADDR6_RX,Reception Buffer Address 6"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR6_RX ,Reception buffer address"
|
|
textline " "
|
|
group.long (0x60+0x0C)++0x03
|
|
line.long 0x00 "USB_COUNT6_RX,Reception Byte Count 6"
|
|
bitfld.long 0x00 15. " BL_SIZE_0 ,Block size 0" "2 byte,32 byte"
|
|
bitfld.long 0x00 10.--14. " NUM_BLOCK_0 ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT6_RX_0 ,Reception byte count 0"
|
|
group.word 0x70++0x01
|
|
line.word 0x00 "USB_ADDR7_TX,Transmission Buffer Address 7"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR7_TX ,Transmission buffer address"
|
|
group.long (0x70+0x04)++0x03
|
|
line.long 0x00 "USB_COUNT7_TX,Transmission Byte Count 7"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT7_TX_0 ,Transmission byte count 0"
|
|
group.word (0x70+0x08)++0x01
|
|
line.word 0x00 "USB_ADDR7_RX,Reception Buffer Address 7"
|
|
hexmask.word 0x00 1.--15. 0x02 " ADDR7_RX ,Reception buffer address"
|
|
textline " "
|
|
group.long (0x70+0x0C)++0x03
|
|
line.long 0x00 "USB_COUNT7_RX,Reception Byte Count 7"
|
|
bitfld.long 0x00 15. " BL_SIZE_0 ,Block size 0" "2 byte,32 byte"
|
|
bitfld.long 0x00 10.--14. " NUM_BLOCK_0 ,Number of blocks 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.word 0x00 0.--9. 1. " COUNT7_RX_0 ,Reception byte count 0"
|
|
tree.end
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"
|
|
tree "HDMI-CEC (HDMI-CEC controller)"
|
|
base ad:0x40007800
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CEC_CR,CEC Control Register"
|
|
bitfld.long 0x00 2. " TXEOM ,Tx end of message" "TXDR with EOM=0,TXDR with EOM=1"
|
|
bitfld.long 0x00 1. " TXSOM ,Tx start of message" "No CEC transmission,CEC transmission"
|
|
bitfld.long 0x00 0. " CECEN ,CEC enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x40007800+0x0)))&0x1)==0x0)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CEC_CFGR,CEC Configuration Register"
|
|
bitfld.long 0x00 31. " LSTN ,Listen mode" "OAR,OAR/positive acknowledge"
|
|
hexmask.long.word 0x00 16.--30. 1. " OAR ,Own address"
|
|
bitfld.long 0x00 8. " SFTOP ,SFT option bit" "On TXSOM set,Automatically"
|
|
bitfld.long 0x00 7. " BRDNOGEN ,Avoid error-bit generation in broadcast" "BRESTP=1 and BREGEN=0 or LBPEGEN=0,Not generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBPEGEN ,Generate error-bit on long bit period error" "Not generated,Generated"
|
|
bitfld.long 0x00 5. " BREGEN ,Generate error-bit on bit rising error" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BRESTP ,Rx-stop on bit rising error" "Not stopped,Stopped"
|
|
bitfld.long 0x00 3. " RXTOL ,Rx-tolerance" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " SFT ,Signal free time" "2.5 periods/4 periods/6 periods,0.5 periods,1.5 periods,2.5 periods,3.5 periods,4.5 periods,5.5 periods,6.5 periods"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CEC_CFGR,CEC Configuration Register"
|
|
bitfld.long 0x00 31. " LSTN ,Listen mode" "OAR,OAR/positive acknowledge"
|
|
hexmask.long.word 0x00 16.--30. 1. " OAR ,Own address"
|
|
bitfld.long 0x00 8. " SFTOP ,SFT option bit" "On TXSOM set,Automatically"
|
|
bitfld.long 0x00 7. " BRDNOGEN ,Avoid error-bit generation in broadcast" "BRESTP=1 and BREGEN=0 or LBPEGEN=0,Not generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBPEGEN ,Generate error-bit on long bit period error" "Not generated,Generated"
|
|
bitfld.long 0x00 5. " BREGEN ,Generate error-bit on bit rising error" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BRESTP ,Rx-stop on bit rising error" "Not stopped,Stopped"
|
|
bitfld.long 0x00 3. " RXTOL ,Rx-tolerance" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " SFT ,Signal free time" "2.5 periods/4 periods/6 periods,0.5 periods,1.5 periods,2.5 periods,3.5 periods,4.5 periods,5.5 periods,6.5 periods"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CEC_TXDR,CEC Tx Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXD ,Tx Data register"
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "CEC_RXDR,CEC Rx Data Register"
|
|
in
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CEC_ISR,CEC Interrupt and Status Register"
|
|
eventfld.long 0x00 12. " TXACKE ,Tx-missing acknowledge error" "No error,Error"
|
|
eventfld.long 0x00 11. " TXERR ,Tx-error" "No error,Error"
|
|
eventfld.long 0x00 10. " TXUDR ,Tx-buffer under-run" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " TXEND ,End of transmission" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TXBR ,Tx-byte request" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " ARBLST ,Arbitration lost" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " RXACKE ,Rx-missing acknowledge" "No error,Error"
|
|
eventfld.long 0x00 5. " LBPE ,Rx-long bit period error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 4. " SBPE ,Rx-short bit period error" "No error,Error"
|
|
eventfld.long 0x00 3. " BRE ,Rx-bit rising error" "No error,Error"
|
|
eventfld.long 0x00 2. " RXOVR ,Rx-overrun" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RXEND ,End of reception" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RXBR ,Rx-byte received" "Not received,Received"
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CEC_IER,CEC Interrupt Enable Register"
|
|
bitfld.long 0x00 12. " TXACKEIE ,Tx-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TXERRIE ,Tx-error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXUDRIE ,Tx-buffer under-run interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TXENDIE ,End of transmission interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXBRIE ,Tx-byte request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ARBLSTIE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXACKEIE ,Rx-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBPEIE ,Long bit period error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SBPEIE ,Short bit period error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " BREIE ,Bit rising error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXOVRIE ,Rx-buffer overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXENDIE ,End of reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXBRIE ,Rx-byte received interrupt enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CEC_IER,CEC Interrupt Enable Register"
|
|
bitfld.long 0x00 12. " TXACKEIE ,Tx-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TXERRIE ,Tx-error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXUDRIE ,Tx-buffer under-run interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TXENDIE ,End of transmission interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXBRIE ,Tx-byte request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ARBLSTIE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXACKEIE ,Rx-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBPEIE ,Long bit period error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SBPEIE ,Short bit period error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " BREIE ,Bit rising error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXOVRIE ,Rx-buffer overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXENDIE ,End of reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXBRIE ,Rx-byte received interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
elif cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"
|
|
tree "HDMI-CEC (HDMI-CEC controller)"
|
|
base ad:0x40007800
|
|
width 10.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CEC_CR,CEC Control Register"
|
|
bitfld.long 0x00 2. " TXEOM ,Tx end of message" "TXDR with EOM=0,TXDR with EOM=1"
|
|
bitfld.long 0x00 1. " TXSOM ,Tx start of message" "No CEC transmission,CEC transmission"
|
|
bitfld.long 0x00 0. " CECEN ,CEC enable" "Disabled,Enabled"
|
|
if (((per.l((ad:0x40007800+0x0)))&0x1)==0x0)
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CEC_CFGR,CEC Configuration Register"
|
|
bitfld.long 0x00 31. " LSTN ,Listen mode" "OAR,OAR/positive acknowledge"
|
|
hexmask.long.word 0x00 16.--30. 1. " OAR ,Own address"
|
|
bitfld.long 0x00 8. " SFTOP ,SFT option bit" "On TXSOM set,Automatically"
|
|
bitfld.long 0x00 7. " BRDNOGEN ,Avoid error-bit generation in broadcast" "BRESTP=1 and BREGEN=0 or LBPEGEN=0,Not generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBPEGEN ,Generate error-bit on long bit period error" "Not generated,Generated"
|
|
bitfld.long 0x00 5. " BREGEN ,Generate error-bit on bit rising error" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BRESTP ,Rx-stop on bit rising error" "Not stopped,Stopped"
|
|
bitfld.long 0x00 3. " RXTOL ,Rx-tolerance" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " SFT ,Signal free time" "2.5 periods/4 periods/6 periods,0.5 periods,1.5 periods,2.5 periods,3.5 periods,4.5 periods,5.5 periods,6.5 periods"
|
|
else
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CEC_CFGR,CEC Configuration Register"
|
|
bitfld.long 0x00 31. " LSTN ,Listen mode" "OAR,OAR/positive acknowledge"
|
|
hexmask.long.word 0x00 16.--30. 1. " OAR ,Own address"
|
|
bitfld.long 0x00 8. " SFTOP ,SFT option bit" "On TXSOM set,Automatically"
|
|
bitfld.long 0x00 7. " BRDNOGEN ,Avoid error-bit generation in broadcast" "BRESTP=1 and BREGEN=0 or LBPEGEN=0,Not generated"
|
|
textline " "
|
|
bitfld.long 0x00 6. " LBPEGEN ,Generate error-bit on long bit period error" "Not generated,Generated"
|
|
bitfld.long 0x00 5. " BREGEN ,Generate error-bit on bit rising error" "Not generated,Generated"
|
|
bitfld.long 0x00 4. " BRESTP ,Rx-stop on bit rising error" "Not stopped,Stopped"
|
|
bitfld.long 0x00 3. " RXTOL ,Rx-tolerance" "Standard,Extended"
|
|
textline " "
|
|
bitfld.long 0x00 0.--2. " SFT ,Signal free time" "2.5 periods/4 periods/6 periods,0.5 periods,1.5 periods,2.5 periods,3.5 periods,4.5 periods,5.5 periods,6.5 periods"
|
|
endif
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "CEC_TXDR,CEC Tx Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " TXD ,Tx Data register"
|
|
hgroup.long 0x0C++0x03
|
|
hide.long 0x00 "CEC_RXDR,CEC Rx Data Register"
|
|
in
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CEC_ISR,CEC Interrupt and Status Register"
|
|
eventfld.long 0x00 12. " TXACKE ,Tx-missing acknowledge error" "No error,Error"
|
|
eventfld.long 0x00 11. " TXERR ,Tx-error" "No error,Error"
|
|
eventfld.long 0x00 10. " TXUDR ,Tx-buffer under-run" "Not occurred,Occurred"
|
|
eventfld.long 0x00 9. " TXEND ,End of transmission" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 8. " TXBR ,Tx-byte request" "Not occurred,Occurred"
|
|
eventfld.long 0x00 7. " ARBLST ,Arbitration lost" "Not occurred,Occurred"
|
|
eventfld.long 0x00 6. " RXACKE ,Rx-missing acknowledge" "No error,Error"
|
|
eventfld.long 0x00 5. " LBPE ,Rx-long bit period error" "No error,Error"
|
|
textline " "
|
|
eventfld.long 0x00 4. " SBPE ,Rx-short bit period error" "No error,Error"
|
|
eventfld.long 0x00 3. " BRE ,Rx-bit rising error" "No error,Error"
|
|
eventfld.long 0x00 2. " RXOVR ,Rx-overrun" "Not occurred,Occurred"
|
|
eventfld.long 0x00 1. " RXEND ,End of reception" "Not occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 0. " RXBR ,Rx-byte received" "Not received,Received"
|
|
if (((per.l(ad:0x40007800))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CEC_IER,CEC Interrupt Enable Register"
|
|
bitfld.long 0x00 12. " TXACKEIE ,Tx-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TXERRIE ,Tx-error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXUDRIE ,Tx-buffer under-run interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TXENDIE ,End of transmission interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXBRIE ,Tx-byte request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ARBLSTIE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXACKEIE ,Rx-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBPEIE ,Long bit period error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SBPEIE ,Short bit period error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " BREIE ,Bit rising error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXOVRIE ,Rx-buffer overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXENDIE ,End of reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXBRIE ,Rx-byte received interrupt enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CEC_IER,CEC Interrupt Enable Register"
|
|
bitfld.long 0x00 12. " TXACKEIE ,Tx-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " TXERRIE ,Tx-error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " TXUDRIE ,Tx-buffer under-run interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " TXENDIE ,End of transmission interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " TXBRIE ,Tx-byte request interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " ARBLSTIE ,Arbitration lost interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " RXACKEIE ,Rx-missing acknowledge error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " LBPEIE ,Long bit period error interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SBPEIE ,Short bit period error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " BREIE ,Bit rising error interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " RXOVRIE ,Rx-buffer overrun interrupt enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " RXENDIE ,End of reception interrupt enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " RXBRIE ,Rx-byte received interrupt enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
tree "DBG (Debug registers)"
|
|
base ad:0xE0042000
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
width 16.
|
|
rgroup.long 0x00++0x3
|
|
line.long 0x00 "DBGMCU_IDCODE,MCU device ID code"
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334*4")||cpuis("STM32F334*6")||cpuis("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
hexmask.long.word 0x00 16.--31. 1. " REV_ID ,Revision Identifier"
|
|
hexmask.long.word 0x00 0.--11. 1. " DEV_ID ,Device Identifier"
|
|
endif
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DBGMCU_CR,Debug MCU configuration Register"
|
|
bitfld.long 0x00 2. " DBG_STANDBY ,Debug Standby mode" "FCLK=Off/HCLK=Off,FCLK=On/HCLK=On"
|
|
bitfld.long 0x00 1. " DBG_STOP ,Debug Stop Mode" "FCLK=Off/HCLK=Off,FCLK=On/HCLK=On"
|
|
bitfld.long 0x00 0. " DBG_SLEEP ,Debug Sleep Mode" "FCLK=On/HCLK=Off,FCLK=On/HCLK=On"
|
|
elif cpuis("STM32F302*6")||cpuis("STM32F302*8")||cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F302*")||cpuis("STM32F303*")||cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC"||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DBGMCU_CR,Debug MCU configuration Register"
|
|
bitfld.long 0x00 6.--7. " TRACE_MODE ,Trace Pin Assignment Control" "Asynchronous,Synchronous/TRACEDATA=1,Synchronous/TRACEDATA=2,Synchronous/TRACEDATA=4"
|
|
bitfld.long 0x00 5. " TRACE_IOEN ,Trace Pin Assignment Control" "Not assigned,Assigned"
|
|
bitfld.long 0x00 2. " DBG_STANDBY ,Debug Standby mode" "FCLK=Off/HCLK=Off,FCLK=On/HCLK=On"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DBG_STOP ,Debug Stop Mode" "FCLK=Off/HCLK=Off,FCLK=On/HCLK=On"
|
|
bitfld.long 0x00 0. " DBG_SLEEP ,Debug Sleep Mode" "FCLK=On/HCLK=Off,FCLK=On/HCLK=On"
|
|
endif
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DBGMCU_APB1_FZ,Debug MCU APB1 freeze register"
|
|
bitfld.long 0x00 30. " DBG_I2C3_SMBUS_TIMEOUT ,MBUS timeout mode stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
elif cpuis("STM32F302*6")||cpuis("STM32F302*8")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DBGMCU_APB1_FZ,Debug MCU APB1 freeze register"
|
|
bitfld.long 0x00 30. " DBG_I2C3_SMBUS_TIMEOUT ,MBUS timeout mode stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 25. " DBG_CAN_STOP ,Debug CAN stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
elif cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"
|
|
sif cpuis("STM32F303?B")||cpuis("STM32F303?C")||cpuis("STM32F358?C")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DBGMCU_APB1_FZ,Debug MCU APB1 freeze register"
|
|
bitfld.long 0x00 25. " DBG_CAN_STOP ,Debug CAN stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 2. " DBG_TIM4_STOP ,TIM4 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
else
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DBGMCU_APB1_FZ,Debug MCU APB1 freeze register"
|
|
bitfld.long 0x00 25. " DBG_CAN_STOP ,Debug CAN stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
elif cpuis("STM32F302*")||cpuis("STM32F303*")||cpuis("STM32F398VE")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DBGMCU_APB1_FZ,Debug MCU APB1 freeze register"
|
|
sif cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 30. " DBG_I2C3_SMBUS_TIMEOUT ,MBUS timeout mode stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 25. " DBG_CAN_STOP ,Debug CAN stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif !cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.long 0x00 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
bitfld.long 0x00 6. " DBG_TIM20_STOP ,TIM20 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")
|
|
bitfld.long 0x00 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif !cpuis("STM32F302?D")&&!cpuis("STM32F302?E")&&!cpuis("STM32F303?D")&&!cpuis("STM32F303?E")&&!cpuis("STM32F398VE")
|
|
bitfld.long 0x00 2. " DBG_TIM4_STOP ,TIM4 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
elif cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DBGMCU_APB1_FZ,Debug MCU APB1 freeze register"
|
|
bitfld.long 0x00 25. " DBG_CAN_STOP ,Debug CAN stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
elif (cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "DBGMCU_APB1_FZ,Debug MCU APB1 freeze register"
|
|
bitfld.long 0x00 25. " DBG_CAN_STOP ,Debug CAN stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 9. " DBG_TIM18_STOP ,TIM18 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 8. " DBG_TIM14_STOP ,TIM14 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 7. " DBG_TIM13_STOP ,TIM13 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 6. " DBG_TIM12_STOP ,TIM12 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DBG_TIM5_STOP ,TIM5 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 2. " DBG_TIM4_STOP ,TIM4 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
sif cpuis("STM32F301*6")||cpuis("STM32F301*8")||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||cpuis("STM32F302*6")||cpuis("STM32F302*8")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DBGMCU_APB2_FZ,Debug MCU APB2 freeze register"
|
|
bitfld.long 0x00 4. " DBG_TIM17_STOP ,TIM17 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 3. " DBG_TIM16_STOP ,TIM16 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 2. " DBG_TIM15_STOP ,TIM15 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped"
|
|
elif cpuis("STM32F303*6")||cpuis("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F358CC"||cpu()=="STM32F358RC"||cpu()=="STM32F358VC"||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
sif cpuis("STM32F303?6")||cpuis("STM32F303?68")||cpuis("STM32F328?8")||cpuis("STM32F302?D")||cpuis("STM32F302?E")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DBGMCU_APB2_FZ,Debug MCU APB2 freeze register"
|
|
bitfld.long 0x00 4. " DBG_TIM17_STOP ,TIM17 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 3. " DBG_TIM16_STOP ,TIM16 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 2. " DBG_TIM15_STOP ,TIM15 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 0. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped"
|
|
elif cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DBGMCU_APB2_FZ,Debug MCU APB2 freeze register"
|
|
bitfld.long 0x00 5. " DBG_TIM20_STOP ,TIM20 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 4. " DBG_TIM17_STOP ,TIM17 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 3. " DBG_TIM16_STOP ,TIM16 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DBG_TIM15_STOP ,TIM15 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 1. " DBG_TIM8_STOP ,TIM8 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 0. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped"
|
|
else
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DBGMCU_APB2_FZ,Debug MCU APB2 freeze register"
|
|
bitfld.long 0x00 4. " DBG_TIM17_STOP ,TIM17 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 3. " DBG_TIM16_STOP ,TIM16 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 2. " DBG_TIM15_STOP ,TIM15 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 1. " DBG_TIM8_STOP ,TIM8 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 0. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
elif cpuis("STM32F334?4")||cpuis("STM32F334?6")||cpuis("STM32F334?8")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DBGMCU_APB2_FZ,Debug MCU APB2 freeze register"
|
|
bitfld.long 0x00 8. " DBG_HRTIM1_STOP ,HRTIM1 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 4. " DBG_TIM17_STOP ,TIM17 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 3. " DBG_TIM16_STOP ,TIM16 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DBG_TIM15_STOP ,TIM15 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 0. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped"
|
|
elif (cpu()=="STM32F378CC"||cpu()=="STM32F378RC"||cpu()=="STM32F378VC")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "DBGMCU_APB2_FZ,Debug MCU APB2 freeze register"
|
|
bitfld.long 0x00 5. " DBG_TIM19_STOP ,TIM19 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 4. " DBG_TIM17_STOP ,TIM17 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x00 3. " DBG_TIM16_STOP ,TIM16 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x00 2. " DBG_TIM15_STOP ,TIM15 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
width 16.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DBGMCU_IDCODE,MCU device ID code"
|
|
sif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")
|
|
hexmask.long.word 0x00 16.--31. 1. " REV_ID ,Revision Identifier"
|
|
bitfld.long 0x00 12.--15. " DIV_ID ,Division identifier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
hexmask.long.word 0x00 0.--11. 1. " DEV_ID ,Device Identifier"
|
|
textline " "
|
|
else
|
|
hexmask.long.word 0x00 16.--31. 1. " REV_ID ,Revision Identifier"
|
|
hexmask.long.word 0x00 0.--11. 1. " DEV_ID ,Device Identifier"
|
|
endif
|
|
group.long 0x04++0x0B
|
|
line.long 0x00 "DBGMCU_CR,Debug MCU Configuration Register"
|
|
sif (CPU()!="STM32F050C4"&&CPU()!="STM32F050C6"&&CPU()!="STM32F050K4"&&CPU()!="STM32F050K6"&&CPU()!="STM32F051C4"&&CPU()!="STM32F051C6"&&CPU()!="STM32F051C8"&&CPU()!="STM32F051K4"&&CPU()!="STM32F051K6"&&CPU()!="STM32F051K8"&&CPU()!="STM32F051R4"&&CPU()!="STM32F051R6"&&CPU()!="STM32F051R8")&&!(cpuis("STM32F038?6"))&&!(cpuis("STM32F048?6"))&&!(cpuis("STM32F058?8"))&&!(cpuis("STM32F078?B"))&&!(cpuis("STM32F091?B"))&&!(cpuis("STM32F098?C"))&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 6.--7. " TRACE_MODE ,Trace Pin Assignment Control" "Asynchronous,Synchronous/TRACEDATA=1,Synchronous/TRACEDATA=2,Synchronous/TRACEDATA=4"
|
|
bitfld.long 0x00 5. " TRACE_IOEN ,Trace Pin Assignment Control" "Not assigned,Assigned"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F038?6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||(cpuis("STM32F410*"))||(cpuis("STM32F412*"))||(cpuis("STM32F469*"))||(cpuis("STM32F479*"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
bitfld.long 0x00 2. " DBG_STANDBY ,Debug Standby mode" "FCLK=Off/HCLK=Off,FCLK=On/HCLK=On"
|
|
bitfld.long 0x00 1. " DBG_STOP ,Debug Stop Mode" "FCLK=Off/HCLK=Off,FCLK=On/HCLK=On"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F038?6"))&&!(cpuis("STM32F048?6"))&&!(cpuis("STM32F058?8"))&&!(cpuis("STM32F078?B"))&&!(cpuis("STM32F091?B"))&&!(cpuis("STM32F098?C"))&&!cpuis("STM32F031E6")&&!cpuis("STM32F038E6")&&!cpuis("STM32F051T8")&&!cpuis("STM32F058T8")&&!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB")
|
|
bitfld.long 0x00 0. " DBG_SLEEP ,Debug Sleep Mode" "FCLK=On/HCLK=Off,FCLK=On/HCLK=On"
|
|
textline " "
|
|
endif
|
|
line.long 0x04 "DBGMCU_APB1_FZ,Debug MCU APB1 freeze register"
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
sif (!cpuis("STM32F401*"))&&!(cpuis("STM32F411*"))&&!(cpuis("STM32F410*"))&&!(cpuis("STM32F413*"))&&!(cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 26. " DBG_CAN2_STOP ,Debug CAN2 stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 25. " DBG_CAN1_STOP ,Debug CAN1 stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
sif (cpuis("STM32F466*")||cpuis("STM32F469*")||cpuis("STM32F479*"))||(cpuis("STM32F410*")&&!cpuis("STM32F410T*"))||(cpuis("STM32F412*"))||(cpuis("STM32F479*"))||cpuis("STM32F413*")||cpuis("STM32F423?H")
|
|
bitfld.long 0x04 24. " DBG_I2CFMP_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
sif cpuis("STM32F410*")
|
|
bitfld.long 0x04 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
else
|
|
bitfld.long 0x04 23. " DBG_I2C3_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 11. " DBG_WWDG_STOP ,Debug Window Wachdog stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*")&&!cpuis("STM32F410*")&&!(cpuis("STM32F413*"))&&!(cpuis("STM32F423?H")))
|
|
bitfld.long 0x04 8. " DBG_TIM14_STOP ,TIM14 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 7. " DBG_TIM13_STOP ,TIM13 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 6. " DBG_TIM12_STOP ,TIM12 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
elif cpuis("STM32F410*")&&!(cpuis("STM32F413*"))&&!(cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
sif (!cpuis("STM32F413*"))&&!(cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 3. " DBG_TIM5_STOP ,TIM5 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
sif !cpuis("STM32F410*")&&!(cpuis("STM32F413*"))&&!(cpuis("STM32F423?H"))
|
|
bitfld.long 0x04 2. " DBG_TIM4_STOP ,TIM4 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
elif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||(cpuis("STM32F050G6"))||(cpuis("STM32F038?6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
sif (cpuis("STM32F050G6"))||(cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))
|
|
bitfld.long 0x04 25. " DBG_CAN_STOP ,Debug CAN stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DBG_IWDG_STOP ,Debug independent watchdog stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 8. " DBG_TIM14_STOP ,TIM14 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif (cpuis("STM32F050G6"))||(cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8")&&!cpuis("STM32F058T8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||cpuis("STM32F070RB")||cpuis("STM32F070CB")||cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
bitfld.long 0x04 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||cpuis("STM32F058T8")||cpuis("STM32F051T8")
|
|
bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
sif (!cpuis("STM32F030CC")&&!cpuis("STM32F030RC")&&!cpuis("STM32F070C6")&&!cpuis("STM32F070CB")&&!cpuis("STM32F070F6")&&!cpuis("STM32F070RB"))
|
|
textline " "
|
|
bitfld.long 0x04 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
else
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x04 25. " DBG_CAN_STOP ,Debug CAN stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 22. " DBG_I2C2_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 21. " DBG_I2C1_SMBUS_TIMEOUT ,SMBUS timeout mode stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 12. " DBG_IWDG_STOP ,Debug Independent Watchdog stopped when Core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 11. " DBG_WWDG_STOP ,Debug Window Watchdog stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x04 10. " DBG_RTC_STOP ,RTC stopped when Core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x04 9. " DBG_TIM18_STOP ,TIM18 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 8. " DBG_TIM14_STOP ,TIM14 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 7. " DBG_TIM13_STOP ,TIM13 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 6. " DBG_TIM12_STOP ,TIM12 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 5. " DBG_TIM7_STOP ,TIM7 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 4. " DBG_TIM6_STOP ,TIM6 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x04 3. " DBG_TIM5_STOP ,TIM5 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x04 2. " DBG_TIM4_STOP ,TIM4 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x04 1. " DBG_TIM3_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x04 0. " DBG_TIM2_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
line.long 0x08 "DBGMCU_APB2_FZ,Debug MCU APB2 freeze register"
|
|
sif !cpuis("STM32F413*")&&!cpuis("STM32F423?H")
|
|
sif (cpuis("STM32F2*")||cpuis("STM32F4*"))
|
|
bitfld.long 0x08 18. " DBG_TIM11_STOP ,TIM11 counter stopped when core is halted" "Started,Stopped"
|
|
sif (!cpuis("STM32F410*"))
|
|
bitfld.long 0x08 17. " DBG_TIM10_STOP ,TIM10 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 16. " DBG_TIM9_STOP ,TIM9 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif (!cpuis("STM32F401*")&&!cpuis("STM32F411*")&&!cpuis("STM32F410*"))
|
|
bitfld.long 0x08 1. " DBG_TIM8_STOP ,TIM8 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 0. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
elif (CPU()=="STM32F050C4"||CPU()=="STM32F050C6"||CPU()=="STM32F050K4"||CPU()=="STM32F050K6"||CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||(cpuis("STM32F050G6"))||(cpuis("STM32F038?6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||cpuis("STM32F030CC")||cpuis("STM32F030RC")||cpuis("STM32F070C6")||cpuis("STM32F070CB")||cpuis("STM32F070F6")||cpuis("STM32F070RB")||cpuis("STM32F031E6")||cpuis("STM32F051T8")
|
|
bitfld.long 0x08 18. " DBG_TIM17_STOP ,TIM17 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x08 17. " DBG_TIM16_STOP ,TIM16 counter stopped when core is halted" "Started,Stopped"
|
|
sif (CPU()=="STM32F051C4"||CPU()=="STM32F051C6"||CPU()=="STM32F051C8"||CPU()=="STM32F051K4"||CPU()=="STM32F051K6"||CPU()=="STM32F051K8"||CPU()=="STM32F051R4"||CPU()=="STM32F051R6"||CPU()=="STM32F051R8")||(cpuis("STM32F050G6"))||(cpuis("STM32F038?6")&&!cpuis("STM32F038E6"))||(cpuis("STM32F048?6"))||(cpuis("STM32F058?8"))||(cpuis("STM32F078?B"))||(cpuis("STM32F091?B"))||(cpuis("STM32F098?C"))||cpuis("STM32F051T8")||cpuis("STM32F070CB")||cpuis("STM32F070RB")||cpuis("STM32F030CC")||cpuis("STM32F030RC")
|
|
textline " "
|
|
bitfld.long 0x08 16. " DBG_TIM15_STOP ,TIM15 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
textline " "
|
|
bitfld.long 0x08 11. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped"
|
|
elif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
sif (cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")
|
|
bitfld.long 0x08 5. " DBG_TIM19_STOP ,TIM19 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x08 4. " DBG_TIM17_STOP ,TIM17 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x08 3. " DBG_TIM16_STOP ,TIM16 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DBG_TIM15_STOP ,TIM15 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")
|
|
bitfld.long 0x08 1. " DBG_TIM8_STOP ,TIM8 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x08 0. " DBG_TIM1_STOP ,TIM1 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
endif
|
|
else
|
|
bitfld.long 0x08 4. " DBG_TIM11_STOP ,TIM4 counter stopped when core is halted" "Started,Stopped"
|
|
bitfld.long 0x08 3. " DBG_TIM10_STOP ,TIM3 counter stopped when core is halted" "Started,Stopped"
|
|
textline " "
|
|
bitfld.long 0x08 2. " DBG_TIM9_STOP ,TIM2 counter stopped when core is halted" "Started,Stopped"
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
endif
|
|
tree.end
|
|
tree "DES (Device Electronic Signature)"
|
|
base ad:0x1FFFF7AC
|
|
width 7.
|
|
rgroup.long 0x00++0x0B
|
|
line.long 0x00 "U_ID0,Unique ID bits register 0"
|
|
line.long 0x04 "U_ID1,Unique ID bits register 1"
|
|
line.long 0x08 "U_ID2,Unique ID bits register 2"
|
|
width 12.
|
|
sif (cpu()=="STM32F302CB")||(cpu()=="STM32F302VB")||(cpu()=="STM32F302CC")||(cpu()=="STM32F302VC")||(cpu()=="STM32F302RB")||(cpu()=="STM32F302RC")||(cpu()=="STM32F303RB")||(cpu()=="STM32F303RC")||(cpu()=="STM32F303CB")||(cpu()=="STM32F303VB")||(cpu()=="STM32F303CC")||(cpu()=="STM32F303VC")||(cpu()=="STM32F313CC")||(cpu()=="STM32F313RC")||(cpu()=="STM32F313VC")||(cpu()=="STM32F372CB")||(cpu()=="STM32F372RC")||(cpu()=="STM32F372CC")||(cpu()=="STM32F372V8")||(cpu()=="STM32F372R8")||(cpu()=="STM32F372VB")||(cpu()=="STM32F372C8")||(cpu()=="STM32F372RB")||(cpu()=="STM32F372VC")||(cpu()=="STM32F373C8")||(cpu()=="STM32F373RB")||(cpu()=="STM32F373VC")||(cpu()=="STM32F373CB")||(cpu()=="STM32F373RC")||(cpu()=="STM32F373CC")||(cpu()=="STM32F373V8")||(cpu()=="STM32F373R8")||(cpu()=="STM32F373VB")||(cpu()=="STM32F383CC")||(cpu()=="STM32F383RC")||(cpu()=="STM32F383VC")||CPUIS("STM32F301*6")||CPUIS("STM32F301*8")||CPUIS("STM32F302*6")||CPUIS("STM32F302*8")||CPUIS("STM32F303*6")||CPUIS("STM32F303*8")||cpu()=="STM32F328C8"||cpu()=="STM32F318C8"||cpu()=="STM32F318K8"||CPUIS("STM32F334*4")||CPUIS("STM32F334*6")||CPUIS("STM32F334*8")||(cpu()=="STM32F358CC")||(cpu()=="STM32F358RC")||(cpu()=="STM32F358VC")||(cpu()=="STM32F378CC")||(cpu()=="STM32F378RC")||(cpu()=="STM32F378VC")||cpuis("STM32F302?D")||cpuis("STM32F302?E")||cpuis("STM32F303?D")||cpuis("STM32F303?E")||cpuis("STM32F398VE")
|
|
rgroup.word 0x20++0x1 "Memory Size Data Register"
|
|
line.word 0x00 "FLASH_SIZE,Flash size data register"
|
|
elif (cpuis("STM32F4*"))
|
|
rgroup.word 0x12++0x1 "Memory Size Data Register"
|
|
line.word 0x00 "FLASH_SIZE,Flash size data register"
|
|
endif
|
|
sif (cpuis("STM32F410*")||cpuis("STM32F412*")||cpuis("STM32F413*")||cpuis("STM32F423*")||cpuis("STM32F469*")||cpuis("STM32F479*"))
|
|
rgroup.word 0x1E0++0x01 "Package Data Register"
|
|
line.word 0x00 "PDR,Package Data Register"
|
|
sif cpuis("STM32F410*")
|
|
bitfld.word 0x00 8.--10. " PKG ,Package type" "WLCSP36,UFQFPN48,,,,,,TQFP64"
|
|
elif cpuis("STM32F412*")
|
|
bitfld.word 0x00 8.--10. " PKG ,Package type" "UFQFPN48,LQFP64,WLCSP64,UFBGA100,LQFP100,,,UFBGA144/LQFP144"
|
|
elif cpuis("STM32F413*")||cpuis("STM32F423*")
|
|
bitfld.word 0x00 8.--10. " PKG ,Package type" "UFQFPN48,LQFP64,,UFBGA100/WLCSP81,LQFP100,,,UFBGA144/LQFP144"
|
|
elif cpuis("STM32F469*")||cpuis("STM32F479*")
|
|
bitfld.word 0x00 8.--10. " PKG ,Package type" ",WLCSP168/UFBGA169,LQFP176/UFBGA176,,LQFP208/TFBGA216,LQFP208/TFBGA216,?..."
|
|
endif
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
textline ""
|