31915 lines
2.5 MiB
31915 lines
2.5 MiB
; --------------------------------------------------------------------------------
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; @Title: S32K On-Chip Peripherals
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; @Props: Released
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; @Author: ASK, TPP, WMA, KOL, KWI, DAB
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; @Changelog: 2015-09-09 ASK
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; 2016-01-20 ASK
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; 2017-02-24 KOL
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; 2017-05-10 ASK
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; 2020-07-06 KWI
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; 2022-02-04 DAB
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; @Manufacturer: NXP - NXP Semiconductors
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; @Doc: SVD generated, based on: S32K116.svd (ver 1.6), S32K118.svd (ver 1.6), S32K142.svd (ver 1.6),
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; S32K144.svd (ver 1.6), S32K146.svd (ver 1.6), S32K148.svd (ver 1.6)
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; @Core: Cortex-M4F, Cortex-M0+
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; @Chip: S32K116, S32K118, S32K142, S32K144, S32K146, S32K148
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; @Copyright: (C) 1989-2022 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: pers32k.per 16922 2023-11-06 17:33:28Z kwisniewski $
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sif (CORENAME()=="CORTEXM4F")
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tree.close "Core Registers (Cortex-M4F)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 9. " DISFPCA ,Disables lazy stacking of floating point context" "No,Yes"
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bitfld.long 0x00 8. " DISOOFP ,Disables floating point instructions completing" "No,Yes"
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bitfld.long 0x00 2. " DISFOLD ,Disables folding of IT instructions" "No,Yes"
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textline " "
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bitfld.long 0x00 1. " DISDEFWBUF ,Disables write buffer use during default memory map accesses" "No,Yes"
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bitfld.long 0x00 0. " DISMCYCINT ,Disables interruption of multi-cycle instructions" "No,Yes"
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group.long 0x10++0x0B
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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textline " "
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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line.long 0x04 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x08 "SYST_CVR,SysTick Current Value Register"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer Code"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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textline " "
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x23
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Set Pending NMI Bit" "Inactive,Active"
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bitfld.long 0x00 28. " PENDSVSET ,Set Pending pendSV Bit" "Not pending,Pending"
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bitfld.long 0x00 27. " PENDSVCLR ,Removes the pending status of the PendSV exception" "No effect,Removed"
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textline " "
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bitfld.long 0x00 26. " PENDSTSET ,Set Pending SysTick Bit" "Not pending,Pending"
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bitfld.long 0x00 25. " PENDSTCLR ,Clear Pending SysTick Bit" "No effect,Removed"
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bitfld.long 0x00 23. " ISRPREEMPT ,Use Only at Debug Time" "Not active,Active"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt" "Not pending,Pending"
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,Pending ISR Number Field"
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bitfld.long 0x00 11. " RETTOBASE ,Interrupt Exception" "Active,Not active"
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textline " "
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEY ,Register Key"
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rbitfld.long 0x08 15. " ENDIANESS ,Data endianness Bit" "Little,Big"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Interrupt Priority Grouping Field" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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textline " "
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bitfld.long 0x08 2. " SYSRESETREQ ,System Reset Request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Clear Active Vector Bit" "No effect,Clear"
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bitfld.long 0x08 0. " VECTRESET ,System Reset" "No effect,Reset"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 9. " STKALIGN ,8-byte Stack Frame Alignment" "4-byte/no adjustment,8-byte/adjustment"
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bitfld.long 0x10 8. " BFHFNMIGN ,Enable NMI and Hard Fault and FAULTMASK to Ignore Bus Fault" "Disabled,Enabled"
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bitfld.long 0x10 4. " DIV_0_TRP ,Trap Divide by Zero" "Disabled,Enabled"
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textline " "
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bitfld.long 0x10 3. " UNALIGN_TRP ,Trap for Unaligned Access" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Denied,Allowed"
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bitfld.long 0x10 0. " NONEBASETHRDENA ,Control Entry to Thread Mode" "Only from last exception,Any level"
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line.long 0x14 "SHPR1,SSystem Handler Priority Register 1"
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hexmask.long.byte 0x14 24.--31. 1. " PRI_7 ,Priority of System Handler 7"
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hexmask.long.byte 0x14 16.--23. 1. " PRI_6 ,Priority of system handler 6(UsageFault)"
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hexmask.long.byte 0x14 8.--15. 1. " PRI_5 ,Priority of system handler 5(BusFault)"
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textline " "
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hexmask.long.byte 0x14 0.--7. 1. " PRI_4 ,Priority of system handler 4(MemManage)"
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line.long 0x18 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x18 24.--31. 1. " PRI_11 ,Priority of system handler 11(SVCall)"
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hexmask.long.byte 0x18 16.--23. 1. " PRI_10 ,Priority of System Handler 10"
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hexmask.long.byte 0x18 8.--15. 1. " PRI_9 ,Priority of System Handler 9"
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textline " "
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hexmask.long.byte 0x18 0.--7. 1. " PRI_8 ,Priority of System Handler 8"
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line.long 0x1C "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x1C 24.--31. 1. " PRI_15 ,Priority of System Handler 15(SysTick)"
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hexmask.long.byte 0x1C 16.--23. 1. " PRI_14 ,Priority of System Handler 14(PendSV)"
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hexmask.long.byte 0x1C 8.--15. 1. " PRI_13 ,Priority of System Handler 13"
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textline " "
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hexmask.long.byte 0x1C 0.--7. 1. " PRI_12 ,Priority of System Handler 12(DebugMonitor)"
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line.long 0x20 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x20 18. " USGFAULTENA ,Enable UsageFault" "Disabled,Enabled"
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bitfld.long 0x20 17. " BUSFAULTENA ,Enable BusFault" "Disabled,Enabled"
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bitfld.long 0x20 16. " MEMFAULTENA ,Enable MemManage fault" "Disabled,Enabled"
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textline " "
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bitfld.long 0x20 15. " SVCALLPENDED ,SVCall is pending" "Not pending,Pending"
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bitfld.long 0x20 14. " BUSFAULTPENDED ,BusFault is pending" "Not pending,Pending"
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bitfld.long 0x20 13. " MEMFAULTPENDED ,MemManage is pending" "Not pending,Pending"
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textline " "
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bitfld.long 0x20 12. " USGFAULTPENDED ,UsageFault is pending" "Not pending,Pending"
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bitfld.long 0x20 11. " SYSTICKACT ,SysTick is Active" "Not active,Active"
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bitfld.long 0x20 10. " PENDSVACT ,PendSV is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 8. " MONITORACT ,Monitor is Active" "Not active,Active"
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bitfld.long 0x20 7. " SVCALLACT ,SVCall is Active" "Not active,Active"
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bitfld.long 0x20 3. " USGFAULTACT ,UsageFault is Active" "Not active,Active"
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textline " "
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bitfld.long 0x20 1. " BUSFAULTACT ,BusFault is Active" "Not active,Active"
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bitfld.long 0x20 0. " MEMFAULTACT ,MemManage is Active" "Not active,Active"
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group.byte 0xD28++0x1
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line.byte 0x00 "MMFSR,MemManage Status Register"
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bitfld.byte 0x00 7. " MMARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x00 5. " MLSPERR ,A MemManage fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x00 4. " MSTKERR ,tacking Access Violations" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x00 3. " MUNSTKERR ,Unstack Access Violations" "Not occurred,Occurred"
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bitfld.byte 0x00 1. " DACCVIOL ,Data Access Violation" "Not occurred,Occurred"
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bitfld.byte 0x00 0. " IACCVIOL ,Instruction Access Violation" "Not occurred,Occurred"
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line.byte 0x01 "BFSR,Bus Fault Status Register"
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bitfld.byte 0x01 7. " BFARVALID ,Address Valid Flag" "Not valid,Valid"
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bitfld.byte 0x01 5. " LSPERR ,A bus fault occurred during FP lazy state preservation" "Not occurred,Occurred"
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bitfld.byte 0x01 4. " STKERR ,Derived bus fault(exception entry)" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 3. " UNSTKERR ,Derived bus fault(exception return)" "Not occurred,Occurred"
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bitfld.byte 0x01 2. " IMPRECISERR ,Imprecise data access error" "Not occurred,Occurred"
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bitfld.byte 0x01 1. " PRECISERR ,Precise data access error" "Not occurred,Occurred"
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textline " "
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bitfld.byte 0x01 0. " IBUSERR ,Bus fault on an instruction prefetch" "Not occurred,Occurred"
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group.word 0xD2A++0x1
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line.word 0x00 "USAFAULT,Usage Fault Status Register"
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bitfld.word 0x00 9. " DIVBYZERO ,Divide by zero error" "No error,Error"
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bitfld.word 0x00 8. " UNALIGNED ,Unaligned access error" "No error,Error"
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bitfld.word 0x00 3. " NOCP ,A coprocessor access error" "No error,Error"
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textline " "
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bitfld.word 0x00 2. " INVPC ,An integrity check error" "No error,Error"
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bitfld.word 0x00 1. " INVSTATE ,Invalid Combination of EPSR and Instruction" "No error,Error"
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bitfld.word 0x00 0. " UNDEFINSTR ,Undefined instruction error" "No error,Error"
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group.long 0xD2C++0x07
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line.long 0x00 "HFSR,Hard Fault Status Register"
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bitfld.long 0x00 31. " DEBUGEVT ,Indicates when a Debug event has occurred" "Not occurred,Occurred"
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bitfld.long 0x00 30. " FORCED ,Indicates that a fault with configurable priority" "Not occurred,Occurred"
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bitfld.long 0x00 1. " VECTTBL ,Indicates when a fault has occurred because of a vector table read error on exception processing" "Not occurred,Occurred"
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line.long 0x04 "DFSR,Debug Fault Status Register"
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bitfld.long 0x04 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of EDBGRQ" "Not asserted,Asserted"
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bitfld.long 0x04 3. " VCATCH ,Vector Catch Flag" "Not occurred,Occurred"
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bitfld.long 0x04 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not occurred,Occurred"
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textline " "
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bitfld.long 0x04 1. " BKPT ,BKPT Flag" "Not executed,Executed"
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bitfld.long 0x04 0. " HALTED ,Indicates a debug event generated by either" "Not requested,Requested"
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group.long 0xD34++0x0B
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line.long 0x00 "MMFAR,MemManage Fault Address Register"
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line.long 0x04 "BFAR,BusFault Address Register"
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line.long 0x08 "AFSR,Auxiliary Fault Status Register"
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group.long 0xD88++0x03
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line.long 0x00 "CPACR,Coprocessor Access Control Register"
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bitfld.long 0x00 22.--23. " CP11 ,Access privileges for coprocessor 11" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 20.--21. " CP10 ,Access privileges for coprocessor 10" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 14.--15. " CP7 ,Access privileges for coprocessor 7" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 12.--13. " CP6 ,Access privileges for coprocessor 6" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 10.--11. " CP5 ,Access privileges for coprocessor 5" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 8.--9. " CP4 ,Access privileges for coprocessor 4" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 6.--7. " CP3 ,Access privileges for coprocessor 3" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 4.--5. " CP2 ,Access privileges for coprocessor 2" "Access denied,Privileged only,Reserved,Full access"
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bitfld.long 0x00 2.--3. " CP1 ,Access privileges for coprocessor 1" "Access denied,Privileged only,Reserved,Full access"
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textline " "
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bitfld.long 0x00 0.--1. " CP0 ,Access privileges for coprocessor 0" "Access denied,Privileged only,Reserved,Full access"
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wgroup.long 0xF00++0x03
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line.long 0x00 "STIR,Software Trigger Interrupt Register"
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hexmask.long.word 0x00 0.--8. 1. " INTID ,Indicates the interrupt to be triggered"
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width 10.
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tree "Feature Registers"
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rgroup.long 0xD40++0x0B
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line.long 0x00 "ID_PFR0,Processor Feature Register 0"
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bitfld.long 0x00 4.--7. " STATE1 ,Thumb instruction set support" ",,,Supported,?..."
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bitfld.long 0x00 0.--3. " STATE0 ,ARM instruction set support" "Not supported,?..."
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line.long 0x04 "ID_PFR1,Processor Feature Register 1"
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bitfld.long 0x04 8.--11. " MPROF ,M profile programmers' model" ",,2-stack,?..."
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line.long 0x08 "ID_DFR0,Debug Feature Register 0"
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bitfld.long 0x08 20.--23. " DBGMOD ,Support for memory-mapped debug model for M profile processors" "Not supported,Supported,?..."
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hgroup.long 0xD4C++0x03
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hide.long 0x00 "ID_AFR0,Auxiliary Feature Register 0"
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rgroup.long 0xD50++0x03
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line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0"
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bitfld.long 0x00 20.--23. " AUXREG ,Indicates the support for Auxiliary registers" "Not supported,ACTLR only,?..."
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bitfld.long 0x00 16.--19. " TCMSUP ,Indicates the support for Tightly Coupled Memory (TCM)" "Not supported,Supported,?..."
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bitfld.long 0x00 12.--15. " SHRLEV ,Indicates the number of shareability levels implemented" "Level 1,?..."
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textline " "
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bitfld.long 0x00 8.--11. " OUTMSHR ,Indicates the outermost shareability domain implemented" "Non-cacheable,,,,,,,,,,,,,,,Ignored"
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bitfld.long 0x00 4.--7. " PMSASUP ,Indicates support for a PMSA" "Not supported,,,PMSAv7,?..."
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hgroup.long 0xD54++0x03
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hide.long 0x00 "ID_MMFR1,Memory Model Feature Register 1"
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rgroup.long 0xD58++0x03
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line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2"
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bitfld.long 0x00 24.--27. " WFISTALL ,Indicates the support for Wait For Interrupt (WFI) stalling" "Not supported,Supported,?..."
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rgroup.long 0xD60++0x13
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line.long 0x00 "ID_ISAR0,Instruction Set Attributes Register 0"
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bitfld.long 0x00 24.--27. " DIVIDE ,Indicates the supported divide instructions" "Not supported,SDIV/UDIV,?..."
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bitfld.long 0x00 20.--23. " DEBUG ,Indicates the supported debug instructions" "Not supported,BKPT,?..."
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bitfld.long 0x00 16.--19. " COPROC ,Indicates the supported coprocessor instructions" "Not supported,CDP/LDC/MCR/STC,CDP2/LDC2/MCR2/STC2,MCRR/MRRC,MCRR2/MRRC2,?..."
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textline " "
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bitfld.long 0x00 12.--15. " CMPBRANCH ,Indicates the supported combined compare and branch instructions" "Not supported,CBNZ/CBZ,?..."
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bitfld.long 0x00 8.--11. " BITFIELD ,Indicates the supported bitfield instructions" "Not supported,BFC/BFI/SBFX/UBFX,?..."
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bitfld.long 0x00 4.--7. " BITCOUNT ,Indicates the supported bit counting instructions" "Not supported,CLZ,?..."
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line.long 0x04 "ID_ISAR1,Instruction Set Attributes Register 1"
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bitfld.long 0x04 24.--27. " INTERWORK ,Indicates the supported Interworking instructions" "Not supported,BX,BX/BLX,?..."
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bitfld.long 0x04 20.--23. " IMMEDIATE ,Indicates the support for data-processing instructions with long immediates" "Not supported,ADDW/MOVW/MOVT/SUBW,?..."
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bitfld.long 0x04 16.--19. " IFTHEN ,Indicates the supported IfThen instructions" "Not supported,IT,?..."
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textline " "
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bitfld.long 0x04 12.--15. " EXTEND ,Indicates the supported Extend instructions" "Not supported,Supported,Supported,?..."
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line.long 0x08 "ID_ISAR2,Instruction Set Attributes Register 2"
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bitfld.long 0x08 24.--27. " REVERSAL ,Indicates the supported reversal instructions" "Not supported,REV/REV16/REVSH,REV/REV16/REVSH/RBIT,?..."
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bitfld.long 0x08 20.--23. " MULTU ,Indicates the supported advanced unsigned multiply instructions" "Not supported,UMULL/UMLAL,UMULL/UMLAL/UMAAL,?..."
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bitfld.long 0x08 16.--19. " MULTS ,Indicates the supported advanced signed multiply instructions" "Not supported,Supported,Supported,Supported,?..."
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textline " "
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bitfld.long 0x08 12.--15. " MULT ,Indicates the supported additional multiply instructions" "Not supported,MLA,MLA/MLS,?..."
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bitfld.long 0x08 8.--11. " MULTIACCESSINT ,Indicates the support for multi-access interruptible instructions" "Not supported,LDM/STM restartable,LDM/STM continuable,?..."
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bitfld.long 0x08 4.--7. " MEMHINT ,Indicates the supported memory hint instructions" "Not supported,,,PLD/PLI,?..."
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textline " "
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bitfld.long 0x08 0.--3. " LOADSTORE ,Indicates the supported additional load and store instructions" "Not supported,LDRD/STRD,?..."
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line.long 0x0C "ID_ISAR3,Instruction Set Attributes Register 3"
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bitfld.long 0x0C 24.--27. " TRUENOP ,Indicates the support for a true NOP instruction" "Not supported,Supported,?..."
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bitfld.long 0x0C 20.--23. " THUMBCOPY ,Indicates the supported non flag-setting MOV instructions" "Not supported,Supported,?..."
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bitfld.long 0x0C 16.--19. " TABBRANCH ,Indicates the supported Table Branch instructions" "Not supported,TBB/TBH,?..."
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textline " "
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bitfld.long 0x0C 12.--15. " SYNCHPRIM ,Indicates the supported Table Branch instructions" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x0C 8.--11. " SVC ,Indicates the supported SVC instructions" "Not supported,SVC,?..."
|
|
bitfld.long 0x0C 4.--7. " SIMD ,Indicates the supported SIMD instructions" "Not supported,Supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x0C 0.--3. " SATURATE ,Indicates the supported Saturate instructions" "Not supported,QADD/QDADD/QDSUB/QSUB,?..."
|
|
line.long 0x10 "ID_ISAR4,Instruction Set Attributes Register 4"
|
|
bitfld.long 0x10 24.--27. " PSR_M ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,?..."
|
|
bitfld.long 0x10 20.--23. " SYNCHPRIMFRAC ,Indicates the supported M profile instructions to modify the PSRs" "Not supported,Supported,Supported,Supported,?..."
|
|
bitfld.long 0x10 16.--19. " BARRIER ,Indicates the supported Barrier instructions" "Not supported,DMB/DSB/ISB,?..."
|
|
textline " "
|
|
bitfld.long 0x10 8.--11. " WRITEBACK ,Indicates the support for writeback addressing modes" "Basic support,Full support,?..."
|
|
bitfld.long 0x10 4.--7. " WITHSHIFTS ,Indicates the support for instructions with shifts" "MOV/shift,Shift LSL 0-3,,Shift other,?..."
|
|
bitfld.long 0x10 0.--3. " UNPRIV ,Indicates the supported unprivileged instructions" "Not supported,LDRBT/LDRT/STRBT/STRT,LDRBT/LDRT/STRBT/STRT/LDRHT/LDRSBT/LDRSHTSTRHT,?..."
|
|
tree.end
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0C "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 16.--23. " IREGION ,Instruction region" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,?..."
|
|
bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,Supported"
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RASR8,MPU Region Attribute and Size Register 8"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RASR9,MPU Region Attribute and Size Register 9"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RASR10,MPU Region Attribute and Size Register 10"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RASR11,MPU Region Attribute and Size Register 11"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RASR12,MPU Region Attribute and Size Register 12"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RASR13,MPU Region Attribute and Size Register 13"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RASR14,MPU Region Attribute and Size Register 14"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RW,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,32 B,64 B,128 B,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RASR15,MPU Region Attribute and Size Register 15"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,33-64,65-96,97-128,129-160,161-192,193-224,225-240,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x100++0x7
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x100++0x0B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x100++0x0F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x100++0x13
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x100++0x17
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x100++0x1B
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x100++0x1F
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
line.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x100++0x1F
|
|
hide.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x04 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x08 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x0c "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x10 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x14 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x18 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
hide.long 0x1c "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 23.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x200++0x07
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x200++0x0B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x200++0x0F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x200++0x13
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x200++0x17
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x200++0x1B
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x200++0x1F
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x04 31. 0x04 31. 0x84 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 30. 0x04 30. 0x84 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 29. 0x04 29. 0x84 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 28. 0x04 28. 0x84 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 27. 0x04 27. 0x84 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 26. 0x04 26. 0x84 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 25. 0x04 25. 0x84 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 24. 0x04 24. 0x84 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 23. 0x04 23. 0x84 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 22. 0x04 22. 0x84 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 21. 0x04 21. 0x84 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 20. 0x04 20. 0x84 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 19. 0x04 19. 0x84 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 18. 0x04 18. 0x84 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 17. 0x04 17. 0x84 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 16. 0x04 16. 0x84 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 15. 0x04 15. 0x84 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 14. 0x04 14. 0x84 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 13. 0x04 13. 0x84 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 12. 0x04 12. 0x84 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 11. 0x04 11. 0x84 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 10. 0x04 10. 0x84 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 9. 0x04 9. 0x84 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 8. 0x04 8. 0x84 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 7. 0x04 7. 0x84 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 6. 0x04 6. 0x84 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 5. 0x04 5. 0x84 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 4. 0x04 4. 0x84 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 3. 0x04 3. 0x84 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 2. 0x04 2. 0x84 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x04 1. 0x04 1. 0x84 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x04 0. 0x04 0. 0x84 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x08 31. 0x08 31. 0x88 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 30. 0x08 30. 0x88 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 29. 0x08 29. 0x88 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 28. 0x08 28. 0x88 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 27. 0x08 27. 0x88 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 26. 0x08 26. 0x88 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 25. 0x08 25. 0x88 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 24. 0x08 24. 0x88 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 23. 0x08 23. 0x88 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 22. 0x08 22. 0x88 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 21. 0x08 21. 0x88 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 20. 0x08 20. 0x88 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 19. 0x08 19. 0x88 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 18. 0x08 18. 0x88 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 17. 0x08 17. 0x88 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 16. 0x08 16. 0x88 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 15. 0x08 15. 0x88 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 14. 0x08 14. 0x88 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 13. 0x08 13. 0x88 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 12. 0x08 12. 0x88 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 11. 0x08 11. 0x88 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 10. 0x08 10. 0x88 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 9. 0x08 9. 0x88 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 8. 0x08 8. 0x88 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 7. 0x08 7. 0x88 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 6. 0x08 6. 0x88 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 5. 0x08 5. 0x88 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 4. 0x08 4. 0x88 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 3. 0x08 3. 0x88 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 2. 0x08 2. 0x88 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x08 1. 0x08 1. 0x88 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x08 0. 0x08 0. 0x88 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x0c 31. 0x0c 31. 0x8c 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 30. 0x0c 30. 0x8c 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 29. 0x0c 29. 0x8c 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 28. 0x0c 28. 0x8c 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 27. 0x0c 27. 0x8c 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 26. 0x0c 26. 0x8c 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 25. 0x0c 25. 0x8c 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 24. 0x0c 24. 0x8c 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 23. 0x0c 23. 0x8c 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 22. 0x0c 22. 0x8c 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 21. 0x0c 21. 0x8c 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 20. 0x0c 20. 0x8c 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 19. 0x0c 19. 0x8c 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 18. 0x0c 18. 0x8c 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 17. 0x0c 17. 0x8c 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 16. 0x0c 16. 0x8c 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 15. 0x0c 15. 0x8c 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 14. 0x0c 14. 0x8c 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 13. 0x0c 13. 0x8c 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 12. 0x0c 12. 0x8c 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 11. 0x0c 11. 0x8c 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 10. 0x0c 10. 0x8c 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 9. 0x0c 9. 0x8c 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 8. 0x0c 8. 0x8c 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 7. 0x0c 7. 0x8c 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 6. 0x0c 6. 0x8c 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 5. 0x0c 5. 0x8c 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 4. 0x0c 4. 0x8c 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 3. 0x0c 3. 0x8c 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 2. 0x0c 2. 0x8c 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x0c 1. 0x0c 1. 0x8c 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x0c 0. 0x0c 0. 0x8c 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x10 31. 0x10 31. 0x90 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 30. 0x10 30. 0x90 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 29. 0x10 29. 0x90 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 28. 0x10 28. 0x90 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 27. 0x10 27. 0x90 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 26. 0x10 26. 0x90 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 25. 0x10 25. 0x90 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 24. 0x10 24. 0x90 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 23. 0x10 23. 0x90 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 22. 0x10 22. 0x90 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 21. 0x10 21. 0x90 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 20. 0x10 20. 0x90 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 19. 0x10 19. 0x90 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 18. 0x10 18. 0x90 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 17. 0x10 17. 0x90 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 16. 0x10 16. 0x90 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 15. 0x10 15. 0x90 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 14. 0x10 14. 0x90 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 13. 0x10 13. 0x90 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 12. 0x10 12. 0x90 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 11. 0x10 11. 0x90 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 10. 0x10 10. 0x90 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 9. 0x10 9. 0x90 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 8. 0x10 8. 0x90 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 7. 0x10 7. 0x90 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 6. 0x10 6. 0x90 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 5. 0x10 5. 0x90 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 4. 0x10 4. 0x90 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 3. 0x10 3. 0x90 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 2. 0x10 2. 0x90 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x10 1. 0x10 1. 0x90 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x10 0. 0x10 0. 0x90 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x14 31. 0x14 31. 0x94 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 30. 0x14 30. 0x94 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 29. 0x14 29. 0x94 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 28. 0x14 28. 0x94 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 27. 0x14 27. 0x94 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 26. 0x14 26. 0x94 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 25. 0x14 25. 0x94 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 24. 0x14 24. 0x94 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 23. 0x14 23. 0x94 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 22. 0x14 22. 0x94 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 21. 0x14 21. 0x94 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 20. 0x14 20. 0x94 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 19. 0x14 19. 0x94 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 18. 0x14 18. 0x94 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 17. 0x14 17. 0x94 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 16. 0x14 16. 0x94 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 15. 0x14 15. 0x94 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 14. 0x14 14. 0x94 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 13. 0x14 13. 0x94 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 12. 0x14 12. 0x94 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 11. 0x14 11. 0x94 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 10. 0x14 10. 0x94 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 9. 0x14 9. 0x94 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 8. 0x14 8. 0x94 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 7. 0x14 7. 0x94 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 6. 0x14 6. 0x94 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 5. 0x14 5. 0x94 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 4. 0x14 4. 0x94 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 3. 0x14 3. 0x94 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 2. 0x14 2. 0x94 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x14 1. 0x14 1. 0x94 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x14 0. 0x14 0. 0x94 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x18 31. 0x18 31. 0x98 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 30. 0x18 30. 0x98 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 29. 0x18 29. 0x98 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 28. 0x18 28. 0x98 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 27. 0x18 27. 0x98 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 26. 0x18 26. 0x98 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 25. 0x18 25. 0x98 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 24. 0x18 24. 0x98 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 23. 0x18 23. 0x98 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 22. 0x18 22. 0x98 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 21. 0x18 21. 0x98 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 20. 0x18 20. 0x98 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 19. 0x18 19. 0x98 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 18. 0x18 18. 0x98 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 17. 0x18 17. 0x98 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 16. 0x18 16. 0x98 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 15. 0x18 15. 0x98 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 14. 0x18 14. 0x98 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 13. 0x18 13. 0x98 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 12. 0x18 12. 0x98 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 11. 0x18 11. 0x98 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 10. 0x18 10. 0x98 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 9. 0x18 9. 0x98 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 8. 0x18 8. 0x98 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 7. 0x18 7. 0x98 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 6. 0x18 6. 0x98 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 5. 0x18 5. 0x98 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 4. 0x18 4. 0x98 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 3. 0x18 3. 0x98 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 2. 0x18 2. 0x98 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x18 1. 0x18 1. 0x98 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x18 0. 0x18 0. 0x98 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
line.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x1c 15. 0x1c 15. 0x9c 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 14. 0x1c 14. 0x9c 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 13. 0x1c 13. 0x9c 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 12. 0x1c 12. 0x9c 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 11. 0x1c 11. 0x9c 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 10. 0x1c 10. 0x9c 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 9. 0x1c 9. 0x9c 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 8. 0x1c 8. 0x9c 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 7. 0x1c 7. 0x9c 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 6. 0x1c 6. 0x9c 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 5. 0x1c 5. 0x9c 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 4. 0x1c 4. 0x9c 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x1c 3. 0x1c 3. 0x9c 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 2. 0x1c 2. 0x9c 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 1. 0x1c 1. 0x9c 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x1c 0. 0x1c 0. 0x9c 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x200++0x1F
|
|
hide.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x04 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x08 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x0c "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x10 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x14 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x18 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
hide.long 0x1c "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 9.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
rgroup.long 0x300++0x07
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
rgroup.long 0x300++0x0B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
rgroup.long 0x300++0x0F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
rgroup.long 0x300++0x13
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
rgroup.long 0x300++0x17
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
rgroup.long 0x300++0x1B
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
rgroup.long 0x300++0x1F
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x04 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x04 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x04 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x08 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x08 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x08 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x0c 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x0c 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x0c 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x10 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x10 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x10 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x14 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x14 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x14 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x18 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x18 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x18 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
line.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
bitfld.long 0x1c 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x1c 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x1c 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x300++0x1F
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
hide.long 0x04 "ACTIVE2,Active Bit Register 2"
|
|
hide.long 0x08 "ACTIVE3,Active Bit Register 3"
|
|
hide.long 0x0c "ACTIVE4,Active Bit Register 4"
|
|
hide.long 0x10 "ACTIVE5,Active Bit Register 5"
|
|
hide.long 0x14 "ACTIVE6,Active Bit Register 6"
|
|
hide.long 0x18 "ACTIVE7,Active Bit Register 7"
|
|
hide.long 0x1c "ACTIVE8,Active Bit Register 8"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x00)
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x01)
|
|
group.long 0x400++0x3F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x02)
|
|
group.long 0x400++0x5F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x03)
|
|
group.long 0x400++0x7F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x04)
|
|
group.long 0x400++0x9F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x05)
|
|
group.long 0x400++0xBF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x06)
|
|
group.long 0x400++0xDF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)==0x07)
|
|
group.long 0x400++0xEF
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
line.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x20 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x20 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x20 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x20 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x24 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x24 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x24 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x24 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x28 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x28 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x28 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x28 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0x2C 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0x2C 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0x2C 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0x2C 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x30 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x30 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x30 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x30 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x34 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x34 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x34 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x34 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x38 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x38 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x38 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x38 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x3C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x3C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x3C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x3C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
line.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x40 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x40 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x40 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x40 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x44 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x44 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x44 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x44 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x48 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x48 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x48 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x48 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4C 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0x4C 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0x4C 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0x4C 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x50 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x50 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x50 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x50 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x54 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x54 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x54 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x54 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x58 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x58 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x58 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x58 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x5C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x5C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x5C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x5C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
line.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x60 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x60 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x60 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x60 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x64 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x64 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x64 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x64 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x68 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x68 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x68 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x68 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0x6C 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0x6C 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0x6C 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0x6C 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x70 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x70 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x70 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x70 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x74 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x74 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x74 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x74 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x78 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x78 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x78 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x78 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x7C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x7C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x7C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x7C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
line.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x80 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x80 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x80 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x80 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x84 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x84 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x84 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x84 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x88 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x88 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x88 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x88 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8C 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0x8C 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0x8C 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0x8C 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x90 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x90 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x90 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x90 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x94 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x94 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x94 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x94 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x98 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x98 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x98 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x98 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x9C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x9C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x9C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x9C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
line.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0xA0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0xA0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0xA0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0xA4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0xA4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0xA4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0xA8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0xA8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0xA8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0xA8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xAC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xAC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xAC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xAC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB0 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0xB0 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0xB0 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0xB0 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB4 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0xB4 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0xB4 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0xB4 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0xB8 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0xB8 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0xB8 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0xB8 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0xBC 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0xBC 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0xBC 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0xBC 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
line.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0xC0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0xC0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0xC0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0xC4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0xC4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0xC4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0xC8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0xC8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0xC8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xCC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xCC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xCC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xCC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD0 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0xD0 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0xD0 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0xD0 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD4 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0xD4 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0xD4 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0xD4 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0xD8 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0xD8 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0xD8 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0xD8 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0xDC 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0xDC 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0xDC 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0xDC 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
line.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0xE0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0xE0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0xE0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0xE4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0xE4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0xE4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0xE8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0xE8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0xE8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0xE8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xEC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xEC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xEC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xEC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xEC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x400++0xEF
|
|
hide.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hide.long 0xC "IPR3,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hide.long 0x20 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x24 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x28 "IPR10,Interrupt Priority Register"
|
|
hide.long 0x2C "IPR11,Interrupt Priority Register"
|
|
hide.long 0x30 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x34 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x38 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x3C "IPR15,Interrupt Priority Register"
|
|
hide.long 0x40 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x44 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x48 "IPR18,Interrupt Priority Register"
|
|
hide.long 0x4C "IPR19,Interrupt Priority Register"
|
|
hide.long 0x50 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x54 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x58 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x5C "IPR23,Interrupt Priority Register"
|
|
hide.long 0x60 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x64 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x68 "IPR26,Interrupt Priority Register"
|
|
hide.long 0x6C "IPR27,Interrupt Priority Register"
|
|
hide.long 0x70 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x74 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x78 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x7C "IPR31,Interrupt Priority Register"
|
|
hide.long 0x80 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x84 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x88 "IPR34,Interrupt Priority Register"
|
|
hide.long 0x8C "IPR35,Interrupt Priority Register"
|
|
hide.long 0x90 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x94 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x98 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x9C "IPR39,Interrupt Priority Register"
|
|
hide.long 0xA0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0xA4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0xA8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xAC "IPR43,Interrupt Priority Register"
|
|
hide.long 0xB0 "IPR44,Interrupt Priority Register"
|
|
hide.long 0xB4 "IPR45,Interrupt Priority Register"
|
|
hide.long 0xB8 "IPR46,Interrupt Priority Register"
|
|
hide.long 0xBC "IPR47,Interrupt Priority Register"
|
|
hide.long 0xC0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0xC4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0xC8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xCC "IPR51,Interrupt Priority Register"
|
|
hide.long 0xD0 "IPR52,Interrupt Priority Register"
|
|
hide.long 0xD4 "IPR53,Interrupt Priority Register"
|
|
hide.long 0xD8 "IPR54,Interrupt Priority Register"
|
|
hide.long 0xDC "IPR55,Interrupt Priority Register"
|
|
hide.long 0xE0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0xE4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0xE8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xEC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
sif CORENAME()=="CORTEXM4F"
|
|
tree "Floating-point Unit (FPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 8.
|
|
group.long 0xF34++0x0B
|
|
line.long 0x00 "FPCCR,Floating-Point Context Control Register"
|
|
bitfld.long 0x00 31. " ASPEN ,Execution of a floating-point instruction sets the CONTROL.FPCA bit to 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " LSPEN ,Enables lazy context save of FP state" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MONRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the DebugMonitor exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 6. " BFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the BusFault exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 5. " MMRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the MemManage exception to pending" "Not able,Able"
|
|
bitfld.long 0x00 4. " HFRDY ,Indicates whether the software executing when the processor allocated the FP stack frame was able to set the HardFault exception to pending" "Not able,Able"
|
|
textline " "
|
|
bitfld.long 0x00 3. " THREAD ,Indicates the processor mode when it allocated the FP stack frame" "Handler,Thread"
|
|
bitfld.long 0x00 1. " USER ,Indicates the privilege level of the software executing" "Privileged,Unprivileged"
|
|
bitfld.long 0x00 0. " LSPACT ,Indicates whether Lazy preservation of the FP state is active" "Not active,Active"
|
|
line.long 0x04 "FPCAR,Floating-Point Context Address Register"
|
|
hexmask.long 0x04 3.--31. 0x8 " ADDRESS ,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
line.long 0x08 "FPDSCR,Floating-Point Default Status Control Register"
|
|
bitfld.long 0x08 26. " AHP ,Default value for FPSCR.AHP" "IEEE 754-2008,Alternative"
|
|
bitfld.long 0x08 25. " DN ,Default value for FPSCR.DN" "NaN operands,Any operation"
|
|
bitfld.long 0x08 24. " FZ ,Default value for FPSCR.FZ" "No Flush mode,Flush mode"
|
|
textline " "
|
|
bitfld.long 0x08 22.--23. " RMODE ,Default value for FPSCR.RMode" "Round to Nearest,Round towards Plus Infinity,Round towards Minus Infinity,Round towards Zero"
|
|
rgroup.long 0xF40++0x07
|
|
line.long 0x00 "MVFR0,Media and FP Feature Register 0"
|
|
bitfld.long 0x00 28.--31. " FPRNDMOD ,Indicates the rounding modes supported by the FP floating-point hardware" ",All supported,?..."
|
|
bitfld.long 0x00 24.--27. " SRTERR ,Indicates the hardware support for FP short vectors" "Not supported,?..."
|
|
bitfld.long 0x00 20.--23. " SQRROOT ,Indicates the hardware support for FP square root operations" ",Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 16.--19. " DIV ,Indicates the hardware support for FP divide operations" ",Supported,?..."
|
|
bitfld.long 0x00 12.--15. " FPEXTRP ,Indicates whether the FP hardware implementation supports exception trapping" "Not supported,?..."
|
|
bitfld.long 0x00 8.--11. " DBLPREC ,Indicates the hardware support for FP double_precision operations" "Not supported,,Supported,?..."
|
|
textline " "
|
|
bitfld.long 0x00 4.--7. " SNGLPREC ,Indicates the hardware support for FP single-precision operations" ",,Supported,?..."
|
|
bitfld.long 0x00 0.--3. " A_SIMD ,Indicates the size of the FP register bank" ",Supported-16x64-bit,?..."
|
|
line.long 0x04 "MVFR1,Media and FP Feature Register 1"
|
|
bitfld.long 0x04 28.--31. " FP_FUSED_MAC ,Indicates whether the FP supports fused multiply accumulate operations" ",Supported,?..."
|
|
bitfld.long 0x04 24.--27. " FP_HPFP ,Indicates whether the FP supports half-precision and double-precision floating-point conversion instructions" ",Half-single,Half-single and half-double,?..."
|
|
textline " "
|
|
bitfld.long 0x04 4.--7. " D_NAN ,Indicates whether the FP hardware implementation supports only the Default NaN mode" ",NaN propagation,?..."
|
|
bitfld.long 0x04 0.--3. " FTZ_MODE ,Indicates whether the FP hardware implementation supports only the Flush-to-Zero mode of operation" ",Full denorm. num. arit.,?..."
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
newline
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
newline
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
newline
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Register Read/Write" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register or special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
newline
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 10.
|
|
group.long 0x00++0x07
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
bitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Version 1,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
textline ""
|
|
line.long 0x04 "FP_REMAP,Flash Patch Remap Register"
|
|
bitfld.long 0x04 29. " RMPSPT ,Indicates whether the FPB unit supports flash patch remap" "Not supported,SRAM region"
|
|
hexmask.long.tbyte 0x04 5.--28. 0x20 " REMAP ,Remap Base Address Field"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x18))&0x01)==0x00)
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "FP_COMP4,Flash Patch Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x1C))&0x01)==0x00)
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FP_COMP5,Flash Patch Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x20))&0x01)==0x00)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "FP_COMP6,Flash Patch Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 30.--31. " REPLACE ,Defines the behaviour when the COMP address is matched" ",Set BKPT on lower halfword,Set BKPT on upper halfword,Set BKPT on both"
|
|
hexmask.long 0x00 2.--28. 0x04 " COMP ,Comparison Address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare and Remap Enable" "Disabled,Enabled"
|
|
elif (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))))&0x10000000)==0x10000000)
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x24))&0x01)==0x00)
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
else
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "FP_COMP7,Flash Patch Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Enable bit for Breakpoint" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0xB
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 15.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
rbitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
rbitfld.long 0x00 26. " NOEXTTRIG ,Shows whether the implementation includes external match signals" "Supported,Not supported"
|
|
textline " "
|
|
rbitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
rbitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLEENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count Register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count Register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,The base CPI counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count Register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
group.long 0x20++0x07
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
line.long 0x04 "DWT_MASK0,DWT Mask Registers 0"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x20)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x1A0)==0x00)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x28))&0x180)==0x80)
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet,UNPREDICTABLE,UNPREDICTABLE,Generate watchpoint debug event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,CMPMATCH[N] event,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
else
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Registers 0"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " CYCMATCH ,Enable cycle count comparison for comparator 0" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x30)++0x07
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
line.long 0x04 "DWT_MASK1,DWT Mask Registers 1"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x20)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08))&0x120)==0x00)
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Registers 1"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x40)++0x07
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
line.long 0x04 "DWT_MASK2,DWT Mask Registers 2"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x20)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08))&0x120)==0x00)
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Registers 2"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
group.long (0x50)++0x07
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
line.long 0x04 "DWT_MASK3,DWT Mask Registers 3"
|
|
bitfld.long 0x04 0.--4. " MASK ,The size of the ignore mask" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x20)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send address trace packet on READ/WRITE,Send data value + address packet on READ/WRITE,Send data value + address packet on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data address trace packet on READ,Send data address trace packet on WRITE,Send data address + PC value on READ,Send data address + PC value on WRITE"
|
|
elif (((per.long(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08))&0x120)==0x00)
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,Send PC value trace packet on READ/WRITE,Send data value trace packet on READ/WRITE,Send data value + PC value on READ/WRITE,Watchpoint debug event on PC match,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,CMPMATCH[N] event on PC match,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ/WRITE,Send data value trace packet on READ,Send data value trace packet on WRITE,Send data value + PC value on READ,Send data value + PC value on WRITE"
|
|
else
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Registers 3"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "No matched,Matched"
|
|
bitfld.long 0x00 16.--19. " DATAVADDR1 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 12.--15. " DATAVADDR0 ,Data Value Comparator ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
bitfld.long 0x00 9. " LNK1ENA ,Supports use of a second linked comparator" "Not Supported,Supported"
|
|
bitfld.long 0x00 8. " DATAVMATCH ,Data value compare" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " EMITRANGE ,Enables generation of Data trace address offset packets" "Disabled,Enabled"
|
|
bitfld.long 0x00 0.--3. " FUNCTION ,Selects action taken on comparator match" "Disabled,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,Watchpoint debug event on READ,Watchpoint debug event on WRITE,Watchpoint debug event on READ/WRITE,UNPREDICTABLE,CMPMATCH[N] event on READ,CMPMATCH[N] event on WRITE,CMPMATCH[N] event on READ,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE,UNPREDICTABLE"
|
|
endif
|
|
width 6.
|
|
tree "CoreSight Identification Registers"
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "PID0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "PID1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "PID2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "PID3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "PID4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "CID0,Component ID0 (Preamble)"
|
|
line.long 0x04 "CID1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Preamble ,Preamble"
|
|
line.long 0x08 "CID2,Component ID2"
|
|
line.long 0x0c "CID3,Component ID3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
elif (CORENAME()=="CORTEXM0+")
|
|
tree.close "Core Registers (Cortex-M0+)"
|
|
AUTOINDENT.PUSH
|
|
AUTOINDENT.OFF
|
|
tree "System Control"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0x8
|
|
if (CORENAME()=="CORTEXM1")
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
else
|
|
group.long 0x10++0x0b
|
|
line.long 0x00 "STCSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
|
|
bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
|
|
bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
|
|
line.long 0x04 "STRVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
|
|
line.long 0x08 "STCVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
|
|
endif
|
|
if (CORENAME()=="CORTEXM1")
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
|
|
bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
|
|
else
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "STCR,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
|
|
bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
|
|
textline " "
|
|
hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
|
|
endif
|
|
rgroup.long 0xd00++0x03
|
|
line.long 0x00 "CPUID,CPU ID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
|
|
hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
|
|
textline " "
|
|
hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
|
|
hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
|
|
group.long 0xd04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control State Register"
|
|
bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
|
|
bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
|
|
bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
|
|
bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
|
|
textline " "
|
|
hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
group.long 0xd08++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
|
|
else
|
|
textline " "
|
|
endif
|
|
group.long 0xd0c++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
|
|
bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
|
|
bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
|
|
group.long 0xd10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
|
|
bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
|
|
textline " "
|
|
bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
|
|
rgroup.long 0xd14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
|
|
bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
|
|
group.long 0xd1c++0x0b
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
|
|
line.long 0x04 "SHPR3,System Handler Priority Register 3"
|
|
bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
|
|
bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
|
|
line.long 0x08 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
|
|
if (CORENAME()=="CORTEXM0+")
|
|
hgroup.long 0x08++0x03
|
|
hide.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
else
|
|
textline " "
|
|
endif
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Memory Protection Unit (MPU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
rgroup.long 0xD90++0x03
|
|
line.long 0x00 "MPU_TYPE,MPU Type Register"
|
|
bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
|
|
group.long 0xD94++0x03
|
|
line.long 0x00 "MPU_CTRL,MPU Control Register"
|
|
bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
|
|
group.long 0xD98++0x03
|
|
line.long 0x00 "MPU_RNR,MPU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
|
|
tree.close "MPU regions"
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
|
|
group.long 0xD9C++0x03 "Region 0"
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
endif
|
|
autoindent.on center tree
|
|
tree "CSE_PRAM"
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
base ad:0x14000800
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "_EmbeddedRAM0,CSE PRAM 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "_EmbeddedRAM0LL,CSE PRAM0LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "_EmbeddedRAM0LU,CSE PRAM0LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "_EmbeddedRAM0HL,CSE PRAM0HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "_EmbeddedRAM0HU,CSE PRAM0HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "_EmbeddedRAM1,CSE PRAM 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "_EmbeddedRAM1LL,CSE PRAM1LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "_EmbeddedRAM1LU,CSE PRAM1LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "_EmbeddedRAM1HL,CSE PRAM1HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "_EmbeddedRAM1HU,CSE PRAM1HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "_EmbeddedRAM2,CSE PRAM 2 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "_EmbeddedRAM2LL,CSE PRAM2LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "_EmbeddedRAM2LU,CSE PRAM2LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM2HL,CSE PRAM2HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM2HU,CSE PRAM2HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "_EmbeddedRAM3,CSE PRAM 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM3LL,CSE PRAM3LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM3LU,CSE PRAM3LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x0E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM3HL,CSE PRAM3HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM3HU,CSE PRAM3HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "_EmbeddedRAM4,CSE PRAM 4 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "_EmbeddedRAM4LL,CSE PRAM4LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "_EmbeddedRAM4LU,CSE PRAM4LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "_EmbeddedRAM4HL,CSE PRAM4HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "_EmbeddedRAM4HU,CSE PRAM4HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "_EmbeddedRAM5,CSE PRAM 5 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "_EmbeddedRAM5LL,CSE PRAM5LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "_EmbeddedRAM5LU,CSE PRAM5LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "_EmbeddedRAM5HL,CSE PRAM5HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "_EmbeddedRAM5HU,CSE PRAM5HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "_EmbeddedRAM6,CSE PRAM 6 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "_EmbeddedRAM6LL,CSE PRAM6LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "_EmbeddedRAM6LU,CSE PRAM6LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM6HL,CSE PRAM6HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM6HU,CSE PRAM6HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "_EmbeddedRAM7,CSE PRAM 7 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM7LL,CSE PRAM7LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM7LU,CSE PRAM7LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM7HL,CSE PRAM7HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM7HU,CSE PRAM7HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "_EmbeddedRAM8,CSE PRAM 8 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "_EmbeddedRAM8LL,CSE PRAM8LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "_EmbeddedRAM8LU,CSE PRAM8LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "_EmbeddedRAM8HL,CSE PRAM8HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "_EmbeddedRAM8HU,CSE PRAM8HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "_EmbeddedRAM9,CSE PRAM 9 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "_EmbeddedRAM9LL,CSE PRAM9LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "_EmbeddedRAM9LU,CSE PRAM9LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "_EmbeddedRAM9HL,CSE PRAM9HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x27++0x00
|
|
line.byte 0x00 "_EmbeddedRAM9HU,CSE PRAM9HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "_EmbeddedRAM10,CSE PRAM 10 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "_EmbeddedRAM10LL,CSE PRAM10LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "_EmbeddedRAM10LU,CSE PRAM10LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM10HL,CSE PRAM10HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM10HU,CSE PRAM10HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "_EmbeddedRAM11,CSE PRAM 11 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM11LL,CSE PRAM11LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM11LU,CSE PRAM11LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM11HL,CSE PRAM11HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM11HU,CSE PRAM11HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "_EmbeddedRAM12,CSE PRAM 12 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "_EmbeddedRAM12LL,CSE PRAM12LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "_EmbeddedRAM12LU,CSE PRAM12LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "_EmbeddedRAM12HL,CSE PRAM12HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "_EmbeddedRAM12HU,CSE PRAM12HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "_EmbeddedRAM13,CSE PRAM 13 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "_EmbeddedRAM13LL,CSE PRAM13LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "_EmbeddedRAM13LU,CSE PRAM13LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "_EmbeddedRAM13HL,CSE PRAM13HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "_EmbeddedRAM13HU,CSE PRAM13HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "_EmbeddedRAM14,CSE PRAM 14 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "_EmbeddedRAM14LL,CSE PRAM14LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "_EmbeddedRAM14LU,CSE PRAM14LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM14HL,CSE PRAM14HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM14HU,CSE PRAM14HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "_EmbeddedRAM15,CSE PRAM 15 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM15LL,CSE PRAM15LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM15LU,CSE PRAM15LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x3E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM15HL,CSE PRAM15HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM15HU,CSE PRAM15HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "_EmbeddedRAM16,CSE PRAM 16 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "_EmbeddedRAM16LL,CSE PRAM16LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "_EmbeddedRAM16LU,CSE PRAM16LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x42++0x00
|
|
line.byte 0x00 "_EmbeddedRAM16HL,CSE PRAM16HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x43++0x00
|
|
line.byte 0x00 "_EmbeddedRAM16HU,CSE PRAM16HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "_EmbeddedRAM17,CSE PRAM 17 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "_EmbeddedRAM17LL,CSE PRAM17LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x45++0x00
|
|
line.byte 0x00 "_EmbeddedRAM17LU,CSE PRAM17LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x46++0x00
|
|
line.byte 0x00 "_EmbeddedRAM17HL,CSE PRAM17HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "_EmbeddedRAM17HU,CSE PRAM17HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "_EmbeddedRAM18,CSE PRAM 18 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "_EmbeddedRAM18LL,CSE PRAM18LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "_EmbeddedRAM18LU,CSE PRAM18LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM18HL,CSE PRAM18HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM18HU,CSE PRAM18HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "_EmbeddedRAM19,CSE PRAM 19 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM19LL,CSE PRAM19LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM19LU,CSE PRAM19LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM19HL,CSE PRAM19HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM19HU,CSE PRAM19HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "_EmbeddedRAM20,CSE PRAM 20 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "_EmbeddedRAM20LL,CSE PRAM20LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "_EmbeddedRAM20LU,CSE PRAM20LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x52++0x00
|
|
line.byte 0x00 "_EmbeddedRAM20HL,CSE PRAM20HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x53++0x00
|
|
line.byte 0x00 "_EmbeddedRAM20HU,CSE PRAM20HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "_EmbeddedRAM21,CSE PRAM 21 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "_EmbeddedRAM21LL,CSE PRAM21LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "_EmbeddedRAM21LU,CSE PRAM21LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x56++0x00
|
|
line.byte 0x00 "_EmbeddedRAM21HL,CSE PRAM21HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "_EmbeddedRAM21HU,CSE PRAM21HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "_EmbeddedRAM22,CSE PRAM 22 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "_EmbeddedRAM22LL,CSE PRAM22LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x59++0x00
|
|
line.byte 0x00 "_EmbeddedRAM22LU,CSE PRAM22LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x5A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM22HL,CSE PRAM22HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x5B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM22HU,CSE PRAM22HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "_EmbeddedRAM23,CSE PRAM 23 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM23LL,CSE PRAM23LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x5D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM23LU,CSE PRAM23LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x5E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM23HL,CSE PRAM23HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x5F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM23HU,CSE PRAM23HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "_EmbeddedRAM24,CSE PRAM 24 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x60++0x00
|
|
line.byte 0x00 "_EmbeddedRAM24LL,CSE PRAM24LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x61++0x00
|
|
line.byte 0x00 "_EmbeddedRAM24LU,CSE PRAM24LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x62++0x00
|
|
line.byte 0x00 "_EmbeddedRAM24HL,CSE PRAM24HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x63++0x00
|
|
line.byte 0x00 "_EmbeddedRAM24HU,CSE PRAM24HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "_EmbeddedRAM25,CSE PRAM 25 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x64++0x00
|
|
line.byte 0x00 "_EmbeddedRAM25LL,CSE PRAM25LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x65++0x00
|
|
line.byte 0x00 "_EmbeddedRAM25LU,CSE PRAM25LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x66++0x00
|
|
line.byte 0x00 "_EmbeddedRAM25HL,CSE PRAM25HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x67++0x00
|
|
line.byte 0x00 "_EmbeddedRAM25HU,CSE PRAM25HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "_EmbeddedRAM26,CSE PRAM 26 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x68++0x00
|
|
line.byte 0x00 "_EmbeddedRAM26LL,CSE PRAM26LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x69++0x00
|
|
line.byte 0x00 "_EmbeddedRAM26LU,CSE PRAM26LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x6A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM26HL,CSE PRAM26HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x6B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM26HU,CSE PRAM26HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "_EmbeddedRAM27,CSE PRAM 27 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x6C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM27LL,CSE PRAM27LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x6D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM27LU,CSE PRAM27LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x6E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM27HL,CSE PRAM27HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x6F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM27HU,CSE PRAM27HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "_EmbeddedRAM28,CSE PRAM 28 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x70++0x00
|
|
line.byte 0x00 "_EmbeddedRAM28LL,CSE PRAM28LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x71++0x00
|
|
line.byte 0x00 "_EmbeddedRAM28LU,CSE PRAM28LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x72++0x00
|
|
line.byte 0x00 "_EmbeddedRAM28HL,CSE PRAM28HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x73++0x00
|
|
line.byte 0x00 "_EmbeddedRAM28HU,CSE PRAM28HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "_EmbeddedRAM29,CSE PRAM 29 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x74++0x00
|
|
line.byte 0x00 "_EmbeddedRAM29LL,CSE PRAM29LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x75++0x00
|
|
line.byte 0x00 "_EmbeddedRAM29LU,CSE PRAM29LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x76++0x00
|
|
line.byte 0x00 "_EmbeddedRAM29HL,CSE PRAM29HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x77++0x00
|
|
line.byte 0x00 "_EmbeddedRAM29HU,CSE PRAM29HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "_EmbeddedRAM30,CSE PRAM 30 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x78++0x00
|
|
line.byte 0x00 "_EmbeddedRAM30LL,CSE PRAM30LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x79++0x00
|
|
line.byte 0x00 "_EmbeddedRAM30LU,CSE PRAM30LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x7A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM30HL,CSE PRAM30HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x7B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM30HU,CSE PRAM30HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "_EmbeddedRAM31,CSE PRAM 31 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x7C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM31LL,CSE PRAM31LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x7D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM31LU,CSE PRAM31LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x7E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM31HL,CSE PRAM31HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x7F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM31HU,CSE PRAM31HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
elif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
base ad:0x14001000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "_EmbeddedRAM0,CSE PRAM 0 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "_EmbeddedRAM0LL,CSE PRAM0LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "_EmbeddedRAM0LU,CSE PRAM0LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "_EmbeddedRAM0HL,CSE PRAM0HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "_EmbeddedRAM0HU,CSE PRAM0HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "_EmbeddedRAM1,CSE PRAM 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "_EmbeddedRAM1LL,CSE PRAM1LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "_EmbeddedRAM1LU,CSE PRAM1LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "_EmbeddedRAM1HL,CSE PRAM1HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "_EmbeddedRAM1HU,CSE PRAM1HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "_EmbeddedRAM2,CSE PRAM 2 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "_EmbeddedRAM2LL,CSE PRAM2LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "_EmbeddedRAM2LU,CSE PRAM2LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM2HL,CSE PRAM2HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x0B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM2HU,CSE PRAM2HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "_EmbeddedRAM3,CSE PRAM 3 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM3LL,CSE PRAM3LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM3LU,CSE PRAM3LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x0E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM3HL,CSE PRAM3HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x0F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM3HU,CSE PRAM3HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "_EmbeddedRAM4,CSE PRAM 4 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "_EmbeddedRAM4LL,CSE PRAM4LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x11++0x00
|
|
line.byte 0x00 "_EmbeddedRAM4LU,CSE PRAM4LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "_EmbeddedRAM4HL,CSE PRAM4HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "_EmbeddedRAM4HU,CSE PRAM4HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "_EmbeddedRAM5,CSE PRAM 5 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "_EmbeddedRAM5LL,CSE PRAM5LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x15++0x00
|
|
line.byte 0x00 "_EmbeddedRAM5LU,CSE PRAM5LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "_EmbeddedRAM5HL,CSE PRAM5HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "_EmbeddedRAM5HU,CSE PRAM5HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "_EmbeddedRAM6,CSE PRAM 6 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "_EmbeddedRAM6LL,CSE PRAM6LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x19++0x00
|
|
line.byte 0x00 "_EmbeddedRAM6LU,CSE PRAM6LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM6HL,CSE PRAM6HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x1B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM6HU,CSE PRAM6HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "_EmbeddedRAM7,CSE PRAM 7 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM7LL,CSE PRAM7LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x1D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM7LU,CSE PRAM7LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM7HL,CSE PRAM7HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x1F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM7HU,CSE PRAM7HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "_EmbeddedRAM8,CSE PRAM 8 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x20++0x00
|
|
line.byte 0x00 "_EmbeddedRAM8LL,CSE PRAM8LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x21++0x00
|
|
line.byte 0x00 "_EmbeddedRAM8LU,CSE PRAM8LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "_EmbeddedRAM8HL,CSE PRAM8HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x23++0x00
|
|
line.byte 0x00 "_EmbeddedRAM8HU,CSE PRAM8HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "_EmbeddedRAM9,CSE PRAM 9 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "_EmbeddedRAM9LL,CSE PRAM9LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x25++0x00
|
|
line.byte 0x00 "_EmbeddedRAM9LU,CSE PRAM9LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "_EmbeddedRAM9HL,CSE PRAM9HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x27++0x00
|
|
line.byte 0x00 "_EmbeddedRAM9HU,CSE PRAM9HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "_EmbeddedRAM10,CSE PRAM 10 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "_EmbeddedRAM10LL,CSE PRAM10LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x29++0x00
|
|
line.byte 0x00 "_EmbeddedRAM10LU,CSE PRAM10LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x2A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM10HL,CSE PRAM10HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x2B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM10HU,CSE PRAM10HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "_EmbeddedRAM11,CSE PRAM 11 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x2C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM11LL,CSE PRAM11LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x2D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM11LU,CSE PRAM11LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM11HL,CSE PRAM11HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM11HU,CSE PRAM11HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "_EmbeddedRAM12,CSE PRAM 12 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x30++0x00
|
|
line.byte 0x00 "_EmbeddedRAM12LL,CSE PRAM12LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x31++0x00
|
|
line.byte 0x00 "_EmbeddedRAM12LU,CSE PRAM12LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "_EmbeddedRAM12HL,CSE PRAM12HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x33++0x00
|
|
line.byte 0x00 "_EmbeddedRAM12HU,CSE PRAM12HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "_EmbeddedRAM13,CSE PRAM 13 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x34++0x00
|
|
line.byte 0x00 "_EmbeddedRAM13LL,CSE PRAM13LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x35++0x00
|
|
line.byte 0x00 "_EmbeddedRAM13LU,CSE PRAM13LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "_EmbeddedRAM13HL,CSE PRAM13HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x37++0x00
|
|
line.byte 0x00 "_EmbeddedRAM13HU,CSE PRAM13HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "_EmbeddedRAM14,CSE PRAM 14 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "_EmbeddedRAM14LL,CSE PRAM14LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x39++0x00
|
|
line.byte 0x00 "_EmbeddedRAM14LU,CSE PRAM14LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x3A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM14HL,CSE PRAM14HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x3B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM14HU,CSE PRAM14HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "_EmbeddedRAM15,CSE PRAM 15 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x3C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM15LL,CSE PRAM15LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x3D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM15LU,CSE PRAM15LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x3E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM15HL,CSE PRAM15HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x3F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM15HU,CSE PRAM15HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "_EmbeddedRAM16,CSE PRAM 16 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "_EmbeddedRAM16LL,CSE PRAM16LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "_EmbeddedRAM16LU,CSE PRAM16LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x42++0x00
|
|
line.byte 0x00 "_EmbeddedRAM16HL,CSE PRAM16HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x43++0x00
|
|
line.byte 0x00 "_EmbeddedRAM16HU,CSE PRAM16HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "_EmbeddedRAM17,CSE PRAM 17 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x44++0x00
|
|
line.byte 0x00 "_EmbeddedRAM17LL,CSE PRAM17LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x45++0x00
|
|
line.byte 0x00 "_EmbeddedRAM17LU,CSE PRAM17LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x46++0x00
|
|
line.byte 0x00 "_EmbeddedRAM17HL,CSE PRAM17HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x47++0x00
|
|
line.byte 0x00 "_EmbeddedRAM17HU,CSE PRAM17HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "_EmbeddedRAM18,CSE PRAM 18 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x48++0x00
|
|
line.byte 0x00 "_EmbeddedRAM18LL,CSE PRAM18LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x49++0x00
|
|
line.byte 0x00 "_EmbeddedRAM18LU,CSE PRAM18LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x4A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM18HL,CSE PRAM18HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x4B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM18HU,CSE PRAM18HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "_EmbeddedRAM19,CSE PRAM 19 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x4C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM19LL,CSE PRAM19LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x4D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM19LU,CSE PRAM19LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x4E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM19HL,CSE PRAM19HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x4F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM19HU,CSE PRAM19HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "_EmbeddedRAM20,CSE PRAM 20 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x50++0x00
|
|
line.byte 0x00 "_EmbeddedRAM20LL,CSE PRAM20LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x51++0x00
|
|
line.byte 0x00 "_EmbeddedRAM20LU,CSE PRAM20LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x52++0x00
|
|
line.byte 0x00 "_EmbeddedRAM20HL,CSE PRAM20HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x53++0x00
|
|
line.byte 0x00 "_EmbeddedRAM20HU,CSE PRAM20HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "_EmbeddedRAM21,CSE PRAM 21 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x54++0x00
|
|
line.byte 0x00 "_EmbeddedRAM21LL,CSE PRAM21LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x55++0x00
|
|
line.byte 0x00 "_EmbeddedRAM21LU,CSE PRAM21LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x56++0x00
|
|
line.byte 0x00 "_EmbeddedRAM21HL,CSE PRAM21HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x57++0x00
|
|
line.byte 0x00 "_EmbeddedRAM21HU,CSE PRAM21HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "_EmbeddedRAM22,CSE PRAM 22 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x58++0x00
|
|
line.byte 0x00 "_EmbeddedRAM22LL,CSE PRAM22LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x59++0x00
|
|
line.byte 0x00 "_EmbeddedRAM22LU,CSE PRAM22LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x5A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM22HL,CSE PRAM22HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x5B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM22HU,CSE PRAM22HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "_EmbeddedRAM23,CSE PRAM 23 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x5C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM23LL,CSE PRAM23LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x5D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM23LU,CSE PRAM23LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x5E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM23HL,CSE PRAM23HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x5F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM23HU,CSE PRAM23HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "_EmbeddedRAM24,CSE PRAM 24 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x60++0x00
|
|
line.byte 0x00 "_EmbeddedRAM24LL,CSE PRAM24LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x61++0x00
|
|
line.byte 0x00 "_EmbeddedRAM24LU,CSE PRAM24LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x62++0x00
|
|
line.byte 0x00 "_EmbeddedRAM24HL,CSE PRAM24HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x63++0x00
|
|
line.byte 0x00 "_EmbeddedRAM24HU,CSE PRAM24HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "_EmbeddedRAM25,CSE PRAM 25 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x64++0x00
|
|
line.byte 0x00 "_EmbeddedRAM25LL,CSE PRAM25LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x65++0x00
|
|
line.byte 0x00 "_EmbeddedRAM25LU,CSE PRAM25LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x66++0x00
|
|
line.byte 0x00 "_EmbeddedRAM25HL,CSE PRAM25HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x67++0x00
|
|
line.byte 0x00 "_EmbeddedRAM25HU,CSE PRAM25HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "_EmbeddedRAM26,CSE PRAM 26 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x68++0x00
|
|
line.byte 0x00 "_EmbeddedRAM26LL,CSE PRAM26LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x69++0x00
|
|
line.byte 0x00 "_EmbeddedRAM26LU,CSE PRAM26LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x6A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM26HL,CSE PRAM26HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x6B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM26HU,CSE PRAM26HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "_EmbeddedRAM27,CSE PRAM 27 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x6C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM27LL,CSE PRAM27LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x6D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM27LU,CSE PRAM27LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x6E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM27HL,CSE PRAM27HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x6F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM27HU,CSE PRAM27HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "_EmbeddedRAM28,CSE PRAM 28 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x70++0x00
|
|
line.byte 0x00 "_EmbeddedRAM28LL,CSE PRAM28LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x71++0x00
|
|
line.byte 0x00 "_EmbeddedRAM28LU,CSE PRAM28LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x72++0x00
|
|
line.byte 0x00 "_EmbeddedRAM28HL,CSE PRAM28HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x73++0x00
|
|
line.byte 0x00 "_EmbeddedRAM28HU,CSE PRAM28HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "_EmbeddedRAM29,CSE PRAM 29 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x74++0x00
|
|
line.byte 0x00 "_EmbeddedRAM29LL,CSE PRAM29LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x75++0x00
|
|
line.byte 0x00 "_EmbeddedRAM29LU,CSE PRAM29LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x76++0x00
|
|
line.byte 0x00 "_EmbeddedRAM29HL,CSE PRAM29HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x77++0x00
|
|
line.byte 0x00 "_EmbeddedRAM29HU,CSE PRAM29HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "_EmbeddedRAM30,CSE PRAM 30 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x78++0x00
|
|
line.byte 0x00 "_EmbeddedRAM30LL,CSE PRAM30LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x79++0x00
|
|
line.byte 0x00 "_EmbeddedRAM30LU,CSE PRAM30LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x7A++0x00
|
|
line.byte 0x00 "_EmbeddedRAM30HL,CSE PRAM30HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x7B++0x00
|
|
line.byte 0x00 "_EmbeddedRAM30HU,CSE PRAM30HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "_EmbeddedRAM31,CSE PRAM 31 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
group.byte 0x7C++0x00
|
|
line.byte 0x00 "_EmbeddedRAM31LL,CSE PRAM31LL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LL,RAM_LL stores the first 8 bits of the 32 bit CRC"
|
|
group.byte 0x7D++0x00
|
|
line.byte 0x00 "_EmbeddedRAM31LU,CSE PRAM31LU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_LU,RAM_LU stores the second 8 bits of the 32 bit CRC"
|
|
group.byte 0x7E++0x00
|
|
line.byte 0x00 "_EmbeddedRAM31HL,CSE PRAM31HL register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HL,RAM_HL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x7F++0x00
|
|
line.byte 0x00 "_EmbeddedRAM31HU,CSE PRAM31HU register"
|
|
hexmask.byte 0x00 0.--7. 1. "RAM_HU,RAM_HU stores the fourth 8 bits of the 32 bit CRC"
|
|
endif
|
|
tree.end
|
|
tree "AIPS (AIPS-Lite Bridge)"
|
|
base ad:0x40000000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MPRA,Master Privilege Register A"
|
|
bitfld.long 0x00 30. "MTR0,Master 0 Trusted For Read" "0: This master is not trusted for read accesses,1: This master is trusted for read accesses"
|
|
bitfld.long 0x00 29. "MTW0,Master 0 Trusted For Writes" "0: This master is not trusted for write accesses,1: This master is trusted for write accesses"
|
|
newline
|
|
bitfld.long 0x00 28. "MPL0,Master 0 Privilege Level" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to.."
|
|
bitfld.long 0x00 26. "MTR1,Master 1 Trusted for Read" "0: This master is not trusted for read accesses,1: This master is trusted for read accesses"
|
|
newline
|
|
bitfld.long 0x00 25. "MTW1,Master 1 Trusted for Writes" "0: This master is not trusted for write accesses,1: This master is trusted for write accesses"
|
|
bitfld.long 0x00 24. "MPL1,Master 1 Privilege Level" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to.."
|
|
newline
|
|
bitfld.long 0x00 22. "MTR2,Master 2 Trusted For Read" "0: This master is not trusted for read accesses,1: This master is trusted for read accesses"
|
|
bitfld.long 0x00 21. "MTW2,Master 2 Trusted For Writes" "0: This master is not trusted for write accesses,1: This master is trusted for write accesses"
|
|
newline
|
|
bitfld.long 0x00 20. "MPL2,Master 2 Privilege Level" "0: Accesses from this master are forced to..,1: Accesses from this master are not forced to.."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PACRA,Peripheral Access Control Register"
|
|
bitfld.long 0x00 30. "SP0,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 29. "WP0,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 28. "TP0,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 26. "SP1,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 25. "WP1,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 24. "TP1,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "PACRB,Peripheral Access Control Register"
|
|
bitfld.long 0x00 30. "SP0,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 29. "WP0,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 28. "TP0,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 26. "SP1,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 25. "WP1,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 24. "TP1,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 10. "SP5,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 9. "WP5,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 8. "TP5,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "PACRC,Peripheral Access Control Register"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PACRD,Peripheral Access Control Register"
|
|
bitfld.long 0x00 30. "SP0,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 29. "WP0,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 28. "TP0,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 26. "SP1,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 25. "WP1,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 24. "TP1,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "OPACRA,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 30. "SP0,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 29. "WP0,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 28. "TP0,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 26. "SP1,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 25. "WP1,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 24. "TP1,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 14. "SP4,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 13. "WP4,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 12. "TP4,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 10. "SP5,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 9. "WP5,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 8. "TP5,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 6. "SP6,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 5. "WP6,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 4. "TP6,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 2. "SP7,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 1. "WP7,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 0. "TP7,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "OPACRB,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 18. "SP3,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 17. "WP3,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 16. "TP3,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 14. "SP4,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 13. "WP4,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 12. "TP4,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 10. "SP5,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 9. "WP5,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 8. "TP5,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 6. "SP6,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 5. "WP6,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 4. "TP6,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "OPACRC,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 26. "SP1,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 25. "WP1,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 24. "TP1,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 22. "SP2,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 21. "WP2,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 20. "TP2,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 6. "SP6,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 5. "WP6,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 4. "TP6,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 2. "SP7,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 1. "WP7,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 0. "TP7,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "OPACRD,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 30. "SP0,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 29. "WP0,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 28. "TP0,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 26. "SP1,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 25. "WP1,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 24. "TP1,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 22. "SP2,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 21. "WP2,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 20. "TP2,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 18. "SP3,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 17. "WP3,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 16. "TP3,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 10. "SP5,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 9. "WP5,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 8. "TP5,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "OPACRE,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 30. "SP0,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 29. "WP0,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 28. "TP0,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 6. "SP6,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 5. "WP6,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 4. "TP6,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "OPACRF,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 30. "SP0,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 29. "WP0,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 28. "TP0,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 26. "SP1,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 25. "WP1,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 24. "TP1,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 22. "SP2,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 21. "WP2,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 20. "TP2,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 18. "SP3,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 17. "WP3,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 16. "TP3,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 14. "SP4,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 13. "WP4,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 12. "TP4,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 10. "SP5,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 9. "WP5,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 8. "TP5,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
sif cpuis("S32K148")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "OPACRG,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 22. "SP2,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 21. "WP2,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 20. "TP2,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 14. "SP4,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 13. "WP4,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 12. "TP4,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 10. "SP5,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 9. "WP5,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 8. "TP5,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "OPACRG,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 22. "SP2,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 21. "WP2,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 20. "TP2,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
endif
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "OPACRH,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 22. "SP2,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 21. "WP2,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 20. "TP2,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OPACRI,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 26. "SP1,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 25. "WP1,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 24. "TP1,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 18. "SP3,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 17. "WP3,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 16. "TP3,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 14. "SP4,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 13. "WP4,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 12. "TP4,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 10. "SP5,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 9. "WP5,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 8. "TP5,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 6. "SP6,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 5. "WP6,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 4. "TP6,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OPACRI,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 26. "SP1,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 25. "WP1,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 24. "TP1,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 18. "SP3,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 17. "WP3,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 16. "TP3,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 14. "SP4,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 13. "WP4,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 12. "TP4,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 10. "SP5,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 9. "WP5,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 8. "TP5,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 6. "SP6,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 5. "WP6,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 4. "TP6,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 2. "SP7,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 1. "WP7,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 0. "TP7,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "OPACRJ,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 22. "SP2,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 21. "WP2,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 20. "TP2,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 18. "SP3,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 17. "WP3,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 16. "TP3,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 14. "SP4,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 13. "WP4,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 12. "TP4,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 6. "SP6,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 5. "WP6,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 4. "TP6,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 2. "SP7,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 1. "WP7,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 0. "TP7,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "OPACRJ,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 22. "SP2,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 21. "WP2,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 20. "TP2,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 18. "SP3,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 17. "WP3,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 16. "TP3,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 14. "SP4,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 13. "WP4,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 12. "TP4,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "OPACRK,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 30. "SP0,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 29. "WP0,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 28. "TP0,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 26. "SP1,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 25. "WP1,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 24. "TP1,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 18. "SP3,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 17. "WP3,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 16. "TP3,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 6. "SP6,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 5. "WP6,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 4. "TP6,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "OPACRK,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 18. "SP3,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 17. "WP3,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 16. "TP3,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "OPACRL,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 26. "SP1,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 25. "WP1,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 24. "TP1,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 10. "SP5,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 9. "WP5,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 8. "TP5,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 6. "SP6,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 5. "WP6,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 4. "TP6,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 2. "SP7,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 1. "WP7,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 0. "TP7,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "OPACRL,Off-Platform Peripheral Access Control Register"
|
|
bitfld.long 0x00 10. "SP5,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 9. "WP5,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 8. "TP5,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
bitfld.long 0x00 6. "SP6,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
newline
|
|
bitfld.long 0x00 5. "WP6,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
bitfld.long 0x00 4. "TP6,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
newline
|
|
bitfld.long 0x00 2. "SP7,Supervisor Protect" "0: This peripheral does not require supervisor..,1: This peripheral requires supervisor privilege.."
|
|
bitfld.long 0x00 1. "WP7,Write Protect" "0: This peripheral allows write accesses,1: This peripheral is write protected"
|
|
newline
|
|
bitfld.long 0x00 0. "TP7,Trusted Protect" "0: Accesses from an untrusted master are allowed,1: Accesses from an untrusted master are not.."
|
|
endif
|
|
tree.end
|
|
tree "MSCM"
|
|
base ad:0x40001000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "CPxTYPE,Processor X Type Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "PERSONALITY,Processor x Personality"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RYPZ,Processor x Revision"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "CPxNUM,Processor X Number Register"
|
|
bitfld.long 0x00 0. "CPN,Processor x Number" "0,1"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CPxMASTER,Processor X Master Register"
|
|
bitfld.long 0x00 0.--5. "PPMN,Processor x Physical Master Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CPxCOUNT,Processor X Count Register"
|
|
bitfld.long 0x00 0.--1. "PCNT,Processor Count" "0,1,2,3"
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CPxCFG0,Processor X Configuration Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ICWY,Level 1 Instruction Cache Ways"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DCSZ,Level 1 Data Cache Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DCWY,Level 1 Data Cache Ways"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "CPxCFG1,Processor X Configuration Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "L2SZ,Level 2 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "L2WY,Level 2 Instruction Cache Ways"
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "CPxCFG2,Processor X Configuration Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TMLSZ,Tightly-coupled Memory Lower Size"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TMUSZ,Tightly-coupled Memory Upper Size"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "CPxCFG3,Processor X Configuration Register 3"
|
|
bitfld.long 0x00 8.--9. "SBP,System Bus Ports" "0,1,2,3"
|
|
bitfld.long 0x00 6. "BB,Bit Banding" "0: Bit Banding is not supported,1: Bit Banding is supported"
|
|
newline
|
|
bitfld.long 0x00 5. "CMP,Core Memory Protection unit" "0: Core Memory Protection is not included,1: Core Memory Protection is included"
|
|
bitfld.long 0x00 4. "TZ,Trust Zone" "0: Trust Zone support is not included,1: Trust Zone support is included"
|
|
newline
|
|
bitfld.long 0x00 3. "MMU,Memory Management Unit" "0: MMU support is not included,1: MMU support is included"
|
|
bitfld.long 0x00 2. "JAZ,Jazelle support" "0: Jazelle support is not included,1: Jazelle support is included"
|
|
newline
|
|
bitfld.long 0x00 1. "SIMD,SIMD/NEON instruction support" "0: SIMD/NEON support is not included,1: SIMD/NEON support is included"
|
|
bitfld.long 0x00 0. "FPU,Floating Point Unit" "0: FPU support is not included,1: FPU support is included"
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "CP0TYPE,Processor 0 Type Register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "PERSONALITY,Processor 0 Personality"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RYPZ,Processor 0 Revision"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CP0NUM,Processor 0 Number Register"
|
|
bitfld.long 0x00 0. "CPN,Processor 0 Number" "0,1"
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "CP0MASTER,Processor 0 Master Register"
|
|
bitfld.long 0x00 0.--5. "PPMN,Processor 0 Physical Master Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "CP0COUNT,Processor 0 Count Register"
|
|
bitfld.long 0x00 0.--1. "PCNT,Processor Count" "0,1,2,3"
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "CP0CFG0,Processor 0 Configuration Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. "ICSZ,Level 1 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "ICWY,Level 1 Instruction Cache Ways"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DCSZ,Level 1 Data Cache Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DCWY,Level 1 Data Cache Ways"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CP0CFG1,Processor 0 Configuration Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "L2SZ,Level 2 Instruction Cache Size"
|
|
hexmask.long.byte 0x00 16.--23. 1. "L2WY,Level 2 Instruction Cache Ways"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "CP0CFG2,Processor 0 Configuration Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TMLSZ,Tightly-coupled Memory Lower Size"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TMUSZ,Tightly-coupled Memory Upper Size"
|
|
rgroup.long 0x3C++0x03
|
|
line.long 0x00 "CP0CFG3,Processor 0 Configuration Register 3"
|
|
bitfld.long 0x00 8.--9. "SBP,System Bus Ports" "0,1,2,3"
|
|
bitfld.long 0x00 6. "BB,Bit Banding" "0: Bit Banding is not supported,1: Bit Banding is supported"
|
|
newline
|
|
bitfld.long 0x00 5. "CMP,Core Memory Protection unit" "0: Core Memory Protection is not included,1: Core Memory Protection is included"
|
|
bitfld.long 0x00 4. "TZ,Trust Zone" "0: Trust Zone support is not included,1: Trust Zone support is included"
|
|
newline
|
|
bitfld.long 0x00 3. "MMU,Memory Management Unit" "0: MMU support is not included,1: MMU support is included"
|
|
bitfld.long 0x00 2. "JAZ,Jazelle support" "0: Jazelle support is not included,1: Jazelle support is included"
|
|
newline
|
|
bitfld.long 0x00 1. "SIMD,SIMD/NEON instruction support" "0: SIMD/NEON support is not included,1: SIMD/NEON support is included"
|
|
bitfld.long 0x00 0. "FPU,Floating Point Unit" "0: FPU support is not included,1: FPU support is included"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,V" "0: OCMEMn is not present,1: OCMEMn is present"
|
|
rbitfld.long 0x00 28. "OCMSZH,OCMSZH" "0: OCMEMn is a power-of-2 capacity,1: OCMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "OCMSZ,OCMSZ" "0: no OCMEMn,1: 1KB OCMEMn,2: 2KB OCMEMn,3: 4KB OCMEMn,4: 8KB OCMEMn,5: 16KB OCMEMn,6: 32KB OCMEMn,7: 64KB OCMEMn,8: 128KB OCMEMn,9: 256KB OCMEMn,10: 512KB OCMEMn,11: 1MB OCMEMn,12: 2MB OCMEMn,13: 4MB OCMEMn,14: 8MB OCMEMn,15: 16MB OCMEMn"
|
|
rbitfld.long 0x00 17.--19. "OCMW,OCMW" "?,?,2: OCMEMn 32-bits wide,3: OCMEMn 64-bits wide,4: OCMEMn 128-bits wide,5: OCMEMn 256-bits wide,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "RO,RO" "0: Writes to the OCMDRn[11:0] are allowed,1: Writes to the OCMDRn[11:0] are ignored"
|
|
rbitfld.long 0x00 13.--15. "OCMT,OCMT" "0: OCMEMn is a System RAM,1: OCMEMn is a Graphics RAM,?,3: OCMEMn is a ROM,4: OCMEMn is a Program Flash,5: OCMEMn is a Data Flash,6: OCMEMn is an EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. "OCMPU,OCMPU" "0,1"
|
|
bitfld.long 0x00 8.--11. "OCM2,OCMEM Control Field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "OCM1,OCMEM Control Field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "OCM0,OCMEM Control Field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "OCMDR0,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,V" "0: OCMEMn is not present,1: OCMEMn is present"
|
|
rbitfld.long 0x00 28. "OCMSZH,OCMSZH" "0: OCMEMn is a power-of-2 capacity,1: OCMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "OCMSZ,OCMSZ" "0: no OCMEMn,1: 1KB OCMEMn,2: 2KB OCMEMn,3: 4KB OCMEMn,4: 8KB OCMEMn,5: 16KB OCMEMn,6: 32KB OCMEMn,7: 64KB OCMEMn,8: 128KB OCMEMn,9: 256KB OCMEMn,10: 512KB OCMEMn,11: 1MB OCMEMn,12: 2MB OCMEMn,13: 4MB OCMEMn,14: 8MB OCMEMn,15: 16MB OCMEMn"
|
|
rbitfld.long 0x00 17.--19. "OCMW,OCMW" "?,?,2: OCMEMn 32-bits wide,3: OCMEMn 64-bits wide,4: OCMEMn 128-bits wide,5: OCMEMn 256-bits wide,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "RO,RO" "0: Writes to the OCMDRn[11:0] are allowed,1: Writes to the OCMDRn[11:0] are ignored"
|
|
rbitfld.long 0x00 13.--15. "OCMT,OCMT" "?,?,?,?,4: OCMEMn is a Program Flash,5: OCMEMn is a Data Flash,6: OCMEMn is an EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. "OCMPU,OCMPU" "0,1"
|
|
bitfld.long 0x00 4.--5. "OCM1,OCMEM Control Field 1" "0,1,2,3"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,V" "0: OCMEMn is not present,1: OCMEMn is present"
|
|
rbitfld.long 0x00 28. "OCMSZH,OCMSZH" "0: OCMEMn is a power-of-2 capacity,1: OCMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "OCMSZ,OCMSZ" "0: no OCMEMn,1: 1KB OCMEMn,2: 2KB OCMEMn,3: 4KB OCMEMn,4: 8KB OCMEMn,5: 16KB OCMEMn,6: 32KB OCMEMn,7: 64KB OCMEMn,8: 128KB OCMEMn,9: 256KB OCMEMn,10: 512KB OCMEMn,11: 1MB OCMEMn,12: 2MB OCMEMn,13: 4MB OCMEMn,14: 8MB OCMEMn,15: 16MB OCMEMn"
|
|
rbitfld.long 0x00 17.--19. "OCMW,OCMW" "?,?,2: OCMEMn 32-bits wide,3: OCMEMn 64-bits wide,4: OCMEMn 128-bits wide,5: OCMEMn 256-bits wide,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "RO,RO" "0: Writes to the OCMDRn[11:0] are allowed,1: Writes to the OCMDRn[11:0] are ignored"
|
|
rbitfld.long 0x00 13.--15. "OCMT,OCMT" "0: OCMEMn is a System RAM,1: OCMEMn is a Graphics RAM,?,3: OCMEMn is a ROM,4: OCMEMn is a Program Flash,5: OCMEMn is a Data Flash,6: OCMEMn is an EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. "OCMPU,OCMPU" "0,1"
|
|
bitfld.long 0x00 8.--11. "OCM2,OCMEM Control Field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "OCM1,OCMEM Control Field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "OCM0,OCMEM Control Field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "OCMDR1,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,V" "0: OCMEMn is not present,1: OCMEMn is present"
|
|
rbitfld.long 0x00 28. "OCMSZH,OCMSZH" "0: OCMEMn is a power-of-2 capacity,1: OCMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "OCMSZ,OCMSZ" "0: no OCMEMn,1: 1KB OCMEMn,2: 2KB OCMEMn,3: 4KB OCMEMn,4: 8KB OCMEMn,5: 16KB OCMEMn,6: 32KB OCMEMn,7: 64KB OCMEMn,8: 128KB OCMEMn,9: 256KB OCMEMn,10: 512KB OCMEMn,11: 1MB OCMEMn,12: 2MB OCMEMn,13: 4MB OCMEMn,14: 8MB OCMEMn,15: 16MB OCMEMn"
|
|
rbitfld.long 0x00 17.--19. "OCMW,OCMW" "?,?,2: OCMEMn 32-bits wide,3: OCMEMn 64-bits wide,4: OCMEMn 128-bits wide,5: OCMEMn 256-bits wide,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "RO,RO" "0: Writes to the OCMDRn[11:0] are allowed,1: Writes to the OCMDRn[11:0] are ignored"
|
|
rbitfld.long 0x00 13.--15. "OCMT,OCMT" "?,?,?,?,4: OCMEMn is a Program Flash,5: OCMEMn is a Data Flash,6: OCMEMn is an EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. "OCMPU,OCMPU" "0,1"
|
|
bitfld.long 0x00 4.--5. "OCM1,OCMEM Control Field 1" "0,1,2,3"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,V" "0: OCMEMn is not present,1: OCMEMn is present"
|
|
rbitfld.long 0x00 28. "OCMSZH,OCMSZH" "0: OCMEMn is a power-of-2 capacity,1: OCMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "OCMSZ,OCMSZ" "0: no OCMEMn,1: 1KB OCMEMn,2: 2KB OCMEMn,3: 4KB OCMEMn,4: 8KB OCMEMn,5: 16KB OCMEMn,6: 32KB OCMEMn,7: 64KB OCMEMn,8: 128KB OCMEMn,9: 256KB OCMEMn,10: 512KB OCMEMn,11: 1MB OCMEMn,12: 2MB OCMEMn,13: 4MB OCMEMn,14: 8MB OCMEMn,15: 16MB OCMEMn"
|
|
rbitfld.long 0x00 17.--19. "OCMW,OCMW" "?,?,2: OCMEMn 32-bits wide,3: OCMEMn 64-bits wide,4: OCMEMn 128-bits wide,5: OCMEMn 256-bits wide,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "RO,RO" "0: Writes to the OCMDRn[11:0] are allowed,1: Writes to the OCMDRn[11:0] are ignored"
|
|
rbitfld.long 0x00 13.--15. "OCMT,OCMT" "0: OCMEMn is a System RAM,1: OCMEMn is a Graphics RAM,?,3: OCMEMn is a ROM,4: OCMEMn is a Program Flash,5: OCMEMn is a Data Flash,6: OCMEMn is an EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. "OCMPU,OCMPU" "0,1"
|
|
bitfld.long 0x00 8.--11. "OCM2,OCMEM Control Field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "OCM1,OCMEM Control Field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "OCM0,OCMEM Control Field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "OCMDR2,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,V" "0: OCMEMn is not present,1: OCMEMn is present"
|
|
rbitfld.long 0x00 28. "OCMSZH,OCMSZH" "0: OCMEMn is a power-of-2 capacity,1: OCMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "OCMSZ,OCMSZ" "0: no OCMEMn,1: 1KB OCMEMn,2: 2KB OCMEMn,3: 4KB OCMEMn,4: 8KB OCMEMn,5: 16KB OCMEMn,6: 32KB OCMEMn,7: 64KB OCMEMn,8: 128KB OCMEMn,9: 256KB OCMEMn,10: 512KB OCMEMn,11: 1MB OCMEMn,12: 2MB OCMEMn,13: 4MB OCMEMn,14: 8MB OCMEMn,15: 16MB OCMEMn"
|
|
rbitfld.long 0x00 17.--19. "OCMW,OCMW" "?,?,2: OCMEMn 32-bits wide,3: OCMEMn 64-bits wide,4: OCMEMn 128-bits wide,5: OCMEMn 256-bits wide,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "RO,RO" "0: Writes to the OCMDRn[11:0] are allowed,1: Writes to the OCMDRn[11:0] are ignored"
|
|
rbitfld.long 0x00 13.--15. "OCMT,OCMT" "?,?,?,?,4: OCMEMn is a Program Flash,5: OCMEMn is a Data Flash,6: OCMEMn is an EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. "OCMPU,OCMPU" "0,1"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "OCMDR3,On-Chip Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,V" "0: OCMEMn is not present,1: OCMEMn is present"
|
|
rbitfld.long 0x00 28. "OCMSZH,OCMSZH" "0: OCMEMn is a power-of-2 capacity,1: OCMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "OCMSZ,OCMSZ" "0: no OCMEMn,1: 1KB OCMEMn,2: 2KB OCMEMn,3: 4KB OCMEMn,4: 8KB OCMEMn,5: 16KB OCMEMn,6: 32KB OCMEMn,7: 64KB OCMEMn,8: 128KB OCMEMn,9: 256KB OCMEMn,10: 512KB OCMEMn,11: 1MB OCMEMn,12: 2MB OCMEMn,13: 4MB OCMEMn,14: 8MB OCMEMn,15: 16MB OCMEMn"
|
|
rbitfld.long 0x00 17.--19. "OCMW,OCMW" "?,?,2: OCMEMn 32-bits wide,3: OCMEMn 64-bits wide,4: OCMEMn 128-bits wide,5: OCMEMn 256-bits wide,?..."
|
|
newline
|
|
bitfld.long 0x00 16. "RO,RO" "0: Writes to the OCMDRn[11:0] are allowed,1: Writes to the OCMDRn[11:0] are ignored"
|
|
rbitfld.long 0x00 13.--15. "OCMT,OCMT" "0: OCMEMn is a System RAM,1: OCMEMn is a Graphics RAM,?,3: OCMEMn is a ROM,4: OCMEMn is a Program Flash,5: OCMEMn is a Data Flash,6: OCMEMn is an EEE,?..."
|
|
newline
|
|
rbitfld.long 0x00 12. "OCMPU,OCMPU" "0,1"
|
|
bitfld.long 0x00 8.--11. "OCM2,OCMEM Control Field 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "OCM1,OCMEM Control Field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "OCM0,OCMEM Control Field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
tree.end
|
|
tree "DMA (Enhanced Direct Memory Access)"
|
|
base ad:0x40008000
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K148")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 17. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer"
|
|
bitfld.long 0x00 16. "ECX,Error Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer in the.."
|
|
newline
|
|
bitfld.long 0x00 7. "EMLM,Enable Minor Loop Mapping" "0: Disabled,1: Enabled"
|
|
bitfld.long 0x00 6. "CLM,Continuous Link Mode" "0: A minor loop channel link made to itself goes..,1: A minor loop channel link made to itself does.."
|
|
newline
|
|
bitfld.long 0x00 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels"
|
|
bitfld.long 0x00 4. "HOE,Halt On Error" "0: Normal operation,1: Any error causes the HALT bit to set"
|
|
newline
|
|
bitfld.long 0x00 2. "ERCA,Enable Round Robin Channel Arbitration" "0,1"
|
|
bitfld.long 0x00 1. "EDBG,Enable Debug" "0,1"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
rbitfld.long 0x00 31. "ACTIVE,DMA Active Status" "0: eDMA is idle,1: eDMA is executing a channel"
|
|
bitfld.long 0x00 17. "CX,Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer"
|
|
newline
|
|
bitfld.long 0x00 16. "ECX,Error Cancel Transfer" "0: Normal operation,1: Cancel the remaining data transfer in the.."
|
|
bitfld.long 0x00 7. "EMLM,Enable Minor Loop Mapping" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "CLM,Continuous Link Mode" "0: A minor loop channel link made to itself goes..,1: A minor loop channel link made to itself does.."
|
|
bitfld.long 0x00 5. "HALT,Halt DMA Operations" "0: Normal operation,1: Stall the start of any new channels"
|
|
newline
|
|
bitfld.long 0x00 4. "HOE,Halt On Error" "0: Normal operation,1: Any error causes the HALT bit to set"
|
|
bitfld.long 0x00 2. "ERCA,Enable Round Robin Channel Arbitration" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "EDBG,Enable Debug" "0,1"
|
|
endif
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "ES,Error Status Register"
|
|
bitfld.long 0x00 31. "VLD,VLD" "0: No ERR bits are set,1: At least one ERR bit is set indicating a.."
|
|
bitfld.long 0x00 16. "ECX,Transfer Canceled" "0: No canceled transfers,1: The last recorded entry was a canceled.."
|
|
newline
|
|
bitfld.long 0x00 14. "CPE,Channel Priority Error" "0: No channel priority error,?..."
|
|
bitfld.long 0x00 8.--11. "ERRCHN,Error Channel Number or Canceled Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 7. "SAE,Source Address Error" "0: No source address configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 6. "SOE,Source Offset Error" "0: No source offset configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 5. "DAE,Destination Address Error" "0: No destination address configuration error,1: The last recorded error was a configuration.."
|
|
bitfld.long 0x00 4. "DOE,Destination Offset Error" "0: No destination offset configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 3. "NCE,NBYTES/CITER Configuration Error" "0: No NBYTES/CITER configuration error,?..."
|
|
bitfld.long 0x00 2. "SGE,Scatter/Gather Configuration Error" "0: No scatter/gather configuration error,1: The last recorded error was a configuration.."
|
|
newline
|
|
bitfld.long 0x00 1. "SBE,Source Bus Error" "0: No source bus error,1: The last recorded error was a bus error on a.."
|
|
bitfld.long 0x00 0. "DBE,Destination Bus Error" "0: No destination bus error,1: The last recorded error was a bus error on a.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "ERQ,Enable Request Register"
|
|
bitfld.long 0x00 15. "ERQ15,Enable DMA Request 15" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 14. "ERQ14,Enable DMA Request 14" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 13. "ERQ13,Enable DMA Request 13" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 12. "ERQ12,Enable DMA Request 12" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 11. "ERQ11,Enable DMA Request 11" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 10. "ERQ10,Enable DMA Request 10" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 9. "ERQ9,Enable DMA Request 9" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 8. "ERQ8,Enable DMA Request 8" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 7. "ERQ7,Enable DMA Request 7" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 6. "ERQ6,Enable DMA Request 6" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 5. "ERQ5,Enable DMA Request 5" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 4. "ERQ4,Enable DMA Request 4" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 3. "ERQ3,Enable DMA Request 3" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 2. "ERQ2,Enable DMA Request 2" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "ERQ1,Enable DMA Request 1" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
bitfld.long 0x00 0. "ERQ0,Enable DMA Request 0" "0: The DMA request signal for the corresponding..,1: The DMA request signal for the corresponding.."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "EEI,Enable Error Interrupt Register"
|
|
bitfld.long 0x00 15. "EEI15,Enable Error Interrupt 15" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 14. "EEI14,Enable Error Interrupt 14" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 13. "EEI13,Enable Error Interrupt 13" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 12. "EEI12,Enable Error Interrupt 12" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 11. "EEI11,Enable Error Interrupt 11" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 10. "EEI10,Enable Error Interrupt 10" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 9. "EEI9,Enable Error Interrupt 9" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 8. "EEI8,Enable Error Interrupt 8" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 7. "EEI7,Enable Error Interrupt 7" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 6. "EEI6,Enable Error Interrupt 6" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 5. "EEI5,Enable Error Interrupt 5" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 4. "EEI4,Enable Error Interrupt 4" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 3. "EEI3,Enable Error Interrupt 3" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 2. "EEI2,Enable Error Interrupt 2" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
newline
|
|
bitfld.long 0x00 1. "EEI1,Enable Error Interrupt 1" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
bitfld.long 0x00 0. "EEI0,Enable Error Interrupt 0" "0: The error signal for corresponding channel..,1: The assertion of the error signal for.."
|
|
wgroup.byte 0x18++0x00
|
|
line.byte 0x00 "CEEI,Clear Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAEE,Clear All Enable Error Interrupts" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CEEI,Clear Enable Error Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.byte 0x19++0x00
|
|
line.byte 0x00 "SEEI,Set Enable Error Interrupt Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAEE,Sets All Enable Error Interrupts" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "SEEI,Set Enable Error Interrupt" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.byte 0x1A++0x00
|
|
line.byte 0x00 "CERQ,Clear Enable Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAER,Clear All Enable Requests" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CERQ,Clear Enable Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.byte 0x1B++0x00
|
|
line.byte 0x00 "SERQ,Set Enable Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAER,Set All Enable Requests" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "SERQ,Set Enable Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.byte 0x1C++0x00
|
|
line.byte 0x00 "CDNE,Clear DONE Status Bit Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CADN,Clears All DONE Bits" "0: Clears only the TCDn_CSR[DONE] bit specified..,1: Clears all bits in TCDn_CSR[DONE]"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CDNE,Clear DONE Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.byte 0x1D++0x00
|
|
line.byte 0x00 "SSRT,Set START Bit Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "SAST,Set All START Bits (activates all channels)" "0: Set only the TCDn_CSR[START] bit specified in..,1: Set all bits in TCDn_CSR[START]"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "SSRT,Set START Bit" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.byte 0x1E++0x00
|
|
line.byte 0x00 "CERR,Clear Error Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAEI,Clear All Error Indicators" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CERR,Clear Error Indicator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
wgroup.byte 0x1F++0x00
|
|
line.byte 0x00 "CINT,Clear Interrupt Request Register"
|
|
bitfld.byte 0x00 7. "NOP,No Op enable" "0: Normal operation,1: No operation ignore the other bits in this.."
|
|
bitfld.byte 0x00 6. "CAIR,Clear All Interrupt Requests" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CINT,Clear Interrupt Request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "INT,Interrupt Request Register"
|
|
bitfld.long 0x00 15. "INT15,Interrupt Request 15" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
bitfld.long 0x00 14. "INT14,Interrupt Request 14" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 13. "INT13,Interrupt Request 13" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
bitfld.long 0x00 12. "INT12,Interrupt Request 12" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 11. "INT11,Interrupt Request 11" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
bitfld.long 0x00 10. "INT10,Interrupt Request 10" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 9. "INT9,Interrupt Request 9" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
bitfld.long 0x00 8. "INT8,Interrupt Request 8" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 7. "INT7,Interrupt Request 7" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
bitfld.long 0x00 6. "INT6,Interrupt Request 6" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 5. "INT5,Interrupt Request 5" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
bitfld.long 0x00 4. "INT4,Interrupt Request 4" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 3. "INT3,Interrupt Request 3" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
bitfld.long 0x00 2. "INT2,Interrupt Request 2" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
newline
|
|
bitfld.long 0x00 1. "INT1,Interrupt Request 1" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
bitfld.long 0x00 0. "INT0,Interrupt Request 0" "0: The interrupt request for corresponding..,1: The interrupt request for corresponding.."
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "ERR,Error Register"
|
|
bitfld.long 0x00 15. "ERR15,Error In Channel 15" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
bitfld.long 0x00 14. "ERR14,Error In Channel 14" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
bitfld.long 0x00 13. "ERR13,Error In Channel 13" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
bitfld.long 0x00 12. "ERR12,Error In Channel 12" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
bitfld.long 0x00 11. "ERR11,Error In Channel 11" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
bitfld.long 0x00 10. "ERR10,Error In Channel 10" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
bitfld.long 0x00 9. "ERR9,Error In Channel 9" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
bitfld.long 0x00 8. "ERR8,Error In Channel 8" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
bitfld.long 0x00 7. "ERR7,Error In Channel 7" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
bitfld.long 0x00 6. "ERR6,Error In Channel 6" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "ERR5,Error In Channel 5" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
bitfld.long 0x00 4. "ERR4,Error In Channel 4" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
bitfld.long 0x00 3. "ERR3,Error In Channel 3" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
bitfld.long 0x00 2. "ERR2,Error In Channel 2" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
newline
|
|
bitfld.long 0x00 1. "ERR1,Error In Channel 1" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
bitfld.long 0x00 0. "ERR0,Error In Channel 0" "0: An error in this channel has not occurred,1: An error in this channel has occurred"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "HRS,Hardware Request Status Register"
|
|
bitfld.long 0x00 15. "HRS15,Hardware Request Status Channel 15" "0: A hardware service request for channel 15 is..,1: A hardware service request for channel 15 is.."
|
|
bitfld.long 0x00 14. "HRS14,Hardware Request Status Channel 14" "0: A hardware service request for channel 14 is..,1: A hardware service request for channel 14 is.."
|
|
newline
|
|
bitfld.long 0x00 13. "HRS13,Hardware Request Status Channel 13" "0: A hardware service request for channel 13 is..,1: A hardware service request for channel 13 is.."
|
|
bitfld.long 0x00 12. "HRS12,Hardware Request Status Channel 12" "0: A hardware service request for channel 12 is..,1: A hardware service request for channel 12 is.."
|
|
newline
|
|
bitfld.long 0x00 11. "HRS11,Hardware Request Status Channel 11" "0: A hardware service request for channel 11 is..,1: A hardware service request for channel 11 is.."
|
|
bitfld.long 0x00 10. "HRS10,Hardware Request Status Channel 10" "0: A hardware service request for channel 10 is..,1: A hardware service request for channel 10 is.."
|
|
newline
|
|
bitfld.long 0x00 9. "HRS9,Hardware Request Status Channel 9" "0: A hardware service request for channel 9 is..,1: A hardware service request for channel 9 is.."
|
|
bitfld.long 0x00 8. "HRS8,Hardware Request Status Channel 8" "0: A hardware service request for channel 8 is..,1: A hardware service request for channel 8 is.."
|
|
newline
|
|
bitfld.long 0x00 7. "HRS7,Hardware Request Status Channel 7" "0: A hardware service request for channel 7 is..,1: A hardware service request for channel 7 is.."
|
|
bitfld.long 0x00 6. "HRS6,Hardware Request Status Channel 6" "0: A hardware service request for channel 6 is..,1: A hardware service request for channel 6 is.."
|
|
newline
|
|
bitfld.long 0x00 5. "HRS5,Hardware Request Status Channel 5" "0: A hardware service request for channel 5 is..,1: A hardware service request for channel 5 is.."
|
|
bitfld.long 0x00 4. "HRS4,Hardware Request Status Channel 4" "0: A hardware service request for channel 4 is..,1: A hardware service request for channel 4 is.."
|
|
newline
|
|
bitfld.long 0x00 3. "HRS3,Hardware Request Status Channel 3" "0: A hardware service request for channel 3 is..,1: A hardware service request for channel 3 is.."
|
|
bitfld.long 0x00 2. "HRS2,Hardware Request Status Channel 2" "0: A hardware service request for channel 2 is..,1: A hardware service request for channel 2 is.."
|
|
newline
|
|
bitfld.long 0x00 1. "HRS1,Hardware Request Status Channel 1" "0: A hardware service request for channel 1 is..,1: A hardware service request for channel 1 is.."
|
|
bitfld.long 0x00 0. "HRS0,Hardware Request Status Channel 0" "0: A hardware service request for channel 0 is..,1: A hardware service request for channel 0 is.."
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "EARS,Enable Asynchronous Request in Stop Register"
|
|
bitfld.long 0x00 15. "EDREQ_15,Enable asynchronous DMA request in stop mode for channel 15" "0: Disable asynchronous DMA request for channel 15,1: Enable asynchronous DMA request for channel 15"
|
|
bitfld.long 0x00 14. "EDREQ_14,Enable asynchronous DMA request in stop mode for channel 14" "0: Disable asynchronous DMA request for channel 14,1: Enable asynchronous DMA request for channel 14"
|
|
newline
|
|
bitfld.long 0x00 13. "EDREQ_13,Enable asynchronous DMA request in stop mode for channel 13" "0: Disable asynchronous DMA request for channel 13,1: Enable asynchronous DMA request for channel 13"
|
|
bitfld.long 0x00 12. "EDREQ_12,Enable asynchronous DMA request in stop mode for channel 12" "0: Disable asynchronous DMA request for channel 12,1: Enable asynchronous DMA request for channel 12"
|
|
newline
|
|
bitfld.long 0x00 11. "EDREQ_11,Enable asynchronous DMA request in stop mode for channel 11" "0: Disable asynchronous DMA request for channel 11,1: Enable asynchronous DMA request for channel 11"
|
|
bitfld.long 0x00 10. "EDREQ_10,Enable asynchronous DMA request in stop mode for channel 10" "0: Disable asynchronous DMA request for channel 10,1: Enable asynchronous DMA request for channel 10"
|
|
newline
|
|
bitfld.long 0x00 9. "EDREQ_9,Enable asynchronous DMA request in stop mode for channel 9" "0: Disable asynchronous DMA request for channel 9,1: Enable asynchronous DMA request for channel 9"
|
|
bitfld.long 0x00 8. "EDREQ_8,Enable asynchronous DMA request in stop mode for channel 8" "0: Disable asynchronous DMA request for channel 8,1: Enable asynchronous DMA request for channel 8"
|
|
newline
|
|
bitfld.long 0x00 7. "EDREQ_7,Enable asynchronous DMA request in stop mode for channel 7" "0: Disable asynchronous DMA request for channel 7,1: Enable asynchronous DMA request for channel 7"
|
|
bitfld.long 0x00 6. "EDREQ_6,Enable asynchronous DMA request in stop mode for channel 6" "0: Disable asynchronous DMA request for channel 6,1: Enable asynchronous DMA request for channel 6"
|
|
newline
|
|
bitfld.long 0x00 5. "EDREQ_5,Enable asynchronous DMA request in stop mode for channel 5" "0: Disable asynchronous DMA request for channel 5,1: Enable asynchronous DMA request for channel 5"
|
|
bitfld.long 0x00 4. "EDREQ_4,Enable asynchronous DMA request in stop mode for channel 4" "0: Disable asynchronous DMA request for channel 4,1: Enable asynchronous DMA request for channel 4"
|
|
newline
|
|
bitfld.long 0x00 3. "EDREQ_3,Enable asynchronous DMA request in stop mode for channel 3" "0: Disable asynchronous DMA request for channel 3,1: Enable asynchronous DMA request for channel 3"
|
|
bitfld.long 0x00 2. "EDREQ_2,Enable asynchronous DMA request in stop mode for channel 2" "0: Disable asynchronous DMA request for channel 2,1: Enable asynchronous DMA request for channel 2"
|
|
newline
|
|
bitfld.long 0x00 1. "EDREQ_1,Enable asynchronous DMA request in stop mode for channel 1" "0: Disable asynchronous DMA request for channel 1,1: Enable asynchronous DMA request for channel 1"
|
|
bitfld.long 0x00 0. "EDREQ_0,Enable asynchronous DMA request in stop mode for channel 0" "0: Disable asynchronous DMA request for channel 0,1: Enable asynchronous DMA request for channel 0"
|
|
repeat 16. (strings "3" "2" "1" "0" "7" "6" "5" "4" "11" "10" "9" "8" "15" "14" "13" "12" )(list 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F )
|
|
group.byte ($2+0x100)++0x00
|
|
line.byte 0x00 "DCHPRI$1,Channel n Priority Register"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
bitfld.byte 0x00 7. "ECP,Enable Channel Preemption" "0: Channel n cannot be suspended by a higher..,1: Channel n can be temporarily suspended by the.."
|
|
bitfld.byte 0x00 6. "DPA,Disable Preempt Ability" "0: Channel n can suspend a lower priority channel,1: Channel n cannot suspend any channel.."
|
|
newline
|
|
bitfld.byte 0x00 0.--3. "CHPRI,Channel n Arbitration Priority" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
repeat.end
|
|
group.long 0x1000++0x03
|
|
line.long 0x00 "TCD0_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1004++0x01
|
|
line.word 0x00 "TCD0_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1006++0x01
|
|
line.word 0x00 "TCD0_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1008++0x03
|
|
line.long 0x00 "TCD0_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x100C++0x03
|
|
line.long 0x00 "TCD0_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1010++0x03
|
|
line.long 0x00 "TCD0_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1014++0x01
|
|
line.word 0x00 "TCD0_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1016++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x1016++0x01
|
|
line.word 0x00 "TCD0_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1018++0x03
|
|
line.long 0x00 "TCD0_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x101C++0x01
|
|
line.word 0x00 "TCD0_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x101E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x101E++0x01
|
|
line.word 0x00 "TCD0_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1020++0x03
|
|
line.long 0x00 "TCD1_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1024++0x01
|
|
line.word 0x00 "TCD1_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1026++0x01
|
|
line.word 0x00 "TCD1_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1028++0x03
|
|
line.long 0x00 "TCD1_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x102C++0x03
|
|
line.long 0x00 "TCD1_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1030++0x03
|
|
line.long 0x00 "TCD1_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1034++0x01
|
|
line.word 0x00 "TCD1_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x1036++0x01
|
|
line.word 0x00 "TCD1_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1038++0x03
|
|
line.long 0x00 "TCD1_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x103C++0x01
|
|
line.word 0x00 "TCD1_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x103E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x103E++0x01
|
|
line.word 0x00 "TCD1_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1040++0x03
|
|
line.long 0x00 "TCD2_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1044++0x01
|
|
line.word 0x00 "TCD2_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1046++0x01
|
|
line.word 0x00 "TCD2_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1048++0x03
|
|
line.long 0x00 "TCD2_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x104C++0x03
|
|
line.long 0x00 "TCD2_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1050++0x03
|
|
line.long 0x00 "TCD2_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1054++0x01
|
|
line.word 0x00 "TCD2_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1056++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x1056++0x01
|
|
line.word 0x00 "TCD2_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1058++0x03
|
|
line.long 0x00 "TCD2_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x105C++0x01
|
|
line.word 0x00 "TCD2_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x105E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x105E++0x01
|
|
line.word 0x00 "TCD2_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1060++0x03
|
|
line.long 0x00 "TCD3_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1064++0x01
|
|
line.word 0x00 "TCD3_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1066++0x01
|
|
line.word 0x00 "TCD3_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1068++0x03
|
|
line.long 0x00 "TCD3_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x106C++0x03
|
|
line.long 0x00 "TCD3_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1070++0x03
|
|
line.long 0x00 "TCD3_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1074++0x01
|
|
line.word 0x00 "TCD3_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1076++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x1076++0x01
|
|
line.word 0x00 "TCD3_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1078++0x03
|
|
line.long 0x00 "TCD3_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x107C++0x01
|
|
line.word 0x00 "TCD3_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x107E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x107E++0x01
|
|
line.word 0x00 "TCD3_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1080++0x03
|
|
line.long 0x00 "TCD4_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1084++0x01
|
|
line.word 0x00 "TCD4_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1086++0x01
|
|
line.word 0x00 "TCD4_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1088++0x03
|
|
line.long 0x00 "TCD4_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x108C++0x03
|
|
line.long 0x00 "TCD4_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1090++0x03
|
|
line.long 0x00 "TCD4_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1094++0x01
|
|
line.word 0x00 "TCD4_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1096++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x1096++0x01
|
|
line.word 0x00 "TCD4_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1098++0x03
|
|
line.long 0x00 "TCD4_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x109C++0x01
|
|
line.word 0x00 "TCD4_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x109E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x109E++0x01
|
|
line.word 0x00 "TCD4_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x10A0++0x03
|
|
line.long 0x00 "TCD5_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10A4++0x01
|
|
line.word 0x00 "TCD5_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10A6++0x01
|
|
line.word 0x00 "TCD5_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10A8++0x03
|
|
line.long 0x00 "TCD5_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10AC++0x03
|
|
line.long 0x00 "TCD5_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10B0++0x03
|
|
line.long 0x00 "TCD5_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10B4++0x01
|
|
line.word 0x00 "TCD5_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10B6++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x10B6++0x01
|
|
line.word 0x00 "TCD5_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10B8++0x03
|
|
line.long 0x00 "TCD5_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10BC++0x01
|
|
line.word 0x00 "TCD5_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10BE++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x10BE++0x01
|
|
line.word 0x00 "TCD5_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x10C0++0x03
|
|
line.long 0x00 "TCD6_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10C4++0x01
|
|
line.word 0x00 "TCD6_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10C6++0x01
|
|
line.word 0x00 "TCD6_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10C8++0x03
|
|
line.long 0x00 "TCD6_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10CC++0x03
|
|
line.long 0x00 "TCD6_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10D0++0x03
|
|
line.long 0x00 "TCD6_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10D4++0x01
|
|
line.word 0x00 "TCD6_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10D6++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x10D6++0x01
|
|
line.word 0x00 "TCD6_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10D8++0x03
|
|
line.long 0x00 "TCD6_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10DC++0x01
|
|
line.word 0x00 "TCD6_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10DE++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x10DE++0x01
|
|
line.word 0x00 "TCD6_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x10E0++0x03
|
|
line.long 0x00 "TCD7_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x10E4++0x01
|
|
line.word 0x00 "TCD7_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x10E6++0x01
|
|
line.word 0x00 "TCD7_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10E8++0x03
|
|
line.long 0x00 "TCD7_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x10EC++0x03
|
|
line.long 0x00 "TCD7_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x10F0++0x03
|
|
line.long 0x00 "TCD7_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x10F4++0x01
|
|
line.word 0x00 "TCD7_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x10F6++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x10F6++0x01
|
|
line.word 0x00 "TCD7_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x10F8++0x03
|
|
line.long 0x00 "TCD7_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x10FC++0x01
|
|
line.word 0x00 "TCD7_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x10FE++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x10FE++0x01
|
|
line.word 0x00 "TCD7_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1100++0x03
|
|
line.long 0x00 "TCD8_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1104++0x01
|
|
line.word 0x00 "TCD8_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1106++0x01
|
|
line.word 0x00 "TCD8_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1108++0x03
|
|
line.long 0x00 "TCD8_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x110C++0x03
|
|
line.long 0x00 "TCD8_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1110++0x03
|
|
line.long 0x00 "TCD8_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1114++0x01
|
|
line.word 0x00 "TCD8_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1116++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x1116++0x01
|
|
line.word 0x00 "TCD8_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1118++0x03
|
|
line.long 0x00 "TCD8_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x111C++0x01
|
|
line.word 0x00 "TCD8_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x111E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x111E++0x01
|
|
line.word 0x00 "TCD8_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1120++0x03
|
|
line.long 0x00 "TCD9_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1124++0x01
|
|
line.word 0x00 "TCD9_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1126++0x01
|
|
line.word 0x00 "TCD9_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1128++0x03
|
|
line.long 0x00 "TCD9_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x112C++0x03
|
|
line.long 0x00 "TCD9_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1130++0x03
|
|
line.long 0x00 "TCD9_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1134++0x01
|
|
line.word 0x00 "TCD9_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1136++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x1136++0x01
|
|
line.word 0x00 "TCD9_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1138++0x03
|
|
line.long 0x00 "TCD9_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x113C++0x01
|
|
line.word 0x00 "TCD9_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x113E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x113E++0x01
|
|
line.word 0x00 "TCD9_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1140++0x03
|
|
line.long 0x00 "TCD10_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1144++0x01
|
|
line.word 0x00 "TCD10_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1146++0x01
|
|
line.word 0x00 "TCD10_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1148++0x03
|
|
line.long 0x00 "TCD10_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x114C++0x03
|
|
line.long 0x00 "TCD10_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1150++0x03
|
|
line.long 0x00 "TCD10_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1154++0x01
|
|
line.word 0x00 "TCD10_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1156++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x1156++0x01
|
|
line.word 0x00 "TCD10_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1158++0x03
|
|
line.long 0x00 "TCD10_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x115C++0x01
|
|
line.word 0x00 "TCD10_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x115E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x115E++0x01
|
|
line.word 0x00 "TCD10_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1160++0x03
|
|
line.long 0x00 "TCD11_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1164++0x01
|
|
line.word 0x00 "TCD11_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1166++0x01
|
|
line.word 0x00 "TCD11_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1168++0x03
|
|
line.long 0x00 "TCD11_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x116C++0x03
|
|
line.long 0x00 "TCD11_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1170++0x03
|
|
line.long 0x00 "TCD11_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1174++0x01
|
|
line.word 0x00 "TCD11_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1176++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x1176++0x01
|
|
line.word 0x00 "TCD11_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1178++0x03
|
|
line.long 0x00 "TCD11_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x117C++0x01
|
|
line.word 0x00 "TCD11_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x117E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x117E++0x01
|
|
line.word 0x00 "TCD11_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x1180++0x03
|
|
line.long 0x00 "TCD12_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x1184++0x01
|
|
line.word 0x00 "TCD12_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x1186++0x01
|
|
line.word 0x00 "TCD12_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x1188++0x03
|
|
line.long 0x00 "TCD12_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x118C++0x03
|
|
line.long 0x00 "TCD12_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x1190++0x03
|
|
line.long 0x00 "TCD12_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x1194++0x01
|
|
line.word 0x00 "TCD12_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x1196++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x1196++0x01
|
|
line.word 0x00 "TCD12_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x1198++0x03
|
|
line.long 0x00 "TCD12_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x119C++0x01
|
|
line.word 0x00 "TCD12_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x119E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x119E++0x01
|
|
line.word 0x00 "TCD12_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x11A0++0x03
|
|
line.long 0x00 "TCD13_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x11A4++0x01
|
|
line.word 0x00 "TCD13_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x11A6++0x01
|
|
line.word 0x00 "TCD13_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11A8++0x03
|
|
line.long 0x00 "TCD13_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11AC++0x03
|
|
line.long 0x00 "TCD13_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x11B0++0x03
|
|
line.long 0x00 "TCD13_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x11B4++0x01
|
|
line.word 0x00 "TCD13_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x11B6++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x11B6++0x01
|
|
line.word 0x00 "TCD13_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x11B8++0x03
|
|
line.long 0x00 "TCD13_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x11BC++0x01
|
|
line.word 0x00 "TCD13_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x11BE++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x11BE++0x01
|
|
line.word 0x00 "TCD13_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x11C0++0x03
|
|
line.long 0x00 "TCD14_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x11C4++0x01
|
|
line.word 0x00 "TCD14_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x11C6++0x01
|
|
line.word 0x00 "TCD14_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11C8++0x03
|
|
line.long 0x00 "TCD14_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11CC++0x03
|
|
line.long 0x00 "TCD14_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x11D0++0x03
|
|
line.long 0x00 "TCD14_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x11D4++0x01
|
|
line.word 0x00 "TCD14_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x11D6++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x11D6++0x01
|
|
line.word 0x00 "TCD14_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x11D8++0x03
|
|
line.long 0x00 "TCD14_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x11DC++0x01
|
|
line.word 0x00 "TCD14_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x11DE++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x11DE++0x01
|
|
line.word 0x00 "TCD14_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
group.long 0x11E0++0x03
|
|
line.long 0x00 "TCD15_SADDR,TCD Source Address"
|
|
hexmask.long 0x00 0.--31. 1. "SADDR,Source Address"
|
|
group.word 0x11E4++0x01
|
|
line.word 0x00 "TCD15_SOFF,TCD Signed Source Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "SOFF,Source address signed offset"
|
|
group.word 0x11E6++0x01
|
|
line.word 0x00 "TCD15_ATTR,TCD Transfer Attributes"
|
|
bitfld.word 0x00 11.--15. "SMOD,Source Address Modulo" "0: Source address modulo feature is disabled,?..."
|
|
bitfld.word 0x00 8.--10. "SSIZE,Source data transfer size" "0: 8-bit,1: 16-bit,2: 32-bit,?..."
|
|
newline
|
|
bitfld.word 0x00 3.--7. "DMOD,Destination Address Modulo" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--2. "DSIZE,Destination data transfer size" "0,1,2,3,4,5,6,7"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFYES,TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long.tbyte 0x00 10.--29. 1. "MLOFF,If SMLOE or DMLOE is set this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes"
|
|
hexmask.long.word 0x00 0.--9. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLOFFNO,TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled)"
|
|
bitfld.long 0x00 31. "SMLOE,Source Minor Loop Offset Enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the SADDR"
|
|
bitfld.long 0x00 30. "DMLOE,Destination Minor Loop Offset enable" "0: The minor loop offset is not applied to the..,1: The minor loop offset is applied to the DADDR"
|
|
newline
|
|
hexmask.long 0x00 0.--29. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11E8++0x03
|
|
line.long 0x00 "TCD15_NBYTES_MLNO,TCD Minor Byte Count (Minor Loop Mapping Disabled)"
|
|
hexmask.long 0x00 0.--31. 1. "NBYTES,Minor Byte Transfer Count"
|
|
group.long 0x11EC++0x03
|
|
line.long 0x00 "TCD15_SLAST,TCD Last Source Address Adjustment"
|
|
hexmask.long 0x00 0.--31. 1. "SLAST,Last Source Address Adjustment"
|
|
group.long 0x11F0++0x03
|
|
line.long 0x00 "TCD15_DADDR,TCD Destination Address"
|
|
hexmask.long 0x00 0.--31. 1. "DADDR,Destination Address"
|
|
group.word 0x11F4++0x01
|
|
line.word 0x00 "TCD15_DOFF,TCD Signed Destination Address Offset"
|
|
hexmask.word 0x00 0.--15. 1. "DOFF,Destination Address Signed Offset"
|
|
group.word 0x11F6++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKYES,TCD Current Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Minor Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "CITER_LE,Current Major Iteration Count"
|
|
group.word 0x11F6++0x01
|
|
line.word 0x00 "TCD15_CITER_ELINKNO,TCD Current Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enable channel-to-channel linking on minor-loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "CITER,Current Major Iteration Count"
|
|
group.long 0x11F8++0x03
|
|
line.long 0x00 "TCD15_DLASTSGA,TCD Last Destination Address Adjustment/Scatter Gather Address"
|
|
hexmask.long 0x00 0.--31. 1. "DLASTSGA,DLASTSGA"
|
|
group.word 0x11FC++0x01
|
|
line.word 0x00 "TCD15_CSR,TCD Control and Status"
|
|
bitfld.word 0x00 14.--15. "BWC,Bandwidth Control" "0: No eDMA engine stalls,?,2: eDMA engine stalls for 4 cycles after each R/W,3: eDMA engine stalls for 8 cycles after each R/W"
|
|
bitfld.word 0x00 8.--11. "MAJORLINKCH,Major Loop Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.word 0x00 7. "DONE,Channel Done" "0,1"
|
|
bitfld.word 0x00 6. "ACTIVE,Channel Active" "0,1"
|
|
newline
|
|
bitfld.word 0x00 5. "MAJORELINK,Enable channel-to-channel linking on major loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 4. "ESG,Enable Scatter/Gather Processing" "0: The current channel's TCD is normal format,1: The current channel's TCD specifies a scatter.."
|
|
newline
|
|
bitfld.word 0x00 3. "DREQ,Disable Request" "0,1"
|
|
bitfld.word 0x00 2. "INTHALF,Enable an interrupt when major counter is half complete" "0: The half-point interrupt is disabled,1: The half-point interrupt is enabled"
|
|
newline
|
|
bitfld.word 0x00 1. "INTMAJOR,Enable an interrupt when major iteration count completes" "0: The end-of-major loop interrupt is disabled,1: The end-of-major loop interrupt is enabled"
|
|
bitfld.word 0x00 0. "START,Channel Start" "0: The channel is not explicitly started,1: The channel is explicitly started via a.."
|
|
group.word 0x11FE++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKYES,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Enabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
bitfld.word 0x00 9.--12. "LINKCH,Link Channel Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.word 0x00 0.--8. 1. "BITER,Starting major iteration count"
|
|
group.word 0x11FE++0x01
|
|
line.word 0x00 "TCD15_BITER_ELINKNO,TCD Beginning Minor Loop Link Major Loop Count (Channel Linking Disabled)"
|
|
bitfld.word 0x00 15. "ELINK,Enables channel-to-channel linking on minor loop complete" "0: The channel-to-channel linking is disabled,1: The channel-to-channel linking is enabled"
|
|
hexmask.word 0x00 0.--14. 1. "BITER,Starting Major Iteration Count"
|
|
endif
|
|
tree.end
|
|
tree "MPU (Memory protection unit)"
|
|
base ad:0x4000D000
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CESR,Control/Error Status Register"
|
|
bitfld.long 0x00 31. "SPERR0,Slave Port 0 Error" "0: No error has occurred for slave port 0,1: An error has occurred for slave port 0"
|
|
bitfld.long 0x00 30. "SPERR1,Slave Port 1 Error" "0: No error has occurred for slave port 1,1: An error has occurred for slave port 1"
|
|
newline
|
|
rbitfld.long 0x00 16.--19. "HRL,Hardware Revision Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. "NSP,Number Of Slave Ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "NRGD,Number Of Region Descriptors" "0: 8 region descriptors,1: 12 region descriptors,2: 16 region descriptors,?..."
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: MPU is disabled,1: MPU is enabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CESR,Control/Error Status Register"
|
|
bitfld.long 0x00 31. "SPERR0,Slave Port 0 Error" "0: No error has occurred for slave port 0,1: An error has occurred for slave port 0"
|
|
bitfld.long 0x00 30. "SPERR1,Slave Port 1 Error" "0: No error has occurred for slave port 1,1: An error has occurred for slave port 1"
|
|
newline
|
|
bitfld.long 0x00 29. "SPERR2,Slave Port 2 Error" "0: No error has occurred for slave port 2,1: An error has occurred for slave port 2"
|
|
bitfld.long 0x00 28. "SPERR3,Slave Port 3 Error" "0: No error has occurred for slave port 3,1: An error has occurred for slave port 3"
|
|
newline
|
|
bitfld.long 0x00 27. "SPERR4,Slave Port 4 Error" "0: No error has occurred for slave port 4,1: An error has occurred for slave port 4"
|
|
rbitfld.long 0x00 16.--19. "HRL,Hardware Revision Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 12.--15. "NSP,Number Of Slave Ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 8.--11. "NRGD,Number Of Region Descriptors" "0: 8 region descriptors,1: 12 region descriptors,2: 16 region descriptors,?..."
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: MPU is disabled,1: MPU is enabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CESR,Control/Error Status Register"
|
|
bitfld.long 0x00 31. "SPERR0,Slave Port 0 Error" "0: No error has occurred for slave port 0,1: An error has occurred for slave port 0"
|
|
bitfld.long 0x00 30. "SPERR1,Slave Port 1 Error" "0: No error has occurred for slave port 1,1: An error has occurred for slave port 1"
|
|
newline
|
|
bitfld.long 0x00 29. "SPERR2,Slave Port 2 Error" "0: No error has occurred for slave port 2,1: An error has occurred for slave port 2"
|
|
bitfld.long 0x00 28. "SPERR3,Slave Port 3 Error" "0: No error has occurred for slave port 3,1: An error has occurred for slave port 3"
|
|
newline
|
|
rbitfld.long 0x00 16.--19. "HRL,Hardware Revision Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rbitfld.long 0x00 12.--15. "NSP,Number Of Slave Ports" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
rbitfld.long 0x00 8.--11. "NRGD,Number Of Region Descriptors" "0: 8 region descriptors,1: 12 region descriptors,2: 16 region descriptors,?..."
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: MPU is disabled,1: MPU is enabled"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "EAR0,Error Address Register slave port 0"
|
|
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "EDR0,Error Detail Register slave port 0"
|
|
hexmask.long.word 0x00 16.--31. 1. "EACD,Error Access Control Detail"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EPID,Error Process Identification"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "EMN,Error Master Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--3. "EATTR,Error Attributes" "0: User mode instruction access,1: User mode data access,2: Supervisor mode instruction access,3: Supervisor mode data access,?..."
|
|
newline
|
|
bitfld.long 0x00 0. "ERW,Error Read/" "0: ,1: "
|
|
rgroup.long 0x18++0x03
|
|
line.long 0x00 "EAR1,Error Address Register slave port 1"
|
|
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "EDR1,Error Detail Register slave port 1"
|
|
hexmask.long.word 0x00 16.--31. 1. "EACD,Error Access Control Detail"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EPID,Error Process Identification"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "EMN,Error Master Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--3. "EATTR,Error Attributes" "0: User mode instruction access,1: User mode data access,2: Supervisor mode instruction access,3: Supervisor mode data access,?..."
|
|
newline
|
|
bitfld.long 0x00 0. "ERW,Error Read/" "0: ,1: "
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
rgroup.long 0x20++0x03
|
|
line.long 0x00 "EAR2,Error Address Register slave port 2"
|
|
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "EDR2,Error Detail Register slave port 2"
|
|
hexmask.long.word 0x00 16.--31. 1. "EACD,Error Access Control Detail"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EPID,Error Process Identification"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "EMN,Error Master Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--3. "EATTR,Error Attributes" "0: User mode instruction access,1: User mode data access,2: Supervisor mode instruction access,3: Supervisor mode data access,?..."
|
|
newline
|
|
bitfld.long 0x00 0. "ERW,Error Read/" "0: ,1: "
|
|
rgroup.long 0x28++0x03
|
|
line.long 0x00 "EAR3,Error Address Register slave port 3"
|
|
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
|
|
rgroup.long 0x2C++0x03
|
|
line.long 0x00 "EDR3,Error Detail Register slave port 3"
|
|
hexmask.long.word 0x00 16.--31. 1. "EACD,Error Access Control Detail"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EPID,Error Process Identification"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "EMN,Error Master Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--3. "EATTR,Error Attributes" "0: User mode instruction access,1: User mode data access,2: Supervisor mode instruction access,3: Supervisor mode data access,?..."
|
|
newline
|
|
bitfld.long 0x00 0. "ERW,Error Read/" "0: ,1: "
|
|
endif
|
|
sif cpuis("S32K148")
|
|
rgroup.long 0x30++0x03
|
|
line.long 0x00 "EAR4,Error Address Register slave port 4"
|
|
hexmask.long 0x00 0.--31. 1. "EADDR,Error Address"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "EDR4,Error Detail Register slave port 4"
|
|
hexmask.long.word 0x00 16.--31. 1. "EACD,Error Access Control Detail"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EPID,Error Process Identification"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "EMN,Error Master Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--3. "EATTR,Error Attributes" "0: User mode instruction access,1: User mode data access,2: Supervisor mode instruction access,3: Supervisor mode data access,?..."
|
|
newline
|
|
bitfld.long 0x00 0. "ERW,Error Read/" "0: ,1: "
|
|
endif
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "RGD0_WORD0,Region Descriptor 0 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "RGD0_WORD1,Region Descriptor 0 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "RGD0_WORD2,Region Descriptor 0 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "RGD0_WORD2,Region Descriptor 0 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "RGD0_WORD3,Region Descriptor 0 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "RGD1_WORD0,Region Descriptor 1 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "RGD1_WORD1,Region Descriptor 1 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "RGD1_WORD2,Region Descriptor 1 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "RGD1_WORD2,Region Descriptor 1 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "RGD1_WORD3,Region Descriptor 1 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x420++0x03
|
|
line.long 0x00 "RGD2_WORD0,Region Descriptor 2 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x424++0x03
|
|
line.long 0x00 "RGD2_WORD1,Region Descriptor 2 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "RGD2_WORD2,Region Descriptor 2 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x428++0x03
|
|
line.long 0x00 "RGD2_WORD2,Region Descriptor 2 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "RGD2_WORD3,Region Descriptor 2 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x430++0x03
|
|
line.long 0x00 "RGD3_WORD0,Region Descriptor 3 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x434++0x03
|
|
line.long 0x00 "RGD3_WORD1,Region Descriptor 3 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "RGD3_WORD2,Region Descriptor 3 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x438++0x03
|
|
line.long 0x00 "RGD3_WORD2,Region Descriptor 3 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x43C++0x03
|
|
line.long 0x00 "RGD3_WORD3,Region Descriptor 3 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x440++0x03
|
|
line.long 0x00 "RGD4_WORD0,Region Descriptor 4 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x444++0x03
|
|
line.long 0x00 "RGD4_WORD1,Region Descriptor 4 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "RGD4_WORD2,Region Descriptor 4 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x448++0x03
|
|
line.long 0x00 "RGD4_WORD2,Region Descriptor 4 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x44C++0x03
|
|
line.long 0x00 "RGD4_WORD3,Region Descriptor 4 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x450++0x03
|
|
line.long 0x00 "RGD5_WORD0,Region Descriptor 5 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x454++0x03
|
|
line.long 0x00 "RGD5_WORD1,Region Descriptor 5 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "RGD5_WORD2,Region Descriptor 5 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x458++0x03
|
|
line.long 0x00 "RGD5_WORD2,Region Descriptor 5 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x45C++0x03
|
|
line.long 0x00 "RGD5_WORD3,Region Descriptor 5 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x460++0x03
|
|
line.long 0x00 "RGD6_WORD0,Region Descriptor 6 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x464++0x03
|
|
line.long 0x00 "RGD6_WORD1,Region Descriptor 6 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "RGD6_WORD2,Region Descriptor 6 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x468++0x03
|
|
line.long 0x00 "RGD6_WORD2,Region Descriptor 6 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x46C++0x03
|
|
line.long 0x00 "RGD6_WORD3,Region Descriptor 6 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x470++0x03
|
|
line.long 0x00 "RGD7_WORD0,Region Descriptor 7 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x474++0x03
|
|
line.long 0x00 "RGD7_WORD1,Region Descriptor 7 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "RGD7_WORD2,Region Descriptor 7 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x478++0x03
|
|
line.long 0x00 "RGD7_WORD2,Region Descriptor 7 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
group.long 0x47C++0x03
|
|
line.long 0x00 "RGD7_WORD3,Region Descriptor 7 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
sif cpuis("S32K148")
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "RGD8_WORD0,Region Descriptor 8 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x484++0x03
|
|
line.long 0x00 "RGD8_WORD1,Region Descriptor 8 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "RGD8_WORD2,Region Descriptor 8 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
group.long 0x48C++0x03
|
|
line.long 0x00 "RGD8_WORD3,Region Descriptor 8 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x490++0x03
|
|
line.long 0x00 "RGD9_WORD0,Region Descriptor 9 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x494++0x03
|
|
line.long 0x00 "RGD9_WORD1,Region Descriptor 9 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x498++0x03
|
|
line.long 0x00 "RGD9_WORD2,Region Descriptor 9 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
group.long 0x49C++0x03
|
|
line.long 0x00 "RGD9_WORD3,Region Descriptor 9 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x4A0++0x03
|
|
line.long 0x00 "RGD10_WORD0,Region Descriptor 10 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x4A4++0x03
|
|
line.long 0x00 "RGD10_WORD1,Region Descriptor 10 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x4A8++0x03
|
|
line.long 0x00 "RGD10_WORD2,Region Descriptor 10 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4AC++0x03
|
|
line.long 0x00 "RGD10_WORD3,Region Descriptor 10 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x4B0++0x03
|
|
line.long 0x00 "RGD11_WORD0,Region Descriptor 11 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x4B4++0x03
|
|
line.long 0x00 "RGD11_WORD1,Region Descriptor 11 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x4B8++0x03
|
|
line.long 0x00 "RGD11_WORD2,Region Descriptor 11 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4BC++0x03
|
|
line.long 0x00 "RGD11_WORD3,Region Descriptor 11 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x4C0++0x03
|
|
line.long 0x00 "RGD12_WORD0,Region Descriptor 12 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x4C4++0x03
|
|
line.long 0x00 "RGD12_WORD1,Region Descriptor 12 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x4C8++0x03
|
|
line.long 0x00 "RGD12_WORD2,Region Descriptor 12 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4CC++0x03
|
|
line.long 0x00 "RGD12_WORD3,Region Descriptor 12 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x4D0++0x03
|
|
line.long 0x00 "RGD13_WORD0,Region Descriptor 13 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x4D4++0x03
|
|
line.long 0x00 "RGD13_WORD1,Region Descriptor 13 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x4D8++0x03
|
|
line.long 0x00 "RGD13_WORD2,Region Descriptor 13 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4DC++0x03
|
|
line.long 0x00 "RGD13_WORD3,Region Descriptor 13 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x4E0++0x03
|
|
line.long 0x00 "RGD14_WORD0,Region Descriptor 14 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x4E4++0x03
|
|
line.long 0x00 "RGD14_WORD1,Region Descriptor 14 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x4E8++0x03
|
|
line.long 0x00 "RGD14_WORD2,Region Descriptor 14 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4EC++0x03
|
|
line.long 0x00 "RGD14_WORD3,Region Descriptor 14 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
group.long 0x4F0++0x03
|
|
line.long 0x00 "RGD15_WORD0,Region Descriptor 15 Word 0"
|
|
hexmask.long 0x00 5.--31. 1. "SRTADDR,Start Address"
|
|
group.long 0x4F4++0x03
|
|
line.long 0x00 "RGD15_WORD1,Region Descriptor 15 Word 1"
|
|
hexmask.long 0x00 5.--31. 1. "ENDADDR,End Address"
|
|
group.long 0x4F8++0x03
|
|
line.long 0x00 "RGD15_WORD2,Region Descriptor 15 Word 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
group.long 0x4FC++0x03
|
|
line.long 0x00 "RGD15_WORD3,Region Descriptor 15 Word 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PID,Process Identifier"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIDMASK,Process Identifier Mask"
|
|
newline
|
|
bitfld.long 0x00 0. "VLD,Valid" "0: Region descriptor is invalid,1: Region descriptor is valid"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x800++0x03
|
|
line.long 0x00 "RGDAAC0,Region Descriptor Alternate Access Control 0"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x04 )
|
|
group.long ($2+0x800)++0x03
|
|
line.long 0x00 "RGDAAC$1,Region Descriptor Alternate Access Control $1"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x804++0x03
|
|
line.long 0x00 "RGDAAC1,Region Descriptor Alternate Access Control 1"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x808++0x03
|
|
line.long 0x00 "RGDAAC2,Region Descriptor Alternate Access Control 2"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
repeat 2. (strings "2" "3" )(list 0x00 0x04 )
|
|
group.long ($2+0x808)++0x03
|
|
line.long 0x00 "RGDAAC$1,Region Descriptor Alternate Access Control $1"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x80C++0x03
|
|
line.long 0x00 "RGDAAC3,Region Descriptor Alternate Access Control 3"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x810++0x03
|
|
line.long 0x00 "RGDAAC4,Region Descriptor Alternate Access Control 4"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "4" "5" )(list 0x00 0x04 )
|
|
group.long ($2+0x810)++0x03
|
|
line.long 0x00 "RGDAAC$1,Region Descriptor Alternate Access Control $1"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x814++0x03
|
|
line.long 0x00 "RGDAAC5,Region Descriptor Alternate Access Control 5"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x818++0x03
|
|
line.long 0x00 "RGDAAC6,Region Descriptor Alternate Access Control 6"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
repeat 2. (strings "6" "7" )(list 0x00 0x04 )
|
|
group.long ($2+0x818)++0x03
|
|
line.long 0x00 "RGDAAC$1,Region Descriptor Alternate Access Control $1"
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 9. (strings "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 )
|
|
group.long ($2+0x81C)++0x03
|
|
line.long 0x00 "RGDAAC$1,Region Descriptor Alternate Access Control $1"
|
|
sif cpuis("S32K148")
|
|
bitfld.long 0x00 31. "M7RE,Bus Master 7 Read Enable" "0: Bus master 7 reads terminate with an access..,1: Bus master 7 reads allowed"
|
|
bitfld.long 0x00 30. "M7WE,Bus Master 7 Write Enable" "0: Bus master 7 writes terminate with an access..,1: Bus master 7 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 29. "M6RE,Bus Master 6 Read Enable" "0: Bus master 6 reads terminate with an access..,1: Bus master 6 reads allowed"
|
|
bitfld.long 0x00 28. "M6WE,Bus Master 6 Write Enable" "0: Bus master 6 writes terminate with an access..,1: Bus master 6 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 27. "M5RE,Bus Master 5 Read Enable" "0: Bus master 5 reads terminate with an access..,1: Bus master 5 reads allowed"
|
|
bitfld.long 0x00 26. "M5WE,Bus Master 5 Write Enable" "0: Bus master 5 writes terminate with an access..,1: Bus master 5 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 25. "M4RE,Bus Master 4 Read Enable" "0: Bus master 4 reads terminate with an access..,1: Bus master 4 reads allowed"
|
|
bitfld.long 0x00 24. "M4WE,Bus Master 4 Write Enable" "0: Bus master 4 writes terminate with an access..,1: Bus master 4 writes allowed"
|
|
newline
|
|
bitfld.long 0x00 21.--22. "M3SM,Bus Master 3 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M3UM"
|
|
bitfld.long 0x00 18.--20. "M3UM,Bus Master 3 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15.--16. "M2SM,Bus Master 2 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M2UM"
|
|
bitfld.long 0x00 12.--14. "M2UM,Bus Master 2 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 11. "M1PE,Bus Master 1 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
bitfld.long 0x00 9.--10. "M1SM,Bus Master 1 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M1UM"
|
|
newline
|
|
bitfld.long 0x00 6.--8. "M1UM,Bus Master 1 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 5. "M0PE,Bus Master 0 Process Identifier Enable" "0: Do not include the process identifier in the..,1: Include the process identifier and mask.."
|
|
newline
|
|
bitfld.long 0x00 3.--4. "M0SM,Bus Master 0 Supervisor Mode Access Control" "0: r/w/x read write and execute allowed,1: r/x read and execute allowed but no,2: r/w read and write allowed but no execute,3: Same as User mode defined in M0UM"
|
|
bitfld.long 0x00 0.--2. "M0UM,Bus Master 0 User Mode Access Control" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
tree "ERM"
|
|
base ad:0x40018000
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,ERM Configuration Register 0"
|
|
bitfld.long 0x00 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.."
|
|
bitfld.long 0x00 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.."
|
|
newline
|
|
bitfld.long 0x00 27. "ESCIE1,ESCIE1" "0: Interrupt notification of Memory 1 single-bit..,1: Interrupt notification of Memory 1 single-bit.."
|
|
bitfld.long 0x00 26. "ENCIE1,ENCIE1" "0: Interrupt notification of Memory 1..,1: Interrupt notification of Memory 1.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CR0,ERM Configuration Register 0"
|
|
bitfld.long 0x00 31. "ESCIE0,ESCIE0" "0: Interrupt notification of Memory 0 single-bit..,1: Interrupt notification of Memory 0 single-bit.."
|
|
bitfld.long 0x00 30. "ENCIE0,ENCIE0" "0: Interrupt notification of Memory 0..,1: Interrupt notification of Memory 0.."
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR0,ERM Status Register 0"
|
|
bitfld.long 0x00 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0.."
|
|
bitfld.long 0x00 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0.."
|
|
newline
|
|
bitfld.long 0x00 27. "SBC1,SBC1" "0: No single-bit correction event on Memory 1..,1: Single-bit correction event on Memory 1.."
|
|
bitfld.long 0x00 26. "NCE1,NCE1" "0: No non-correctable error event on Memory 1..,1: Non-correctable error event on Memory 1.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SR0,ERM Status Register 0"
|
|
bitfld.long 0x00 31. "SBC0,SBC0" "0: No single-bit correction event on Memory 0..,1: Single-bit correction event on Memory 0.."
|
|
bitfld.long 0x00 30. "NCE0,NCE0" "0: No non-correctable error event on Memory 0..,1: Non-correctable error event on Memory 0.."
|
|
endif
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x10 )
|
|
rgroup.long ($2+0x100)++0x03
|
|
line.long 0x00 "EAR$1,ERM Memory n Error Address Register"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
hexmask.long 0x00 0.--31. 1. "EAR,EAR"
|
|
endif
|
|
repeat.end
|
|
tree.end
|
|
tree "EIM (Error Injection Module)"
|
|
base ad:0x40019000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "EIMCR,Error Injection Module Configuration Register"
|
|
bitfld.long 0x00 0. "GEIEN,Global Error Injection Enable" "0: Disabled,1: Enabled"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EICHEN,Error Injection Channel Enable register"
|
|
bitfld.long 0x00 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
|
|
bitfld.long 0x00 30. "EICH1EN,Error Injection Channel 1 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EICHEN,Error Injection Channel Enable register"
|
|
bitfld.long 0x00 31. "EICH0EN,Error Injection Channel 0 Enable" "0: Error injection is disabled on Error..,1: Error injection is enabled on Error Injection.."
|
|
endif
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "EICHD0_WORD0,Error Injection Channel Descriptor n Word0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "CHKBIT_MASK,Checkbit Mask"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "EICHD0_WORD1,Error Injection Channel Descriptor n Word1"
|
|
hexmask.long 0x00 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "EICHD1_WORD0,Error Injection Channel Descriptor n Word0"
|
|
hexmask.long.byte 0x00 25.--31. 1. "CHKBIT_MASK,Checkbit Mask"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "EICHD1_WORD1,Error Injection Channel Descriptor n Word1"
|
|
hexmask.long 0x00 0.--31. 1. "B0_3DATA_MASK,Data Mask Bytes 0-3"
|
|
endif
|
|
tree.end
|
|
tree "FTFC"
|
|
base ad:0x40020000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "FSTAT,Flash Status Register"
|
|
bitfld.byte 0x00 7. "CCIF,Command Complete Interrupt Flag" "0,1"
|
|
bitfld.byte 0x00 6. "RDCOLERR,FTFC Read Collision Error Flag" "0: No collision error detected,1: Collision error detected"
|
|
newline
|
|
bitfld.byte 0x00 5. "ACCERR,Flash Access Error Flag" "0: No access error detected,1: Access error detected"
|
|
bitfld.byte 0x00 4. "FPVIOL,Flash Protection Violation Flag" "0: No protection violation detected,1: Protection violation detected"
|
|
newline
|
|
rbitfld.byte 0x00 0. "MGSTAT0,Memory Controller Command Completion Status Flag" "0,1"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "FCNFG,Flash Configuration Register"
|
|
bitfld.byte 0x00 7. "CCIE,Command Complete Interrupt Enable" "0: Command complete interrupt disabled,1: Command complete interrupt enabled"
|
|
bitfld.byte 0x00 6. "RDCOLLIE,Read Collision Error Interrupt Enable" "0: Read collision error interrupt disabled,1: Read collision error interrupt enabled"
|
|
newline
|
|
rbitfld.byte 0x00 5. "ERSAREQ,Erase All Request" "0: No request or request complete,?..."
|
|
bitfld.byte 0x00 4. "ERSSUSP,Erase Suspend" "0: No suspend requested,1: Suspend the current Erase Flash Sector.."
|
|
newline
|
|
rbitfld.byte 0x00 1. "RAMRDY,RAM Ready" "0,1"
|
|
rbitfld.byte 0x00 0. "EEERDY,EEERDY" "0,1"
|
|
rgroup.byte 0x02++0x00
|
|
line.byte 0x00 "FSEC,Flash Security Register"
|
|
bitfld.byte 0x00 6.--7. "KEYEN,Backdoor Key Security Enable" "0: Backdoor key access disabled,1: Backdoor key access disabled (preferred KEYEN..,2: Backdoor key access enabled,3: Backdoor key access disabled"
|
|
bitfld.byte 0x00 4.--5. "MEEN,Mass Erase Enable Bits" "0: Mass erase is enabled,1: Mass erase is enabled,?,3: Mass erase is enabled"
|
|
newline
|
|
bitfld.byte 0x00 2.--3. "FSLACC,Factory Failure Analysis Access Code" "0: Factory access granted,?,?,3: Factory access granted"
|
|
bitfld.byte 0x00 0.--1. "SEC,Flash Security" "?,?,2: MCU security status is unsecure (The standard..,?..."
|
|
rgroup.byte 0x03++0x00
|
|
line.byte 0x00 "FOPT,Flash Option Register"
|
|
hexmask.byte 0x00 0.--7. 1. "OPT,Nonvolatile Option"
|
|
repeat 8. (strings "3" "2" "1" "0" "7" "6" "5" "4" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )
|
|
group.byte ($2+0x04)++0x00
|
|
line.byte 0x00 "FCCOB$1,Flash Common Command Object Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "CCOBn,CCOBn"
|
|
repeat.end
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "FCCOBB,Flash Common Command Object Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "CCOBn,CCOBn"
|
|
group.byte 0x0D++0x00
|
|
line.byte 0x00 "FCCOBA,Flash Common Command Object Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "CCOBn,CCOBn"
|
|
repeat 2. (strings "9" "8" )(list 0x0 0x1 )
|
|
group.byte ($2+0x0E)++0x00
|
|
line.byte 0x00 "FCCOB$1,Flash Common Command Object Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "CCOBn,CCOBn"
|
|
repeat.end
|
|
repeat 4. (strings "3" "2" "1" "0" )(list 0x0 0x1 0x2 0x3 )
|
|
group.byte ($2+0x10)++0x00
|
|
line.byte 0x00 "FPROT$1,Program Flash Protection Registers"
|
|
hexmask.byte 0x00 0.--7. 1. "PROT,Program Flash Region Protect"
|
|
repeat.end
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "FEPROT,EEPROM Protection Register"
|
|
hexmask.byte 0x00 0.--7. 1. "EPROT,EEPROM Region Protect"
|
|
group.byte 0x17++0x00
|
|
line.byte 0x00 "FDPROT,Data Flash Protection Register"
|
|
hexmask.byte 0x00 0.--7. 1. "DPROT,Data Flash Region Protect"
|
|
rgroup.byte 0x2C++0x00
|
|
line.byte 0x00 "FCSESTAT,Flash CSEc Status Register"
|
|
bitfld.byte 0x00 7. "IDB,Internal Debug" "0,1"
|
|
bitfld.byte 0x00 6. "EDB,External Debug" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "RIN,Random Number Generator Initialized" "0,1"
|
|
bitfld.byte 0x00 4. "BOK,Secure Boot OK" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 3. "BFN,Secure Boot Finished" "0,1"
|
|
bitfld.byte 0x00 2. "BIN,Secure Boot Initialization" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "SB,Secure Boot" "0,1"
|
|
bitfld.byte 0x00 0. "BSY,Busy" "0,1"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "FERSTAT,Flash Error Status Register"
|
|
bitfld.byte 0x00 1. "DFDIF,Double Bit Fault Detect Interrupt Flag" "0: Double bit fault not detected during a valid..,1: Double bit fault detected (or FERCNFG[FDFD].."
|
|
group.byte 0x2F++0x00
|
|
line.byte 0x00 "FERCNFG,Flash Error Configuration Register"
|
|
bitfld.byte 0x00 5. "FDFD,Force Double Bit Fault Detect" "0: FERSTAT[DFDIF] sets only if a double bit..,1: FERSTAT[DFDIF] sets during any valid flash.."
|
|
bitfld.byte 0x00 1. "DFDIE,Double Bit Fault Detect Interrupt Enable" "0: Double bit fault detect interrupt disabled,1: Double bit fault detect interrupt enabled"
|
|
tree.end
|
|
tree "DMAMUX (DMA channel multiplexor)"
|
|
base ad:0x40021000
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )
|
|
group.byte ($2+0x00)++0x00
|
|
line.byte 0x00 "CHCFG$1,Channel Configuration register"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
bitfld.byte 0x00 7. "ENBL,DMA Channel Enable" "0: DMA channel is disabled,1: DMA channel is enabled"
|
|
bitfld.byte 0x00 6. "TRIG,DMA Channel Trigger Enable" "0: Triggering is disabled,1: Triggering is enabled"
|
|
newline
|
|
bitfld.byte 0x00 0.--5. "SOURCE,DMA Channel Source (Slot)" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
repeat.end
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check)"
|
|
base ad:0x40032000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "DATA,CRC Data register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "HU,CRC High Upper Byte"
|
|
hexmask.long.byte 0x00 16.--23. 1. "HL,CRC High Lower Byte"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "LU,CRC Low Upper Byte"
|
|
hexmask.long.byte 0x00 0.--7. 1. "LL,CRC Low Lower Byte"
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DATAL,CRC_DATAL register"
|
|
hexmask.word 0x00 0.--15. 1. "DATAL,DATAL stores the lower 16 bits of the 16/32 bit CRC"
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "DATALL,CRC_DATALL register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATALL,CRCLL stores the first 8 bits of the 32 bit DATA"
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "DATALU,CRC_DATALU register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATALU,DATALL stores the second 8 bits of the 32 bit CRC"
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "DATAH,CRC_DATAH register"
|
|
hexmask.word 0x00 0.--15. 1. "DATAH,DATAH stores the high 16 bits of the 16/32 bit CRC"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "DATAHL,CRC_DATAHL register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATAHL,DATAHL stores the third 8 bits of the 32 bit CRC"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "DATAHU,CRC_DATAHU register"
|
|
hexmask.byte 0x00 0.--7. 1. "DATAHU,DATAHU stores the fourth 8 bits of the 32 bit CRC"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "GPOLY,CRC Polynomial register"
|
|
hexmask.long.word 0x00 16.--31. 1. "HIGH,High Polynominal Half-word"
|
|
hexmask.long.word 0x00 0.--15. 1. "LOW,Low Polynominal Half-word"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,CRC Control register"
|
|
bitfld.long 0x00 30.--31. "TOT,Type Of Transpose For Writes" "0: No transposition,1: Bits in bytes are transposed bytes are not..,2: Both bits in bytes and bytes are transposed,3: Only bytes are transposed no bits in a byte.."
|
|
bitfld.long 0x00 28.--29. "TOTR,Type Of Transpose For Read" "0: No transposition,1: Bits in bytes are transposed bytes are not..,2: Both bits in bytes and bytes are transposed,3: Only bytes are transposed no bits in a byte.."
|
|
newline
|
|
bitfld.long 0x00 26. "FXOR,Complement Read Of CRC Data Register" "0: No XOR on reading,1: Invert or complement the read value of the.."
|
|
bitfld.long 0x00 25. "WAS,Write CRC Data Register As Seed" "0: Writes to the CRC data register are data values,1: Writes to the CRC data register are seed values"
|
|
newline
|
|
bitfld.long 0x00 24. "TCRC,TCRC" "0: 16-bit CRC protocol,1: 32-bit CRC protocol"
|
|
tree.end
|
|
tree "LPIT0 (Low Power Periodic Interrupt Timer (LPIT))"
|
|
base ad:0x40037000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "EXT_TRIG,Number of External Trigger Inputs"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CHANNEL,Number of Timer Channels"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MCR,Module Control Register"
|
|
bitfld.long 0x00 3. "DBG_EN,Debug Enable Bit" "0: Timer channels are stopped in Debug mode,1: Timer channels continue to run in Debug mode"
|
|
bitfld.long 0x00 2. "DOZE_EN,DOZE Mode Enable Bit" "0: Timer channels are stopped in DOZE mode,1: Timer channels continue to run in DOZE mode"
|
|
newline
|
|
bitfld.long 0x00 1. "SW_RST,Software Reset Bit" "0: Timer channels and registers are not reset,1: Timer channels and registers are reset"
|
|
bitfld.long 0x00 0. "M_CEN,Module Clock Enable" "0: Peripheral clock to timers is disabled,1: Peripheral clock to timers is enabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "MSR,Module Status Register"
|
|
bitfld.long 0x00 3. "TIF3,Channel 3 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred"
|
|
bitfld.long 0x00 2. "TIF2,Channel 2 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred"
|
|
newline
|
|
bitfld.long 0x00 1. "TIF1,Channel 1 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred"
|
|
bitfld.long 0x00 0. "TIF0,Channel 0 Timer Interrupt Flag" "0: Timer has not timed out,1: Timeout has occurred"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MIER,Module Interrupt Enable Register"
|
|
bitfld.long 0x00 3. "TIE3,Channel 3 Timer Interrupt Enable" "0: Interrupt generation is disabled,1: Interrupt generation is enabled"
|
|
bitfld.long 0x00 2. "TIE2,Channel 2 Timer Interrupt Enable" "0: Interrupt generation is disabled,1: Interrupt generation is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "TIE1,Channel 1 Timer Interrupt Enable" "0: Interrupt generation is disabled,1: Interrupt generation is enabled"
|
|
bitfld.long 0x00 0. "TIE0,Channel 0 Timer Interrupt Enable" "0: Interrupt generation is disabled,1: Interrupt generation is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SETTEN,Set Timer Enable Register"
|
|
bitfld.long 0x00 3. "SET_T_EN_3,Set Timer 3 Enable" "0: No effect,1: Enables the Timer Channel 3"
|
|
bitfld.long 0x00 2. "SET_T_EN_2,Set Timer 2 Enable" "0: No Effect,1: Enables the Timer Channel 2"
|
|
newline
|
|
bitfld.long 0x00 1. "SET_T_EN_1,Set Timer 1 Enable" "0: No Effect,1: Enables the Timer Channel 1"
|
|
bitfld.long 0x00 0. "SET_T_EN_0,Set Timer 0 Enable" "0: No effect,1: Enables the Timer Channel 0"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CLRTEN,Clear Timer Enable Register"
|
|
bitfld.long 0x00 3. "CLR_T_EN_3,Clear Timer 3 Enable" "0: No Action,1: Clear T_EN bit for Timer Channel 3"
|
|
bitfld.long 0x00 2. "CLR_T_EN_2,Clear Timer 2 Enable" "0: No Action,1: Clear T_EN bit for Timer Channel 2"
|
|
newline
|
|
bitfld.long 0x00 1. "CLR_T_EN_1,Clear Timer 1 Enable" "0: No Action,1: Clear T_EN bit for Timer Channel 1"
|
|
bitfld.long 0x00 0. "CLR_T_EN_0,Clear Timer 0 Enable" "0: No action,1: Clear T_EN bit for Timer Channel 0"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "TVAL0,Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_VAL,Timer Value"
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "CVAL0,Current Timer Value"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_CUR_VAL,Current Timer Value"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TCTRL0,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. "TRG_SEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "TRG_SRC,Trigger Source" "0: Trigger source selected in external,1: Trigger source selected is the internal trigger"
|
|
newline
|
|
bitfld.long 0x00 18. "TROT,Timer Reload On Trigger" "0: Timer will not reload on selected trigger,1: Timer will reload on selected trigger"
|
|
bitfld.long 0x00 17. "TSOI,Timer Stop On Interrupt" "0: The channel timer does not stop after timeout,1: The channel timer will stop after a timeout.."
|
|
newline
|
|
bitfld.long 0x00 16. "TSOT,Timer Start On Trigger" "0: Timer starts to decrement immediately based..,1: Timer starts to decrement when rising edge on.."
|
|
bitfld.long 0x00 2.--3. "MODE,Timer Operation Mode" "0: 32-bit Periodic Counter,1: Dual 16-bit Periodic Counter,2: 32-bit Trigger Accumulator,3: 32-bit Trigger Input Capture"
|
|
newline
|
|
bitfld.long 0x00 1. "CHAIN,Chain Channel" "0: Channel Chaining is disabled,1: Channel Chaining is enabled"
|
|
bitfld.long 0x00 0. "T_EN,Timer Enable" "0: Timer Channel is disabled,1: Timer Channel is enabled"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TVAL1,Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_VAL,Timer Value"
|
|
rgroup.long 0x34++0x03
|
|
line.long 0x00 "CVAL1,Current Timer Value"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_CUR_VAL,Current Timer Value"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TCTRL1,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. "TRG_SEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "TRG_SRC,Trigger Source" "0: Trigger source selected in external,1: Trigger source selected is the internal trigger"
|
|
newline
|
|
bitfld.long 0x00 18. "TROT,Timer Reload On Trigger" "0: Timer will not reload on selected trigger,1: Timer will reload on selected trigger"
|
|
bitfld.long 0x00 17. "TSOI,Timer Stop On Interrupt" "0: The channel timer does not stop after timeout,1: The channel timer will stop after a timeout.."
|
|
newline
|
|
bitfld.long 0x00 16. "TSOT,Timer Start On Trigger" "0: Timer starts to decrement immediately based..,1: Timer starts to decrement when rising edge on.."
|
|
bitfld.long 0x00 2.--3. "MODE,Timer Operation Mode" "0: 32-bit Periodic Counter,1: Dual 16-bit Periodic Counter,2: 32-bit Trigger Accumulator,3: 32-bit Trigger Input Capture"
|
|
newline
|
|
bitfld.long 0x00 1. "CHAIN,Chain Channel" "0: Channel Chaining is disabled,1: Channel Chaining is enabled"
|
|
bitfld.long 0x00 0. "T_EN,Timer Enable" "0: Timer Channel is disabled,1: Timer Channel is enabled"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "TVAL2,Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_VAL,Timer Value"
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CVAL2,Current Timer Value"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_CUR_VAL,Current Timer Value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TCTRL2,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. "TRG_SEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "TRG_SRC,Trigger Source" "0: Trigger source selected in external,1: Trigger source selected is the internal trigger"
|
|
newline
|
|
bitfld.long 0x00 18. "TROT,Timer Reload On Trigger" "0: Timer will not reload on selected trigger,1: Timer will reload on selected trigger"
|
|
bitfld.long 0x00 17. "TSOI,Timer Stop On Interrupt" "0: The channel timer does not stop after timeout,1: The channel timer will stop after a timeout.."
|
|
newline
|
|
bitfld.long 0x00 16. "TSOT,Timer Start On Trigger" "0: Timer starts to decrement immediately based..,1: Timer starts to decrement when rising edge on.."
|
|
bitfld.long 0x00 2.--3. "MODE,Timer Operation Mode" "0: 32-bit Periodic Counter,1: Dual 16-bit Periodic Counter,2: 32-bit Trigger Accumulator,3: 32-bit Trigger Input Capture"
|
|
newline
|
|
bitfld.long 0x00 1. "CHAIN,Chain Channel" "0: Channel Chaining is disabled,1: Channel Chaining is enabled"
|
|
bitfld.long 0x00 0. "T_EN,Timer Enable" "0: Timer Channel is disabled,1: Timer Channel is enabled"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TVAL3,Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_VAL,Timer Value"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "CVAL3,Current Timer Value"
|
|
hexmask.long 0x00 0.--31. 1. "TMR_CUR_VAL,Current Timer Value"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "TCTRL3,Timer Control Register"
|
|
bitfld.long 0x00 24.--27. "TRG_SEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "TRG_SRC,Trigger Source" "0: Trigger source selected in external,1: Trigger source selected is the internal trigger"
|
|
newline
|
|
bitfld.long 0x00 18. "TROT,Timer Reload On Trigger" "0: Timer will not reload on selected trigger,1: Timer will reload on selected trigger"
|
|
bitfld.long 0x00 17. "TSOI,Timer Stop On Interrupt" "0: The channel timer does not stop after timeout,1: The channel timer will stop after a timeout.."
|
|
newline
|
|
bitfld.long 0x00 16. "TSOT,Timer Start On Trigger" "0: Timer starts to decrement immediately based..,1: Timer starts to decrement when rising edge on.."
|
|
bitfld.long 0x00 2.--3. "MODE,Timer Operation Mode" "0: 32-bit Periodic Counter,1: Dual 16-bit Periodic Counter,2: 32-bit Trigger Accumulator,3: 32-bit Trigger Input Capture"
|
|
newline
|
|
bitfld.long 0x00 1. "CHAIN,Chain Channel" "0: Channel Chaining is disabled,1: Channel Chaining is enabled"
|
|
bitfld.long 0x00 0. "T_EN,Timer Enable" "0: Timer Channel is disabled,1: Timer Channel is enabled"
|
|
tree.end
|
|
tree "RTC (Real-time Counter)"
|
|
base ad:0x4003D000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TSR,RTC Time Seconds Register"
|
|
hexmask.long 0x00 0.--31. 1. "TSR,Time Seconds Register"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TPR,RTC Time Prescaler Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TPR,Time Prescaler Register"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TAR,RTC Time Alarm Register"
|
|
hexmask.long 0x00 0.--31. 1. "TAR,Time Alarm Register"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TCR,RTC Time Compensation Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "CIC,Compensation Interval Counter"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TCV,Time Compensation Value"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "CIR,Compensation Interval Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TCR,Time Compensation Register"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24. "CPE,Clock Pin Enable" "0: Disable RTC_CLKOUT pin,1: Enable RTC_CLKOUT pin"
|
|
bitfld.long 0x00 7. "LPOS,LPO Select" "0: RTC prescaler increments using 32kHz crystal,1: RTC prescaler increments using 1kHz LPO bits.."
|
|
newline
|
|
bitfld.long 0x00 5. "CPS,Clock Pin Select" "0: The prescaler output clock (as configured by..,1: The RTC 32kHz crystal clock is output on.."
|
|
bitfld.long 0x00 3. "UM,Update Mode" "0: Registers cannot be written when locked,1: Registers can be written when locked under.."
|
|
newline
|
|
bitfld.long 0x00 2. "SUP,Supervisor Access" "0: Non-supervisor mode write accesses are not..,1: Non-supervisor mode write accesses are.."
|
|
bitfld.long 0x00 0. "SWR,Software Reset" "0: No effect,?..."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,RTC Control Register"
|
|
bitfld.long 0x00 24. "CPE,Clock Pin Enable" "0: The RTC_CLKOUT function is disabled,1: Enable RTC_CLKOUT function"
|
|
bitfld.long 0x00 9. "CLKO,Clock Output" "0: The 32 kHz clock is output to other peripherals,1: The 32 kHz clock is not output to other.."
|
|
newline
|
|
bitfld.long 0x00 7. "LPOS,LPO Select" "0: RTC prescaler increments using 32.768 kHz clock,1: RTC prescaler increments using 1 kHz LPO bits.."
|
|
bitfld.long 0x00 5. "CPS,Clock Pin Select" "0: The prescaler output clock (as configured by..,1: The RTC 32.768 kHz clock is output on.."
|
|
newline
|
|
bitfld.long 0x00 3. "UM,Update Mode" "0: Registers cannot be written when locked,1: Registers can be written when locked under.."
|
|
bitfld.long 0x00 2. "SUP,Supervisor Access" "0: Non-supervisor mode write accesses are not..,1: Non-supervisor mode write accesses are.."
|
|
newline
|
|
bitfld.long 0x00 0. "SWR,Software Reset" "0: No effect,?..."
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,RTC Status Register"
|
|
bitfld.long 0x00 4. "TCE,Time Counter Enable" "0: Time counter is disabled,1: Time counter is enabled"
|
|
rbitfld.long 0x00 2. "TAF,Time Alarm Flag" "0: Time alarm has not occurred,1: Time alarm has occurred"
|
|
newline
|
|
rbitfld.long 0x00 1. "TOF,Time Overflow Flag" "0: Time overflow has not occurred,1: Time overflow has occurred and time counter.."
|
|
rbitfld.long 0x00 0. "TIF,Time Invalid Flag" "0: Time is valid,1: Time is invalid and time counter is read as.."
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "LR,RTC Lock Register"
|
|
bitfld.long 0x00 6. "LRL,Lock Register Lock" "0: Lock Register is locked and writes are ignored,1: Lock Register is not locked and writes.."
|
|
bitfld.long 0x00 5. "SRL,Status Register Lock" "0: Status Register is locked and writes are..,1: Status Register is not locked and writes.."
|
|
newline
|
|
bitfld.long 0x00 4. "CRL,Control Register Lock" "0: Control Register is locked and writes are..,1: Control Register is not locked and writes.."
|
|
bitfld.long 0x00 3. "TCL,Time Compensation Lock" "0: Time Compensation Register is locked and..,1: Time Compensation Register is not locked and.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IER,RTC Interrupt Enable Register"
|
|
bitfld.long 0x00 16.--18. "TSIC,Timer Seconds Interrupt Configuration" "0: 1 Hz,1: 2 Hz,2: 4 Hz,3: 8 Hz,4: 16 Hz,5: 32 Hz,6: 64 Hz,7: 128 Hz"
|
|
bitfld.long 0x00 4. "TSIE,Time Seconds Interrupt Enable" "0: Seconds interrupt is disabled,1: Seconds interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TAIE,Time Alarm Interrupt Enable" "0: Time alarm flag does not generate an interrupt,1: Time alarm flag does generate an interrupt"
|
|
bitfld.long 0x00 1. "TOIE,Time Overflow Interrupt Enable" "0: Time overflow flag does not generate an..,1: Time overflow flag does generate an interrupt"
|
|
newline
|
|
bitfld.long 0x00 0. "TIIE,Time Invalid Interrupt Enable" "0: Time invalid flag does not generate an..,1: Time invalid flag does generate an interrupt"
|
|
tree.end
|
|
tree "LPTMR0 (Low Power Timer)"
|
|
base ad:0x40040000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,Low Power Timer Control Status Register"
|
|
bitfld.long 0x00 8. "TDRE,Timer DMA Request Enable" "0: Timer DMA Request disabled,1: Timer DMA Request enabled"
|
|
bitfld.long 0x00 7. "TCF,Timer Compare Flag" "0: The value of CNR is not equal to CMR and..,1: The value of CNR is equal to CMR and increments"
|
|
newline
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Timer interrupt disabled,1: Timer interrupt enabled"
|
|
bitfld.long 0x00 4.--5. "TPS,Timer Pin Select" "0: Pulse counter input 0 is selected,1: Pulse counter input 1 is selected,2: Pulse counter input 2 is selected,3: Pulse counter input 3 is selected"
|
|
newline
|
|
bitfld.long 0x00 3. "TPP,Timer Pin Polarity" "0: Pulse Counter input source is active-high and..,1: Pulse Counter input source is active-low and.."
|
|
bitfld.long 0x00 2. "TFC,Timer Free-Running Counter" "0: CNR is reset whenever TCF is set,1: CNR is reset on overflow"
|
|
newline
|
|
bitfld.long 0x00 1. "TMS,Timer Mode Select" "0: Time Counter mode,1: Pulse Counter mode"
|
|
bitfld.long 0x00 0. "TEN,Timer Enable" "0: LPTMR is disabled and internal logic is reset,1: LPTMR is enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "PSR,Low Power Timer Prescale Register"
|
|
bitfld.long 0x00 3.--6. "PRESCALE,Prescale Value" "0: Prescaler divides the prescaler clock by 2..,1: Prescaler divides the prescaler clock by 4..,2: Prescaler divides the prescaler clock by 8..,3: Prescaler divides the prescaler clock by 16..,4: Prescaler divides the prescaler clock by 32..,5: Prescaler divides the prescaler clock by 64..,6: Prescaler divides the prescaler clock by 128..,7: Prescaler divides the prescaler clock by 256..,8: Prescaler divides the prescaler clock by 512..,9: Prescaler divides the prescaler clock by 1024..,10: Prescaler divides the prescaler clock by..,11: Prescaler divides the prescaler clock by..,12: Prescaler divides the prescaler clock by..,13: Prescaler divides the prescaler clock by 16..,14: Prescaler divides the prescaler clock by 32..,15: Prescaler divides the prescaler clock by 65.."
|
|
bitfld.long 0x00 2. "PBYP,Prescaler Bypass" "0: Prescaler/glitch filter is enabled,1: Prescaler/glitch filter is bypassed"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "PCS,Prescaler Clock Select" "0: Prescaler/glitch filter clock 0 selected,1: Prescaler/glitch filter clock 1 selected,2: Prescaler/glitch filter clock 2 selected,3: Prescaler/glitch filter clock 3 selected"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CMR,Low Power Timer Compare Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COMPARE,Compare Value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CNR,Low Power Timer Counter Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNTER,Counter Value"
|
|
tree.end
|
|
tree "SIM (System Integration Module)"
|
|
base ad:0x40048000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CHIPCTL,Chip Control register"
|
|
bitfld.long 0x00 21. "SRAML_RETEN,SRAML_RETEN" "0: SRAML contents are retained across resets,1: No SRAML retention"
|
|
bitfld.long 0x00 20. "SRAMU_RETEN,SRAMU_RETEN" "0: SRAMU contents are retained across resets,1: No SRAMU retention"
|
|
newline
|
|
bitfld.long 0x00 19. "ADC_SUPPLYEN,ADC_SUPPLYEN" "0: Disable internal supply monitoring,1: Enable internal supply monitoring"
|
|
bitfld.long 0x00 16.--18. "ADC_SUPPLY,ADC_SUPPLY" "0: 5 V input VDD supply (VDD),1: 5 V input analog supply (VDDA),2: ADC Reference Supply (VREFH),3: 3.3 V Oscillator Regulator Output (VDD_3V),4: 3.3 V flash regulator output (VDD_flash_3V),5: 1.2 V core regulator output (VDD_LV),?..."
|
|
newline
|
|
bitfld.long 0x00 13. "PDB_BB_SEL,PDB back-to-back select" "0: PDB0 channel 0 back-to-back operation with..,1: Channel 0 of PDB0 and PDB1 back-to-back.."
|
|
bitfld.long 0x00 12. "TRACECLK_SEL,Debug trace clock select" "0: Core clock,1: Platform clock"
|
|
newline
|
|
bitfld.long 0x00 11. "CLKOUTEN,CLKOUT enable" "0: Clockout disable,1: Clockout enable"
|
|
bitfld.long 0x00 8.--10. "CLKOUTDIV,CLKOUT Divide Ratio" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CLKOUTSEL,CLKOUT Select" "0: SCG CLKOUT,?,2: SOSC DIV2 CLK,?,4: SIRC DIV2 CLK,5: For S32K148,6: FIRC DIV2 CLK,7: 0111,8: SPLL DIV2 CLK,9: BUS_CLK,10: LPO128K_CLK,11: For S32K148,12: LPO_CLK as selected by SIM_LPOCLKS[LPOCLKSEL],13: For S32K148,14: RTC_CLK as selected by SIM_LPOCLKS[RTCCLKSEL],15: For S32K148"
|
|
bitfld.long 0x00 0.--3. "ADC_INTERLEAVE_EN,ADC interleave channel enable" "0: Interleaving disabled,1: PTB0 to ADC0_SE4 and ADC1_SE14,2: PTB1 to ADC0_SE5 and ADC1_SE15,3: PTB1 to ADC0_SE5 and ADC1_SE15,4: PTB13 to ADC1_SE8 and ADC0_SE8,5: PTB13 to ADC1_SE8 and ADC0_SE8,6: PTB13 to ADC1_SE8 and ADC0_SE8,7: PTB13 to ADC1_SE8 and ADC0_SE8,8: PTB14 to ADC1_SE9 and ADC0_SE9,9: PTB14 to ADC1_SE9 and ADC0_SE9,10: PTB14 to ADC1_SE9 and ADC0_SE9,11: PTB14 to ADC1_SE9 and ADC0_SE9,12: PTB14 to ADC1_SE9 and ADC0_SE9,13: PTB14 to ADC1_SE9 and ADC0_SE9,14: PTB14 to ADC1_SE9 and ADC0_SE9,15: PTB14 to ADC1_SE9 and ADC0_SE9"
|
|
sif cpuis("S32K146")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FTMOPT0,FTM Option Register 0"
|
|
bitfld.long 0x00 30.--31. "FTM3CLKSEL,FTM3 External Clock Pin Select" "0: FTM3 external clock driven by TCLK0 pin,1: FTM3 external clock driven by TCLK1 pin,2: FTM3 external clock driven by TCLK2 pin,3: No clock input"
|
|
bitfld.long 0x00 28.--29. "FTM2CLKSEL,FTM2 External Clock Pin Select" "0: FTM2 external clock driven by TCLK0 pin,1: FTM2 external clock driven by TCLK1 pin,2: FTM2 external clock driven by TCLK2 pin,3: No clock input"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "FTM1CLKSEL,FTM1 External Clock Pin Select" "0: FTM1 external clock driven by TCLK0 pin,1: FTM1 external clock driven by TCLK1 pin,2: FTM1 external clock driven by TCLK2 pin,3: No clock input"
|
|
bitfld.long 0x00 24.--25. "FTM0CLKSEL,FTM0 External Clock Pin Select" "0: FTM0 external clock driven by TCLK0 pin,1: FTM0 external clock driven by TCLK1 pin,2: FTM0 external clock driven by TCLK2 pin,3: No clock input"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "FTM5CLKSEL,FTM5 External Clock Pin Select" "0: FTM5 external clock driven by TCLK0 pin,1: FTM5 external clock driven by TCLK1 pin,2: FTM5 external clock driven by TCLK2 pin,3: No clock input"
|
|
bitfld.long 0x00 16.--17. "FTM4CLKSEL,FTM4 External Clock Pin Select" "0: FTM4 external clock driven by TCLK0 pin,1: FTM4 external clock driven by TCLK1 pin,2: FTM4 external clock driven by TCLK2 pin,3: No clock input"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "FTM3FLTxSEL,FTM3 Fault X Select" "0: FTM3_FLTx pin,1: TRGMUX_FTM3 out,?..."
|
|
bitfld.long 0x00 8.--10. "FTM2FLTxSEL,FTM2 Fault X Select" "0: FTM2_FLTx pin,1: TRGMUX_FTM2 out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "FTM1FLTxSEL,FTM1 Fault X Select" "0: FTM1_FLTx pin,1: TRGMUX_FTM1 out,?..."
|
|
bitfld.long 0x00 0.--2. "FTM0FLTxSEL,FTM0 Fault X Select" "0: FTM0_FLTx pin,1: TRGMUX_FTM0 out,?..."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FTMOPT0,FTM Option Register 0"
|
|
bitfld.long 0x00 30.--31. "FTM3CLKSEL,FTM3 External Clock Pin Select" "0: FTM3 external clock driven by TCLK0 pin,1: FTM3 external clock driven by TCLK1 pin,2: FTM3 external clock driven by TCLK2 pin,3: No clock input"
|
|
bitfld.long 0x00 28.--29. "FTM2CLKSEL,FTM2 External Clock Pin Select" "0: FTM2 external clock driven by TCLK0 pin,1: FTM2 external clock driven by TCLK1 pin,2: FTM2 external clock driven by TCLK2 pin,3: No clock input"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "FTM1CLKSEL,FTM1 External Clock Pin Select" "0: FTM1 external clock driven by TCLK0 pin,1: FTM1 external clock driven by TCLK1 pin,2: FTM1 external clock driven by TCLK2 pin,3: No clock input"
|
|
bitfld.long 0x00 24.--25. "FTM0CLKSEL,FTM0 External Clock Pin Select" "0: FTM0 external clock driven by TCLK0 pin,1: FTM0 external clock driven by TCLK1 pin,2: FTM0 external clock driven by TCLK2 pin,3: No clock input"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "FTM3FLTxSEL,FTM3 Fault X Select" "0: FTM3_FLTx pin,1: TRGMUX_FTM3 out,?..."
|
|
bitfld.long 0x00 8.--10. "FTM2FLTxSEL,FTM2 Fault X Select" "0: FTM2_FLTx pin,1: TRGMUX_FTM2 out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "FTM1FLTxSEL,FTM1 Fault X Select" "0: FTM1_FLTx pin,1: TRGMUX_FTM1 out,?..."
|
|
bitfld.long 0x00 0.--2. "FTM0FLTxSEL,FTM0 Fault X Select" "0: FTM0_FLTx pin,1: TRGMUX_FTM0 out,?..."
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FTMOPT0,FTM Option Register 0"
|
|
bitfld.long 0x00 30.--31. "FTM3CLKSEL,FTM3 External Clock Pin Select" "0: FTM3 external clock driven by TCLK0 pin,1: FTM3 external clock driven by TCLK1 pin,2: FTM3 external clock driven by TCLK2 pin,3: No clock input"
|
|
bitfld.long 0x00 28.--29. "FTM2CLKSEL,FTM2 External Clock Pin Select" "0: FTM2 external clock driven by TCLK0 pin,1: FTM2 external clock driven by TCLK1 pin,2: FTM2 external clock driven by TCLK2 pin,3: No clock input"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "FTM1CLKSEL,FTM1 External Clock Pin Select" "0: FTM1 external clock driven by TCLK0 pin,1: FTM1 external clock driven by TCLK1 pin,2: FTM1 external clock driven by TCLK2 pin,3: No clock input"
|
|
bitfld.long 0x00 24.--25. "FTM0CLKSEL,FTM0 External Clock Pin Select" "0: FTM0 external clock driven by TCLK0 pin,1: FTM0 external clock driven by TCLK1 pin,2: FTM0 external clock driven by TCLK2 pin,3: No clock input"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "FTM7CLKSEL,FTM7 External Clock Pin Select" "0: FTM7 external clock driven by TCLK0 pin,1: FTM7 external clock driven by TCLK1 pin,2: FTM7 external clock driven by TCLK2 pin,3: No clock input"
|
|
bitfld.long 0x00 20.--21. "FTM6CLKSEL,FTM6 External Clock Pin Select" "0: FTM6 external clock driven by TCLK0 pin,1: FTM6 external clock driven by TCLK1 pin,2: FTM6 external clock driven by TCLK2 pin,3: No clock input"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "FTM5CLKSEL,FTM5 External Clock Pin Select" "0: FTM5 external clock driven by TCLK0 pin,1: FTM5 external clock driven by TCLK1 pin,2: FTM5 external clock driven by TCLK2 pin,3: No clock input"
|
|
bitfld.long 0x00 16.--17. "FTM4CLKSEL,FTM4 External Clock Pin Select" "0: FTM4 external clock driven by TCLK0 pin,1: FTM4 external clock driven by TCLK1 pin,2: FTM4 external clock driven by TCLK2 pin,3: No clock input"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "FTM3FLTxSEL,FTM3 Fault X Select" "0: FTM3_FLTx pin,1: TRGMUX_FTM3 out,?..."
|
|
bitfld.long 0x00 8.--10. "FTM2FLTxSEL,FTM2 Fault X Select" "0: FTM2_FLTx pin,1: TRGMUX_FTM2 out,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--6. "FTM1FLTxSEL,FTM1 Fault X Select" "0: FTM1_FLTx pin,1: TRGMUX_FTM1 out,?..."
|
|
bitfld.long 0x00 0.--2. "FTM0FLTxSEL,FTM0 Fault X Select" "0: FTM0_FLTx pin,1: TRGMUX_FTM0 out,?..."
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "LPOCLKS,LPO Clock Select Register"
|
|
bitfld.long 0x00 4.--5. "RTCCLKSEL,32 kHz clock source select" "0: SOSCDIV1_CLK,1: 32 kHz LPO_CLK,2: RTC_CLKIN clock,3: FIRCDIV1_CLK"
|
|
bitfld.long 0x00 2.--3. "LPOCLKSEL,LPO clock source select" "0: 128 kHz LPO_CLK,1: No clock,2: 32 kHz LPO_CLK which is derived from the 128..,3: 1 kHz LPO_CLK which is derived from the 128.."
|
|
newline
|
|
bitfld.long 0x00 1. "LPO32KCLKEN,32 kHz LPO_CLK enable" "0: Disable 32 kHz LPO_CLK output,1: Enable 32 kHz LPO_CLK output"
|
|
bitfld.long 0x00 0. "LPO1KCLKEN,1 kHz LPO_CLK enable" "0: Disable 1 kHz LPO_CLK output,1: Enable 1 kHz LPO_CLK output"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "ADCOPT,ADC Options Register"
|
|
bitfld.long 0x00 12.--13. "ADC1PRETRGSEL,ADC1 pretrigger source select" "0: PDB pretrigger (default),1: TRGMUX pretrigger,2: Software pretrigger,?..."
|
|
bitfld.long 0x00 9.--11. "ADC1SWPRETRG,ADC1 software pretrigger sources" "0: Software pretrigger disabled,1: Reserved (do not use),2: Reserved (do not use),3: Reserved (do not use),4: Software pretrigger 0,5: Software pretrigger 1,6: Software pretrigger 2,7: Software pretrigger 3"
|
|
newline
|
|
bitfld.long 0x00 8. "ADC1TRGSEL,ADC1 trigger source select" "0: PDB output,1: TRGMUX output"
|
|
bitfld.long 0x00 4.--5. "ADC0PRETRGSEL,ADC0 pretrigger source select" "0: PDB pretrigger (default),1: TRGMUX pretrigger,2: Software pretrigger,?..."
|
|
newline
|
|
bitfld.long 0x00 1.--3. "ADC0SWPRETRG,ADC0 software pretrigger sources" "0: Software pretrigger disabled,1: Reserved (do not use),2: Reserved (do not use),3: Reserved (do not use),4: Software pretrigger 0,5: Software pretrigger 1,6: Software pretrigger 2,7: Software pretrigger 3"
|
|
bitfld.long 0x00 0. "ADC0TRGSEL,ADC0 trigger source select" "0: PDB output,1: TRGMUX output"
|
|
sif cpuis("S32K148")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FTMOPT1,FTM Option Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "FTM3_OUTSEL,FTM3 channel modulation select with FTM2_CH1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FTM0_OUTSEL,FTM0 channel modulation select with FTM1_CH1"
|
|
newline
|
|
bitfld.long 0x00 15. "FTMGLDOK,FTM global load enable" "0: FTM Global load mechanism disabled,1: FTM Global load mechanism enabled"
|
|
bitfld.long 0x00 14. "FTM7SYNCBIT,FTM7 Sync Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "FTM6SYNCBIT,FTM6 Sync Bit" "0,1"
|
|
bitfld.long 0x00 12. "FTM5SYNCBIT,FTM5 Sync Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "FTM4SYNCBIT,FTM4 Sync Bit" "0,1"
|
|
bitfld.long 0x00 8. "FTM2CH1SEL,FTM2 CH1 Select" "0: FTM2_CH1 input,1: exclusive OR of FTM2_CH0 FTM2_CH1 and FTM1_CH1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "FTM2CH0SEL,FTM2 CH0 Select" "0: FTM2_CH0 input,1: CMP0 output,?..."
|
|
bitfld.long 0x00 4.--5. "FTM1CH0SEL,FTM1 CH0 Select" "0: FTM1_CH0 input,1: CMP0 output,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FTM3SYNCBIT,FTM3 Sync Bit" "0,1"
|
|
bitfld.long 0x00 2. "FTM2SYNCBIT,FTM2 Sync Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "FTM1SYNCBIT,FTM1 Sync Bit" "0,1"
|
|
bitfld.long 0x00 0. "FTM0SYNCBIT,FTM0 Sync Bit" "0,1"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FTMOPT1,FTM Option Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "FTM3_OUTSEL,FTM3 channel modulation select with FTM2_CH1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FTM0_OUTSEL,FTM0 channel modulation select with FTM1_CH1"
|
|
newline
|
|
bitfld.long 0x00 15. "FTMGLDOK,FTM global load enable" "0: FTM Global load mechanism disabled,1: FTM Global load mechanism enabled"
|
|
bitfld.long 0x00 8. "FTM2CH1SEL,FTM2 CH1 Select" "0: FTM2_CH1 input,1: exclusive OR of FTM2_CH0 FTM2_CH1 and FTM1_CH1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "FTM2CH0SEL,FTM2 CH0 Select" "0: FTM2_CH0 input,1: CMP0 output,?..."
|
|
bitfld.long 0x00 4.--5. "FTM1CH0SEL,FTM1 CH0 Select" "0: FTM1_CH0 input,1: CMP0 output,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FTM3SYNCBIT,FTM3 Sync Bit" "0,1"
|
|
bitfld.long 0x00 2. "FTM2SYNCBIT,FTM2 Sync Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "FTM1SYNCBIT,FTM1 Sync Bit" "0,1"
|
|
bitfld.long 0x00 0. "FTM0SYNCBIT,FTM0 Sync Bit" "0,1"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "FTMOPT1,FTM Option Register 1"
|
|
hexmask.long.byte 0x00 24.--31. 1. "FTM3_OUTSEL,FTM3 channel modulation select with FTM2_CH1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "FTM0_OUTSEL,FTM0 channel modulation select with FTM1_CH1"
|
|
newline
|
|
bitfld.long 0x00 15. "FTMGLDOK,FTM global load enable" "0: FTM Global load mechanism disabled,1: FTM Global load mechanism enabled"
|
|
bitfld.long 0x00 12. "FTM5SYNCBIT,FTM5 Sync Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "FTM4SYNCBIT,FTM4 Sync Bit" "0,1"
|
|
bitfld.long 0x00 8. "FTM2CH1SEL,FTM2 CH1 Select" "0: FTM2_CH1 input,1: exclusive OR of FTM2_CH0 FTM2_CH1 and FTM1_CH1"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "FTM2CH0SEL,FTM2 CH0 Select" "0: FTM2_CH0 input,1: CMP0 output,?..."
|
|
bitfld.long 0x00 4.--5. "FTM1CH0SEL,FTM1 CH0 Select" "0: FTM1_CH0 input,1: CMP0 output,?..."
|
|
newline
|
|
bitfld.long 0x00 3. "FTM3SYNCBIT,FTM3 Sync Bit" "0,1"
|
|
bitfld.long 0x00 2. "FTM2SYNCBIT,FTM2 Sync Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "FTM1SYNCBIT,FTM1 Sync Bit" "0,1"
|
|
bitfld.long 0x00 0. "FTM0SYNCBIT,FTM0 Sync Bit" "0,1"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MISCTRL0,Miscellaneous control register 0"
|
|
bitfld.long 0x00 26. "QSPI_CLK_SEL,QSPI CLK Select bit" "0: QuadSPI internal reference clock is gated,1: QuadSPI internal reference clock is enabled"
|
|
bitfld.long 0x00 25. "RMII_CLK_SEL,RMII CLK Select bit" "0: FIRCDIV1_CLK,1: SOSCDIV1_CLK"
|
|
newline
|
|
bitfld.long 0x00 24. "RMII_CLK_OBE,RMII CLK OBE bit" "0,1"
|
|
bitfld.long 0x00 23. "FTM7_OBE_CTRL,FTM7 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
newline
|
|
bitfld.long 0x00 22. "FTM6_OBE_CTRL,FTM6 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
bitfld.long 0x00 21. "FTM5_OBE_CTRL,FTM5 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
newline
|
|
bitfld.long 0x00 20. "FTM4_OBE_CTRL,FTM4 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
bitfld.long 0x00 19. "FTM3_OBE_CTRL,FTM3 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
newline
|
|
bitfld.long 0x00 18. "FTM2_OBE_CTRL,FTM2 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
bitfld.long 0x00 17. "FTM1_OBE_CTRL,FTM1 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
newline
|
|
bitfld.long 0x00 16. "FTM0_OBE_CTRL,FTM0 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
bitfld.long 0x00 14. "FTM_GTB_SPLIT_EN,FTM GTB split enable/disable bit" "0: All the FTMs have a single global time-base,1: FTM0-3 have a common time-base and others.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MISCTRL0,Miscellaneous control register 0"
|
|
bitfld.long 0x00 19. "FTM3_OBE_CTRL,FTM3 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
bitfld.long 0x00 18. "FTM2_OBE_CTRL,FTM2 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
newline
|
|
bitfld.long 0x00 17. "FTM1_OBE_CTRL,FTM1 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
bitfld.long 0x00 16. "FTM0_OBE_CTRL,FTM0 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MISCTRL0,Miscellaneous control register 0"
|
|
bitfld.long 0x00 23. "FTM7_OBE_CTRL,FTM7 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
bitfld.long 0x00 22. "FTM6_OBE_CTRL,FTM6 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
newline
|
|
bitfld.long 0x00 21. "FTM5_OBE_CTRL,FTM5 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
bitfld.long 0x00 20. "FTM4_OBE_CTRL,FTM4 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
newline
|
|
bitfld.long 0x00 19. "FTM3_OBE_CTRL,FTM3 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
bitfld.long 0x00 18. "FTM2_OBE_CTRL,FTM2 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
newline
|
|
bitfld.long 0x00 17. "FTM1_OBE_CTRL,FTM1 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
bitfld.long 0x00 16. "FTM0_OBE_CTRL,FTM0 OBE CTRL bit" "0: The FTM channel output is put to safe state..,1: The FTM channel output state is retained when.."
|
|
newline
|
|
bitfld.long 0x00 14. "FTM_GTB_SPLIT_EN,FTM GTB split enable/disable bit" "0: All the FTMs have a single global time-base,1: FTM0-3 have a common time-base and others.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K148")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SDID,System Device Identification Register"
|
|
bitfld.long 0x00 28.--31. "GENERATION,S32K product series generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "SUBSERIES,Subseries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DERIVATE,Derivate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "RAMSIZE,RAM size" "?,?,?,?,?,?,?,7: 128 KB (S32K148) Reserved (others),?,9: 160 KB (S32K148) Reserved (others),?,11: 192 KB (S32K148) 16 KB (S32K142) Reserved..,?,13: 48 KB (S32K144) 24 KB (S32K142) Reserved..,?,15: 256 KB (S32K148) 64 KB (S32K144) 32 KB.."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "REVID,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PACKAGE,Package" "?,?,2: 48 LQFP,3: 64 LQFP,4: 100 LQFP,?,6: 144 LQFP,7: 176 LQFP,8: 100 MAP BGA,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "FEATURES,Features"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
rgroup.long 0x24++0x03
|
|
line.long 0x00 "SDID,System Device Identification Register"
|
|
bitfld.long 0x00 28.--31. "GENERATION,S32K product series generation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 24.--27. "SUBSERIES,Subseries" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 20.--23. "DERIVATE,Derivate" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "RAMSIZE,RAM size" "?,?,?,?,?,?,?,7: 128 KB (S32K148) Reserved (others),?,9: 160 KB (S32K148) 80 KB (S32K146) Reserved..,?,11: 192 KB (S32K148) 96 KB (S32K146) 16 KB..,?,13: 48 KB (S32K144) 24 KB (S32K142) Reserved..,?,15: 256 KB (S32K148) 128 KB (S32K146) 64 KB.."
|
|
newline
|
|
bitfld.long 0x00 12.--15. "REVID,Device revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "PACKAGE,Package" "?,?,2: 48 LQFP,3: 64 LQFP,4: 100 LQFP,?,6: 144 LQFP,7: 176 LQFP,8: 100 MAP BGA,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "FEATURES,Features"
|
|
endif
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "PLATCGC,Platform Clock Gating Control Register"
|
|
bitfld.long 0x00 4. "CGCEIM,EIM Clock Gating Control" "0: Clock disabled,1: Clock enabled"
|
|
bitfld.long 0x00 3. "CGCERM,ERM Clock Gating Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "CGCDMA,DMA Clock Gating Control" "0: Clock disabled,1: Clock enabled"
|
|
bitfld.long 0x00 1. "CGCMPU,MPU Clock Gating Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "CGCMSCM,MSCM Clock Gating Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "FCFG1,Flash Configuration Register 1"
|
|
rbitfld.long 0x00 16.--19. "EEERAMSIZE,EEE SRAM SIZE" "?,?,2: 0010,3: 0011,4: 0100,5: 512 Bytes,6: 256 Bytes,7: 128 Bytes,8: 64 Bytes,9: 32 Bytes,?,?,?,?,?,15: 0 Bytes"
|
|
rbitfld.long 0x00 12.--15. "DEPART,FlexNVM partition" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "UIDH,Unique Identification Register High"
|
|
hexmask.long 0x00 0.--31. 1. "UID127_96,Unique Identification"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "UIDMH,Unique Identification Register Mid-High"
|
|
hexmask.long 0x00 0.--31. 1. "UID95_64,Unique Identification"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "UIDML,Unique Identification Register Mid Low"
|
|
hexmask.long 0x00 0.--31. 1. "UID63_32,Unique Identification"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "UIDL,Unique Identification Register Low"
|
|
hexmask.long 0x00 0.--31. 1. "UID31_0,Unique Identification"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CLKDIV4,System Clock Divider Register 4"
|
|
bitfld.long 0x00 28. "TRACEDIVEN,Debug Trace Divider control" "0: Debug trace divider disabled,1: Debug trace divider enabled"
|
|
bitfld.long 0x00 1.--3. "TRACEDIV,Trace Clock Divider value To configure TRACEDIV you must first disable TRACEDIVEN then enable it after setting TRACEDIV" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0. "TRACEFRAC,Trace Clock Divider fraction To configure TRACEDIV and TRACEFRAC you must first clear TRACEDIVEN to disable the trace clock divide function" "0,1"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "MISCTRL1,Miscellaneous Control register 1"
|
|
bitfld.long 0x00 0. "SW_TRG,Software trigger to TRGMUX" "0,1"
|
|
tree.end
|
|
tree "WDOG (Watchdog Timer Unit)"
|
|
base ad:0x40052000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CS,Watchdog Control and Status Register"
|
|
bitfld.long 0x00 15. "WIN,Watchdog Window" "0: Window mode disabled,1: Window mode enabled"
|
|
bitfld.long 0x00 14. "FLG,Watchdog Interrupt Flag" "0: No interrupt occurred,1: An interrupt occurred"
|
|
newline
|
|
bitfld.long 0x00 13. "CMD32EN,Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words" "0: Disables support for 32-bit refresh/unlock..,1: Enables support for 32-bit refresh/unlock.."
|
|
bitfld.long 0x00 12. "PRES,Watchdog prescaler" "0: 256 prescaler disabled,1: 256 prescaler enabled"
|
|
newline
|
|
rbitfld.long 0x00 11. "ULK,Unlock status" "0: WDOG is locked,1: WDOG is unlocked"
|
|
rbitfld.long 0x00 10. "RCS,Reconfiguration Success" "0: Reconfiguring WDOG,1: Reconfiguration is successful"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "CLK,Watchdog Clock" "0: Bus clock,1: LPO clock,2: INTCLK (internal clock),3: ERCLK (external reference clock)"
|
|
bitfld.long 0x00 7. "EN,Watchdog Enable" "0: Watchdog disabled,1: Watchdog enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "INT,Watchdog Interrupt" "0: Watchdog interrupts are disabled,1: Watchdog interrupts are enabled"
|
|
bitfld.long 0x00 5. "UPDATE,Allow updates" "0: Updates not allowed,1: Updates allowed"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "TST,Watchdog Test" "0: Watchdog test mode disabled,1: Watchdog user mode enabled,2: Watchdog test mode enabled only the low byte..,3: Watchdog test mode enabled only the high byte.."
|
|
bitfld.long 0x00 2. "DBG,Debug Enable" "0: Watchdog disabled in chip debug mode,1: Watchdog enabled in chip debug mode"
|
|
newline
|
|
bitfld.long 0x00 1. "WAIT,Wait Enable" "0: Watchdog disabled in chip wait mode,1: Watchdog enabled in chip wait mode"
|
|
bitfld.long 0x00 0. "STOP,Stop Enable" "0: Watchdog disabled in chip stop mode,1: Watchdog enabled in chip stop mode"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Watchdog Counter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "CNTHIGH,High byte of the Watchdog Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CNTLOW,Low byte of the Watchdog Counter"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TOVAL,Watchdog Timeout Value Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOVALHIGH,High byte of the timeout value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TOVALLOW,Low byte of the timeout value"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "WIN,Watchdog Window Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "WINHIGH,High byte of Watchdog Window"
|
|
hexmask.long.byte 0x00 0.--7. 1. "WINLOW,Low byte of Watchdog Window"
|
|
tree.end
|
|
tree "FLEXIO (The FLEXIO Memory Map/Register Definition can be found here.)"
|
|
base ad:0x4005A000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "TRIGGER,Trigger Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PIN,Pin Number"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "TIMER,Timer Number"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SHIFTER,Shifter Number"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CTRL,FlexIO Control Register"
|
|
bitfld.long 0x00 31. "DOZEN,Doze Enable" "0: FlexIO enabled in Doze modes,1: FlexIO disabled in Doze modes"
|
|
bitfld.long 0x00 30. "DBGE,Debug Enable" "0: FlexIO is disabled in debug modes,1: FlexIO is enabled in debug modes"
|
|
newline
|
|
bitfld.long 0x00 2. "FASTACC,Fast Access" "0: Configures for normal register accesses to..,1: Configures for fast register accesses to FlexIO"
|
|
bitfld.long 0x00 1. "SWRST,Software Reset" "0: Software reset is disabled,1: Software reset is enabled all FlexIO.."
|
|
newline
|
|
bitfld.long 0x00 0. "FLEXEN,FlexIO Enable" "0: FlexIO module is disabled,1: FlexIO module is enabled"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "PIN,Pin State Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PDI,Pin Data Input"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SHIFTSTAT,Shifter Status Register"
|
|
bitfld.long 0x00 0.--3. "SSF,Shifter Status Flag" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SHIFTERR,Shifter Error Register"
|
|
bitfld.long 0x00 0.--3. "SEF,Shifter Error Flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "TIMSTAT,Timer Status Register"
|
|
bitfld.long 0x00 0.--3. "TSF,Timer Status Flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SHIFTSIEN,Shifter Status Interrupt Enable"
|
|
bitfld.long 0x00 0.--3. "SSIE,Shifter Status Interrupt Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SHIFTEIEN,Shifter Error Interrupt Enable"
|
|
bitfld.long 0x00 0.--3. "SEIE,Shifter Error Interrupt Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TIMIEN,Timer Interrupt Enable Register"
|
|
bitfld.long 0x00 0.--3. "TEIE,Timer Status Interrupt Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SHIFTSDEN,Shifter Status DMA Enable"
|
|
bitfld.long 0x00 0.--3. "SSDE,Shifter Status DMA Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "SHIFTCTL$1,Shifter Control N Register"
|
|
bitfld.long 0x00 24.--25. "TIMSEL,Timer Select" "0,1,2,3"
|
|
bitfld.long 0x00 23. "TIMPOL,Timer Polarity" "0: Shift on posedge of Shift clock,1: Shift on negedge of Shift clock"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "PINCFG,Shifter Pin Configuration" "0: Shifter pin output disabled,1: Shifter pin open drain or bidirectional..,2: Shifter pin bidirectional output data,3: Shifter pin output"
|
|
bitfld.long 0x00 8.--10. "PINSEL,Shifter Pin Select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 7. "PINPOL,Shifter Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
bitfld.long 0x00 0.--2. "SMOD,Shifter Mode" "0: Disabled,1: Receive mode,2: Transmit mode,?,4: Match Store mode,5: Match Continuous mode,?..."
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "SHIFTCFG$1,Shifter Configuration N Register"
|
|
bitfld.long 0x00 8. "INSRC,Input Source" "0: Pin,1: Shifter N+1 Output"
|
|
bitfld.long 0x00 4.--5. "SSTOP,Shifter Stop bit" "0: Stop bit disabled for..,1: Reserved for transmitter/receiver/match store,2: Transmitter outputs stop bit value 0 on store..,3: Transmitter outputs stop bit value 1 on store.."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "SSTART,Shifter Start bit" "0: Start bit disabled for..,1: Start bit disabled for..,2: Transmitter outputs start bit value 0 before..,3: Transmitter outputs start bit value 1 before.."
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "SHIFTBUF$1,Shifter Buffer N Register"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUF,Shift Buffer"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x280)++0x03
|
|
line.long 0x00 "SHIFTBUFBIS$1,Shifter Buffer N Bit Swapped Register"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBIS,Shift Buffer"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x300)++0x03
|
|
line.long 0x00 "SHIFTBUFBYS$1,Shifter Buffer N Byte Swapped Register"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBYS,Shift Buffer"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x380)++0x03
|
|
line.long 0x00 "SHIFTBUFBBS$1,Shifter Buffer N Bit Byte Swapped Register"
|
|
hexmask.long 0x00 0.--31. 1. "SHIFTBUFBBS,Shift Buffer"
|
|
repeat.end
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K148")
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "TIMCTL0,Timer Control N Register"
|
|
bitfld.long 0x00 24.--27. "TRGSEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "TRGPOL,Trigger Polarity" "0: Trigger active high,1: Trigger active low"
|
|
newline
|
|
bitfld.long 0x00 22. "TRGSRC,Trigger Source" "0: External trigger selected,1: Internal trigger selected"
|
|
bitfld.long 0x00 16.--17. "PINCFG,Timer Pin Configuration" "0: Timer pin output disabled,1: Timer pin open drain or bidirectional output..,2: Timer pin bidirectional output data,3: Timer pin output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "PINSEL,Timer Pin Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "PINPOL,Timer Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TIMOD,Timer Mode" "0: Timer Disabled,1: Dual 8-bit counters baud/bit mode,2: Dual 8-bit counters PWM mode,3: Single 16-bit counter mode"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
repeat 2. (strings "0" "1" )(list 0x00 0x04 )
|
|
group.long ($2+0x400)++0x03
|
|
line.long 0x00 "TIMCTL$1,Timer Control N Register"
|
|
bitfld.long 0x00 24.--27. "TRGSEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "TRGPOL,Trigger Polarity" "0: Trigger active high,1: Trigger active low"
|
|
newline
|
|
bitfld.long 0x00 22. "TRGSRC,Trigger Source" "0: External trigger selected,1: Internal trigger selected"
|
|
bitfld.long 0x00 16.--17. "PINCFG,Timer Pin Configuration" "0: Timer pin output disabled,1: Timer pin open drain or bidirectional output..,2: Timer pin bidirectional output data,3: Timer pin output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "PINSEL,Timer Pin Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "PINPOL,Timer Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TIMOD,Timer Mode" "0: Timer Disabled,1: Dual 8-bit counters baud mode,2: Dual 8-bit counters PWM high mode,3: Single 16-bit counter mode"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "2" )(list 0x00 0x04 )
|
|
group.long ($2+0x404)++0x03
|
|
line.long 0x00 "TIMCTL$1,Timer Control N Register"
|
|
bitfld.long 0x00 24.--27. "TRGSEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "TRGPOL,Trigger Polarity" "0: Trigger active high,1: Trigger active low"
|
|
newline
|
|
bitfld.long 0x00 22. "TRGSRC,Trigger Source" "0: External trigger selected,1: Internal trigger selected"
|
|
bitfld.long 0x00 16.--17. "PINCFG,Timer Pin Configuration" "0: Timer pin output disabled,1: Timer pin open drain or bidirectional output..,2: Timer pin bidirectional output data,3: Timer pin output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "PINSEL,Timer Pin Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "PINPOL,Timer Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TIMOD,Timer Mode" "0: Timer Disabled,1: Dual 8-bit counters baud/bit mode,2: Dual 8-bit counters PWM mode,3: Single 16-bit counter mode"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "TIMCTL2,Timer Control N Register"
|
|
bitfld.long 0x00 24.--27. "TRGSEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "TRGPOL,Trigger Polarity" "0: Trigger active high,1: Trigger active low"
|
|
newline
|
|
bitfld.long 0x00 22. "TRGSRC,Trigger Source" "0: External trigger selected,1: Internal trigger selected"
|
|
bitfld.long 0x00 16.--17. "PINCFG,Timer Pin Configuration" "0: Timer pin output disabled,1: Timer pin open drain or bidirectional output..,2: Timer pin bidirectional output data,3: Timer pin output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "PINSEL,Timer Pin Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "PINPOL,Timer Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TIMOD,Timer Mode" "0: Timer Disabled,1: Dual 8-bit counters baud mode,2: Dual 8-bit counters PWM high mode,3: Single 16-bit counter mode"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K148")
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "TIMCTL3,Timer Control N Register"
|
|
bitfld.long 0x00 24.--27. "TRGSEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "TRGPOL,Trigger Polarity" "0: Trigger active high,1: Trigger active low"
|
|
newline
|
|
bitfld.long 0x00 22. "TRGSRC,Trigger Source" "0: External trigger selected,1: Internal trigger selected"
|
|
bitfld.long 0x00 16.--17. "PINCFG,Timer Pin Configuration" "0: Timer pin output disabled,1: Timer pin open drain or bidirectional output..,2: Timer pin bidirectional output data,3: Timer pin output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "PINSEL,Timer Pin Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "PINPOL,Timer Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TIMOD,Timer Mode" "0: Timer Disabled,1: Dual 8-bit counters baud/bit mode,2: Dual 8-bit counters PWM mode,3: Single 16-bit counter mode"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "TIMCTL3,Timer Control N Register"
|
|
bitfld.long 0x00 24.--27. "TRGSEL,Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 23. "TRGPOL,Trigger Polarity" "0: Trigger active high,1: Trigger active low"
|
|
newline
|
|
bitfld.long 0x00 22. "TRGSRC,Trigger Source" "0: External trigger selected,1: Internal trigger selected"
|
|
bitfld.long 0x00 16.--17. "PINCFG,Timer Pin Configuration" "0: Timer pin output disabled,1: Timer pin open drain or bidirectional output..,2: Timer pin bidirectional output data,3: Timer pin output"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "PINSEL,Timer Pin Select" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 7. "PINPOL,Timer Pin Polarity" "0: Pin is active high,1: Pin is active low"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "TIMOD,Timer Mode" "0: Timer Disabled,1: Dual 8-bit counters baud mode,2: Dual 8-bit counters PWM high mode,3: Single 16-bit counter mode"
|
|
endif
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x480)++0x03
|
|
line.long 0x00 "TIMCFG$1,Timer Configuration N Register"
|
|
bitfld.long 0x00 24.--25. "TIMOUT,Timer Output" "0: Timer output is logic one when enabled and is..,1: Timer output is logic zero when enabled and..,2: Timer output is logic one when enabled and on..,3: Timer output is logic zero when enabled and.."
|
|
bitfld.long 0x00 20.--21. "TIMDEC,Timer Decrement" "0: Decrement counter on FlexIO clock Shift clock..,1: Decrement counter on Trigger input (both..,2: Decrement counter on Pin input (both edges)..,3: Decrement counter on Trigger input (both.."
|
|
newline
|
|
bitfld.long 0x00 16.--18. "TIMRST,Timer Reset" "0: Timer never reset,?,2: Timer reset on Timer Pin equal to Timer Output,3: Timer reset on Timer Trigger equal to Timer..,4: Timer reset on Timer Pin rising edge,?,6: Timer reset on Trigger rising edge,7: Timer reset on Trigger rising or falling edge"
|
|
bitfld.long 0x00 12.--14. "TIMDIS,Timer Disable" "0: Timer never disabled,1: Timer disabled on Timer N-1 disable,2: Timer disabled on Timer compare,3: Timer disabled on Timer compare and Trigger Low,4: Timer disabled on Pin rising or falling edge,5: Timer disabled on Pin rising or falling edge..,6: Timer disabled on Trigger falling edge,?..."
|
|
newline
|
|
bitfld.long 0x00 8.--10. "TIMENA,Timer Enable" "0: Timer always enabled,1: Timer enabled on Timer N-1 enable,2: Timer enabled on Trigger high,3: Timer enabled on Trigger high and Pin high,4: Timer enabled on Pin rising edge,5: Timer enabled on Pin rising edge and Trigger..,6: Timer enabled on Trigger rising edge,7: Timer enabled on Trigger rising or falling edge"
|
|
bitfld.long 0x00 4.--5. "TSTOP,Timer Stop Bit" "0: Stop bit disabled,1: Stop bit is enabled on timer compare,2: Stop bit is enabled on timer disable,3: Stop bit is enabled on timer compare and.."
|
|
newline
|
|
bitfld.long 0x00 1. "TSTART,Timer Start Bit" "0: Start bit disabled,1: Start bit enabled"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x500)++0x03
|
|
line.long 0x00 "TIMCMP$1,Timer Compare N Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CMP,Timer Compare Value"
|
|
repeat.end
|
|
tree.end
|
|
sif cpuis("S32K148")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")
|
|
tree "EWM (External Watchdog Monitor)"
|
|
base ad:0x40061000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "CTRL,Control Register"
|
|
bitfld.byte 0x00 3. "INTEN,Interrupt Enable" "0,1"
|
|
bitfld.byte 0x00 2. "INEN,Input Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 1. "ASSIN,EWM_in's Assertion State Select" "0,1"
|
|
bitfld.byte 0x00 0. "EWMEN,EWM enable" "0,1"
|
|
wgroup.byte 0x01++0x00
|
|
line.byte 0x00 "SERV,Service Register"
|
|
hexmask.byte 0x00 0.--7. 1. "SERVICE,SERVICE"
|
|
wgroup.byte 0x02++0x00
|
|
line.byte 0x00 "CMPL,Compare Low Register"
|
|
hexmask.byte 0x00 0.--7. 1. "COMPAREL,COMPAREL"
|
|
wgroup.byte 0x03++0x00
|
|
line.byte 0x00 "CMPH,Compare High Register"
|
|
hexmask.byte 0x00 0.--7. 1. "COMPAREH,COMPAREH"
|
|
wgroup.byte 0x05++0x00
|
|
line.byte 0x00 "CLKPRESCALER,Clock Prescaler Register"
|
|
hexmask.byte 0x00 0.--7. 1. "CLK_DIV,CLK_DIV"
|
|
tree.end
|
|
endif
|
|
tree "TRGMUX"
|
|
base ad:0x40063000
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TRGMUX_DMAMUX0,TRGMUX DMAMUX0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "TRGMUX_DMAMUX0,TRGMUX DMAMUX0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "SEL3,Trigger MUX Input 3 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "SEL2,Trigger MUX Input 2 Source Select"
|
|
hexmask.long.byte 0x00 8.--14. 1. "SEL1,Trigger MUX Input 1 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TRGMUX_EXTOUT0,TRGMUX EXTOUT0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "SEL3,Trigger MUX Input 3 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "SEL2,Trigger MUX Input 2 Source Select"
|
|
hexmask.long.byte 0x00 8.--14. 1. "SEL1,Trigger MUX Input 1 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "TRGMUX_EXTOUT0,TRGMUX EXTOUT0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TRGMUX_EXTOUT1,TRGMUX EXTOUT1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TRGMUX_EXTOUT1,TRGMUX EXTOUT1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "SEL3,Trigger MUX Input 3 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "SEL2,Trigger MUX Input 2 Source Select"
|
|
hexmask.long.byte 0x00 8.--14. 1. "SEL1,Trigger MUX Input 1 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TRGMUX_ADC0,TRGMUX ADC0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "SEL3,Trigger MUX Input 3 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "SEL2,Trigger MUX Input 2 Source Select"
|
|
hexmask.long.byte 0x00 8.--14. 1. "SEL1,Trigger MUX Input 1 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "TRGMUX_ADC0,TRGMUX ADC0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRGMUX_ADC1,TRGMUX ADC1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "TRGMUX_ADC1,TRGMUX ADC1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "SEL3,Trigger MUX Input 3 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "SEL2,Trigger MUX Input 2 Source Select"
|
|
hexmask.long.byte 0x00 8.--14. 1. "SEL1,Trigger MUX Input 1 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TRGMUX_CMP0,TRGMUX CMP0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "TRGMUX_CMP0,TRGMUX CMP0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TRGMUX_FTM0,TRGMUX FTM0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "TRGMUX_FTM0,TRGMUX FTM0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "SEL3,Trigger MUX Input 3 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "SEL2,Trigger MUX Input 2 Source Select"
|
|
hexmask.long.byte 0x00 8.--14. 1. "SEL1,Trigger MUX Input 1 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TRGMUX_FTM1,TRGMUX FTM1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "SEL3,Trigger MUX Input 3 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "SEL2,Trigger MUX Input 2 Source Select"
|
|
hexmask.long.byte 0x00 8.--14. 1. "SEL1,Trigger MUX Input 1 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "TRGMUX_FTM1,TRGMUX FTM1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TRGMUX_FTM2,TRGMUX FTM2 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "TRGMUX_FTM2,TRGMUX FTM2 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "SEL3,Trigger MUX Input 3 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "SEL2,Trigger MUX Input 2 Source Select"
|
|
hexmask.long.byte 0x00 8.--14. 1. "SEL1,Trigger MUX Input 1 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TRGMUX_FTM3,TRGMUX FTM3 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "TRGMUX_FTM3,TRGMUX FTM3 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "SEL3,Trigger MUX Input 3 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "SEL2,Trigger MUX Input 2 Source Select"
|
|
hexmask.long.byte 0x00 8.--14. 1. "SEL1,Trigger MUX Input 1 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TRGMUX_PDB0,TRGMUX PDB0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "TRGMUX_PDB0,TRGMUX PDB0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TRGMUX_PDB1,TRGMUX PDB1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "TRGMUX_PDB1,TRGMUX PDB1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TRGMUX_FLEXIO,TRGMUX FLEXIO Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "TRGMUX_FLEXIO,TRGMUX FLEXIO Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "SEL3,Trigger MUX Input 3 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "SEL2,Trigger MUX Input 2 Source Select"
|
|
hexmask.long.byte 0x00 8.--14. 1. "SEL1,Trigger MUX Input 1 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRGMUX_LPIT0,TRGMUX LPIT0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 24.--29. "SEL3,Trigger MUX Input 3 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 16.--21. "SEL2,Trigger MUX Input 2 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 8.--13. "SEL1,Trigger MUX Input 1 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "TRGMUX_LPIT0,TRGMUX LPIT0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 24.--30. 1. "SEL3,Trigger MUX Input 3 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--22. 1. "SEL2,Trigger MUX Input 2 Source Select"
|
|
hexmask.long.byte 0x00 8.--14. 1. "SEL1,Trigger MUX Input 1 Source Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRGMUX_LPUART0,TRGMUX LPUART0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "TRGMUX_LPUART0,TRGMUX LPUART0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRGMUX_LPUART1,TRGMUX LPUART1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "TRGMUX_LPUART1,TRGMUX LPUART1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRGMUX_LPI2C0,TRGMUX LPI2C0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "TRGMUX_LPI2C0,TRGMUX LPI2C0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRGMUX_LPSPI0,TRGMUX LPSPI0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "TRGMUX_LPSPI0,TRGMUX LPSPI0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRGMUX_LPSPI1,TRGMUX LPSPI1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TRGMUX_LPSPI1,TRGMUX LPSPI1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRGMUX_LPTMR0,TRGMUX LPTMR0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "TRGMUX_LPTMR0,TRGMUX LPTMR0 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
bitfld.long 0x00 0.--5. "SEL0,Trigger MUX Input 0 Source Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "TRGMUX_LPI2C1,TRGMUX LPI2C1 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "TRGMUX_FTM4,TRGMUX FTM4 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "TRGMUX_FTM5,TRGMUX FTM5 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "TRGMUX_FTM6,TRGMUX FTM6 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "TRGMUX_FTM7,TRGMUX FTM7 Register"
|
|
bitfld.long 0x00 31. "LK,TRGMUX register lock" "0: Register can be written,1: Register cannot be written until the next.."
|
|
hexmask.long.byte 0x00 0.--6. 1. "SEL0,Trigger MUX Input 0 Source Select"
|
|
endif
|
|
tree.end
|
|
tree "SCG (System Clock Generator)"
|
|
base ad:0x40064000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long 0x00 0.--31. 1. "VERSION,SCG Version Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 27.--31. "DIVPRES,Divider Present" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLKPRES,Clock Present"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CSR,Clock Status Register"
|
|
bitfld.long 0x00 24.--27. "SCS,System Clock Source" "?,1: System OSC (SOSC_CLK),2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),?,?,6: System PLL (SPLL_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,?..."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "CSR,Clock Status Register"
|
|
bitfld.long 0x00 24.--27. "SCS,System Clock Source" "?,1: System OSC (SOSC_CLK),2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,?..."
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RCCR,Run Clock Control Register"
|
|
bitfld.long 0x00 24.--27. "SCS,System Clock Source" "?,1: System OSC (SOSC_CLK),2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,?..."
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RCCR,Run Clock Control Register"
|
|
bitfld.long 0x00 24.--27. "SCS,System Clock Source" "?,1: System OSC (SOSC_CLK),2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),?,?,6: System PLL (SPLL_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,?..."
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "VCCR,VLPR Clock Control Register"
|
|
bitfld.long 0x00 24.--27. "SCS,System Clock Source" "?,?,2: Slow IRC (SIRC_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,?..."
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "HCCR,HSRUN Clock Control Register"
|
|
bitfld.long 0x00 24.--27. "SCS,System Clock Source" "?,1: System OSC (SOSC_CLK),2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),?,?,6: System PLL (SPLL_CLK),?..."
|
|
bitfld.long 0x00 16.--19. "DIVCORE,Core Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
newline
|
|
bitfld.long 0x00 4.--7. "DIVBUS,Bus Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,8: Divide-by-9,9: Divide-by-10,10: Divide-by-11,11: Divide-by-12,12: Divide-by-13,13: Divide-by-14,14: Divide-by-15,15: Divide-by-16"
|
|
bitfld.long 0x00 0.--3. "DIVSLOW,Slow Clock Divide Ratio" "0: Divide-by-1,1: Divide-by-2,2: Divide-by-3,3: Divide-by-4,4: Divide-by-5,5: Divide-by-6,6: Divide-by-7,7: Divide-by-8,?..."
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CLKOUTCNFG,SCG CLKOUT Configuration Register"
|
|
bitfld.long 0x00 24.--27. "CLKOUTSEL,SCG Clkout Select" "0: SCG SLOW Clock,1: System OSC (SOSC_CLK),2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),?,?,6: System PLL (SPLL_CLK),?..."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CLKOUTCNFG,SCG CLKOUT Configuration Register"
|
|
bitfld.long 0x00 24.--27. "CLKOUTSEL,SCG Clkout Select" "0: SCG SLOW Clock,1: System OSC (SOSC_CLK),2: Slow IRC (SIRC_CLK),3: Fast IRC (FIRC_CLK),?..."
|
|
endif
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SOSCCSR,System OSC Control Status Register"
|
|
bitfld.long 0x00 26. "SOSCERR,System OSC Clock Error" "0: System OSC Clock Monitor is disabled or has..,1: System OSC Clock Monitor is enabled and.."
|
|
rbitfld.long 0x00 25. "SOSCSEL,System OSC Selected" "0: System OSC is not the system clock source,1: System OSC is the system clock source"
|
|
newline
|
|
rbitfld.long 0x00 24. "SOSCVLD,System OSC Valid" "0: System OSC is not enabled or clock is not valid,1: System OSC is enabled and output clock is valid"
|
|
bitfld.long 0x00 23. "LK,Lock Register" "0: This Control Status Register can be written,1: This Control Status Register cannot be written"
|
|
newline
|
|
bitfld.long 0x00 17. "SOSCCMRE,System OSC Clock Monitor Reset Enable" "0: Clock Monitor generates interrupt when error..,1: Clock Monitor generates reset when error.."
|
|
bitfld.long 0x00 16. "SOSCCM,System OSC Clock Monitor" "0: System OSC Clock Monitor is disabled,1: System OSC Clock Monitor is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "SOSCEN,System OSC Enable" "0: System OSC is disabled,1: System OSC is enabled"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "SOSCDIV,System OSC Divide Register"
|
|
bitfld.long 0x00 8.--10. "SOSCDIV2,System OSC Clock Divide 2" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
bitfld.long 0x00 0.--2. "SOSCDIV1,System OSC Clock Divide 1" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "SOSCCFG,System Oscillator Configuration Register"
|
|
bitfld.long 0x00 4.--5. "RANGE,System OSC Range Select" "?,1: Low frequency range selected for the crystal..,2: Medium frequency range selected for the..,3: High frequency range selected for the crystal.."
|
|
bitfld.long 0x00 3. "HGO,High Gain Oscillator Select" "0: Configure crystal oscillator for low-gain..,1: Configure crystal oscillator for high-gain.."
|
|
newline
|
|
bitfld.long 0x00 2. "EREFS,External Reference Select" "0: External reference clock selected,1: Internal crystal oscillator of OSC selected"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SIRCCSR,Slow IRC Control Status Register"
|
|
rbitfld.long 0x00 25. "SIRCSEL,Slow IRC Selected" "0: Slow IRC is not the system clock source,1: Slow IRC is the system clock source"
|
|
rbitfld.long 0x00 24. "SIRCVLD,Slow IRC Valid" "0: Slow IRC is not enabled or clock is not valid,1: Slow IRC is enabled and output clock is valid"
|
|
newline
|
|
bitfld.long 0x00 23. "LK,Lock Register" "0: Control Status Register can be written,1: Control Status Register cannot be written"
|
|
bitfld.long 0x00 2. "SIRCLPEN,Slow IRC Low Power Enable" "0: Slow IRC is disabled in VLP modes,1: Slow IRC is enabled in VLP modes"
|
|
newline
|
|
bitfld.long 0x00 1. "SIRCSTEN,Slow IRC Stop Enable" "0: Slow IRC is disabled in supported Stop modes,1: Slow IRC is enabled in supported Stop modes"
|
|
bitfld.long 0x00 0. "SIRCEN,Slow IRC Enable" "0: Slow IRC is disabled,1: Slow IRC is enabled"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "SIRCDIV,Slow IRC Divide Register"
|
|
bitfld.long 0x00 8.--10. "SIRCDIV2,Slow IRC Clock Divide 2" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
bitfld.long 0x00 0.--2. "SIRCDIV1,Slow IRC Clock Divide 1" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "SIRCCFG,Slow IRC Configuration Register"
|
|
bitfld.long 0x00 0. "RANGE,Frequency Range" "0: Slow IRC low range clock (2 MHz),1: Slow IRC high range clock (8 MHz )"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "FIRCCSR,Fast IRC Control Status Register"
|
|
bitfld.long 0x00 26. "FIRCERR,Fast IRC Clock Error" "0: Error not detected with the Fast IRC trimming,1: Error detected with the Fast IRC trimming"
|
|
rbitfld.long 0x00 25. "FIRCSEL,Fast IRC Selected status" "0: Fast IRC is not the system clock source,1: Fast IRC is the system clock source"
|
|
newline
|
|
rbitfld.long 0x00 24. "FIRCVLD,Fast IRC Valid status" "0: Fast IRC is not enabled or clock is not valid,1: Fast IRC is enabled and output clock is valid"
|
|
bitfld.long 0x00 23. "LK,Lock Register" "0: Control Status Register can be written,1: Control Status Register cannot be written"
|
|
newline
|
|
bitfld.long 0x00 3. "FIRCREGOFF,Fast IRC Regulator Enable" "0: Fast IRC Regulator is enabled,1: Fast IRC Regulator is disabled"
|
|
bitfld.long 0x00 0. "FIRCEN,Fast IRC Enable" "0: Fast IRC is disabled,1: Fast IRC is enabled"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "FIRCDIV,Fast IRC Divide Register"
|
|
bitfld.long 0x00 8.--10. "FIRCDIV2,Fast IRC Clock Divide 2" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
bitfld.long 0x00 0.--2. "FIRCDIV1,Fast IRC Clock Divide 1" "0: Output disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "FIRCCFG,Fast IRC Configuration Register"
|
|
bitfld.long 0x00 0.--1. "RANGE,Frequency Range" "0: Fast IRC is trimmed to 48 MHz,1: Fast IRC is trimmed to 52 MHz,2: Fast IRC is trimmed to 56 MHz,3: Fast IRC is trimmed to 60 MHz"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x600++0x03
|
|
line.long 0x00 "SPLLCSR,System PLL Control Status Register"
|
|
bitfld.long 0x00 26. "SPLLERR,System PLL Clock Error" "0: System PLL Clock Monitor is disabled or has..,1: System PLL Clock Monitor is enabled and.."
|
|
rbitfld.long 0x00 25. "SPLLSEL,System PLL Selected" "0: System PLL is not the system clock source,1: System PLL is the system clock source"
|
|
newline
|
|
rbitfld.long 0x00 24. "SPLLVLD,System PLL Valid" "0: System PLL is not enabled or clock is not valid,1: System PLL is enabled and output clock is valid"
|
|
bitfld.long 0x00 23. "LK,Lock Register" "0: Control Status Register can be written,1: Control Status Register cannot be written"
|
|
newline
|
|
bitfld.long 0x00 17. "SPLLCMRE,System PLL Clock Monitor Reset Enable" "0: Clock Monitor generates interrupt when error..,1: Clock Monitor generates reset when error.."
|
|
bitfld.long 0x00 16. "SPLLCM,System PLL Clock Monitor" "0: System PLL Clock Monitor is disabled,1: System PLL Clock Monitor is enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "SPLLEN,System PLL Enable" "0: System PLL is disabled,1: System PLL is enabled"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "SPLLDIV,System PLL Divide Register"
|
|
bitfld.long 0x00 8.--10. "SPLLDIV2,System PLL Clock Divide 2" "0: Clock disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
bitfld.long 0x00 0.--2. "SPLLDIV1,System PLL Clock Divide 1" "0: Clock disabled,1: Divide by 1,2: Divide by 2,3: Divide by 4,4: Divide by 8,5: Divide by 16,6: Divide by 32,7: Divide by 64"
|
|
group.long 0x608++0x03
|
|
line.long 0x00 "SPLLCFG,System PLL Configuration Register"
|
|
bitfld.long 0x00 16.--20. "MULT,System PLL Multiplier" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 8.--10. "PREDIV,PLL Reference Clock Divider" "0,1,2,3,4,5,6,7"
|
|
endif
|
|
tree.end
|
|
tree "PCC"
|
|
base ad:0x40065000
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "PCC_FTFC,PCC FTFC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "PCC_DMAMUX,PCC DMAMUX Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "PCC_FlexCAN0,PCC FlexCAN0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "PCC_FlexCAN1,PCC FlexCAN1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PCC_FTM3,PCC FTM3 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "PCC_ADC1,PCC ADC1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
endif
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "PCC_FlexCAN2,PCC FlexCAN2 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
endif
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PCC_LPSPI0,PCC LPSPI0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "PCC_LPSPI1,PCC LPSPI1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
endif
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PCC_LPSPI2,PCC LPSPI2 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "PCC_PDB1,PCC PDB1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
endif
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "PCC_CRC,PCC CRC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "PCC_PDB0,PCC PDB0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "PCC_LPIT,PCC LPIT Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "PCC_FTM0,PCC FTM0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PCC_FTM1,PCC FTM1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "PCC_FTM2,PCC FTM2 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
endif
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "PCC_ADC0,PCC ADC0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "PCC_RTC,PCC RTC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "PCC_CMU0,PCC CMU0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "PCC_CMU1,PCC CMU1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCC_LPTMR0,PCC LPTMR0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
bitfld.long 0x00 4. "FRAC,Peripheral Clock Divider Fraction" "0: Fractional value is 0,1: Fractional value is 1"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "PCD,Peripheral Clock Divider Select" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,?..."
|
|
endif
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "PCC_LPTMR0,PCC LPTMR0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
bitfld.long 0x00 3. "FRAC,Peripheral Clock Divider Fraction" "0: Fractional value is 0,1: Fractional value is 1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "PCD,Peripheral Clock Divider Select" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
|
|
endif
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "PCC_PORTA,PCC PORTA Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "PCC_PORTB,PCC PORTB Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "PCC_PORTC,PCC PORTC Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "PCC_PORTD,PCC PORTD Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "PCC_PORTE,PCC PORTE Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
sif cpuis("S32K148")
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "PCC_SAI0,PCC SAI0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "PCC_SAI1,PCC SAI1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "PCC_FlexIO,PCC FlexIO Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
endif
|
|
sif cpuis("S32K144")
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "PCC_FLEXIO,PCC FlexIO Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "PCC_EWM,PCC EWM Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
endif
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "PCC_LPI2C0,PCC LPI2C0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
sif cpuis("S32K148")
|
|
group.long 0x19C++0x03
|
|
line.long 0x00 "PCC_LPI2C1,PCC LPI2C1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
endif
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "PCC_LPUART0,PCC LPUART0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "PCC_LPUART1,PCC LPUART1 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "PCC_LPUART2,PCC LPUART2 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "PCC_FTM4,PCC FTM4 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x1BC++0x03
|
|
line.long 0x00 "PCC_FTM5,PCC FTM5 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "PCC_FTM6,PCC FTM6 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "PCC_FTM7,PCC FTM7 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
endif
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "PCC_CMP0,PCC CMP0 Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
sif cpuis("S32K148")
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "PCC_QSPI,PCC QSPI Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "PCC_ENET,PCC ENET Register"
|
|
rbitfld.long 0x00 31. "PR,Present" "0: Peripheral is not present,1: Peripheral is present"
|
|
bitfld.long 0x00 30. "CGC,Clock Gate Control" "0: Clock disabled,1: Clock enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--26. "PCS,Peripheral Clock Source Select" "0: Clock is off,1: Clock option 1,2: Clock option 2,3: Clock option 3,4: Clock option 4,5: Clock option 5,6: Clock option 6,7: Clock option 7"
|
|
bitfld.long 0x00 3. "FRAC,Peripheral Clock Divider Fraction" "0: Fractional value is 0,1: Fractional value is 1"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "PCD,Peripheral Clock Divider Select" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8"
|
|
endif
|
|
tree.end
|
|
tree "CMP0 (High-Speed Comparator (CMP) Voltage Reference (VREF) Digital-to-Analog Converter (DAC) and Analog Mux (ANMUX))"
|
|
base ad:0x40073000
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "C0,CMP Control Register 0"
|
|
bitfld.long 0x00 30. "DMAEN,DMA Enable" "0: DMA is disabled,1: DMA is enabled"
|
|
bitfld.long 0x00 28. "IER,Comparator Interrupt Enable Rising" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 27. "IEF,Comparator Interrupt Enable Falling" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.long 0x00 26. "CFR,Analog Comparator Flag Rising" "0: A rising edge has not been detected on COUT,1: A rising edge on COUT has occurred"
|
|
newline
|
|
bitfld.long 0x00 25. "CFF,Analog Comparator Flag Falling" "0: A falling edge has not been detected on COUT,1: A falling edge on COUT has occurred"
|
|
rbitfld.long 0x00 24. "COUT,Analog Comparator Output" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "FPR,Filter Sample Period"
|
|
bitfld.long 0x00 15. "SE,Sample Enable" "0: Sampling mode is not selected,1: Sampling mode is selected"
|
|
newline
|
|
bitfld.long 0x00 14. "WE,Windowing Enable" "0: Windowing mode is not selected,1: Windowing mode is selected"
|
|
bitfld.long 0x00 12. "PMODE,Power Mode Select" "0: Low Speed (LS) comparison mode is selected,1: High Speed (HS) comparison mode is selected.."
|
|
newline
|
|
bitfld.long 0x00 11. "INVT,Comparator invert" "0: Does not invert the comparator output,1: Inverts the comparator output"
|
|
bitfld.long 0x00 10. "COS,Comparator Output Select" "0: Set CMPO to equal COUT (filtered comparator..,1: Set CMPO to equal COUTA (unfiltered.."
|
|
newline
|
|
bitfld.long 0x00 9. "OPE,Comparator Output Pin Enable" "0: When OPE is 0 the comparator output (after..,1: When OPE is 1 and if the software has.."
|
|
bitfld.long 0x00 8. "EN,Comparator Module Enable" "0: Analog Comparator is disabled,1: Analog Comparator is enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "FILTER_CNT,Filter Sample Count" "0: Filter is disabled,1: 1 consecutive sample must agree (comparator..,2: 2 consecutive samples must agree,3: 3 consecutive samples must agree,4: 4 consecutive samples must agree,5: 5 consecutive samples must agree,6: 6 consecutive samples must agree,7: 7 consecutive samples must agree"
|
|
bitfld.long 0x00 2. "OFFSET,Comparator hard block offset control" "0: The comparator hard block output has level 0..,1: The comparator hard block output has level 1.."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "HYSTCTR,Comparator hard block hysteresis control" "0: The hard block output has level 0 hysteresis..,1: The hard block output has level 1 hysteresis..,2: The hard block output has level 2 hysteresis..,3: The hard block output has level 3 hysteresis.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "C0,CMP Control Register 0"
|
|
bitfld.long 0x00 30. "DMAEN,DMA Enable" "0: DMA is disabled,1: DMA is enabled"
|
|
bitfld.long 0x00 28. "IER,Comparator Interrupt Enable Rising" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 27. "IEF,Comparator Interrupt Enable Falling" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
bitfld.long 0x00 26. "CFR,Analog Comparator Flag Rising" "0: A rising edge has not been detected on COUT,1: A rising edge on COUT has occurred"
|
|
newline
|
|
bitfld.long 0x00 25. "CFF,Analog Comparator Flag Falling" "0: A falling edge has not been detected on COUT,1: A falling edge on COUT has occurred"
|
|
rbitfld.long 0x00 24. "COUT,Analog Comparator Output" "0,1"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "FPR,Filter Sample Period"
|
|
bitfld.long 0x00 15. "SE,Sample Enable" "0: Sampling mode is not selected,1: Sampling mode is selected"
|
|
newline
|
|
bitfld.long 0x00 14. "WE,Windowing Enable" "0: Windowing mode is not selected,1: Windowing mode is selected"
|
|
bitfld.long 0x00 12. "PMODE,Power Mode Select" "0: Low Speed (LS) comparison mode is selected,1: High Speed (HS) comparison mode is selected.."
|
|
newline
|
|
bitfld.long 0x00 11. "INVT,Comparator invert" "0: Does not invert the comparator output,1: Inverts the comparator output"
|
|
bitfld.long 0x00 10. "COS,Comparator Output Select" "0: Set CMPO to equal COUT (filtered comparator..,1: Set CMPO to equal COUTA (unfiltered.."
|
|
newline
|
|
bitfld.long 0x00 9. "OPE,Comparator Output Pin Enable" "0: When OPE is 0 the comparator output (after..,1: When OPE is 1 and if the software has.."
|
|
bitfld.long 0x00 8. "EN,Comparator Module Enable" "0: Analog Comparator is disabled,1: Analog Comparator is enabled"
|
|
newline
|
|
bitfld.long 0x00 4.--6. "FILTER_CNT,Filter Sample Count" "0: Filter is disabled,1: 1 consecutive sample must agree (comparator..,2: 2 consecutive samples must agree,3: 3 consecutive samples must agree,4: 4 consecutive samples must agree,5: 5 consecutive samples must agree,6: 6 consecutive samples must agree,7: 7 consecutive samples must agree"
|
|
bitfld.long 0x00 2. "OFFSET,Comparator hard block offset control" "0: The comparator hard block output has level 0..,1: The comparator hard block output has level 1.."
|
|
newline
|
|
bitfld.long 0x00 0.--1. "HYSTCTR,Comparator hard block hysteresis control" "0: The hard block output has level 0 hysteresis..,1: The hard block output has level 1 hysteresis..,2: The hard block output has level 2 hysteresis..,3: The hard block output has level 3 hysteresis.."
|
|
endif
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "C1,CMP Control Register 1"
|
|
bitfld.long 0x00 27.--28. "INPSEL,Selection of the input to the positive port of the comparator" "0: IN0 from the 8-bit DAC output,1: IN1 from the analog 8-1 mux,?..."
|
|
bitfld.long 0x00 24.--25. "INNSEL,Selection of the input to the negative port of the comparator" "0: IN0 from the 8-bit DAC output,1: IN1 from the analog 8-1 mux,?..."
|
|
newline
|
|
bitfld.long 0x00 23. "CHN7,Channel 7 input enable" "0,1"
|
|
bitfld.long 0x00 22. "CHN6,Channel 6 input enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "CHN5,Channel 5 input enable" "0,1"
|
|
bitfld.long 0x00 20. "CHN4,Channel 4 input enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CHN3,Channel 3 input enable" "0,1"
|
|
bitfld.long 0x00 18. "CHN2,Channel 2 input enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CHN1,Channel 1 input enable" "0,1"
|
|
bitfld.long 0x00 16. "CHN0,Channel 0 input enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "DACEN,DAC Enable" "0: DAC is disabled,1: DAC is enabled"
|
|
bitfld.long 0x00 14. "VRSEL,Supply Voltage Reference Source Select" "0: Vin1 is selected as resistor ladder network..,1: Vin2 is selected as resistor ladder network.."
|
|
newline
|
|
bitfld.long 0x00 11.--13. "PSEL,Plus Input MUX Control" "0: 000,1: 001,2: 010,3: 011,4: 100,5: 101,6: 110,7: 111"
|
|
bitfld.long 0x00 8.--10. "MSEL,Minus Input MUX Control" "0: 000,1: 001,2: 010,3: 011,4: 100,5: 101,6: 110,7: 111"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "VOSEL,DAC Output Voltage Select"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "C2,CMP Control Register 2"
|
|
bitfld.long 0x00 31. "RRE,Round-Robin Enable" "0: Round-robin operation is disabled,1: Round-robin operation is enabled"
|
|
bitfld.long 0x00 30. "RRIE,Round-Robin interrupt enable" "0: The round-robin interrupt is disabled,1: The round-robin interrupt is enabled when a.."
|
|
newline
|
|
bitfld.long 0x00 29. "FXMP,Fixed MUX Port" "0: The Plus port is fixed,1: The Minus port is fixed"
|
|
bitfld.long 0x00 25.--27. "FXMXCH,Fixed channel selection" "0: Channel 0 is selected as the fixed reference..,1: Channel 1 is selected as the fixed reference..,2: Channel 2 is selected as the fixed reference..,3: Channel 3 is selected as the fixed reference..,4: Channel 4 is selected as the fixed reference..,5: Channel 5 is selected as the fixed reference..,6: Channel 6 is selected as the fixed reference..,7: Channel 7 is selected as the fixed reference.."
|
|
newline
|
|
bitfld.long 0x00 23. "CH7F,Channel 7 input changed flag" "0,1"
|
|
bitfld.long 0x00 22. "CH6F,Channel 6 input changed flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "CH5F,Channel 5 input changed flag" "0,1"
|
|
bitfld.long 0x00 20. "CH4F,Channel 4 input changed flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CH3F,Channel 3 input changed flag" "0,1"
|
|
bitfld.long 0x00 18. "CH2F,Channel 2 input changed flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CH1F,Channel 1 input changed flag" "0,1"
|
|
bitfld.long 0x00 16. "CH0F,Channel 0 input changed flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "NSAM,Number of sample clocks" "0: The comparison result is sampled as soon as..,1: The sampling takes place 1 round-robin clock..,2: The sampling takes place 2 round-robin clock..,3: The sampling takes place 3 round-robin clock.."
|
|
bitfld.long 0x00 8.--13. "INITMOD,Comparator and DAC initialization delay modulus" "0: The modulus is set to 64(same with 111111),?..."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "ACOn,The result of the input comparison for channel n"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "C2,CMP Control Register 2"
|
|
bitfld.long 0x00 31. "RRE,Round-Robin Enable" "0: Round-robin operation is disabled,1: Round-robin operation is enabled"
|
|
bitfld.long 0x00 30. "RRIE,Round-Robin interrupt enable" "0: The round-robin interrupt is disabled,1: The round-robin interrupt is enabled when a.."
|
|
newline
|
|
bitfld.long 0x00 29. "FXMP,Fixed MUX Port" "0: The Plus port is fixed,1: The Minus port is fixed"
|
|
bitfld.long 0x00 25.--27. "FXMXCH,Fixed channel selection" "0: Channel 0 is selected as the fixed reference..,1: Channel 1 is selected as the fixed reference..,2: Channel 2 is selected as the fixed reference..,3: Channel 3 is selected as the fixed reference..,4: Channel 4 is selected as the fixed reference..,5: Channel 5 is selected as the fixed reference..,6: Channel 6 is selected as the fixed reference..,7: Channel 7 is selected as the fixed reference.."
|
|
newline
|
|
bitfld.long 0x00 23. "CH7F,Channel 7 input changed flag" "0,1"
|
|
bitfld.long 0x00 22. "CH6F,Channel 6 input changed flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "CH5F,Channel 5 input changed flag" "0,1"
|
|
bitfld.long 0x00 20. "CH4F,Channel 4 input changed flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 19. "CH3F,Channel 3 input changed flag" "0,1"
|
|
bitfld.long 0x00 18. "CH2F,Channel 2 input changed flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "CH1F,Channel 1 input changed flag" "0,1"
|
|
bitfld.long 0x00 16. "CH0F,Channel 0 input changed flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "NSAM,Number of sample clocks" "0: The comparison result is sampled as soon as..,1: The sampling takes place 1 round-robin clock..,2: The sampling takes place 2 round-robin clock..,3: The sampling takes place 3 round-robin clock.."
|
|
bitfld.long 0x00 8.--13. "INITMOD,Comparator and DAC initialization delay modulus" "0: The modulus is set to 64 (same with 111111),?..."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "ACOn,The result of the input comparison for channel n"
|
|
endif
|
|
tree.end
|
|
sif cpuis("S32K148")
|
|
tree "QUADSPI (QuadSPI)"
|
|
base ad:0x40076000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCLKCFG,Serial Clock Configuration"
|
|
bitfld.long 0x00 19. "ISD3FB,Idle Signal Drive IOFB[3] Flash B" "0: IOFB[3] is driven to logic L,1: IOFB[3] is driven to logic H"
|
|
newline
|
|
bitfld.long 0x00 18. "ISD2FB,Idle Signal Drive IOFB[2] Flash B" "0: IOFB[2] is driven to logic L,1: IOFB[2] is driven to logic H"
|
|
bitfld.long 0x00 17. "ISD3FA,Idle Signal Drive IOFA[3] Flash A" "0: IOFA[3] is driven to logic L,1: IOFA[3] is driven to logic H"
|
|
newline
|
|
bitfld.long 0x00 16. "ISD2FA,Idle Signal Drive IOFA[2] Flash A" "0: IOFA[2] is driven to logic L,1: IOFA[2] is driven to logic H"
|
|
bitfld.long 0x00 15. "DOZE,Doze Enable" "0: A doze request will be ignored by the QuadSPI..,1: A doze request will be processed by the.."
|
|
newline
|
|
bitfld.long 0x00 14. "MDIS,Module Disable" "0: Enable QuadSPI clocks,1: Allow external logic to disable QuadSPI clocks"
|
|
bitfld.long 0x00 11. "CLR_TXF,Clear TX FIFO/Buffer" "0: No action,1: Read and write pointers of the TX Buffer are.."
|
|
newline
|
|
bitfld.long 0x00 10. "CLR_RXF,Clear RX FIFO" "0: No action,1: Read and write pointers of the RX Buffer are.."
|
|
bitfld.long 0x00 8. "VAR_LAT_EN,This field is used to enable variable latency feature in the controller" "0: Fixed latency,1: Variable latency"
|
|
newline
|
|
bitfld.long 0x00 7. "DDR_EN,DDR mode enable" "0: 2x clock are disabled for SDR instructions only,1: 2x clock are enabled supports both SDR and.."
|
|
bitfld.long 0x00 6. "DQS_EN,DQS enable" "0: DQS disabled,1: DQS enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "DQS_LAT_EN,DQS Latency Enable" "0: DQS Latency disabled,1: DQS feature with latency included enabled"
|
|
bitfld.long 0x00 4. "DQS_OUT_EN,This field is valid when Data Strobe is also used as an output from controller during Write data phase" "0: DQS as an output from controller is disabled,1: DQS as an output from controller is enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "END_CFG,Defines the endianness of the QuadSPI module" "0,1,2,3"
|
|
bitfld.long 0x00 1. "SWRSTHD,Software reset for AHB domain" "0: No action,1: AHB domain flops are reset"
|
|
newline
|
|
bitfld.long 0x00 0. "SWRSTSD,Software reset for serial flash domain" "0: No action,1: Serial Flash domain flops are reset"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "IPCR,IP Configuration Register"
|
|
bitfld.long 0x00 24.--27. "SEQID,Points to a sequence in the Look-up table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--15. 1. "IDATSZ,IP data transfer size"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "FLSHCR,Flash Configuration Register"
|
|
bitfld.long 0x00 16.--17. "TDH,Serial flash data in hold time" "0: Data aligned with the posedge of Internal..,1: Data aligned with 2x serial flash half clock,?..."
|
|
bitfld.long 0x00 8.--11. "TCSH,Serial flash CS hold time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "TCSS,Serial flash CS setup time in terms of serial flash clock cycles" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BUF0CR,Buffer0 Configuration Register"
|
|
bitfld.long 0x00 31. "HP_EN,High Priority Enable" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "ADATSZ,AHB data transfer size"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "MSTRID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "BUF1CR,Buffer1 Configuration Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "ADATSZ,AHB data transfer size"
|
|
bitfld.long 0x00 0.--3. "MSTRID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "BUF2CR,Buffer2 Configuration Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "ADATSZ,AHB data transfer size"
|
|
bitfld.long 0x00 0.--3. "MSTRID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "BUF3CR,Buffer3 Configuration Register"
|
|
bitfld.long 0x00 31. "ALLMST,All master enable" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "ADATSZ,AHB data transfer size"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "MSTRID,Master ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "BFGENCR,Buffer Generic Configuration Register"
|
|
bitfld.long 0x00 12.--15. "SEQID,Points to a sequence in the Look-up-table" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SOCCR,SOC Configuration Register"
|
|
hexmask.long 0x00 0.--31. 1. "SOCCFG,SOC Configuration For details refer to chip-specific QuadSPI information"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "BUF0IND,Buffer0 Top Index Register"
|
|
hexmask.long 0x00 3.--31. 1. "TPINDX0,Top index of buffer 0"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "BUF1IND,Buffer1 Top Index Register"
|
|
hexmask.long 0x00 3.--31. 1. "TPINDX1,Top index of buffer 1"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "BUF2IND,Buffer2 Top Index Register"
|
|
hexmask.long 0x00 3.--31. 1. "TPINDX2,Top index of buffer 2"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SFAR,Serial Flash Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "SFADR,Serial Flash Address"
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "SFACR,Serial Flash Address Configuration Register"
|
|
bitfld.long 0x00 16. "WA,Word Addressable" "0: Byte addressable serial flash mode,1: Word (2 byte) addressable serial flash mode"
|
|
bitfld.long 0x00 0.--3. "CAS,Column Address Space" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "SMPR,Sampling Register"
|
|
bitfld.long 0x00 6. "FSDLY,Full Speed Delay selection for SDR instructions" "0: One clock cycle delay,1: Two clock cycles delay"
|
|
bitfld.long 0x00 5. "FSPHS,Full Speed Phase selection for SDR instructions" "0: Select sampling at non-inverted clock,1: Select sampling at inverted clock"
|
|
rgroup.long 0x10C++0x03
|
|
line.long 0x00 "RBSR,RX Buffer Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "RDCTR,Read Counter"
|
|
bitfld.long 0x00 8.--13. "RDBFL,RX Buffer Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "RBCT,RX Buffer Control Register"
|
|
bitfld.long 0x00 8. "RXBRD,RX Buffer Readout" "0: RX Buffer content is read using the AHB Bus..,1: RX Buffer content is read using the IP Bus.."
|
|
bitfld.long 0x00 0.--4. "WMRK,RX Buffer Watermark" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "TBSR,TX Buffer Status Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "TRCTR,Transmit Counter"
|
|
bitfld.long 0x00 8.--13. "TRBFL,TX Buffer Fill Level" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "TBDR,TX Buffer Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "TXDATA,TX Data On write access the data is written into the next available entry of the TX Buffer and the QPSI_TBSR[TRBFL] field is updated accordingly"
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "TBCT,Tx Buffer Control Register"
|
|
bitfld.long 0x00 0.--4. "WMRK,Determines the watermark for the TX Buffer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rgroup.long 0x15C++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
bitfld.long 0x00 27. "TXFULL,TX Buffer Full" "0,1"
|
|
bitfld.long 0x00 26. "TXDMA,TXDMA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "TXWA,TX Buffer watermark Available" "0,1"
|
|
bitfld.long 0x00 24. "TXEDA,Tx Buffer Enough Data Available" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "RXDMA,RX Buffer DMA" "0,1"
|
|
bitfld.long 0x00 19. "RXFULL,RX Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "RXWE,RX Buffer Watermark Exceeded" "0,1"
|
|
bitfld.long 0x00 14. "AHB3FUL,AHB 3 Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 13. "AHB2FUL,AHB 2 Buffer Full" "0,1"
|
|
bitfld.long 0x00 12. "AHB1FUL,AHB 1 Buffer Full" "0,1"
|
|
newline
|
|
bitfld.long 0x00 11. "AHB0FUL,AHB 0 Buffer Full" "0,1"
|
|
bitfld.long 0x00 10. "AHB3NE,AHB 3 Buffer Not Empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "AHB2NE,AHB 2 Buffer Not Empty" "0,1"
|
|
bitfld.long 0x00 8. "AHB1NE,AHB 1 Buffer Not Empty" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "AHB0NE,AHB 0 Buffer Not Empty" "0,1"
|
|
bitfld.long 0x00 6. "AHBTRN,AHB Access Transaction pending" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "AHBGNT,AHB Command priority Granted: Asserted when another module has been granted priority of AHB Commands against IP Commands" "0,1"
|
|
bitfld.long 0x00 2. "AHB_ACC,AHB Access" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "IP_ACC,IP Access" "0,1"
|
|
bitfld.long 0x00 0. "BUSY,Module Busy" "0,1"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "FR,Flag Register"
|
|
bitfld.long 0x00 27. "TBFF,TX Buffer Fill Flag" "0,1"
|
|
bitfld.long 0x00 26. "TBUF,TX Buffer Underrun Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "ILLINE,Illegal Instruction Error Flag" "0,1"
|
|
bitfld.long 0x00 17. "RBOF,RX Buffer Overflow Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "RBDF,RX Buffer Drain Flag" "0,1"
|
|
bitfld.long 0x00 15. "ABSEF,AHB Sequence Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 14. "AITEF,AHB Illegal transaction error flag" "0,1"
|
|
bitfld.long 0x00 13. "AIBSEF,AHB Illegal Burst Size Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 12. "ABOF,AHB Buffer Overflow Flag" "0,1"
|
|
bitfld.long 0x00 7. "IPAEF,IP Command Trigger during AHB Access Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "IPIEF,IP Command Trigger could not be executed Error Flag" "0,1"
|
|
bitfld.long 0x00 4. "IPGEF,IP Command Trigger during AHB Grant Error Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "TFF,IP Command Transaction Finished Flag" "0,1"
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "RSER,Interrupt and DMA Request Select and Enable Register"
|
|
bitfld.long 0x00 27. "TBFIE,TX Buffer Fill Interrupt Enable" "0: No TBFF interrupt will be generated,1: TBFF interrupt will be generated"
|
|
bitfld.long 0x00 26. "TBUIE,TX Buffer Underrun Interrupt Enable" "0: No TBUF interrupt will be generated,1: TBUF interrupt will be generated"
|
|
newline
|
|
bitfld.long 0x00 25. "TBFDE,TX Buffer Fill DMA Enable" "0: No DMA request will be generated,1: DMA request will be generated"
|
|
bitfld.long 0x00 23. "ILLINIE,Illegal Instruction Error Interrupt Enable" "0: No ILLINE interrupt will be generated,1: ILLINE interrupt will be generated"
|
|
newline
|
|
bitfld.long 0x00 21. "RBDDE,RX Buffer Drain DMA Enable: Enables generation of DMA requests for RX Buffer Drain" "0: No DMA request will be generated,1: DMA request will be generated"
|
|
bitfld.long 0x00 17. "RBOIE,RX Buffer Overflow Interrupt Enable" "0: No RBOF interrupt will be generated,1: RBOF interrupt will be generated"
|
|
newline
|
|
bitfld.long 0x00 16. "RBDIE,RX Buffer Drain Interrupt Enable: Enables generation of IRQ requests for RX Buffer Drain" "0: No RBDF interrupt will be generated,1: RBDF Interrupt will be generated"
|
|
bitfld.long 0x00 15. "ABSEIE,AHB Sequence Error Interrupt Enable: Triggered by ABSEF flags of QSPI_FR" "0: No ABSEF interrupt will be generated,1: ABSEF interrupt will be generated"
|
|
newline
|
|
bitfld.long 0x00 14. "AITIE,AHB Illegal transaction interrupt enable" "0: No AITEF interrupt will be generated,1: AITEF interrupt will be generated"
|
|
bitfld.long 0x00 13. "AIBSIE,AHB Illegal Burst Size Interrupt Enable" "0: No AIBSEF interrupt will be generated,1: AIBSEF interrupt will be generated"
|
|
newline
|
|
bitfld.long 0x00 12. "ABOIE,AHB Buffer Overflow Interrupt Enable" "0: No ABOF interrupt will be generated,1: ABOF interrupt will be generated"
|
|
bitfld.long 0x00 7. "IPAEIE,IP Command Trigger during AHB Access Error Interrupt Enable" "0: No IPAEF interrupt will be generated,1: IPAEF interrupt will be generated"
|
|
newline
|
|
bitfld.long 0x00 6. "IPIEIE,IP Command Trigger during IP Access Error Interrupt Enable" "0: No IPIEF interrupt will be generated,1: IPIEF interrupt will be generated"
|
|
bitfld.long 0x00 4. "IPGEIE,IP Command Trigger during AHB Grant Error Interrupt Enable" "0: No IPGEF interrupt will be generated,1: IPGEF interrupt will be generated"
|
|
newline
|
|
bitfld.long 0x00 0. "TFIE,Transaction Finished Interrupt Enable" "0: No TFF interrupt will be generated,1: TFF interrupt will be generated"
|
|
rgroup.long 0x168++0x03
|
|
line.long 0x00 "SPNDST,Sequence Suspend Status Register"
|
|
hexmask.long.byte 0x00 9.--15. 1. "DATLFT,Data left: Provides information about the amount of data left to be read in the suspended sequence"
|
|
bitfld.long 0x00 6.--7. "SPDBUF,Suspended Buffer: Provides the suspended buffer number" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 0. "SUSPND,When set it signifies that a sequence is in suspended state" "0,1"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "SPTRCLR,Sequence Pointer Clear Register"
|
|
bitfld.long 0x00 8. "IPPTRC,IP Pointer Clear" "0,1"
|
|
bitfld.long 0x00 0. "BFPTRC,Buffer Pointer Clear" "0,1"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SFA1AD,Serial Flash A1 Top Address"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "TPADA1,Top address for Serial Flash A1"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SFA2AD,Serial Flash A2 Top Address"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "TPADA2,Top address for Serial Flash A2"
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "SFB1AD,Serial Flash B1 Top Address"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "TPADB1,Top address for Serial Flash B1.In effect TPxxAD is the first location of the next memory"
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "SFB2AD,Serial Flash B2 Top Address"
|
|
hexmask.long.tbyte 0x00 10.--31. 1. "TPADB2,Top address for Serial Flash B2"
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x200)++0x03
|
|
line.long 0x00 "RBDR$1,RX Buffer Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "RXDATA,RX Data"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
rgroup.long ($2+0x240)++0x03
|
|
line.long 0x00 "RBDR$1,RX Buffer Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "RXDATA,RX Data"
|
|
repeat.end
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "LUTKEY,LUT Key Register"
|
|
hexmask.long 0x00 0.--31. 1. "KEY,The key to lock or unlock the LUT"
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "LCKCR,LUT Lock Configuration Register"
|
|
bitfld.long 0x00 1. "UNLOCK,Unlocks the LUT when the following two conditions are met: 1" "0,1"
|
|
bitfld.long 0x00 0. "LOCK,Locks the LUT when the following condition is met: This register is written just after the LUTKEYLUT Key Register The LUT key register was written with 0x5AF05AF0 key" "0,1"
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x310)++0x03
|
|
line.long 0x00 "LUT$1,Look-up Table register"
|
|
bitfld.long 0x00 26.--31. "INSTR1,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "OPRND1,Operand for INSTR1"
|
|
bitfld.long 0x00 10.--15. "INSTR0,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OPRND0,Operand for INSTR0"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x350)++0x03
|
|
line.long 0x00 "LUT$1,Look-up Table register"
|
|
bitfld.long 0x00 26.--31. "INSTR1,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "OPRND1,Operand for INSTR1"
|
|
bitfld.long 0x00 10.--15. "INSTR0,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OPRND0,Operand for INSTR0"
|
|
repeat.end
|
|
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x390)++0x03
|
|
line.long 0x00 "LUT$1,Look-up Table register"
|
|
bitfld.long 0x00 26.--31. "INSTR1,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "OPRND1,Operand for INSTR1"
|
|
bitfld.long 0x00 10.--15. "INSTR0,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OPRND0,Operand for INSTR0"
|
|
repeat.end
|
|
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x3D0)++0x03
|
|
line.long 0x00 "LUT$1,Look-up Table register"
|
|
bitfld.long 0x00 26.--31. "INSTR1,Instruction 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 24.--25. "PAD1,Pad information for INSTR1" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads"
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "OPRND1,Operand for INSTR1"
|
|
bitfld.long 0x00 10.--15. "INSTR0,Instruction 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "PAD0,Pad information for INSTR0" "0: 1 Pad,1: 2 Pads,2: 4 Pads,3: 8 Pads"
|
|
hexmask.long.byte 0x00 0.--7. 1. "OPRND0,Operand for INSTR0"
|
|
repeat.end
|
|
tree.end
|
|
tree "ENET (Ethernet MAC)"
|
|
base ad:0x40079000
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "EIR,Interrupt Event Register"
|
|
bitfld.long 0x00 30. "BABR,Babbling Receive Error" "0,1"
|
|
bitfld.long 0x00 29. "BABT,Babbling Transmit Error" "0,1"
|
|
newline
|
|
bitfld.long 0x00 28. "GRA,Graceful Stop Complete" "0,1"
|
|
bitfld.long 0x00 27. "TXF,Transmit Frame Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 26. "TXB,Transmit Buffer Interrupt" "0,1"
|
|
bitfld.long 0x00 25. "RXF,Receive Frame Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 24. "RXB,Receive Buffer Interrupt" "0,1"
|
|
bitfld.long 0x00 23. "MII,MII Interrupt" "0,1"
|
|
newline
|
|
bitfld.long 0x00 22. "EBERR,Ethernet Bus Error" "0,1"
|
|
bitfld.long 0x00 21. "LC,Late Collision" "0,1"
|
|
newline
|
|
bitfld.long 0x00 20. "RL,Collision Retry Limit" "0,1"
|
|
bitfld.long 0x00 19. "UN,Transmit FIFO Underrun" "0,1"
|
|
newline
|
|
bitfld.long 0x00 18. "PLR,Payload Receive Error" "0,1"
|
|
bitfld.long 0x00 17. "WAKEUP,Node Wakeup Request Indication" "0,1"
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|
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bitfld.long 0x00 16. "TS_AVAIL,Transmit Timestamp Available" "0,1"
|
|
bitfld.long 0x00 15. "TS_TIMER,Timestamp Timer" "0,1"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "EIMR,Interrupt Mask Register"
|
|
bitfld.long 0x00 30. "BABR,BABR Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
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|
bitfld.long 0x00 29. "BABT,BABT Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
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|
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bitfld.long 0x00 28. "GRA,GRA Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
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|
bitfld.long 0x00 27. "TXF,TXF Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
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|
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bitfld.long 0x00 26. "TXB,TXB Interrupt Mask" "0: The corresponding interrupt source is masked,1: The corresponding interrupt source is not.."
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|
bitfld.long 0x00 25. "RXF,RXF Interrupt Mask" "0,1"
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|
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bitfld.long 0x00 24. "RXB,RXB Interrupt Mask" "0,1"
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|
bitfld.long 0x00 23. "MII,MII Interrupt Mask" "0,1"
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|
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bitfld.long 0x00 22. "EBERR,EBERR Interrupt Mask" "0,1"
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|
bitfld.long 0x00 21. "LC,LC Interrupt Mask" "0,1"
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|
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bitfld.long 0x00 20. "RL,RL Interrupt Mask" "0,1"
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|
bitfld.long 0x00 19. "UN,UN Interrupt Mask" "0,1"
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|
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bitfld.long 0x00 18. "PLR,PLR Interrupt Mask" "0,1"
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|
bitfld.long 0x00 17. "WAKEUP,WAKEUP Interrupt Mask" "0,1"
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|
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bitfld.long 0x00 16. "TS_AVAIL,TS_AVAIL Interrupt Mask" "0,1"
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|
bitfld.long 0x00 15. "TS_TIMER,TS_TIMER Interrupt Mask" "0,1"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RDAR,Receive Descriptor Active Register"
|
|
bitfld.long 0x00 24. "RDAR,Receive Descriptor Active" "0,1"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "TDAR,Transmit Descriptor Active Register"
|
|
bitfld.long 0x00 24. "TDAR,Transmit Descriptor Active" "0,1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "ECR,Ethernet Control Register"
|
|
bitfld.long 0x00 8. "DBSWP,Descriptor Byte Swapping Enable" "0: The buffer descriptor bytes are not swapped..,1: The buffer descriptor bytes are swapped to.."
|
|
bitfld.long 0x00 6. "DBGEN,Debug Enable" "0: MAC continues operation in debug mode,1: MAC enters hardware freeze mode when the.."
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|
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bitfld.long 0x00 4. "EN1588,EN1588 Enable" "0: Legacy FEC buffer descriptors and functions..,1: Enhanced frame time-stamping functions enabled"
|
|
bitfld.long 0x00 3. "SLEEP,Sleep Mode Enable" "0: Normal operating mode,1: Sleep mode"
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|
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bitfld.long 0x00 2. "MAGICEN,Magic Packet Detection Enable" "0: Magic detection logic disabled,1: The MAC core detects magic packets and.."
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|
bitfld.long 0x00 1. "ETHEREN,Ethernet Enable" "0: Reception immediately stops and transmission..,1: MAC is enabled and reception and transmission.."
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|
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bitfld.long 0x00 0. "RESET,Ethernet MAC Reset" "0,1"
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|
group.long 0x40++0x03
|
|
line.long 0x00 "MMFR,MII Management Frame Register"
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|
bitfld.long 0x00 30.--31. "ST,Start Of Frame Delimiter" "0,1,2,3"
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|
bitfld.long 0x00 28.--29. "OP,Operation Code" "0,1,2,3"
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|
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bitfld.long 0x00 23.--27. "PA,PHY Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
bitfld.long 0x00 18.--22. "RA,Register Address" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
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bitfld.long 0x00 16.--17. "TA,Turn Around" "0,1,2,3"
|
|
hexmask.long.word 0x00 0.--15. 1. "DATA,Management Frame Data"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "MSCR,MII Speed Control Register"
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|
bitfld.long 0x00 8.--10. "HOLDTIME,Hold time On MDIO Output" "0: 1 internal module clock cycle,1: 2 internal module clock cycles,2: 3 internal module clock cycles,?,?,?,?,7: 8 internal module clock cycles"
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bitfld.long 0x00 7. "DIS_PRE,Disable Preamble" "0: Preamble enabled,1: Preamble (32 ones) is not prepended to the.."
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bitfld.long 0x00 1.--6. "MII_SPEED,MII Speed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0x64++0x03
|
|
line.long 0x00 "MIBC,MIB Control Register"
|
|
bitfld.long 0x00 31. "MIB_DIS,Disable MIB Logic" "0: MIB logic is enabled,1: MIB logic is disabled"
|
|
rbitfld.long 0x00 30. "MIB_IDLE,MIB Idle" "0: The MIB block is updating MIB counters,1: The MIB block is not currently updating any.."
|
|
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bitfld.long 0x00 29. "MIB_CLEAR,MIB Clear" "0: See note above,1: All statistics counters are reset to 0"
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RCR,Receive Control Register"
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|
rbitfld.long 0x00 31. "GRS,Graceful Receive Stopped" "0,1"
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|
bitfld.long 0x00 30. "NLC,Payload Length Check Disable" "0: The payload length check is disabled,1: The core checks the frame's payload length.."
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|
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hexmask.long.word 0x00 16.--29. 1. "MAX_FL,Maximum Frame Length"
|
|
bitfld.long 0x00 15. "CFEN,MAC Control Frame Enable" "0: MAC control frames with any opcode other than..,1: MAC control frames with any opcode other than.."
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|
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bitfld.long 0x00 14. "CRCFWD,Terminate/Forward Received CRC" "0: The CRC field of received frames is..,1: The CRC field is stripped from the frame"
|
|
bitfld.long 0x00 13. "PAUFWD,Terminate/Forward Pause Frames" "0: Pause frames are terminated and discarded in..,1: Pause frames are forwarded to the user.."
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|
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bitfld.long 0x00 12. "PADEN,Enable Frame Padding Remove On Receive" "0: No padding is removed on receive by the MAC,1: Padding is removed from received frames"
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|
bitfld.long 0x00 9. "RMII_10T,Enables 10-Mbit/s mode of the RMII" "0: 100-Mbit/s operation,1: 10-Mbit/s operation"
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|
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bitfld.long 0x00 8. "RMII_MODE,RMII Mode Enable" "0: MAC configured for MII mode,1: MAC configured for RMII operation"
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|
bitfld.long 0x00 5. "FCE,Flow Control Enable" "0,1"
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|
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bitfld.long 0x00 4. "BC_REJ,Broadcast Frame Reject" "0,1"
|
|
bitfld.long 0x00 3. "PROM,Promiscuous Mode" "0: Disabled,1: Enabled"
|
|
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|
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bitfld.long 0x00 2. "MII_MODE,Media Independent Interface Mode" "?,1: MII or RMII mode as indicated by the.."
|
|
bitfld.long 0x00 1. "DRT,Disable Receive On Transmit" "0: Receive path operates independently of..,1: Disable reception of frames while transmitting"
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|
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bitfld.long 0x00 0. "LOOP,Internal Loopback" "0: Loopback disabled,1: Transmitted frames are looped back internal.."
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "TCR,Transmit Control Register"
|
|
bitfld.long 0x00 9. "CRCFWD,Forward Frame From Application With CRC" "0: TxBD[TC] controls whether the frame has a CRC..,1: The transmitter does not append any CRC to.."
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bitfld.long 0x00 8. "ADDINS,Set MAC Address On Transmit" "0: The source MAC address is not modified by the..,1: The MAC overwrites the source MAC address.."
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|
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bitfld.long 0x00 5.--7. "ADDSEL,Source MAC Address Select On Transmit" "0: Node MAC address programmed on PADDR1/2..,?..."
|
|
rbitfld.long 0x00 4. "RFC_PAUSE,Receive Frame Control Pause" "0,1"
|
|
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bitfld.long 0x00 3. "TFC_PAUSE,Transmit Frame Control Pause" "0: No PAUSE frame transmitted,1: The MAC stops transmission of data frames.."
|
|
bitfld.long 0x00 2. "FDEN,Full-Duplex Enable" "0,1"
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|
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bitfld.long 0x00 0. "GTS,Graceful Transmit Stop" "0,1"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "PALR,Physical Address Lower Register"
|
|
hexmask.long 0x00 0.--31. 1. "PADDR1,Pause Address"
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|
group.long 0xE8++0x03
|
|
line.long 0x00 "PAUR,Physical Address Upper Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "PADDR2,Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match and the source address field in PAUSE frames"
|
|
hexmask.long.word 0x00 0.--15. 1. "TYPE,Type Field In PAUSE Frames"
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "OPD,Opcode/Pause Duration Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "OPCODE,Opcode Field In PAUSE Frames"
|
|
hexmask.long.word 0x00 0.--15. 1. "PAUSE_DUR,Pause Duration"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IAUR,Descriptor Individual Upper Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "IADDR1,Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address"
|
|
group.long 0x11C++0x03
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line.long 0x00 "IALR,Descriptor Individual Lower Address Register"
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hexmask.long 0x00 0.--31. 1. "IADDR2,Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address"
|
|
group.long 0x120++0x03
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|
line.long 0x00 "GAUR,Descriptor Group Upper Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "GADDR1,Contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address"
|
|
group.long 0x124++0x03
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line.long 0x00 "GALR,Descriptor Group Lower Address Register"
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|
hexmask.long 0x00 0.--31. 1. "GADDR2,Contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address"
|
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group.long 0x144++0x03
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|
line.long 0x00 "TFWR,Transmit FIFO Watermark Register"
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|
bitfld.long 0x00 8. "STRFWD,Store And Forward Enable" "0: Reset,1: Enabled"
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bitfld.long 0x00 0.--5. "TFWR,Transmit FIFO" "0: 64 bytes written,1: 64 bytes written,2: 128 bytes written,3: 192 bytes written,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,?,31: 1984 bytes written,?..."
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|
group.long 0x180++0x03
|
|
line.long 0x00 "RDSR,Receive Descriptor Ring Start Register"
|
|
hexmask.long 0x00 3.--31. 1. "R_DES_START,Pointer to the beginning of the receive buffer descriptor queue"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "TDSR,Transmit Buffer Descriptor Ring Start Register"
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|
hexmask.long 0x00 3.--31. 1. "X_DES_START,Pointer to the beginning of the transmit buffer descriptor queue"
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group.long 0x188++0x03
|
|
line.long 0x00 "MRBR,Maximum Receive Buffer Size Register"
|
|
hexmask.long.word 0x00 4.--13. 1. "R_BUF_SIZE,Receive buffer size in bytes"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "RSFL,Receive FIFO Section Full Threshold"
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|
hexmask.long.byte 0x00 0.--7. 1. "RX_SECTION_FULL,Value Of Receive FIFO Section Full Threshold"
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|
group.long 0x194++0x03
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|
line.long 0x00 "RSEM,Receive FIFO Section Empty Threshold"
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|
bitfld.long 0x00 16.--20. "STAT_SECTION_EMPTY,RX Status FIFO Section Empty Threshold" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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|
hexmask.long.byte 0x00 0.--7. 1. "RX_SECTION_EMPTY,Value Of The Receive FIFO Section Empty Threshold"
|
|
group.long 0x198++0x03
|
|
line.long 0x00 "RAEM,Receive FIFO Almost Empty Threshold"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RX_ALMOST_EMPTY,Value Of The Receive FIFO Almost Empty Threshold"
|
|
group.long 0x19C++0x03
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|
line.long 0x00 "RAFL,Receive FIFO Almost Full Threshold"
|
|
hexmask.long.byte 0x00 0.--7. 1. "RX_ALMOST_FULL,Value Of The Receive FIFO Almost Full Threshold"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "TSEM,Transmit FIFO Section Empty Threshold"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TX_SECTION_EMPTY,Value Of The Transmit FIFO Section Empty Threshold"
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "TAEM,Transmit FIFO Almost Empty Threshold"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TX_ALMOST_EMPTY,Value of Transmit FIFO Almost Empty Threshold"
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "TAFL,Transmit FIFO Almost Full Threshold"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TX_ALMOST_FULL,Value Of The Transmit FIFO Almost Full Threshold"
|
|
group.long 0x1AC++0x03
|
|
line.long 0x00 "TIPG,Transmit Inter-Packet Gap"
|
|
bitfld.long 0x00 0.--4. "IPG,Transmit Inter-Packet Gap" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "FTRL,Frame Truncation Length"
|
|
hexmask.long.word 0x00 0.--13. 1. "TRUNC_FL,Frame Truncation Length"
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "TACC,Transmit Accelerator Function Configuration"
|
|
bitfld.long 0x00 4. "PROCHK,Enables insertion of protocol checksum" "0: Checksum not inserted,1: If an IP frame with a known protocol is.."
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bitfld.long 0x00 3. "IPCHK,Enables insertion of IP header checksum" "0: Checksum is not inserted,1: If an IP frame is transmitted the checksum is.."
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|
newline
|
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bitfld.long 0x00 0. "SHIFT16,TX FIFO Shift-16" "0: Disabled,1: Indicates to the transmit data FIFO that the.."
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|
group.long 0x1C4++0x03
|
|
line.long 0x00 "RACC,Receive Accelerator Function Configuration"
|
|
bitfld.long 0x00 7. "SHIFT16,RX FIFO Shift-16" "0: Disabled,1: Instructs the MAC to write two additional.."
|
|
bitfld.long 0x00 6. "LINEDIS,Enable Discard Of Frames With MAC Layer Errors" "0: Frames with errors are not discarded,1: Any frame received with a CRC length or PHY.."
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|
newline
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bitfld.long 0x00 2. "PRODIS,Enable Discard Of Frames With Wrong Protocol Checksum" "0: Frames with wrong checksum are not discarded,1: If a TCP/IP UDP/IP or ICMP/IP frame is.."
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|
bitfld.long 0x00 1. "IPDIS,Enable Discard Of Frames With Wrong IPv4 Header Checksum" "0: Frames with wrong IPv4 header checksum are..,1: If an IPv4 frame is received with a.."
|
|
newline
|
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bitfld.long 0x00 0. "PADREM,Enable Padding Removal For Short IP Frames" "0: Padding not removed,1: Any bytes following the IP payload section of.."
|
|
rgroup.long 0x200++0x03
|
|
line.long 0x00 "RMON_T_DROP,Reserved Statistic Register"
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "RMON_T_PACKETS,Tx Packet Count Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Packet count"
|
|
rgroup.long 0x208++0x03
|
|
line.long 0x00 "RMON_T_BC_PKT,Tx Broadcast Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Broadcast packets"
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|
rgroup.long 0x20C++0x03
|
|
line.long 0x00 "RMON_T_MC_PKT,Tx Multicast Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Multicast packets"
|
|
rgroup.long 0x210++0x03
|
|
line.long 0x00 "RMON_T_CRC_ALIGN,Tx Packets with CRC/Align Error Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Packets with CRC/align error"
|
|
rgroup.long 0x214++0x03
|
|
line.long 0x00 "RMON_T_UNDERSIZE,Tx Packets Less Than Bytes and Good CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit packets less than 64 bytes with good CRC"
|
|
rgroup.long 0x218++0x03
|
|
line.long 0x00 "RMON_T_OVERSIZE,Tx Packets GT MAX_FL bytes and Good CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit packets greater than MAX_FL bytes with good CRC"
|
|
rgroup.long 0x21C++0x03
|
|
line.long 0x00 "RMON_T_FRAG,Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of packets less than 64 bytes with bad CRC"
|
|
rgroup.long 0x220++0x03
|
|
line.long 0x00 "RMON_T_JAB,Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit packets greater than MAX_FL bytes and bad CRC"
|
|
rgroup.long 0x224++0x03
|
|
line.long 0x00 "RMON_T_COL,Tx Collision Count Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit collisions"
|
|
rgroup.long 0x228++0x03
|
|
line.long 0x00 "RMON_T_P64,Tx 64-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 64-byte transmit packets"
|
|
rgroup.long 0x22C++0x03
|
|
line.long 0x00 "RMON_T_P65TO127,Tx 65- to 127-byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 65- to 127-byte transmit packets"
|
|
rgroup.long 0x230++0x03
|
|
line.long 0x00 "RMON_T_P128TO255,Tx 128- to 255-byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 128- to 255-byte transmit packets"
|
|
rgroup.long 0x234++0x03
|
|
line.long 0x00 "RMON_T_P256TO511,Tx 256- to 511-byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 256- to 511-byte transmit packets"
|
|
rgroup.long 0x238++0x03
|
|
line.long 0x00 "RMON_T_P512TO1023,Tx 512- to 1023-byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 512- to 1023-byte transmit packets"
|
|
rgroup.long 0x23C++0x03
|
|
line.long 0x00 "RMON_T_P1024TO2047,Tx 1024- to 2047-byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of 1024- to 2047-byte transmit packets"
|
|
rgroup.long 0x240++0x03
|
|
line.long 0x00 "RMON_T_P_GTE2048,Tx Packets Greater Than 2048 Bytes Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TXPKTS,Number of transmit packets greater than 2048 bytes"
|
|
rgroup.long 0x244++0x03
|
|
line.long 0x00 "RMON_T_OCTETS,Tx Octets Statistic Register"
|
|
hexmask.long 0x00 0.--31. 1. "TXOCTS,Number of transmit octets"
|
|
rgroup.long 0x248++0x03
|
|
line.long 0x00 "IEEE_T_DROP,Reserved Statistic Register"
|
|
rgroup.long 0x24C++0x03
|
|
line.long 0x00 "IEEE_T_FRAME_OK,Frames Transmitted OK Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted OK"
|
|
rgroup.long 0x250++0x03
|
|
line.long 0x00 "IEEE_T_1COL,Frames Transmitted with Single Collision Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with one collision"
|
|
rgroup.long 0x254++0x03
|
|
line.long 0x00 "IEEE_T_MCOL,Frames Transmitted with Multiple Collisions Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with multiple collisions"
|
|
rgroup.long 0x258++0x03
|
|
line.long 0x00 "IEEE_T_DEF,Frames Transmitted after Deferral Delay Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with deferral delay"
|
|
rgroup.long 0x25C++0x03
|
|
line.long 0x00 "IEEE_T_LCOL,Frames Transmitted with Late Collision Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with late collision"
|
|
rgroup.long 0x260++0x03
|
|
line.long 0x00 "IEEE_T_EXCOL,Frames Transmitted with Excessive Collisions Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with excessive collisions"
|
|
rgroup.long 0x264++0x03
|
|
line.long 0x00 "IEEE_T_MACERR,Frames Transmitted with Tx FIFO Underrun Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with transmit FIFO underrun"
|
|
rgroup.long 0x268++0x03
|
|
line.long 0x00 "IEEE_T_CSERR,Frames Transmitted with Carrier Sense Error Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames transmitted with carrier sense error"
|
|
rgroup.long 0x26C++0x03
|
|
line.long 0x00 "IEEE_T_SQE,Reserved Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,This read-only field is reserved and always has the value 0"
|
|
rgroup.long 0x270++0x03
|
|
line.long 0x00 "IEEE_T_FDXFC,Flow Control Pause Frames Transmitted Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of flow-control pause frames transmitted"
|
|
rgroup.long 0x274++0x03
|
|
line.long 0x00 "IEEE_T_OCTETS_OK,Octet Count for Frames Transmitted w/o Error Statistic Register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Octet count for frames transmitted without error Counts total octets (includes header and FCS fields)"
|
|
rgroup.long 0x284++0x03
|
|
line.long 0x00 "RMON_R_PACKETS,Rx Packet Count Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of packets received"
|
|
rgroup.long 0x288++0x03
|
|
line.long 0x00 "RMON_R_BC_PKT,Rx Broadcast Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive broadcast packets"
|
|
rgroup.long 0x28C++0x03
|
|
line.long 0x00 "RMON_R_MC_PKT,Rx Multicast Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive multicast packets"
|
|
rgroup.long 0x290++0x03
|
|
line.long 0x00 "RMON_R_CRC_ALIGN,Rx Packets with CRC/Align Error Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets with CRC or align error"
|
|
rgroup.long 0x294++0x03
|
|
line.long 0x00 "RMON_R_UNDERSIZE,Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets with less than 64 bytes and good CRC"
|
|
rgroup.long 0x298++0x03
|
|
line.long 0x00 "RMON_R_OVERSIZE,Rx Packets Greater Than MAX_FL and Good CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets greater than MAX_FL and good CRC"
|
|
rgroup.long 0x29C++0x03
|
|
line.long 0x00 "RMON_R_FRAG,Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets with less than 64 bytes and bad CRC"
|
|
rgroup.long 0x2A0++0x03
|
|
line.long 0x00 "RMON_R_JAB,Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of receive packets greater than MAX_FL and bad CRC"
|
|
rgroup.long 0x2A4++0x03
|
|
line.long 0x00 "RMON_R_RESVD_0,Reserved Statistic Register"
|
|
rgroup.long 0x2A8++0x03
|
|
line.long 0x00 "RMON_R_P64,Rx 64-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 64-byte receive packets"
|
|
rgroup.long 0x2AC++0x03
|
|
line.long 0x00 "RMON_R_P65TO127,Rx 65- to 127-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 65- to 127-byte recieve packets"
|
|
rgroup.long 0x2B0++0x03
|
|
line.long 0x00 "RMON_R_P128TO255,Rx 128- to 255-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 128- to 255-byte recieve packets"
|
|
rgroup.long 0x2B4++0x03
|
|
line.long 0x00 "RMON_R_P256TO511,Rx 256- to 511-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 256- to 511-byte recieve packets"
|
|
rgroup.long 0x2B8++0x03
|
|
line.long 0x00 "RMON_R_P512TO1023,Rx 512- to 1023-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 512- to 1023-byte recieve packets"
|
|
rgroup.long 0x2BC++0x03
|
|
line.long 0x00 "RMON_R_P1024TO2047,Rx 1024- to 2047-Byte Packets Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of 1024- to 2047-byte recieve packets"
|
|
rgroup.long 0x2C0++0x03
|
|
line.long 0x00 "RMON_R_P_GTE2048,Rx Packets Greater than 2048 Bytes Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of greater-than-2048-byte recieve packets"
|
|
rgroup.long 0x2C4++0x03
|
|
line.long 0x00 "RMON_R_OCTETS,Rx Octets Statistic Register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Number of receive octets"
|
|
rgroup.long 0x2C8++0x03
|
|
line.long 0x00 "IEEE_R_DROP,Frames not Counted Correctly Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Frame count"
|
|
rgroup.long 0x2CC++0x03
|
|
line.long 0x00 "IEEE_R_FRAME_OK,Frames Received OK Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames received OK"
|
|
rgroup.long 0x2D0++0x03
|
|
line.long 0x00 "IEEE_R_CRC,Frames Received with CRC Error Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames received with CRC error"
|
|
rgroup.long 0x2D4++0x03
|
|
line.long 0x00 "IEEE_R_ALIGN,Frames Received with Alignment Error Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of frames received with alignment error"
|
|
rgroup.long 0x2D8++0x03
|
|
line.long 0x00 "IEEE_R_MACERR,Receive FIFO Overflow Count Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Receive FIFO overflow count"
|
|
rgroup.long 0x2DC++0x03
|
|
line.long 0x00 "IEEE_R_FDXFC,Flow Control Pause Frames Received Statistic Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Number of flow-control pause frames received"
|
|
rgroup.long 0x2E0++0x03
|
|
line.long 0x00 "IEEE_R_OCTETS_OK,Octet Count for Frames Received without Error Statistic Register"
|
|
hexmask.long 0x00 0.--31. 1. "COUNT,Number of octets for frames received without error"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "ATCR,Adjustable Timer Control Register"
|
|
bitfld.long 0x00 13. "SLAVE,Enable Timer Slave Mode" "0: The timer is active and all configuration..,1: The internal timer is disabled and the.."
|
|
bitfld.long 0x00 11. "CAPTURE,Capture Timer Value" "0: No effect,1: The current time is captured and can be read.."
|
|
newline
|
|
bitfld.long 0x00 9. "RESTART,Reset Timer" "0,1"
|
|
bitfld.long 0x00 7. "PINPER,Enables event signal output assertion on period event" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x00 4. "PEREN,Enable Periodical Event" "0: Disable,1: A period event interrupt can be generated.."
|
|
bitfld.long 0x00 3. "OFFRST,Reset Timer On Offset Event" "0: The timer is not affected and no action..,1: If OFFEN is set the timer resets to zero when.."
|
|
newline
|
|
bitfld.long 0x00 2. "OFFEN,Enable One-Shot Offset Event" "0: Disable,1: The timer can be reset to zero when the given.."
|
|
bitfld.long 0x00 0. "EN,Enable Timer" "0: The timer stops at the current value,1: The timer starts incrementing"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "ATVR,Timer Value Register"
|
|
hexmask.long 0x00 0.--31. 1. "ATIME,A write sets the timer"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "ATOFF,Timer Offset Register"
|
|
hexmask.long 0x00 0.--31. 1. "OFFSET,Offset value for one-shot event generation"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "ATPER,Timer Period Register"
|
|
hexmask.long 0x00 0.--31. 1. "PERIOD,Value for generating periodic events"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "ATCOR,Timer Correction Register"
|
|
hexmask.long 0x00 0.--30. 1. "COR,Correction Counter Wrap-Around Value"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "ATINC,Time-Stamping Clock Period Register"
|
|
hexmask.long.byte 0x00 8.--14. 1. "INC_CORR,Correction Increment Value"
|
|
hexmask.long.byte 0x00 0.--6. 1. "INC,Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds"
|
|
rgroup.long 0x418++0x03
|
|
line.long 0x00 "ATSTMP,Timestamp of Last Transmitted Frame"
|
|
hexmask.long 0x00 0.--31. 1. "TIMESTAMP,Timestamp of the last frame transmitted by the core that had TxBD[TS] set"
|
|
group.long 0x604++0x03
|
|
line.long 0x00 "TGSR,Timer Global Status Register"
|
|
bitfld.long 0x00 3. "TF3,Copy Of Timer Flag For Channel 3" "0: Timer Flag for Channel 3 is clear,1: Timer Flag for Channel 3 is set"
|
|
bitfld.long 0x00 2. "TF2,Copy Of Timer Flag For Channel 2" "0: Timer Flag for Channel 2 is clear,1: Timer Flag for Channel 2 is set"
|
|
newline
|
|
bitfld.long 0x00 1. "TF1,Copy Of Timer Flag For Channel 1" "0: Timer Flag for Channel 1 is clear,1: Timer Flag for Channel 1 is set"
|
|
bitfld.long 0x00 0. "TF0,Copy Of Timer Flag For Channel 0" "0: Timer Flag for Channel 0 is clear,1: Timer Flag for Channel 0 is set"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x08 0x10 0x18 )
|
|
group.long ($2+0x608)++0x03
|
|
line.long 0x00 "TCSR$1,Timer Control Status Register"
|
|
bitfld.long 0x00 7. "TF,Timer Flag" "0: Input Capture or Output Compare has not..,1: Input Capture or Output Compare has occurred"
|
|
bitfld.long 0x00 6. "TIE,Timer Interrupt Enable" "0: Interrupt is disabled,1: Interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 2.--5. "TMODE,Timer Mode" "0: Timer Channel is disabled,1: Timer Channel is configured for Input Capture..,2: Timer Channel is configured for Input Capture..,3: Timer Channel is configured for Input Capture..,4: Timer Channel is configured for Output..,5: Timer Channel is configured for Output..,6: Timer Channel is configured for Output..,7: Timer Channel is configured for Output..,?,?,10: Timer Channel is configured for Output..,?,?,?,14: Timer Channel is configured for Output..,15: Timer Channel is configured for Output.."
|
|
bitfld.long 0x00 0. "TDRE,Timer DMA Request Enable" "0: DMA request is disabled,1: DMA request is enabled"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x08 0x10 0x18 )
|
|
group.long ($2+0x60C)++0x03
|
|
line.long 0x00 "TCCR$1,Timer Compare Capture Register"
|
|
hexmask.long 0x00 0.--31. 1. "TCC,Timer Capture Compare"
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "PMC"
|
|
base ad:0x4007D000
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "LVDSC1,Low Voltage Detect Status and Control 1 Register"
|
|
rbitfld.byte 0x00 7. "LVDF,Low Voltage Detect Flag" "0: Low-voltage event not detected,1: Low-voltage event detected"
|
|
bitfld.byte 0x00 6. "LVDACK,Low Voltage Detect Acknowledge" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "LVDIE,Low Voltage Detect Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when LVDF = 1"
|
|
bitfld.byte 0x00 4. "LVDRE,Low Voltage Detect Reset Enable" "0: No system resets on low voltage detect events,?..."
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "LVDSC2,Low Voltage Detect Status and Control 2 Register"
|
|
rbitfld.byte 0x00 7. "LVWF,Low-Voltage Warning Flag" "0: Low-voltage warning event not detected,1: Low-voltage warning event detected"
|
|
bitfld.byte 0x00 6. "LVWACK,Low-Voltage Warning Acknowledge" "0,1"
|
|
newline
|
|
bitfld.byte 0x00 5. "LVWIE,Low-Voltage Warning Interrupt Enable" "0: Hardware interrupt disabled (use polling),1: Request a hardware interrupt when LVWF=1"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "REGSC,Regulator Status and Control Register"
|
|
bitfld.byte 0x00 7. "LPODIS,LPO Disable Bit" "0: Low power oscillator enabled,1: Low power oscillator disabled"
|
|
rbitfld.byte 0x00 6. "LPOSTAT,LPO Status Bit" "0: Low power oscillator in low phase,1: Low power oscillator in high phase"
|
|
newline
|
|
rbitfld.byte 0x00 2. "REGFPM,Regulator in Full Performance Mode Status Bit" "0: Regulator is in low power mode or transition..,1: Regulator is in full performance mode"
|
|
bitfld.byte 0x00 1. "CLKBIASDIS,Clock Bias Disable Bit" "0: No effect,1: In VLPS mode the bias currents and reference.."
|
|
newline
|
|
bitfld.byte 0x00 0. "BIASEN,Bias Enable Bit" "0: Biasing disabled core logic can run in full..,1: Biasing enabled core logic is slower and.."
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "LPOTRIM,Low Power Oscillator Trim Register"
|
|
bitfld.byte 0x00 0.--4. "LPOTRIM,LPO trimming bits" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "SMC (System Mode Controller)"
|
|
base ad:0x4007E000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,SMC Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,SMC Parameter Register"
|
|
bitfld.long 0x00 6. "EVLLS0,Existence of VLLS0 feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 5. "ELLS2,Existence of LLS2 feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 3. "ELLS,Existence of LLS feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 0. "EHSRUN,Existence of HSRUN feature" "0: The feature is not available,1: The feature is available"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PMPROT,Power Mode Protection register"
|
|
bitfld.long 0x00 7. "AHSRUN,Allow High Speed Run mode" "0: HSRUN is not allowed,1: HSRUN is allowed"
|
|
bitfld.long 0x00 5. "AVLP,Allow Very-Low-Power Modes" "0: VLPR and VLPS are not allowed,1: VLPR and VLPS are allowed"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PMPROT,Power Mode Protection register"
|
|
bitfld.long 0x00 5. "AVLP,Allow Very-Low-Power Modes" "0: VLPR and VLPS are not allowed,1: VLPR and VLPS are allowed"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PMCTRL,Power Mode Control register"
|
|
bitfld.long 0x00 5.--6. "RUNM,Run Mode Control" "0: Normal Run mode (RUN),?,2: Very-Low-Power Run mode (VLPR),3: High Speed Run mode (HSRUN)"
|
|
rbitfld.long 0x00 3. "VLPSA,Very Low Power Stop Aborted" "0: The previous stop mode entry was successful,1: The previous stop mode entry was aborted"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "STOPM,Stop Mode Control" "0: Normal Stop (STOP),?,2: Very-Low-Power Stop (VLPS),?,?,?,6: Reseved,?..."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PMCTRL,Power Mode Control register"
|
|
bitfld.long 0x00 5.--6. "RUNM,Run Mode Control" "0: Normal Run mode (RUN),?,2: Very-Low-Power Run mode (VLPR),?..."
|
|
rbitfld.long 0x00 3. "VLPSA,Very Low Power Stop Aborted" "0: The previous stop mode entry was successful,1: The previous stop mode entry was aborted"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "STOPM,Stop Mode Control" "0: Normal Stop (STOP),?,2: Very-Low-Power Stop (VLPS),?,?,?,6: Reseved,?..."
|
|
endif
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "STOPCTRL,Stop Control Register"
|
|
bitfld.long 0x00 6.--7. "STOPO,Stop Option" "?,1: STOP1 - Stop with both system and bus clocks..,2: STOP2 - Stop with system clock disabled and..,?..."
|
|
rgroup.long 0x14++0x03
|
|
line.long 0x00 "PMSTAT,Power Mode Status register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PMSTAT,Power Mode Status"
|
|
tree.end
|
|
tree "RCM (Reset Control Module)"
|
|
base ad:0x4007F000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 16. "ECORE1,Existence of SRS[CORE1] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 15. "ETAMPER,Existence of SRS[TAMPER] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 13. "ESACKERR,Existence of SRS[SACKERR] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 11. "EMDM_AP,Existence of SRS[MDM_AP] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 10. "ESW,Existence of SRS[SW] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 9. "ELOCKUP,Existence of SRS[LOCKUP] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 8. "EJTAG,Existence of SRS[JTAG] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 7. "EPOR,Existence of SRS[POR] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 6. "EPIN,Existence of SRS[PIN] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 5. "EWDOG,Existence of SRS[WDOG] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 4. "ECMU_LOC,Existence of SRS[CMU_LOC] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 3. "ELOL,Existence of SRS[LOL] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 2. "ELOC,Existence of SRS[LOC] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 1. "ELVD,Existence of SRS[LVD] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 0. "EWAKEUP,Existence of SRS[WAKEUP] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 16. "ECORE1,Existence of SRS[CORE1] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 15. "ETAMPER,Existence of SRS[TAMPER] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 13. "ESACKERR,Existence of SRS[SACKERR] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 11. "EMDM_AP,Existence of SRS[MDM_AP] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 10. "ESW,Existence of SRS[SW] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 9. "ELOCKUP,Existence of SRS[LOCKUP] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 8. "EJTAG,Existence of SRS[JTAG] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 7. "EPOR,Existence of SRS[POR] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 6. "EPIN,Existence of SRS[PIN] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 5. "EWDOG,Existence of SRS[WDOG] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 3. "ELOL,Existence of SRS[LOL] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 2. "ELOC,Existence of SRS[LOC] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
newline
|
|
bitfld.long 0x00 1. "ELVD,Existence of SRS[LVD] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
bitfld.long 0x00 0. "EWAKEUP,Existence of SRS[WAKEUP] status indication feature" "0: The feature is not available,1: The feature is available"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SRS,System Reset Status Register"
|
|
bitfld.long 0x00 13. "SACKERR,Stop Acknowledge Error" "0: Reset not caused by peripheral failure to..,1: Reset caused by peripheral failure to.."
|
|
bitfld.long 0x00 11. "MDM_AP,MDM-AP System Reset Request" "0: Reset was not caused by host debugger system..,1: Reset was caused by host debugger system.."
|
|
newline
|
|
bitfld.long 0x00 10. "SW,Software" "0: Reset not caused by software setting of..,1: Reset caused by software setting of.."
|
|
bitfld.long 0x00 9. "LOCKUP,Core Lockup" "0: Reset not caused by core LOCKUP event,1: Reset caused by core LOCKUP event"
|
|
newline
|
|
bitfld.long 0x00 8. "JTAG,JTAG generated reset" "0: Reset not caused by JTAG,1: Reset caused by JTAG"
|
|
bitfld.long 0x00 7. "POR,Power-On Reset" "0: Reset not caused by POR,1: Reset caused by POR"
|
|
newline
|
|
bitfld.long 0x00 6. "PIN,External Reset Pin" "0: Reset not caused by external reset pin,1: Reset caused by external reset pin"
|
|
bitfld.long 0x00 5. "WDOG,Watchdog" "0: Reset not caused by watchdog timeout,1: Reset caused by watchdog timeout"
|
|
newline
|
|
bitfld.long 0x00 4. "CMU_LOC,CMU Loss-of-Clock Reset" "0: Reset not caused by the CMU loss-of-clock..,1: Reset caused by the CMU loss-of-clock circuit"
|
|
bitfld.long 0x00 3. "LOL,Loss-of-Lock Reset" "0: Reset not caused by a loss of lock in the..,1: Reset caused by a loss of lock in the PLL/FLL"
|
|
newline
|
|
bitfld.long 0x00 2. "LOC,Loss-of-Clock Reset" "0: Reset not caused by a loss of external clock,1: Reset caused by a loss of external clock"
|
|
bitfld.long 0x00 1. "LVD,Low-Voltage Detect Reset or High-Voltage Detect Reset" "0: Reset not caused by LVD trip HVD trip or POR,1: Reset caused by LVD trip HVD trip or POR"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "SRS,System Reset Status Register"
|
|
bitfld.long 0x00 13. "SACKERR,Stop Acknowledge Error" "0: Reset not caused by peripheral failure to..,1: Reset caused by peripheral failure to.."
|
|
bitfld.long 0x00 11. "MDM_AP,MDM-AP System Reset Request" "0: Reset was not caused by host debugger system..,1: Reset was caused by host debugger system.."
|
|
newline
|
|
bitfld.long 0x00 10. "SW,Software" "0: Reset not caused by software setting of..,1: Reset caused by software setting of.."
|
|
bitfld.long 0x00 9. "LOCKUP,Core Lockup" "0: Reset not caused by core LOCKUP event,1: Reset caused by core LOCKUP event"
|
|
newline
|
|
bitfld.long 0x00 8. "JTAG,JTAG generated reset" "0: Reset not caused by JTAG,1: Reset caused by JTAG"
|
|
bitfld.long 0x00 7. "POR,Power-On Reset" "0: Reset not caused by POR,1: Reset caused by POR"
|
|
newline
|
|
bitfld.long 0x00 6. "PIN,External Reset Pin" "0: Reset not caused by external reset pin,1: Reset caused by external reset pin"
|
|
bitfld.long 0x00 5. "WDOG,Watchdog" "0: Reset not caused by watchdog timeout,1: Reset caused by watchdog timeout"
|
|
newline
|
|
bitfld.long 0x00 3. "LOL,Loss-of-Lock Reset" "0: Reset not caused by a loss of lock in the..,1: Reset caused by a loss of lock in the PLL/FLL"
|
|
bitfld.long 0x00 2. "LOC,Loss-of-Clock Reset" "0: Reset not caused by a loss of external clock,1: Reset caused by a loss of external clock"
|
|
newline
|
|
bitfld.long 0x00 1. "LVD,Low-Voltage Detect Reset or High-Voltage Detect Reset" "0: Reset not caused by LVD trip HVD trip or POR,1: Reset caused by LVD trip HVD trip or POR"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "RPC,Reset Pin Control register"
|
|
bitfld.long 0x00 8.--12. "RSTFLTSEL,Reset Pin Filter Bus Clock Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 2. "RSTFLTSS,Reset Pin Filter Select in Stop Mode" "0: All filtering disabled,1: LPO clock filter enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "RSTFLTSRW,Reset Pin Filter Select in Run and Wait Modes" "0: All filtering disabled,1: Bus clock filter enabled for normal operation,2: LPO clock filter enabled for normal operation,?..."
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SSRS,Sticky System Reset Status Register"
|
|
bitfld.long 0x00 13. "SSACKERR,Sticky Stop Acknowledge Error" "0: Reset not caused by peripheral failure to..,1: Reset caused by peripheral failure to.."
|
|
bitfld.long 0x00 11. "SMDM_AP,Sticky MDM-AP System Reset Request" "0: Reset was not caused by host debugger system..,1: Reset was caused by host debugger system.."
|
|
newline
|
|
bitfld.long 0x00 10. "SSW,Sticky Software" "0: Reset not caused by software setting of..,1: Reset caused by software setting of.."
|
|
bitfld.long 0x00 9. "SLOCKUP,Sticky Core Lockup" "0: Reset not caused by core LOCKUP event,1: Reset caused by core LOCKUP event"
|
|
newline
|
|
bitfld.long 0x00 8. "SJTAG,Sticky JTAG generated reset" "0: Reset not caused by JTAG,1: Reset caused by JTAG"
|
|
bitfld.long 0x00 7. "SPOR,Sticky Power-On Reset" "0: Reset not caused by POR,1: Reset caused by POR"
|
|
newline
|
|
bitfld.long 0x00 6. "SPIN,Sticky External Reset Pin" "0: Reset not caused by external reset pin,1: Reset caused by external reset pin"
|
|
bitfld.long 0x00 5. "SWDOG,Sticky Watchdog" "0: Reset not caused by watchdog timeout,1: Reset caused by watchdog timeout"
|
|
newline
|
|
bitfld.long 0x00 3. "SLOL,Sticky Loss-of-Lock Reset" "0: Reset not caused by a loss of lock in the..,1: Reset caused by a loss of lock in the PLL/FLL"
|
|
bitfld.long 0x00 2. "SLOC,Sticky Loss-of-Clock Reset" "0: Reset not caused by a loss of external clock,1: Reset caused by a loss of external clock"
|
|
newline
|
|
bitfld.long 0x00 1. "SLVD,Sticky Low-Voltage Detect Reset" "0: Reset not caused by LVD trip or POR,1: Reset caused by LVD trip or POR"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SSRS,Sticky System Reset Status Register"
|
|
bitfld.long 0x00 13. "SSACKERR,Sticky Stop Acknowledge Error" "0: Reset not caused by peripheral failure to..,1: Reset caused by peripheral failure to.."
|
|
bitfld.long 0x00 11. "SMDM_AP,Sticky MDM-AP System Reset Request" "0: Reset was not caused by host debugger system..,1: Reset was caused by host debugger system.."
|
|
newline
|
|
bitfld.long 0x00 10. "SSW,Sticky Software" "0: Reset not caused by software setting of..,1: Reset caused by software setting of.."
|
|
bitfld.long 0x00 9. "SLOCKUP,Sticky Core Lockup" "0: Reset not caused by core LOCKUP event,1: Reset caused by core LOCKUP event"
|
|
newline
|
|
bitfld.long 0x00 8. "SJTAG,Sticky JTAG generated reset" "0: Reset not caused by JTAG,1: Reset caused by JTAG"
|
|
bitfld.long 0x00 7. "SPOR,Sticky Power-On Reset" "0: Reset not caused by POR,1: Reset caused by POR"
|
|
newline
|
|
bitfld.long 0x00 6. "SPIN,Sticky External Reset Pin" "0: Reset not caused by external reset pin,1: Reset caused by external reset pin"
|
|
bitfld.long 0x00 5. "SWDOG,Sticky Watchdog" "0: Reset not caused by watchdog timeout,1: Reset caused by watchdog timeout"
|
|
newline
|
|
bitfld.long 0x00 4. "SCMU_LOC,Sticky CMU Loss-of-Clock Reset" "0: Reset not caused by the CMU loss-of-clock..,1: Reset caused by the CMU loss-of-clock circuit"
|
|
bitfld.long 0x00 3. "SLOL,Sticky Loss-of-Lock Reset" "0: Reset not caused by a loss of lock in the..,1: Reset caused by a loss of lock in the PLL/FLL"
|
|
newline
|
|
bitfld.long 0x00 2. "SLOC,Sticky Loss-of-Clock Reset" "0: Reset not caused by a loss of external clock,1: Reset caused by a loss of external clock"
|
|
bitfld.long 0x00 1. "SLVD,Sticky Low-Voltage Detect Reset" "0: Reset not caused by LVD trip or POR,1: Reset caused by LVD trip or POR"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SRIE,System Reset Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "SACKERR,Stop Acknowledge Error Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 11. "MDM_AP,MDM-AP System Reset Request" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "SW,Software Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "LOCKUP,Core Lockup Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "JTAG,JTAG generated reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 7. "GIE,Global Interrupt Enable" "0: All interrupt sources disabled,1: All interrupt sources enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "PIN,External Reset Pin Interrupt" "0: Reset not caused by external reset pin,1: Reset caused by external reset pin"
|
|
bitfld.long 0x00 5. "WDOG,Watchdog Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "LOL,Loss-of-Lock Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 2. "LOC,Loss-of-Clock Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--1. "DELAY,Reset Delay Time" "0: 10 LPO cycles,1: 34 LPO cycles,2: 130 LPO cycles,3: 514 LPO cycles"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SRIE,System Reset Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "SACKERR,Stop Acknowledge Error Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 11. "MDM_AP,MDM-AP System Reset Request" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "SW,Software Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "LOCKUP,Core Lockup Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "JTAG,JTAG generated reset" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 7. "GIE,Global Interrupt Enable" "0: All interrupt sources disabled,1: All interrupt sources enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "PIN,External Reset Pin Interrupt" "0: Reset not caused by external reset pin,1: Reset caused by external reset pin"
|
|
bitfld.long 0x00 5. "WDOG,Watchdog Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "CMU_LOC,CMU Loss-of-Clock Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 3. "LOL,Loss-of-Lock Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "LOC,Loss-of-Clock Interrupt" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0.--1. "DELAY,Reset Delay Time" "0: 10 LPO cycles,1: 34 LPO cycles,2: 130 LPO cycles,3: 514 LPO cycles"
|
|
endif
|
|
tree.end
|
|
tree "S32_SCB (System Control Registers)"
|
|
base ad:0xE000E000
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
bitfld.long 0x00 9. "DISOOFP,Disables floating point instructions completing out of order with respect to integer instructions" "0,1"
|
|
bitfld.long 0x00 8. "DISFPCA,SBZP / Disables automatic update of CONTROL.FPCA" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DISFOLD,Disables folding of IT instructions" "0,1"
|
|
bitfld.long 0x00 1. "DISDEFWBUF,Disables write buffer use during default memory map accesses" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "DISMCYCINT,Disables interruption of multi-cycle instructions" "0,1"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "ACTLR,Auxiliary Control Register"
|
|
endif
|
|
rgroup.long 0xD00++0x03
|
|
line.long 0x00 "CPUID,CPUID Base Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "IMPLEMENTER,Implementer code"
|
|
bitfld.long 0x00 20.--23. "VARIANT,Indicates processor revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 4.--15. 1. "PARTNO,Indicates part number"
|
|
bitfld.long 0x00 0.--3. "REVISION,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0xD04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control and State Register"
|
|
bitfld.long 0x00 31. "NMIPENDSET,NMI set-pending bit" "0: write: no effect read: NMI exception is not..,1: write: changes NMI exception state to pending.."
|
|
bitfld.long 0x00 28. "PENDSVSET,PendSV set-pending bit" "0: write: no effect read: PendSV exception is..,1: write: changes PendSV exception state to.."
|
|
newline
|
|
bitfld.long 0x00 27. "PENDSVCLR,PendSV clear-pending bit" "0: no effect,1: removes the pending state from the PendSV.."
|
|
bitfld.long 0x00 26. "PENDSTSET,SysTick exception set-pending bit" "0: write: no effect read: SysTick exception is..,1: write: changes SysTick exception state to.."
|
|
newline
|
|
bitfld.long 0x00 25. "PENDSTCLR,SysTick exception clear-pending bit" "0: no effect,1: removes the pending state from the SysTick.."
|
|
rbitfld.long 0x00 22. "ISRPENDING,Interrupt pending flag excluding NMI and Faults" "0: interrupt not pending,1: interrupt pending"
|
|
newline
|
|
rbitfld.long 0x00 12.--17. "VECTPENDING,Exception number of the highest priority pending enabled exception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
rbitfld.long 0x00 0.--5. "VECTACTIVE,Active exception number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xD04++0x03
|
|
line.long 0x00 "ICSR,Interrupt Control and State Register"
|
|
bitfld.long 0x00 31. "NMIPENDSET,NMI set-pending bit" "0: write: no effect read: NMI exception is not..,1: write: changes NMI exception state to pending.."
|
|
bitfld.long 0x00 28. "PENDSVSET,PendSV set-pending bit" "0: write: no effect read: PendSV exception is..,1: write: changes PendSV exception state to.."
|
|
newline
|
|
bitfld.long 0x00 27. "PENDSVCLR,PendSV clear-pending bit" "0: no effect,1: removes the pending state from the PendSV.."
|
|
bitfld.long 0x00 26. "PENDSTSET,SysTick exception set-pending bit" "0: write: no effect read: SysTick exception is..,1: write: changes SysTick exception state to.."
|
|
newline
|
|
bitfld.long 0x00 25. "PENDSTCLR,SysTick exception clear-pending bit" "0: no effect,1: removes the pending state from the SysTick.."
|
|
rbitfld.long 0x00 23. "ISRPREEMPT,no description available" "0: Will not service,1: Will service a pending exception"
|
|
newline
|
|
rbitfld.long 0x00 22. "ISRPENDING,Interrupt pending flag excluding NMI and Faults" "0: interrupt not pending,1: interrupt pending"
|
|
rbitfld.long 0x00 12.--17. "VECTPENDING,Exception number of the highest priority pending enabled exception" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
rbitfld.long 0x00 11. "RETTOBASE,Indicates whether there are preempted active exceptions" "0: there are preempted active exceptions to..,1: there are no active exceptions or the.."
|
|
hexmask.long.word 0x00 0.--8. 1. "VECTACTIVE,Active exception number"
|
|
endif
|
|
group.long 0xD08++0x03
|
|
line.long 0x00 "VTOR,Vector Table Offset Register"
|
|
hexmask.long 0x00 7.--31. 1. "TBLOFF,Vector table base offset"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xD0C++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTKEY,Register key"
|
|
rbitfld.long 0x00 15. "ENDIANNESS,Data endianness bit is implementation defined" "0: Little-endian,1: Big-endian"
|
|
newline
|
|
bitfld.long 0x00 8.--10. "PRIGROUP,Interrupt priority grouping field" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 2. "SYSRESETREQ,System reset request bit is implementation defined" "0: no system reset request,1: asserts a signal to the outer system that.."
|
|
newline
|
|
bitfld.long 0x00 1. "VECTCLRACTIVE,Reserved for Debug use" "0,1"
|
|
bitfld.long 0x00 0. "VECTRESET,Reserved for Debug use" "0,1"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0xD0C++0x03
|
|
line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "VECTKEY,Register key"
|
|
rbitfld.long 0x00 15. "ENDIANNESS,Data endianness implemented" "0: Little-endian,1: Big-endian"
|
|
newline
|
|
bitfld.long 0x00 2. "SYSRESETREQ,System reset request" "0: no system reset request,1: asserts a signal to the outer system that.."
|
|
bitfld.long 0x00 1. "VECTCLRACTIVE,Reserved for debug use" "0,1"
|
|
endif
|
|
group.long 0xD10++0x03
|
|
line.long 0x00 "SCR,System Control Register"
|
|
bitfld.long 0x00 4. "SEVONPEND,Send Event on Pending bit" "0: only enabled interrupts or events can wakeup..,1: enabled events and all interrupts including.."
|
|
bitfld.long 0x00 2. "SLEEPDEEP,Controls whether the processor uses sleep or deep sleep as its low power mode" "0: sleep,1: deep sleep"
|
|
newline
|
|
bitfld.long 0x00 1. "SLEEPONEXIT,Indicates sleep-on-exit when returning from Handler mode to Thread mode" "0: o not sleep when returning to Thread mode,1: enter sleep or deep sleep on return from an ISR"
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
rgroup.long 0xD14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. "STKALIGN,Indicates stack alignment on exception entry" "0,1"
|
|
bitfld.long 0x00 3. "UNALIGN_TRP,Always reads as one indicates that all unaligned accesses generate a HardFault" "0,1"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xD14++0x03
|
|
line.long 0x00 "CCR,Configuration and Control Register"
|
|
bitfld.long 0x00 9. "STKALIGN,Indicates stack alignment on exception entry" "0: 4-byte aligned,1: 8-byte aligned"
|
|
bitfld.long 0x00 8. "BFHFNMIGN,Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions" "0: data bus faults caused by load and store..,1: handlers running at priority -1 and -2 ignore.."
|
|
newline
|
|
bitfld.long 0x00 4. "DIV_0_TRP,Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0" "0: do not trap divide by 0,1: trap divide by 0"
|
|
bitfld.long 0x00 3. "UNALIGN_TRP,Enables unaligned access traps" "0: do not trap unaligned halfword and word..,1: trap unaligned halfword and word accesses"
|
|
newline
|
|
bitfld.long 0x00 1. "USERSETMPEND,Enables unprivileged software access to the STIR" "0: disable,1: enable"
|
|
bitfld.long 0x00 0. "NONBASETHRDENA,no description available" "0: processor can enter Thread mode only when no..,1: processor can enter Thread mode from any.."
|
|
group.long 0xD18++0x03
|
|
line.long 0x00 "SHPR1,System Handler Priority Register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_6,Priority of system handler 6 UsageFault"
|
|
hexmask.long.byte 0x00 8.--15. 1. "PRI_5,Priority of system handler 5 BusFault"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_4,Priority of system handler 4 MemManage"
|
|
endif
|
|
group.long 0xD1C++0x03
|
|
line.long 0x00 "SHPR2,System Handler Priority Register 2"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRI_11,Priority of system handler 11 SVCall"
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0xD20++0x03
|
|
line.long 0x00 "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRI_15,Priority of system handler 15 SysTick exception"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_14,Priority of system handler 14 PendSV"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xD20++0x03
|
|
line.long 0x00 "SHPR3,System Handler Priority Register 3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRI_15,Priority of system handler 15 SysTick exception"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_14,Priority of system handler 14 PendSV"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_12,Priority of system handler 12 DebugMonitor"
|
|
group.long 0xD24++0x03
|
|
line.long 0x00 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x00 18. "USGFAULTENA,UsageFault enable bit set to 1 to enable" "0: disable the exception,1: enable the exception"
|
|
bitfld.long 0x00 17. "BUSFAULTENA,BusFault enable bit set to 1 to enable" "0: disable the exception,1: enable the exception"
|
|
newline
|
|
bitfld.long 0x00 16. "MEMFAULTENA,MemManage enable bit set to 1 to enable" "0: disable the exception,1: enable the exception"
|
|
bitfld.long 0x00 15. "SVCALLPENDED,SVCall pending bit reads as 1 if exception is pending" "0: exception is not pending,1: exception is pending"
|
|
newline
|
|
bitfld.long 0x00 14. "BUSFAULTPENDED,BusFault exception pending bit reads as 1 if exception is pending" "0: exception is not pending,1: exception is pending"
|
|
bitfld.long 0x00 13. "MEMFAULTPENDED,MemManage exception pending bit reads as 1 if exception is pending" "0: exception is not pending,1: exception is pending"
|
|
newline
|
|
bitfld.long 0x00 12. "USGFAULTPENDED,UsageFault exception pending bit reads as 1 if exception is pending" "0: exception is not pending,1: exception is pending"
|
|
bitfld.long 0x00 11. "SYSTICKACT,SysTick exception active bit reads as 1 if exception is active" "0: exception is not active,1: exception is active"
|
|
newline
|
|
bitfld.long 0x00 10. "PENDSVACT,PendSV exception active bit reads as 1 if exception is active" "0: exception is not active,1: exception is active"
|
|
bitfld.long 0x00 8. "MONITORACT,Debug monitor active bit reads as 1 if Debug monitor is active" "0: exception is not active,1: exception is active"
|
|
newline
|
|
bitfld.long 0x00 7. "SVCALLACT,SVCall active bit reads as 1 if SVC call is active" "0: exception is not active,1: exception is active"
|
|
bitfld.long 0x00 3. "USGFAULTACT,UsageFault exception active bit reads as 1 if exception is active" "0: exception is not active,1: exception is active"
|
|
newline
|
|
bitfld.long 0x00 1. "BUSFAULTACT,BusFault exception active bit reads as 1 if exception is active" "0: exception is not active,1: exception is active"
|
|
bitfld.long 0x00 0. "MEMFAULTACT,MemManage exception active bit reads as 1 if exception is active" "0: exception is not active,1: exception is active"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0xD24++0x03
|
|
line.long 0x00 "SHCSR,System Handler Control and State Register"
|
|
bitfld.long 0x00 15. "SVCALLPENDED,SVCall pending bit reads as 1 if exception is pending" "0: exception is not pending,1: exception is pending"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xD28++0x03
|
|
line.long 0x00 "CFSR,Configurable Fault Status Registers"
|
|
bitfld.long 0x00 25. "DIVBYZERO,Divide by zero UsageFault" "0: no divide by zero fault or divide by zero..,1: the processor has executed an SDIV or UDIV.."
|
|
bitfld.long 0x00 24. "UNALIGNED,Unaligned access UsageFault" "0: no unaligned access fault or unaligned access..,1: the processor has made an unaligned memory.."
|
|
newline
|
|
bitfld.long 0x00 19. "NOCP,No coprocessor UsageFault" "0: no UsageFault caused by attempting to access..,1: the processor has attempted to access a.."
|
|
bitfld.long 0x00 18. "INVPC,Invalid PC load UsageFault caused by an invalid PC load by EXC_RETURN" "0: no invalid PC load UsageFault,1: the processor has attempted an illegal load.."
|
|
newline
|
|
bitfld.long 0x00 17. "INVSTATE,Invalid state UsageFault" "0: no invalid state UsageFault,1: the processor has attempted to execute an.."
|
|
bitfld.long 0x00 16. "UNDEFINSTR,Undefined instruction UsageFault" "0: no undefined instruction UsageFault,1: the processor has attempted to execute an.."
|
|
newline
|
|
bitfld.long 0x00 15. "BFARVALID,BusFault Address Register (BFAR) valid flag" "0: value in BFAR is not a valid fault address,1: BFAR holds a valid fault address"
|
|
bitfld.long 0x00 13. "LSPERR,no description available" "0: No bus fault occurred during floating-point..,1: A bus fault occurred during floating-point.."
|
|
newline
|
|
bitfld.long 0x00 12. "STKERR,BusFault on stacking for exception entry" "0: no stacking fault,1: stacking for an exception entry has caused.."
|
|
bitfld.long 0x00 11. "UNSTKERR,BusFault on unstacking for a return from exception" "0: no unstacking fault,1: unstack for an exception return has caused.."
|
|
newline
|
|
bitfld.long 0x00 10. "IMPRECISERR,Imprecise data bus error" "0: no imprecise data bus error,1: a data bus error has occurred but the return.."
|
|
bitfld.long 0x00 9. "PRECISERR,Precise data bus error" "0: no precise data bus error,1: a data bus error has occurred and the PC.."
|
|
newline
|
|
bitfld.long 0x00 8. "IBUSERR,Instruction bus error" "0: no instruction bus error,1: instruction bus error"
|
|
bitfld.long 0x00 7. "MMARVALID,MemManage Fault Address Register (MMFAR) valid flag" "0: value in MMAR is not a valid fault address,1: MMAR holds a valid fault address"
|
|
newline
|
|
bitfld.long 0x00 5. "MLSPERR,no description available" "0: No MemManage fault occurred during..,1: A MemManage fault occurred during.."
|
|
bitfld.long 0x00 4. "MSTKERR,MemManage fault on stacking for exception entry" "0: no stacking fault,1: stacking for an exception entry has caused.."
|
|
newline
|
|
bitfld.long 0x00 3. "MUNSTKERR,MemManage fault on unstacking for a return from exception" "0: no unstacking fault,1: unstack for an exception return has caused.."
|
|
bitfld.long 0x00 1. "DACCVIOL,Data access violation flag" "0: no data access violation fault,1: the processor attempted a load or store at a.."
|
|
newline
|
|
bitfld.long 0x00 0. "IACCVIOL,Instruction access violation flag" "0: no instruction access violation fault,1: the processor attempted an instruction fetch.."
|
|
group.long 0xD2C++0x03
|
|
line.long 0x00 "HFSR,HardFault Status register"
|
|
bitfld.long 0x00 31. "DEBUGEVT,Reserved for Debug use" "0,1"
|
|
bitfld.long 0x00 30. "FORCED,Indicates a forced hard fault generated by escalation of a fault with configurable priority that cannot be handles either because of priority or because it is disabled" "0: no forced HardFault,1: forced HardFault"
|
|
newline
|
|
bitfld.long 0x00 1. "VECTTBL,Indicates a BusFault on a vector table read during exception processing" "0: no BusFault on vector table,1: BusFault on vector table"
|
|
endif
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
bitfld.long 0x00 4. "EXTERNAL,no description available" "0: No EDBGRQ debug event,1: EDBGRQ debug event"
|
|
bitfld.long 0x00 3. "VCATCH,no description available" "0: No Vector catch triggered,1: Vector catch triggered"
|
|
newline
|
|
bitfld.long 0x00 2. "DWTTRAP,no description available" "0: No current debug events generated by the DWT,1: At least one current debug event generated by.."
|
|
bitfld.long 0x00 1. "BKPT,no description available" "0: No current breakpoint debug event,1: At least one current breakpoint debug event"
|
|
newline
|
|
bitfld.long 0x00 0. "HALTED,no description available" "0: No active halt request debug event,1: Halt request debug event active"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xD34++0x03
|
|
line.long 0x00 "MMFAR,MemManage Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of MemManage fault location"
|
|
group.long 0xD38++0x03
|
|
line.long 0x00 "BFAR,BusFault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "ADDRESS,Address of the BusFault location"
|
|
group.long 0xD3C++0x03
|
|
line.long 0x00 "AFSR,Auxiliary Fault Status Register"
|
|
hexmask.long 0x00 0.--31. 1. "AUXFAULT,Latched version of the AUXFAULT inputs"
|
|
group.long 0xD88++0x03
|
|
line.long 0x00 "CPACR,Coprocessor Access Control Register"
|
|
bitfld.long 0x00 22.--23. "CP11,Access privileges for coprocessor 11" "0: Access denied,1: Privileged access only,2: Reserved,3: Full access"
|
|
bitfld.long 0x00 20.--21. "CP10,Access privileges for coprocessor 10" "0: Access denied,1: Privileged access only,2: Reserved,3: Full access"
|
|
group.long 0xF34++0x03
|
|
line.long 0x00 "FPCCR,Floating-point Context Control Register"
|
|
bitfld.long 0x00 31. "ASPEN,Enables CONTROL2 setting on execution of a floating-point instruction" "0: Disable CONTROL2 setting on execution of a..,1: Enable CONTROL2 setting on execution of a.."
|
|
bitfld.long 0x00 30. "LSPEN,Lazy state preservation for floating-point context" "0: Disable automatic lazy state preservation for..,1: Enable automatic lazy state preservation for.."
|
|
newline
|
|
bitfld.long 0x00 8. "MONRDY,Permission to set the MON_PEND when the floating-point stack frame was allocated" "0: DebugMonitor is disabled or priority did not..,1: DebugMonitor is enabled and priority permits.."
|
|
bitfld.long 0x00 6. "BFRDY,Permission to set the BusFault handler to the pending state when the floating-point stack frame was allocated" "0: BusFault is disabled or priority did not..,1: BusFault is disabled or priority did not.."
|
|
newline
|
|
bitfld.long 0x00 5. "MMRDY,Permission to set the MemManage handler to the pending state when the floating-point stack frame was allocated" "0: MemManage is disabled or priority did not..,1: MemManage is enabled and priority permitted.."
|
|
bitfld.long 0x00 4. "HFRDY,Permission to set the HardFault handler to the pending state when the floating-point stack frame was allocated" "0: Priority did not permit setting the HardFault..,1: Priority permitted setting the HardFault.."
|
|
newline
|
|
bitfld.long 0x00 3. "THREAD,Mode when the floating-point stack frame was allocated" "0: Mode was not Thread Mode when the..,1: Mode was Thread Mode when the floating-point.."
|
|
bitfld.long 0x00 1. "USER,Privilege level when the floating-point stack frame was allocated" "0: Privilege level was not user when the..,1: Privilege level was user when the.."
|
|
newline
|
|
bitfld.long 0x00 0. "LSPACT,Lazy state preservation" "0: Lazy state preservation is not active,1: Lazy state preservation is active"
|
|
group.long 0xF38++0x03
|
|
line.long 0x00 "FPCAR,Floating-point Context Address Register"
|
|
hexmask.long 0x00 3.--31. 1. "ADDRESS,The location of the unpopulated floating-point register space allocated on an exception stack frame"
|
|
group.long 0xF3C++0x03
|
|
line.long 0x00 "FPDSCR,Floating-point Default Status Control Register"
|
|
bitfld.long 0x00 26. "AHP,Default value for FPSCR.AHP (Alternative half-precision control bit)" "0: IEEE half-precision format selected,1: Alternative half-precision format selected"
|
|
bitfld.long 0x00 25. "DN,Default value for FPSCR.DN (Default NaN mode control bit)" "0: NaN operands propagate through to the output..,1: Any operation involving one or more NaNs.."
|
|
newline
|
|
bitfld.long 0x00 24. "FZ,Default value for FPSCR.FZ (Flush-to-zero mode control bit)" "0: Flush-to-zero mode disabled,1: Flush-to-zero mode enabled"
|
|
bitfld.long 0x00 22.--23. "RMode,Default value for FPSCR.RMode (Rounding Mode control field)" "0: Round to Nearest (RN) mode,1: Round towards Plus Infinity (RP) mode,2: Round towards Minus Infinity (RM) mode,3: Round towards Zero (RZ) mode"
|
|
endif
|
|
tree.end
|
|
tree "S32_SYSTICK (System timer)"
|
|
base ad:0xE000E010
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "CSR,SysTick Control and Status Register"
|
|
bitfld.long 0x00 16. "COUNTFLAG,Returns 1 if timer counted to 0 since last time this was" "0,1"
|
|
bitfld.long 0x00 2. "CLKSOURCE,Indicates the clock source" "0: external clock,1: processor clock"
|
|
newline
|
|
bitfld.long 0x00 1. "TICKINT,Enables SysTick exception request" "0: counting down to 0 does not assert the..,1: counting down to 0 asserts the SysTick.."
|
|
bitfld.long 0x00 0. "ENABLE,Enables the counter" "0: counter disabled,1: counter enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "RVR,SysTick Reload Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "RELOAD,Value to load into the SysTick Current Value Register when the counter reaches 0"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "CVR,SysTick Current Value Register"
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "CURRENT,Current value at the time the register is accessed"
|
|
rgroup.long 0x0C++0x03
|
|
line.long 0x00 "CALIB,SysTick Calibration Value Register"
|
|
bitfld.long 0x00 31. "NOREF,Indicates whether the device provides a reference clock to the processor" "0: The reference clock is provided,1: The reference clock is not provided"
|
|
bitfld.long 0x00 30. "SKEW,Indicates whether the TENMS value is exact" "0: TENMS value is exact,1: TENMS value is inexact or not given"
|
|
newline
|
|
hexmask.long.tbyte 0x00 0.--23. 1. "TENMS,Reload value to use for 10ms timing"
|
|
tree.end
|
|
tree "S32_NVIC (Nested Vectored Interrupt Controller)"
|
|
base ad:0xE000E100
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "NVICISER0,Interrupt Set Enable Register n"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt set enable bits"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "S32_NVIC_ISER,Interrupt Set Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt set enable bits"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x04)++0x03
|
|
line.long 0x00 "NVICISER$1,Interrupt Set Enable Register n"
|
|
hexmask.long 0x00 0.--31. 1. "SETENA,Interrupt set enable bits"
|
|
repeat.end
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "NVICICER0,Interrupt Clear Enable Register n"
|
|
hexmask.long 0x00 0.--31. 1. "CLRENA,Interrupt clear-enable bits"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "S32_NVIC_ICER,Interrupt Clear Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "CLRENA,Interrupt clear-enable bits"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 3. (strings "1" "2" "3" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x84)++0x03
|
|
line.long 0x00 "NVICICER$1,Interrupt Clear Enable Register n"
|
|
hexmask.long 0x00 0.--31. 1. "CLRENA,Interrupt clear-enable bits"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "S32_NVIC_ISPR,Interrupt Set Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt set-pending bits"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "NVICISPR$1,Interrupt Set Pending Register n"
|
|
hexmask.long 0x00 0.--31. 1. "SETPEND,Interrupt set-pending bits"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "S32_NVIC_ICPR,Interrupt Clear Pending Register"
|
|
hexmask.long 0x00 0.--31. 1. "CLRPEND,Interrupt clear-pending bits"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "NVICICPR$1,Interrupt Clear Pending Register n"
|
|
hexmask.long 0x00 0.--31. 1. "CLRPEND,Interrupt clear-pending bits"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x00 0x04 0x08 0x0C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "NVICIABR$1,Interrupt Active bit Register n"
|
|
hexmask.long 0x00 0.--31. 1. "ACTIVE,Interrupt active flags"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "S32_NVIC_IPR0,Interrupt Priority Register n"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRI_3,Priority of interrupt 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_2,Priority of interrupt 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "PRI_1,Priority of interrupt 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_0,Priority of interrupt 0"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.byte 0x300++0x00
|
|
line.byte 0x00 "NVICIP0,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI0,Priority of interrupt 0"
|
|
group.byte 0x301++0x00
|
|
line.byte 0x00 "NVICIP1,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI1,Priority of interrupt 1"
|
|
group.byte 0x302++0x00
|
|
line.byte 0x00 "NVICIP2,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI2,Priority of interrupt 2"
|
|
group.byte 0x303++0x00
|
|
line.byte 0x00 "NVICIP3,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI3,Priority of interrupt 3"
|
|
group.byte 0x304++0x00
|
|
line.byte 0x00 "NVICIP4,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI4,Priority of interrupt 4"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x304++0x03
|
|
line.long 0x00 "S32_NVIC_IPR1,Interrupt Priority Register n"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRI_3,Priority of interrupt 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_2,Priority of interrupt 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "PRI_1,Priority of interrupt 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_0,Priority of interrupt 0"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.byte 0x305++0x00
|
|
line.byte 0x00 "NVICIP5,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI5,Priority of interrupt 5"
|
|
group.byte 0x306++0x00
|
|
line.byte 0x00 "NVICIP6,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI6,Priority of interrupt 6"
|
|
group.byte 0x307++0x00
|
|
line.byte 0x00 "NVICIP7,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI7,Priority of interrupt 7"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x308++0x03
|
|
line.long 0x00 "S32_NVIC_IPR2,Interrupt Priority Register n"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRI_3,Priority of interrupt 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_2,Priority of interrupt 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "PRI_1,Priority of interrupt 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_0,Priority of interrupt 0"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.byte 0x308++0x00
|
|
line.byte 0x00 "NVICIP8,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI8,Priority of interrupt 8"
|
|
group.byte 0x309++0x00
|
|
line.byte 0x00 "NVICIP9,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI9,Priority of interrupt 9"
|
|
group.byte 0x30A++0x00
|
|
line.byte 0x00 "NVICIP10,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI10,Priority of interrupt 10"
|
|
group.byte 0x30B++0x00
|
|
line.byte 0x00 "NVICIP11,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI11,Priority of interrupt 11"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x30C++0x03
|
|
line.long 0x00 "S32_NVIC_IPR3,Interrupt Priority Register n"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRI_3,Priority of interrupt 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_2,Priority of interrupt 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "PRI_1,Priority of interrupt 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_0,Priority of interrupt 0"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.byte 0x30C++0x00
|
|
line.byte 0x00 "NVICIP12,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI12,Priority of interrupt 12"
|
|
group.byte 0x30D++0x00
|
|
line.byte 0x00 "NVICIP13,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI13,Priority of interrupt 13"
|
|
group.byte 0x30E++0x00
|
|
line.byte 0x00 "NVICIP14,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI14,Priority of interrupt 14"
|
|
group.byte 0x30F++0x00
|
|
line.byte 0x00 "NVICIP15,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI15,Priority of interrupt 15"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "S32_NVIC_IPR4,Interrupt Priority Register n"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRI_3,Priority of interrupt 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_2,Priority of interrupt 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "PRI_1,Priority of interrupt 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_0,Priority of interrupt 0"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.byte 0x310++0x00
|
|
line.byte 0x00 "NVICIP16,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI16,Priority of interrupt 16"
|
|
group.byte 0x311++0x00
|
|
line.byte 0x00 "NVICIP17,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI17,Priority of interrupt 17"
|
|
group.byte 0x312++0x00
|
|
line.byte 0x00 "NVICIP18,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI18,Priority of interrupt 18"
|
|
group.byte 0x313++0x00
|
|
line.byte 0x00 "NVICIP19,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI19,Priority of interrupt 19"
|
|
group.byte 0x314++0x00
|
|
line.byte 0x00 "NVICIP20,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI20,Priority of interrupt 20"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x314++0x03
|
|
line.long 0x00 "S32_NVIC_IPR5,Interrupt Priority Register n"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRI_3,Priority of interrupt 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_2,Priority of interrupt 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "PRI_1,Priority of interrupt 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_0,Priority of interrupt 0"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.byte 0x315++0x00
|
|
line.byte 0x00 "NVICIP21,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI21,Priority of interrupt 21"
|
|
group.byte 0x316++0x00
|
|
line.byte 0x00 "NVICIP22,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI22,Priority of interrupt 22"
|
|
group.byte 0x317++0x00
|
|
line.byte 0x00 "NVICIP23,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI23,Priority of interrupt 23"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x318++0x03
|
|
line.long 0x00 "S32_NVIC_IPR6,Interrupt Priority Register n"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRI_3,Priority of interrupt 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_2,Priority of interrupt 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "PRI_1,Priority of interrupt 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_0,Priority of interrupt 0"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.byte 0x318++0x00
|
|
line.byte 0x00 "NVICIP24,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI24,Priority of interrupt 24"
|
|
group.byte 0x319++0x00
|
|
line.byte 0x00 "NVICIP25,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI25,Priority of interrupt 25"
|
|
group.byte 0x31A++0x00
|
|
line.byte 0x00 "NVICIP26,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI26,Priority of interrupt 26"
|
|
group.byte 0x31B++0x00
|
|
line.byte 0x00 "NVICIP27,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI27,Priority of interrupt 27"
|
|
group.byte 0x31C++0x00
|
|
line.byte 0x00 "NVICIP28,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI28,Priority of interrupt 28"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x31C++0x03
|
|
line.long 0x00 "S32_NVIC_IPR7,Interrupt Priority Register n"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRI_3,Priority of interrupt 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PRI_2,Priority of interrupt 2"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "PRI_1,Priority of interrupt 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PRI_0,Priority of interrupt 0"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.byte 0x31D++0x00
|
|
line.byte 0x00 "NVICIP29,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI29,Priority of interrupt 29"
|
|
group.byte 0x31E++0x00
|
|
line.byte 0x00 "NVICIP30,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI30,Priority of interrupt 30"
|
|
group.byte 0x31F++0x00
|
|
line.byte 0x00 "NVICIP31,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI31,Priority of interrupt 31"
|
|
group.byte 0x320++0x00
|
|
line.byte 0x00 "NVICIP32,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI32,Priority of interrupt 32"
|
|
group.byte 0x321++0x00
|
|
line.byte 0x00 "NVICIP33,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI33,Priority of interrupt 33"
|
|
group.byte 0x322++0x00
|
|
line.byte 0x00 "NVICIP34,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI34,Priority of interrupt 34"
|
|
group.byte 0x323++0x00
|
|
line.byte 0x00 "NVICIP35,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI35,Priority of interrupt 35"
|
|
group.byte 0x324++0x00
|
|
line.byte 0x00 "NVICIP36,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI36,Priority of interrupt 36"
|
|
group.byte 0x325++0x00
|
|
line.byte 0x00 "NVICIP37,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI37,Priority of interrupt 37"
|
|
group.byte 0x326++0x00
|
|
line.byte 0x00 "NVICIP38,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI38,Priority of interrupt 38"
|
|
group.byte 0x327++0x00
|
|
line.byte 0x00 "NVICIP39,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI39,Priority of interrupt 39"
|
|
group.byte 0x328++0x00
|
|
line.byte 0x00 "NVICIP40,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI40,Priority of interrupt 40"
|
|
group.byte 0x329++0x00
|
|
line.byte 0x00 "NVICIP41,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI41,Priority of interrupt 41"
|
|
group.byte 0x32A++0x00
|
|
line.byte 0x00 "NVICIP42,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI42,Priority of interrupt 42"
|
|
group.byte 0x32B++0x00
|
|
line.byte 0x00 "NVICIP43,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI43,Priority of interrupt 43"
|
|
group.byte 0x32C++0x00
|
|
line.byte 0x00 "NVICIP44,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI44,Priority of interrupt 44"
|
|
group.byte 0x32D++0x00
|
|
line.byte 0x00 "NVICIP45,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI45,Priority of interrupt 45"
|
|
group.byte 0x32E++0x00
|
|
line.byte 0x00 "NVICIP46,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI46,Priority of interrupt 46"
|
|
group.byte 0x32F++0x00
|
|
line.byte 0x00 "NVICIP47,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI47,Priority of interrupt 47"
|
|
group.byte 0x330++0x00
|
|
line.byte 0x00 "NVICIP48,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI48,Priority of interrupt 48"
|
|
group.byte 0x331++0x00
|
|
line.byte 0x00 "NVICIP49,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI49,Priority of interrupt 49"
|
|
group.byte 0x332++0x00
|
|
line.byte 0x00 "NVICIP50,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI50,Priority of interrupt 50"
|
|
group.byte 0x333++0x00
|
|
line.byte 0x00 "NVICIP51,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI51,Priority of interrupt 51"
|
|
group.byte 0x334++0x00
|
|
line.byte 0x00 "NVICIP52,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI52,Priority of interrupt 52"
|
|
group.byte 0x335++0x00
|
|
line.byte 0x00 "NVICIP53,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI53,Priority of interrupt 53"
|
|
group.byte 0x336++0x00
|
|
line.byte 0x00 "NVICIP54,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI54,Priority of interrupt 54"
|
|
group.byte 0x337++0x00
|
|
line.byte 0x00 "NVICIP55,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI55,Priority of interrupt 55"
|
|
group.byte 0x338++0x00
|
|
line.byte 0x00 "NVICIP56,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI56,Priority of interrupt 56"
|
|
group.byte 0x339++0x00
|
|
line.byte 0x00 "NVICIP57,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI57,Priority of interrupt 57"
|
|
group.byte 0x33A++0x00
|
|
line.byte 0x00 "NVICIP58,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI58,Priority of interrupt 58"
|
|
group.byte 0x33B++0x00
|
|
line.byte 0x00 "NVICIP59,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI59,Priority of interrupt 59"
|
|
group.byte 0x33C++0x00
|
|
line.byte 0x00 "NVICIP60,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI60,Priority of interrupt 60"
|
|
group.byte 0x33D++0x00
|
|
line.byte 0x00 "NVICIP61,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI61,Priority of interrupt 61"
|
|
group.byte 0x33E++0x00
|
|
line.byte 0x00 "NVICIP62,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI62,Priority of interrupt 62"
|
|
group.byte 0x33F++0x00
|
|
line.byte 0x00 "NVICIP63,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI63,Priority of interrupt 63"
|
|
group.byte 0x340++0x00
|
|
line.byte 0x00 "NVICIP64,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI64,Priority of interrupt 64"
|
|
group.byte 0x341++0x00
|
|
line.byte 0x00 "NVICIP65,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI65,Priority of interrupt 65"
|
|
group.byte 0x342++0x00
|
|
line.byte 0x00 "NVICIP66,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI66,Priority of interrupt 66"
|
|
group.byte 0x343++0x00
|
|
line.byte 0x00 "NVICIP67,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI67,Priority of interrupt 67"
|
|
group.byte 0x344++0x00
|
|
line.byte 0x00 "NVICIP68,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI68,Priority of interrupt 68"
|
|
group.byte 0x345++0x00
|
|
line.byte 0x00 "NVICIP69,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI69,Priority of interrupt 69"
|
|
group.byte 0x346++0x00
|
|
line.byte 0x00 "NVICIP70,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI70,Priority of interrupt 70"
|
|
group.byte 0x347++0x00
|
|
line.byte 0x00 "NVICIP71,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI71,Priority of interrupt 71"
|
|
group.byte 0x348++0x00
|
|
line.byte 0x00 "NVICIP72,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI72,Priority of interrupt 72"
|
|
group.byte 0x349++0x00
|
|
line.byte 0x00 "NVICIP73,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI73,Priority of interrupt 73"
|
|
group.byte 0x34A++0x00
|
|
line.byte 0x00 "NVICIP74,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI74,Priority of interrupt 74"
|
|
group.byte 0x34B++0x00
|
|
line.byte 0x00 "NVICIP75,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI75,Priority of interrupt 75"
|
|
group.byte 0x34C++0x00
|
|
line.byte 0x00 "NVICIP76,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI76,Priority of interrupt 76"
|
|
group.byte 0x34D++0x00
|
|
line.byte 0x00 "NVICIP77,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI77,Priority of interrupt 77"
|
|
group.byte 0x34E++0x00
|
|
line.byte 0x00 "NVICIP78,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI78,Priority of interrupt 78"
|
|
group.byte 0x34F++0x00
|
|
line.byte 0x00 "NVICIP79,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI79,Priority of interrupt 79"
|
|
group.byte 0x350++0x00
|
|
line.byte 0x00 "NVICIP80,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI80,Priority of interrupt 80"
|
|
group.byte 0x351++0x00
|
|
line.byte 0x00 "NVICIP81,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI81,Priority of interrupt 81"
|
|
group.byte 0x352++0x00
|
|
line.byte 0x00 "NVICIP82,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI82,Priority of interrupt 82"
|
|
group.byte 0x353++0x00
|
|
line.byte 0x00 "NVICIP83,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI83,Priority of interrupt 83"
|
|
group.byte 0x354++0x00
|
|
line.byte 0x00 "NVICIP84,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI84,Priority of interrupt 84"
|
|
group.byte 0x355++0x00
|
|
line.byte 0x00 "NVICIP85,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI85,Priority of interrupt 85"
|
|
group.byte 0x356++0x00
|
|
line.byte 0x00 "NVICIP86,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI86,Priority of interrupt 86"
|
|
group.byte 0x357++0x00
|
|
line.byte 0x00 "NVICIP87,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI87,Priority of interrupt 87"
|
|
group.byte 0x358++0x00
|
|
line.byte 0x00 "NVICIP88,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI88,Priority of interrupt 88"
|
|
group.byte 0x359++0x00
|
|
line.byte 0x00 "NVICIP89,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI89,Priority of interrupt 89"
|
|
group.byte 0x35A++0x00
|
|
line.byte 0x00 "NVICIP90,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI90,Priority of interrupt 90"
|
|
group.byte 0x35B++0x00
|
|
line.byte 0x00 "NVICIP91,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI91,Priority of interrupt 91"
|
|
group.byte 0x35C++0x00
|
|
line.byte 0x00 "NVICIP92,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI92,Priority of interrupt 92"
|
|
group.byte 0x35D++0x00
|
|
line.byte 0x00 "NVICIP93,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI93,Priority of interrupt 93"
|
|
group.byte 0x35E++0x00
|
|
line.byte 0x00 "NVICIP94,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI94,Priority of interrupt 94"
|
|
group.byte 0x35F++0x00
|
|
line.byte 0x00 "NVICIP95,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI95,Priority of interrupt 95"
|
|
group.byte 0x360++0x00
|
|
line.byte 0x00 "NVICIP96,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI96,Priority of interrupt 96"
|
|
group.byte 0x361++0x00
|
|
line.byte 0x00 "NVICIP97,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI97,Priority of interrupt 97"
|
|
group.byte 0x362++0x00
|
|
line.byte 0x00 "NVICIP98,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI98,Priority of interrupt 98"
|
|
group.byte 0x363++0x00
|
|
line.byte 0x00 "NVICIP99,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI99,Priority of interrupt 99"
|
|
group.byte 0x364++0x00
|
|
line.byte 0x00 "NVICIP100,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI100,Priority of interrupt 100"
|
|
group.byte 0x365++0x00
|
|
line.byte 0x00 "NVICIP101,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI101,Priority of interrupt 101"
|
|
group.byte 0x366++0x00
|
|
line.byte 0x00 "NVICIP102,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI102,Priority of interrupt 102"
|
|
group.byte 0x367++0x00
|
|
line.byte 0x00 "NVICIP103,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI103,Priority of interrupt 103"
|
|
group.byte 0x368++0x00
|
|
line.byte 0x00 "NVICIP104,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI104,Priority of interrupt 104"
|
|
group.byte 0x369++0x00
|
|
line.byte 0x00 "NVICIP105,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI105,Priority of interrupt 105"
|
|
group.byte 0x36A++0x00
|
|
line.byte 0x00 "NVICIP106,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI106,Priority of interrupt 106"
|
|
group.byte 0x36B++0x00
|
|
line.byte 0x00 "NVICIP107,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI107,Priority of interrupt 107"
|
|
group.byte 0x36C++0x00
|
|
line.byte 0x00 "NVICIP108,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI108,Priority of interrupt 108"
|
|
group.byte 0x36D++0x00
|
|
line.byte 0x00 "NVICIP109,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI109,Priority of interrupt 109"
|
|
group.byte 0x36E++0x00
|
|
line.byte 0x00 "NVICIP110,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI110,Priority of interrupt 110"
|
|
group.byte 0x36F++0x00
|
|
line.byte 0x00 "NVICIP111,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI111,Priority of interrupt 111"
|
|
group.byte 0x370++0x00
|
|
line.byte 0x00 "NVICIP112,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI112,Priority of interrupt 112"
|
|
group.byte 0x371++0x00
|
|
line.byte 0x00 "NVICIP113,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI113,Priority of interrupt 113"
|
|
group.byte 0x372++0x00
|
|
line.byte 0x00 "NVICIP114,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI114,Priority of interrupt 114"
|
|
group.byte 0x373++0x00
|
|
line.byte 0x00 "NVICIP115,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI115,Priority of interrupt 115"
|
|
group.byte 0x374++0x00
|
|
line.byte 0x00 "NVICIP116,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI116,Priority of interrupt 116"
|
|
group.byte 0x375++0x00
|
|
line.byte 0x00 "NVICIP117,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI117,Priority of interrupt 117"
|
|
group.byte 0x376++0x00
|
|
line.byte 0x00 "NVICIP118,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI118,Priority of interrupt 118"
|
|
group.byte 0x377++0x00
|
|
line.byte 0x00 "NVICIP119,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI119,Priority of interrupt 119"
|
|
group.byte 0x378++0x00
|
|
line.byte 0x00 "NVICIP120,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI120,Priority of interrupt 120"
|
|
group.byte 0x379++0x00
|
|
line.byte 0x00 "NVICIP121,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI121,Priority of interrupt 121"
|
|
group.byte 0x37A++0x00
|
|
line.byte 0x00 "NVICIP122,Interrupt Priority Register n"
|
|
hexmask.byte 0x00 0.--7. 1. "PRI122,Priority of interrupt 122"
|
|
wgroup.long 0xE00++0x03
|
|
line.long 0x00 "NVICSTIR,Software Trigger Interrupt Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "INTID,Interrupt ID of the interrupt to trigger in the range 0-239"
|
|
endif
|
|
tree.end
|
|
tree "MCM (Core Platform Miscellaneous Control Module)"
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
base ad:0xF0003000
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration"
|
|
hexmask.word.byte 0x00 0.--7. 1. "ASC,Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port"
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "PLAMC,Crossbar Switch (AXBS) Master Configuration"
|
|
hexmask.word.byte 0x00 0.--7. 1. "AMC,Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CPCR,Core Platform Control Register"
|
|
bitfld.long 0x00 30. "SRAMLWP,SRAM_L Write Protect" "0,1"
|
|
bitfld.long 0x00 28.--29. "SRAMLAP,SRAM_L Arbitration Priority" "0: Round robin,1: Special round robin (favors SRAM backdoor..,2: Fixed priority,3: Fixed priority"
|
|
newline
|
|
bitfld.long 0x00 26. "SRAMUWP,SRAM_U Write Protect" "0,1"
|
|
bitfld.long 0x00 24.--25. "SRAMUAP,SRAM_U Arbitration Priority" "0: Round robin,1: Special round robin (favors SRAM backdoor..,2: Fixed priority,3: Fixed priority"
|
|
newline
|
|
bitfld.long 0x00 9. "CBRR,Crossbar Round-robin Arbitration Enable" "0: Fixed-priority arbitration,1: Round-robin arbitration"
|
|
rbitfld.long 0x00 6. "PBRIDGE_IDLE,Peripheral Bridge Idle" "0: PBRIDGE is not idle,1: PBRIDGE is currently idle"
|
|
newline
|
|
rbitfld.long 0x00 4. "FMC_PF_IDLE,Flash Memory Controller Program Flash Idle" "0: FMC program flash is not idle,1: FMC program flash is currently idle"
|
|
rbitfld.long 0x00 3. "AXBS_HLTD,AXBS Halted" "0: AXBS is not currently halted,1: AXBS is currently halted"
|
|
newline
|
|
rbitfld.long 0x00 2. "AXBS_HLT_REQ,AXBS Halt Request" "0: AXBS is not receiving halt request,1: AXBS is receiving halt request"
|
|
rbitfld.long 0x00 0.--1. "HLT_FSM_ST,AXBS Halt State Machine Status" "0: Waiting for request,1: Waiting for platform idle,2: Unused state,3: Platform stalled"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CPCR,Core Platform Control Register"
|
|
bitfld.long 0x00 9. "CBRR,Crossbar Round-robin Arbitration Enable" "0: Fixed-priority arbitration,1: Round-robin arbitration"
|
|
rbitfld.long 0x00 6. "PBRIDGE_IDLE,Peripheral Bridge Idle" "0: PBRIDGE is not idle,1: PBRIDGE is currently idle"
|
|
newline
|
|
rbitfld.long 0x00 4. "FMC_PF_IDLE,Flash Memory Controller Program Flash Idle" "0: FMC program flash is not idle,1: FMC program flash is currently idle"
|
|
rbitfld.long 0x00 3. "AXBS_HLTD,AXBS Halted" "0: AXBS is not currently halted,1: AXBS is currently halted"
|
|
newline
|
|
rbitfld.long 0x00 2. "AXBS_HLT_REQ,AXBS Halt Request" "0: AXBS is not receiving halt request,1: AXBS is receiving halt request"
|
|
rbitfld.long 0x00 0.--1. "HLT_FSM_ST,AXBS Halt State Machine Status" "0: Waiting for request,1: Waiting for platform idle,2: Unused state,3: Platform stalled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ISCR,Interrupt Status and Control Register"
|
|
bitfld.long 0x00 31. "FIDCE,FPU Input Denormal Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 28. "FIXCE,FPU Inexact Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x00 27. "FUFCE,FPU Underflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 26. "FOFCE,FPU Overflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x00 25. "FDZCE,FPU Divide-by-Zero Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 24. "FIOCE,FPU Invalid Operation Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
rbitfld.long 0x00 15. "FIDC,FPU Input Denormal Interrupt Status" "0: No interrupt,1: Interrupt occurred"
|
|
rbitfld.long 0x00 12. "FIXC,FPU Inexact Interrupt Status" "0: No interrupt,1: Interrupt occurred"
|
|
newline
|
|
rbitfld.long 0x00 11. "FUFC,FPU Underflow Interrupt Status" "0: No interrupt,1: Interrupt occurred"
|
|
rbitfld.long 0x00 10. "FOFC,FPU Overflow Interrupt Status" "0: No interrupt,1: Interrupt occurred"
|
|
newline
|
|
rbitfld.long 0x00 9. "FDZC,FPU Divide-by-Zero Interrupt Status" "0: No interrupt,1: Interrupt occurred"
|
|
rbitfld.long 0x00 8. "FIOC,FPU Invalid Operation Interrupt Status" "0: No interrupt,1: Interrupt occurred"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PID,Process ID Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PID,M0_PID and M1_PID for MPU"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CPO,Compute Operation Control Register"
|
|
bitfld.long 0x00 2. "CPOWOI,Compute Operation Wakeup On Interrupt" "0: No effect,1: When set the CPOREQ is cleared on any.."
|
|
rbitfld.long 0x00 1. "CPOACK,Compute Operation Acknowledge" "0: Compute operation entry has not completed or..,1: Compute operation entry has completed or.."
|
|
newline
|
|
bitfld.long 0x00 0. "CPOREQ,Compute Operation Request" "0: Request is cleared,1: Request Compute Operation"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "LMDR0,Local Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,Local Memory Valid" "0: LMEMn is not present,1: LMEMn is present"
|
|
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "LMSZ,LMEM Size" "0: no LMEMn (0 KB),1: 1 KB LMEMn,2: 2 KB LMEMn,3: 4 KB LMEMn,4: 8 KB LMEMn,5: 16 KB LMEMn,6: 32 KB LMEMn,7: 64 KB LMEMn,8: 128 KB LMEMn,9: 256 KB LMEMn,10: 512 KB LMEMn,11: 1024 KB LMEMn,12: 2048 KB LMEMn,13: 4096 KB LMEMn,14: 8192 KB LMEMn,15: 16384 KB LMEMn"
|
|
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No Cache,?,2: 2-Way Set Associative,?,4: 4-Way Set Associative,?..."
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "DPW,LMEM Data Path Width" "?,?,2: LMEMn 32-bits wide,3: LMEMn 64-bits wide,?..."
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0: Writes to the LMDRn[7:0] are allowed,1: Writes to the LMDRn[7:0] are ignored"
|
|
newline
|
|
rbitfld.long 0x00 13.--15. "MT,Memory Type" "0: SRAM_L,1: SRAM_U,?..."
|
|
bitfld.long 0x00 0.--3. "CF0,Control Field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "LMDR0,Local Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,Local Memory Valid" "0: LMEMn is not present,1: LMEMn is present"
|
|
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "LMSZ,LMEM Size" "0: no LMEMn (0 KB),1: 1 KB LMEMn,2: 2 KB LMEMn,3: 4 KB LMEMn,4: 8 KB LMEMn,5: 16 KB LMEMn,6: 32 KB LMEMn,7: 64 KB LMEMn,8: 128 KB LMEMn,9: 256 KB LMEMn,10: 512 KB LMEMn,11: 1024 KB LMEMn,12: 2048 KB LMEMn,13: 4096 KB LMEMn,14: 8192 KB LMEMn,15: 16384 KB LMEMn"
|
|
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No Cache,?,2: 2-Way Set Associative,?,4: 4-Way Set Associative,?..."
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "DPW,LMEM Data Path Width" "?,?,2: LMEMn 32-bits wide,3: LMEMn 64-bits wide,?..."
|
|
rbitfld.long 0x00 13.--15. "MT,Memory Type" "0: SRAM_L,1: SRAM_U,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "CF0,Control Field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "LMDR1,Local Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,Local Memory Valid" "0: LMEMn is not present,1: LMEMn is present"
|
|
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "LMSZ,LMEM Size" "0: no LMEMn (0 KB),1: 1 KB LMEMn,2: 2 KB LMEMn,3: 4 KB LMEMn,4: 8 KB LMEMn,5: 16 KB LMEMn,6: 32 KB LMEMn,7: 64 KB LMEMn,8: 128 KB LMEMn,9: 256 KB LMEMn,10: 512 KB LMEMn,11: 1024 KB LMEMn,12: 2048 KB LMEMn,13: 4096 KB LMEMn,14: 8192 KB LMEMn,15: 16384 KB LMEMn"
|
|
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No Cache,?,2: 2-Way Set Associative,?,4: 4-Way Set Associative,?..."
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "DPW,LMEM Data Path Width" "?,?,2: LMEMn 32-bits wide,3: LMEMn 64-bits wide,?..."
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0: Writes to the LMDRn[7:0] are allowed,1: Writes to the LMDRn[7:0] are ignored"
|
|
newline
|
|
rbitfld.long 0x00 13.--15. "MT,Memory Type" "0: SRAM_L,1: SRAM_U,?..."
|
|
bitfld.long 0x00 0.--3. "CF0,Control Field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "LMDR1,Local Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,Local Memory Valid" "0: LMEMn is not present,1: LMEMn is present"
|
|
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "LMSZ,LMEM Size" "0: no LMEMn (0 KB),1: 1 KB LMEMn,2: 2 KB LMEMn,3: 4 KB LMEMn,4: 8 KB LMEMn,5: 16 KB LMEMn,6: 32 KB LMEMn,7: 64 KB LMEMn,8: 128 KB LMEMn,9: 256 KB LMEMn,10: 512 KB LMEMn,11: 1024 KB LMEMn,12: 2048 KB LMEMn,13: 4096 KB LMEMn,14: 8192 KB LMEMn,15: 16384 KB LMEMn"
|
|
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No Cache,?,2: 2-Way Set Associative,?,4: 4-Way Set Associative,?..."
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "DPW,LMEM Data Path Width" "?,?,2: LMEMn 32-bits wide,3: LMEMn 64-bits wide,?..."
|
|
rbitfld.long 0x00 13.--15. "MT,Memory Type" "0: SRAM_L,1: SRAM_U,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "CF0,Control Field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "LMDR2,Local Memory Descriptor Register2"
|
|
rbitfld.long 0x00 31. "V,Local Memory Valid" "0: LMEMn is not present,1: LMEMn is present"
|
|
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "LMSZ,LMEM Size" "?,?,?,?,4: 4 KB LMEMn,?..."
|
|
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No Cache,?,2: 2-Way Set Associative,?,4: 4-Way Set Associative,?..."
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "DPW,LMEM Data Path Width" "?,?,2: LMEMn 32-bits wide,3: LMEMn 64-bits wide,?..."
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0: Writes to the LMDRn[7:0] are allowed,1: Writes to the LMDRn[7:0] are ignored"
|
|
newline
|
|
rbitfld.long 0x00 13.--15. "MT,Memory Type" "?,?,2: PC Cache,?..."
|
|
bitfld.long 0x00 4.--7. "CF1,Control Field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "LMDR2,Local Memory Descriptor Register2"
|
|
rbitfld.long 0x00 31. "V,Local Memory Valid" "0: LMEMn is not present,1: LMEMn is present"
|
|
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "LMSZ,LMEM Size" "?,?,?,?,4: 4 KB LMEMn,?..."
|
|
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No Cache,?,2: 2-Way Set Associative,?,4: 4-Way Set Associative,?..."
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "DPW,LMEM Data Path Width" "?,?,2: LMEMn 32-bits wide,3: LMEMn 64-bits wide,?..."
|
|
rbitfld.long 0x00 13.--15. "MT,Memory Type" "?,?,2: PC Cache,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CF1,Control Field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "LMPECR,LMEM Parity and ECC Control Register"
|
|
bitfld.long 0x00 20. "ECPR,Enable Cache Parity Reporting" "0: Reporting disabled,1: Reporting enabled"
|
|
bitfld.long 0x00 8. "ER1BR,Enable RAM ECC 1 Bit Reporting" "0: Reporting disabled,1: Reporting enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ERNCR,Enable RAM ECC Noncorrectable Reporting" "0: Reporting disabled,1: Reporting enabled"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "LMPECR,LMEM Parity and ECC Control Register"
|
|
bitfld.long 0x00 8. "ER1BR,Enable RAM ECC 1 Bit Reporting" "0: Reporting disabled,1: Reporting enabled"
|
|
bitfld.long 0x00 0. "ERNCR,Enable RAM ECC Noncorrectable Reporting" "0: Reporting disabled,1: Reporting enabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "LMPEIR,LMEM Parity and ECC Interrupt Register"
|
|
rbitfld.long 0x00 31. "V,Valid Bit" "0,1"
|
|
rbitfld.long 0x00 24.--28. "PEELOC,Parity or ECC Error Location" "0: Non-correctable ECC event from SRAM_L,1: Non-correctable ECC event from SRAM_U,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "PE,Cache Parity Error"
|
|
hexmask.long.byte 0x00 8.--15. 1. "E1B,E1Bn = ECC 1-bit Error n"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "ENC,ENCn = ECC Noncorrectable Error n"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "LMPEIR,LMEM Parity and ECC Interrupt Register"
|
|
rbitfld.long 0x00 31. "V,Valid Bit" "0,1"
|
|
rbitfld.long 0x00 24.--28. "PEELOC,Parity or ECC Error Location" "0: Non-correctable ECC event from SRAM_L,1: Non-correctable ECC event from SRAM_U,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "E1B,E1Bn = ECC 1-bit Error n"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ENC,ENCn = ECC Noncorrectable Error n"
|
|
endif
|
|
rgroup.long 0x490++0x03
|
|
line.long 0x00 "LMFAR,LMEM Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "EFADD,ECC Fault Address"
|
|
rgroup.long 0x494++0x03
|
|
line.long 0x00 "LMFATR,LMEM Fault Attribute Register"
|
|
bitfld.long 0x00 31. "OVR,Overrun" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "PEFMST,Parity/ECC Fault Master Number"
|
|
newline
|
|
bitfld.long 0x00 7. "PEFW,Parity/ECC Fault" "0,1"
|
|
bitfld.long 0x00 4.--6. "PEFSIZE,Parity/ECC Fault Master Size" "0: 8-bit access,1: 16-bit access,2: 32-bit access,3: 64-bit access,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "PEFPRT,Parity/ECC Fault Protection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x4A0++0x03
|
|
line.long 0x00 "LMFDHR,LMEM Fault Data High Register"
|
|
hexmask.long 0x00 0.--31. 1. "PEFDH,Parity or ECC Fault Data High"
|
|
rgroup.long 0x4A4++0x03
|
|
line.long 0x00 "LMFDLR,LMEM Fault Data Low Register"
|
|
hexmask.long 0x00 0.--31. 1. "PEFDL,Parity or ECC Fault Data Low"
|
|
elif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
base ad:0xE0080000
|
|
rgroup.word 0x08++0x01
|
|
line.word 0x00 "PLASC,Crossbar Switch (AXBS) Slave Configuration"
|
|
hexmask.word.byte 0x00 0.--7. 1. "ASC,Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port"
|
|
rgroup.word 0x0A++0x01
|
|
line.word 0x00 "PLAMC,Crossbar Switch (AXBS) Master Configuration"
|
|
hexmask.word.byte 0x00 0.--7. 1. "AMC,Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CPCR,Core Platform Control Register"
|
|
bitfld.long 0x00 30. "SRAMLWP,SRAM_L Write Protect" "0,1"
|
|
bitfld.long 0x00 28.--29. "SRAMLAP,SRAM_L Arbitration Priority" "0: Round robin,1: Special round robin (favors SRAM backdoor..,2: Fixed priority,3: Fixed priority"
|
|
newline
|
|
bitfld.long 0x00 26. "SRAMUWP,SRAM_U Write Protect" "0,1"
|
|
bitfld.long 0x00 24.--25. "SRAMUAP,SRAM_U Arbitration Priority" "0: Round robin,1: Special round robin (favors SRAM backdoor..,2: Fixed priority,3: Fixed priority"
|
|
newline
|
|
bitfld.long 0x00 9. "CBRR,Crossbar Round-robin Arbitration Enable" "0: Fixed-priority arbitration,1: Round-robin arbitration"
|
|
rbitfld.long 0x00 6. "PBRIDGE_IDLE,Peripheral Bridge Idle" "0: PBRIDGE is not idle,1: PBRIDGE is currently idle"
|
|
newline
|
|
rbitfld.long 0x00 4. "FMC_PF_IDLE,Flash Memory Controller Program Flash Idle" "0: FMC program flash is not idle,1: FMC program flash is currently idle"
|
|
rbitfld.long 0x00 3. "AXBS_HLTD,AXBS Halted" "0: AXBS is not currently halted,1: AXBS is currently halted"
|
|
newline
|
|
rbitfld.long 0x00 2. "AXBS_HLT_REQ,AXBS Halt Request" "0: AXBS is not receiving halt request,1: AXBS is receiving halt request"
|
|
rbitfld.long 0x00 0.--1. "HLT_FSM_ST,AXBS Halt State Machine Status" "0: Waiting for request,1: Waiting for platform idle,2: Unused state,3: Platform stalled"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "CPCR,Core Platform Control Register"
|
|
bitfld.long 0x00 9. "CBRR,Crossbar Round-robin Arbitration Enable" "0: Fixed-priority arbitration,1: Round-robin arbitration"
|
|
rbitfld.long 0x00 6. "PBRIDGE_IDLE,Peripheral Bridge Idle" "0: PBRIDGE is not idle,1: PBRIDGE is currently idle"
|
|
newline
|
|
rbitfld.long 0x00 4. "FMC_PF_IDLE,Flash Memory Controller Program Flash Idle" "0: FMC program flash is not idle,1: FMC program flash is currently idle"
|
|
rbitfld.long 0x00 3. "AXBS_HLTD,AXBS Halted" "0: AXBS is not currently halted,1: AXBS is currently halted"
|
|
newline
|
|
rbitfld.long 0x00 2. "AXBS_HLT_REQ,AXBS Halt Request" "0: AXBS is not receiving halt request,1: AXBS is receiving halt request"
|
|
rbitfld.long 0x00 0.--1. "HLT_FSM_ST,AXBS Halt State Machine Status" "0: Waiting for request,1: Waiting for platform idle,2: Unused state,3: Platform stalled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "ISCR,Interrupt Status and Control Register"
|
|
bitfld.long 0x00 31. "FIDCE,FPU Input Denormal Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 28. "FIXCE,FPU Inexact Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x00 27. "FUFCE,FPU Underflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 26. "FOFCE,FPU Overflow Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x00 25. "FDZCE,FPU Divide-by-Zero Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x00 24. "FIOCE,FPU Invalid Operation Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
rbitfld.long 0x00 15. "FIDC,FPU Input Denormal Interrupt Status" "0: No interrupt,1: Interrupt occurred"
|
|
rbitfld.long 0x00 12. "FIXC,FPU Inexact Interrupt Status" "0: No interrupt,1: Interrupt occurred"
|
|
newline
|
|
rbitfld.long 0x00 11. "FUFC,FPU Underflow Interrupt Status" "0: No interrupt,1: Interrupt occurred"
|
|
rbitfld.long 0x00 10. "FOFC,FPU Overflow Interrupt Status" "0: No interrupt,1: Interrupt occurred"
|
|
newline
|
|
rbitfld.long 0x00 9. "FDZC,FPU Divide-by-Zero Interrupt Status" "0: No interrupt,1: Interrupt occurred"
|
|
rbitfld.long 0x00 8. "FIOC,FPU Invalid Operation Interrupt Status" "0: No interrupt,1: Interrupt occurred"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "PID,Process ID Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "PID,M0_PID and M1_PID for MPU"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CPO,Compute Operation Control Register"
|
|
bitfld.long 0x00 2. "CPOWOI,Compute Operation Wakeup On Interrupt" "0: No effect,1: When set the CPOREQ is cleared on any.."
|
|
rbitfld.long 0x00 1. "CPOACK,Compute Operation Acknowledge" "0: Compute operation entry has not completed or..,1: Compute operation entry has completed or.."
|
|
newline
|
|
bitfld.long 0x00 0. "CPOREQ,Compute Operation Request" "0: Request is cleared,1: Request Compute Operation"
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "LMDR0,Local Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,Local Memory Valid" "0: LMEMn is not present,1: LMEMn is present"
|
|
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "LMSZ,LMEM Size" "0: no LMEMn (0 KB),1: 1 KB LMEMn,2: 2 KB LMEMn,3: 4 KB LMEMn,4: 8 KB LMEMn,5: 16 KB LMEMn,6: 32 KB LMEMn,7: 64 KB LMEMn,8: 128 KB LMEMn,9: 256 KB LMEMn,10: 512 KB LMEMn,11: 1024 KB LMEMn,12: 2048 KB LMEMn,13: 4096 KB LMEMn,14: 8192 KB LMEMn,15: 16384 KB LMEMn"
|
|
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No Cache,?,2: 2-Way Set Associative,?,4: 4-Way Set Associative,?..."
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "DPW,LMEM Data Path Width" "?,?,2: LMEMn 32-bits wide,3: LMEMn 64-bits wide,?..."
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0: Writes to the LMDRn[7:0] are allowed,1: Writes to the LMDRn[7:0] are ignored"
|
|
newline
|
|
rbitfld.long 0x00 13.--15. "MT,Memory Type" "0: SRAM_L,1: SRAM_U,?..."
|
|
bitfld.long 0x00 0.--3. "CF0,Control Field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "LMDR0,Local Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,Local Memory Valid" "0: LMEMn is not present,1: LMEMn is present"
|
|
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "LMSZ,LMEM Size" "0: no LMEMn (0 KB),1: 1 KB LMEMn,2: 2 KB LMEMn,3: 4 KB LMEMn,4: 8 KB LMEMn,5: 16 KB LMEMn,6: 32 KB LMEMn,7: 64 KB LMEMn,8: 128 KB LMEMn,9: 256 KB LMEMn,10: 512 KB LMEMn,11: 1024 KB LMEMn,12: 2048 KB LMEMn,13: 4096 KB LMEMn,14: 8192 KB LMEMn,15: 16384 KB LMEMn"
|
|
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No Cache,?,2: 2-Way Set Associative,?,4: 4-Way Set Associative,?..."
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "DPW,LMEM Data Path Width" "?,?,2: LMEMn 32-bits wide,3: LMEMn 64-bits wide,?..."
|
|
rbitfld.long 0x00 13.--15. "MT,Memory Type" "0: SRAM_L,1: SRAM_U,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "CF0,Control Field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "LMDR1,Local Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,Local Memory Valid" "0: LMEMn is not present,1: LMEMn is present"
|
|
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "LMSZ,LMEM Size" "0: no LMEMn (0 KB),1: 1 KB LMEMn,2: 2 KB LMEMn,3: 4 KB LMEMn,4: 8 KB LMEMn,5: 16 KB LMEMn,6: 32 KB LMEMn,7: 64 KB LMEMn,8: 128 KB LMEMn,9: 256 KB LMEMn,10: 512 KB LMEMn,11: 1024 KB LMEMn,12: 2048 KB LMEMn,13: 4096 KB LMEMn,14: 8192 KB LMEMn,15: 16384 KB LMEMn"
|
|
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No Cache,?,2: 2-Way Set Associative,?,4: 4-Way Set Associative,?..."
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "DPW,LMEM Data Path Width" "?,?,2: LMEMn 32-bits wide,3: LMEMn 64-bits wide,?..."
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0: Writes to the LMDRn[7:0] are allowed,1: Writes to the LMDRn[7:0] are ignored"
|
|
newline
|
|
rbitfld.long 0x00 13.--15. "MT,Memory Type" "0: SRAM_L,1: SRAM_U,?..."
|
|
bitfld.long 0x00 0.--3. "CF0,Control Field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "LMDR1,Local Memory Descriptor Register"
|
|
rbitfld.long 0x00 31. "V,Local Memory Valid" "0: LMEMn is not present,1: LMEMn is present"
|
|
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "LMSZ,LMEM Size" "0: no LMEMn (0 KB),1: 1 KB LMEMn,2: 2 KB LMEMn,3: 4 KB LMEMn,4: 8 KB LMEMn,5: 16 KB LMEMn,6: 32 KB LMEMn,7: 64 KB LMEMn,8: 128 KB LMEMn,9: 256 KB LMEMn,10: 512 KB LMEMn,11: 1024 KB LMEMn,12: 2048 KB LMEMn,13: 4096 KB LMEMn,14: 8192 KB LMEMn,15: 16384 KB LMEMn"
|
|
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No Cache,?,2: 2-Way Set Associative,?,4: 4-Way Set Associative,?..."
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "DPW,LMEM Data Path Width" "?,?,2: LMEMn 32-bits wide,3: LMEMn 64-bits wide,?..."
|
|
rbitfld.long 0x00 13.--15. "MT,Memory Type" "0: SRAM_L,1: SRAM_U,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "CF0,Control Field 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "LMDR2,Local Memory Descriptor Register2"
|
|
rbitfld.long 0x00 31. "V,Local Memory Valid" "0: LMEMn is not present,1: LMEMn is present"
|
|
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "LMSZ,LMEM Size" "?,?,?,?,4: 4 KB LMEMn,?..."
|
|
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No Cache,?,2: 2-Way Set Associative,?,4: 4-Way Set Associative,?..."
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "DPW,LMEM Data Path Width" "?,?,2: LMEMn 32-bits wide,3: LMEMn 64-bits wide,?..."
|
|
bitfld.long 0x00 16. "LOCK,LOCK" "0: Writes to the LMDRn[7:0] are allowed,1: Writes to the LMDRn[7:0] are ignored"
|
|
newline
|
|
rbitfld.long 0x00 13.--15. "MT,Memory Type" "?,?,2: PC Cache,?..."
|
|
bitfld.long 0x00 4.--7. "CF1,Control Field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "LMDR2,Local Memory Descriptor Register2"
|
|
rbitfld.long 0x00 31. "V,Local Memory Valid" "0: LMEMn is not present,1: LMEMn is present"
|
|
rbitfld.long 0x00 28. "LMSZH,LMEM Size Hole" "0: LMEMn is a power-of-2 capacity,1: LMEMn is not a power-of-2 with a capacity is.."
|
|
newline
|
|
rbitfld.long 0x00 24.--27. "LMSZ,LMEM Size" "?,?,?,?,4: 4 KB LMEMn,?..."
|
|
rbitfld.long 0x00 20.--23. "WY,Level 1 Cache Ways" "0: No Cache,?,2: 2-Way Set Associative,?,4: 4-Way Set Associative,?..."
|
|
newline
|
|
rbitfld.long 0x00 17.--19. "DPW,LMEM Data Path Width" "?,?,2: LMEMn 32-bits wide,3: LMEMn 64-bits wide,?..."
|
|
rbitfld.long 0x00 13.--15. "MT,Memory Type" "?,?,2: PC Cache,?..."
|
|
newline
|
|
bitfld.long 0x00 4.--7. "CF1,Control Field 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "LMPECR,LMEM Parity and ECC Control Register"
|
|
bitfld.long 0x00 20. "ECPR,Enable Cache Parity Reporting" "0: Reporting disabled,1: Reporting enabled"
|
|
bitfld.long 0x00 8. "ER1BR,Enable RAM ECC 1 Bit Reporting" "0: Reporting disabled,1: Reporting enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ERNCR,Enable RAM ECC Noncorrectable Reporting" "0: Reporting disabled,1: Reporting enabled"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x480++0x03
|
|
line.long 0x00 "LMPECR,LMEM Parity and ECC Control Register"
|
|
bitfld.long 0x00 8. "ER1BR,Enable RAM ECC 1 Bit Reporting" "0: Reporting disabled,1: Reporting enabled"
|
|
bitfld.long 0x00 0. "ERNCR,Enable RAM ECC Noncorrectable Reporting" "0: Reporting disabled,1: Reporting enabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "LMPEIR,LMEM Parity and ECC Interrupt Register"
|
|
rbitfld.long 0x00 31. "V,Valid Bit" "0,1"
|
|
rbitfld.long 0x00 24.--28. "PEELOC,Parity or ECC Error Location" "0: Non-correctable ECC event from SRAM_L,1: Non-correctable ECC event from SRAM_U,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 16.--23. 1. "PE,Cache Parity Error"
|
|
hexmask.long.byte 0x00 8.--15. 1. "E1B,E1Bn = ECC 1-bit Error n"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "ENC,ENCn = ECC Noncorrectable Error n"
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
group.long 0x488++0x03
|
|
line.long 0x00 "LMPEIR,LMEM Parity and ECC Interrupt Register"
|
|
rbitfld.long 0x00 31. "V,Valid Bit" "0,1"
|
|
rbitfld.long 0x00 24.--28. "PEELOC,Parity or ECC Error Location" "0: Non-correctable ECC event from SRAM_L,1: Non-correctable ECC event from SRAM_U,?..."
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "E1B,E1Bn = ECC 1-bit Error n"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ENC,ENCn = ECC Noncorrectable Error n"
|
|
endif
|
|
rgroup.long 0x490++0x03
|
|
line.long 0x00 "LMFAR,LMEM Fault Address Register"
|
|
hexmask.long 0x00 0.--31. 1. "EFADD,ECC Fault Address"
|
|
rgroup.long 0x494++0x03
|
|
line.long 0x00 "LMFATR,LMEM Fault Attribute Register"
|
|
bitfld.long 0x00 31. "OVR,Overrun" "0,1"
|
|
hexmask.long.byte 0x00 8.--15. 1. "PEFMST,Parity/ECC Fault Master Number"
|
|
newline
|
|
bitfld.long 0x00 7. "PEFW,Parity/ECC Fault" "0,1"
|
|
bitfld.long 0x00 4.--6. "PEFSIZE,Parity/ECC Fault Master Size" "0: 8-bit access,1: 16-bit access,2: 32-bit access,3: 64-bit access,?..."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "PEFPRT,Parity/ECC Fault Protection" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x4A0++0x03
|
|
line.long 0x00 "LMFDHR,LMEM Fault Data High Register"
|
|
hexmask.long 0x00 0.--31. 1. "PEFDH,Parity or ECC Fault Data High"
|
|
rgroup.long 0x4A4++0x03
|
|
line.long 0x00 "LMFDLR,LMEM Fault Data Low Register"
|
|
hexmask.long 0x00 0.--31. 1. "PEFDL,Parity or ECC Fault Data Low"
|
|
endif
|
|
tree.end
|
|
tree "LMEM (Local Memory Controller)"
|
|
base ad:0xE0082000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "LMEM_PCCCR,Cache control register"
|
|
bitfld.long 0x00 31. "GO,Initiate Cache Command" "0: Write: no effect,1: Write: initiate command indicated by bits 27-24"
|
|
bitfld.long 0x00 27. "PUSHW1,Push Way 1" "0: No operation,1: When setting the GO bit push all modified.."
|
|
newline
|
|
bitfld.long 0x00 26. "INVW1,Invalidate Way 1" "0: No operation,1: When setting the GO bit invalidate all lines.."
|
|
bitfld.long 0x00 25. "PUSHW0,Push Way 0" "0: No operation,1: When setting the GO bit push all modified.."
|
|
newline
|
|
bitfld.long 0x00 24. "INVW0,Invalidate Way 0" "0: No operation,1: When setting the GO bit invalidate all lines.."
|
|
bitfld.long 0x00 3. "PCCR3,Forces no allocation on cache misses (must also have PCCR2 asserted)" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "PCCR2,Forces all cacheable spaces to write through" "0,1"
|
|
bitfld.long 0x00 0. "ENCACHE,Cache enable" "0: Cache disabled,1: Cache enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "LMEM_PCCLCR,Cache line control register"
|
|
bitfld.long 0x00 27. "LACC,Line access type" "0: ,1: "
|
|
bitfld.long 0x00 26. "LADSEL,Line Address Select" "0: Cache address,1: Physical address"
|
|
newline
|
|
bitfld.long 0x00 24.--25. "LCMD,Line Command" "0: Search and read or write,1: Invalidate,2: Push,3: Clear"
|
|
bitfld.long 0x00 22. "LCWAY,Line Command Way" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "LCIMB,Line Command Initial Modified Bit" "0,1"
|
|
bitfld.long 0x00 20. "LCIVB,Line Command Initial Valid Bit" "0,1"
|
|
newline
|
|
bitfld.long 0x00 16. "TDSEL,Tag/Data Select" "0: Data,1: Tag"
|
|
bitfld.long 0x00 14. "WSEL,Way select" "0: Way 0,1: Way 1"
|
|
newline
|
|
hexmask.long.word 0x00 2.--13. 1. "CACHEADDR,Cache address"
|
|
bitfld.long 0x00 0. "LGO,Initiate Cache Line Command" "0: Write: no effect,1: Write: initiate line command indicated by.."
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "LMEM_PCCSAR,Cache search address register"
|
|
hexmask.long 0x00 2.--31. 1. "PHYADDR,Physical Address"
|
|
bitfld.long 0x00 0. "LGO,Initiate Cache Line Command" "0: Write: no effect,1: Write: initiate line command indicated by.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "LMEM_PCCCVR,Cache read/write value register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Cache read/write Data"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "PCCRMR,Cache regions mode register"
|
|
bitfld.long 0x00 30.--31. "R0,Region 0 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
bitfld.long 0x00 28.--29. "R1,Region 1 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
newline
|
|
bitfld.long 0x00 26.--27. "R2,Region 2 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
bitfld.long 0x00 24.--25. "R3,Region 3 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
newline
|
|
bitfld.long 0x00 22.--23. "R4,Region 4 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
bitfld.long 0x00 20.--21. "R5,Region 5 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
newline
|
|
bitfld.long 0x00 18.--19. "R6,Region 6 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
bitfld.long 0x00 16.--17. "R7,Region 7 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
newline
|
|
bitfld.long 0x00 14.--15. "R8,Region 8 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
bitfld.long 0x00 12.--13. "R9,Region 9 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
newline
|
|
bitfld.long 0x00 10.--11. "R10,Region 10 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
bitfld.long 0x00 8.--9. "R11,Region 11 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
newline
|
|
bitfld.long 0x00 6.--7. "R12,Region 12 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
bitfld.long 0x00 4.--5. "R13,Region 13 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
newline
|
|
bitfld.long 0x00 2.--3. "R14,Region 14 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
bitfld.long 0x00 0.--1. "R15,Region 15 mode" "0: Non-cacheable,1: Non-cacheable,2: Write-through,3: Write-back"
|
|
tree.end
|
|
sif cpuis("S32K148")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")
|
|
tree "CAN (Flex Controller Area Network module)"
|
|
tree "CAN0"
|
|
base ad:0x40024000
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. "MDIS,Module Disable" "0: Enable the FlexCAN module,1: Disable the FlexCAN module"
|
|
bitfld.long 0x00 30. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode,1: Enabled to enter Freeze mode"
|
|
newline
|
|
bitfld.long 0x00 29. "RFEN,Rx FIFO Enable" "0: Rx FIFO not enabled,1: Rx FIFO enabled"
|
|
bitfld.long 0x00 28. "HALT,Halt FlexCAN" "0: No Freeze mode request,1: Enters Freeze mode if the FRZ bit is asserted"
|
|
newline
|
|
rbitfld.long 0x00 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN module is either in Normal mode..,?..."
|
|
bitfld.long 0x00 25. "SOFTRST,Soft Reset" "0: No reset request,1: Resets the registers affected by soft reset"
|
|
newline
|
|
rbitfld.long 0x00 24. "FRZACK,Freeze Mode Acknowledge" "0: FlexCAN not in Freeze mode prescaler running,1: FlexCAN in Freeze mode prescaler stopped"
|
|
bitfld.long 0x00 23. "SUPV,Supervisor Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WRNEN,Warning Interrupt Enable" "0: TWRNINT and RWRNINT bits are zero independent..,1: TWRNINT and RWRNINT bits are set when the.."
|
|
rbitfld.long 0x00 20. "LPMACK,Low-Power Mode Acknowledge" "0: FlexCAN is not in a low-power mode,1: FlexCAN is in a low-power mode"
|
|
newline
|
|
bitfld.long 0x00 17. "SRXDIS,Self Reception Disable" "0: Self reception enabled,1: Self reception disabled"
|
|
bitfld.long 0x00 16. "IRMQ,Individual Rx Masking And Queue Enable" "0: Individual Rx masking and queue feature are..,1: Individual Rx masking and queue feature are.."
|
|
newline
|
|
bitfld.long 0x00 15. "DMA,DMA Enable" "0: DMA feature for RX FIFO disabled,1: DMA feature for RX FIFO enabled"
|
|
bitfld.long 0x00 14. "PNET_EN,Pretended Networking Enable" "0: Pretended Networking mode is disabled,1: Pretended Networking mode is enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "LPRIOEN,Local Priority Enable" "0: Local Priority disabled,1: Local Priority enabled"
|
|
bitfld.long 0x00 12. "AEN,Abort Enable" "0: Abort disabled,1: Abort enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FDEN,CAN FD operation enable" "0: CAN FD is disabled,1: CAN FD is enabled"
|
|
bitfld.long 0x00 8.--9. "IDAM,ID Acceptance Mode" "0: Format A,1: Format B,2: Format C,3: Format D"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB,Number Of The Last Message Buffer"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRESDIV,Prescaler Division Factor"
|
|
bitfld.long 0x00 22.--23. "RJW,Resync Jump Width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Bus Off interrupt disabled,1: Bus Off interrupt enabled"
|
|
bitfld.long 0x00 14. "ERRMSK,Error Interrupt Mask" "0: Error interrupt disabled,1: Error interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "CLKSRC,CAN Engine Clock Source" "0: The CAN engine clock source is the oscillator..,1: The CAN engine clock source is the peripheral.."
|
|
bitfld.long 0x00 12. "LPB,Loop Back Mode" "0: Loop Back disabled,1: Loop Back enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TWRNMSK,Tx Warning Interrupt Mask" "0: Tx Warning Interrupt disabled,1: Tx Warning Interrupt enabled"
|
|
bitfld.long 0x00 10. "RWRNMSK,Rx Warning Interrupt Mask" "0: Rx Warning Interrupt disabled,1: Rx Warning Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SMP,CAN Bit Sampling" "0: Just one sample is used to determine the bit..,1: Three samples are used to determine the value.."
|
|
bitfld.long 0x00 6. "BOFFREC,Bus Off Recovery" "0: Automatic recovering from Bus Off state enabled,1: Automatic recovering from Bus Off state.."
|
|
newline
|
|
bitfld.long 0x00 5. "TSYN,Timer Sync" "0: Timer Sync feature disabled,1: Timer Sync feature enabled"
|
|
bitfld.long 0x00 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted..,1: Lowest number buffer is transmitted first"
|
|
newline
|
|
bitfld.long 0x00 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated,1: FlexCAN module operates in Listen-Only mode"
|
|
bitfld.long 0x00 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMER,Free Running Timer"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMER,Timer Value"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. "MG,Rx Mailboxes Global Mask Bits"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RX14MASK,Rx 14 Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "RX14M,Rx Buffer 14 Mask Bits"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RX15MASK,Rx 15 Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "RX15M,Rx Buffer 15 Mask Bits"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ECR,Error Counter"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for fast bits"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for fast bits"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXERRCNT,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXERRCNT,Transmit Error Counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ESR1,Error and Status 1 register"
|
|
rbitfld.long 0x00 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as recessive is.."
|
|
rbitfld.long 0x00 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as dominant is received.."
|
|
newline
|
|
rbitfld.long 0x00 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A CRC error occurred since last read of this.."
|
|
rbitfld.long 0x00 27. "FRMERR_FAST,Form Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A Form Error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A Stuffing Error occurred since last read of.."
|
|
bitfld.long 0x00 21. "ERROVR,Error Overrun bit" "0: Overrun has not occurred,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 20. "ERRINT_FAST,Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: Indicates setting of any Error Bit detected.."
|
|
bitfld.long 0x00 19. "BOFFDONEINT,Bus Off Done Interrupt" "0: No such occurrence,1: FlexCAN module has completed Bus Off process"
|
|
newline
|
|
rbitfld.long 0x00 18. "SYNCH,CAN Synchronization Status" "0: FlexCAN is not synchronized to the CAN bus,1: FlexCAN is synchronized to the CAN bus"
|
|
bitfld.long 0x00 17. "TWRNINT,Tx Warning Interrupt Flag" "0: No such occurrence,1: The Tx error counter transitioned from less.."
|
|
newline
|
|
bitfld.long 0x00 16. "RWRNINT,Rx Warning Interrupt Flag" "0: No such occurrence,1: The Rx error counter transitioned from less.."
|
|
rbitfld.long 0x00 15. "BIT1ERR,Bit1 Error" "0: No such occurrence,1: At least one bit sent as recessive is.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIT0ERR,Bit0 Error" "0: No such occurrence,1: At least one bit sent as dominant is received.."
|
|
rbitfld.long 0x00 13. "ACKERR,Acknowledge Error" "0: No such occurrence,1: An ACK error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 12. "CRCERR,Cyclic Redundancy Check Error" "0: No such occurrence,1: A CRC error occurred since last read of this.."
|
|
rbitfld.long 0x00 11. "FRMERR,Form Error" "0: No such occurrence,1: A Form Error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 10. "STFERR,Stuffing Error" "0: No such occurrence,1: A Stuffing Error occurred since last read of.."
|
|
rbitfld.long 0x00 9. "TXWRN,TX Error Warning" "0: No such occurrence,1: TXERRCNT is greater than or equal to 96"
|
|
newline
|
|
rbitfld.long 0x00 8. "RXWRN,Rx Error Warning" "0: No such occurrence,1: RXERRCNT is greater than or equal to 96"
|
|
rbitfld.long 0x00 7. "IDLE,IDLE" "0: No such occurrence,1: CAN bus is now IDLE"
|
|
newline
|
|
rbitfld.long 0x00 6. "TX,FlexCAN In Transmission" "0: FlexCAN is not transmitting a message,1: FlexCAN is transmitting a message"
|
|
rbitfld.long 0x00 4.--5. "FLTCONF,Fault Confinement State" "0: Error Active,1: Error Passive,2: Bus Off,3: Bus Off"
|
|
newline
|
|
rbitfld.long 0x00 3. "RX,FlexCAN In Reception" "0: FlexCAN is not receiving a message,1: FlexCAN is receiving a message"
|
|
bitfld.long 0x00 2. "BOFFINT,Bus Off Interrupt" "0: No such occurrence,1: FlexCAN module entered Bus Off state"
|
|
newline
|
|
bitfld.long 0x00 1. "ERRINT,Error Interrupt" "0: No such occurrence,1: Indicates setting of any Error Bit in the.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMASK1,Interrupt Masks 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "BUF31TO0M,Buffer MB i Mask"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IFLAG1,Interrupt Flags 1 register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt"
|
|
bitfld.long 0x00 7. "BUF7I,Buffer MB7 Interrupt Or Rx FIFO Overflow" "0: No occurrence of MB7 completing..,1: MB7 completed transmission/reception when.."
|
|
newline
|
|
bitfld.long 0x00 6. "BUF6I,Buffer MB6 Interrupt Or Rx FIFO Warning" "0: No occurrence of MB6 completing..,1: MB6 completed transmission/reception when.."
|
|
bitfld.long 0x00 5. "BUF5I,Buffer MB5 Interrupt Or Frames available in Rx FIFO" "0: No occurrence of MB5 completing..,1: MB5 completed transmission/reception when.."
|
|
newline
|
|
bitfld.long 0x00 1.--4. "BUF4TO1I,Buffer MB i Interrupt Or reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "BUF0I,Buffer MB0 Interrupt Or Clear FIFO bit" "0: The corresponding buffer has no occurrence of..,1: The corresponding buffer has successfully.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL2,Control 2 register"
|
|
bitfld.long 0x00 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames" "0: ERRINT_FAST Error interrupt disabled,1: ERRINT_FAST Error interrupt enabled"
|
|
bitfld.long 0x00 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Bus Off Done interrupt disabled,1: Bus Off Done interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "RFFN,Number Of Rx FIFO Filters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. "TASD,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 18. "MRP,Mailboxes Reception Priority" "0: Matching starts from Rx FIFO and continues on..,1: Matching starts from Mailboxes and continues.."
|
|
bitfld.long 0x00 17. "RRS,Remote Request Storing" "0: Remote Response Frame is generated,1: Remote Request Frame is stored"
|
|
newline
|
|
bitfld.long 0x00 16. "EACEN,Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes" "0: Rx Mailbox filter's IDE bit is always..,1: Enables the comparison of both Rx Mailbox.."
|
|
bitfld.long 0x00 15. "TIMER_SRC,Timer Source" "0: The Free Running Timer is clocked by the CAN..,1: The Free Running Timer is clocked by an.."
|
|
newline
|
|
bitfld.long 0x00 14. "PREXCEN,Protocol Exception Enable" "0: Protocol Exception is disabled,1: Protocol Exception is enabled"
|
|
bitfld.long 0x00 12. "ISOCANFDEN,ISO CAN FD Enable" "0: FlexCAN operates using the non-ISO CAN FD..,1: FlexCAN operates using the ISO CAN FD.."
|
|
newline
|
|
bitfld.long 0x00 11. "EDFLTDIS,Edge Filter Disable" "0: Edge Filter is enabled,1: Edge Filter is disabled"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "ESR2,Error and Status 2 register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "LPTM,Lowest Priority Tx Mailbox"
|
|
bitfld.long 0x00 14. "VPS,Valid Priority Status" "0: Contents of IMB and LPTM are invalid,1: Contents of IMB and LPTM are valid"
|
|
newline
|
|
bitfld.long 0x00 13. "IMB,Inactive Mailbox" "0: If ESR2[VPS] is asserted the ESR2[LPTM] is..,1: If ESR2[VPS] is asserted there is at least.."
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "MBCRC,CRC Mailbox"
|
|
hexmask.long.word 0x00 0.--14. 1. "TXCRC,Transmitted CRC value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "FGM,Rx FIFO Global Mask Bits"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. "BTF,Bit Timing Format Enable" "0: Extended bit time definitions disabled,1: Extended bit time definitions enabled"
|
|
hexmask.long.word 0x00 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "ERJW,Extended Resync Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--15. "EPROPSEG,Extended Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "EPSEG1,Extended Phase Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "EPSEG2,Extended Phase Segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RAMn0,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "EmbeddedRAM0,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RAMn1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x84)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RAMn2,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "EmbeddedRAM3,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "3" "4" )(list 0x0 0x4 )
|
|
group.long ($2+0x8C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "4" "5" )(list 0x0 0x4 )
|
|
group.long ($2+0x90)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "RAMn5,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "EmbeddedRAM6,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "RAMn6,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "EmbeddedRAM7,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "7" "8" )(list 0x0 0x4 )
|
|
group.long ($2+0x9C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "8" "9" )(list 0x0 0x4 )
|
|
group.long ($2+0xA0)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "9" "10" )(list 0x0 0x4 )
|
|
group.long ($2+0xA4)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "EmbeddedRAM10,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "RAMn11,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "11" "12" )(list 0x0 0x4 )
|
|
group.long ($2+0xAC)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "RAMn12,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "EmbeddedRAM13,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "13" "14" )(list 0x0 0x4 )
|
|
group.long ($2+0xB4)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "14" "15" )(list 0x0 0x4 )
|
|
group.long ($2+0xB8)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "RAMn15,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "EmbeddedRAM16,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RAMn16,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "EmbeddedRAM17,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "17" "18" )(list 0x0 0x4 )
|
|
group.long ($2+0xC4)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "18" "19" )(list 0x0 0x4 )
|
|
group.long ($2+0xC8)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "RAMn19,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "EmbeddedRAM20,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "RAMn20,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "EmbeddedRAM21,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "RAMn21,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "EmbeddedRAM22,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "22" "23" )(list 0x0 0x4 )
|
|
group.long ($2+0xD8)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "EmbeddedRAM23,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RAMn24,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "24" "25" )(list 0x0 0x4 )
|
|
group.long ($2+0xE0)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "25" "26" )(list 0x0 0x4 )
|
|
group.long ($2+0xE4)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "EmbeddedRAM26,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "RAMn27,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "EmbeddedRAM27,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "RAMn28,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "EmbeddedRAM28,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "RAMn29,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "29" "30" )(list 0x0 0x4 )
|
|
group.long ($2+0xF4)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "RAMn30,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "EmbeddedRAM31,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "RAMn31,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "EmbeddedRAM32,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "RAMn32,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "EmbeddedRAM33,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "33" "34" )(list 0x00 0x04 )
|
|
group.long ($2+0x104)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "34" "35" )(list 0x00 0x04 )
|
|
group.long ($2+0x108)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "RAMn35,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "EmbeddedRAM36,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "RAMn36,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "EmbeddedRAM37,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "RAMn37,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "EmbeddedRAM38,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "RAMn38,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "EmbeddedRAM39,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "RAMn39,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "EmbeddedRAM40,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "40" "41" )(list 0x00 0x04 )
|
|
group.long ($2+0x120)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "41" "42" )(list 0x00 0x04 )
|
|
group.long ($2+0x124)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "42" "43" )(list 0x00 0x04 )
|
|
group.long ($2+0x128)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "EmbeddedRAM43,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "RAMn44,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "EmbeddedRAM44,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "RAMn45,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "EmbeddedRAM45,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "RAMn46,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "46" "47" )(list 0x00 0x04 )
|
|
group.long ($2+0x138)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "RAMn47,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "EmbeddedRAM48,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RAMn48,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "EmbeddedRAM49,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "49" "50" )(list 0x00 0x04 )
|
|
group.long ($2+0x144)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "EmbeddedRAM50,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "RAMn51,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "51" "52" )(list 0x00 0x04 )
|
|
group.long ($2+0x14C)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "RAMn52,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "EmbeddedRAM53,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "53" "54" )(list 0x00 0x04 )
|
|
group.long ($2+0x154)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "54" "55" )(list 0x00 0x04 )
|
|
group.long ($2+0x158)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "55" "56" )(list 0x00 0x04 )
|
|
group.long ($2+0x15C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "EmbeddedRAM56,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "RAMn57,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "57" "58" )(list 0x00 0x04 )
|
|
group.long ($2+0x164)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "RAMn58,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "EmbeddedRAM59,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "59" "60" )(list 0x00 0x04 )
|
|
group.long ($2+0x16C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "60" "61" )(list 0x00 0x04 )
|
|
group.long ($2+0x170)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "RAMn61,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "EmbeddedRAM62,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "62" "63" )(list 0x00 0x04 )
|
|
group.long ($2+0x178)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "63" "64" )(list 0x00 0x04 )
|
|
group.long ($2+0x17C)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "RAMn64,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "EmbeddedRAM65,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "RAMn65,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "EmbeddedRAM66,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "RAMn66,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "EmbeddedRAM67,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "67" "68" )(list 0x00 0x04 )
|
|
group.long ($2+0x18C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "68" "69" )(list 0x00 0x04 )
|
|
group.long ($2+0x190)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "69" "70" )(list 0x00 0x04 )
|
|
group.long ($2+0x194)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "70" "71" )(list 0x00 0x04 )
|
|
group.long ($2+0x198)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "71" "72" )(list 0x00 0x04 )
|
|
group.long ($2+0x19C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "EmbeddedRAM72,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "RAMn73,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "EmbeddedRAM73,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "RAMn74,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "74" "75" )(list 0x00 0x04 )
|
|
group.long ($2+0x1A8)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "75" "76" )(list 0x00 0x04 )
|
|
group.long ($2+0x1AC)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "EmbeddedRAM76,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "RAMn77,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "EmbeddedRAM77,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "RAMn78,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "78" "79" )(list 0x00 0x04 )
|
|
group.long ($2+0x1B8)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "79" "80" )(list 0x00 0x04 )
|
|
group.long ($2+0x1BC)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "EmbeddedRAM80,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "RAMn81,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "EmbeddedRAM81,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "RAMn82,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "EmbeddedRAM82,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "RAMn83,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "83" "84" )(list 0x00 0x04 )
|
|
group.long ($2+0x1CC)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "RAMn84,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "EmbeddedRAM85,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "RAMn85,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "EmbeddedRAM86,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "RAMn86,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "EmbeddedRAM87,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "87" "88" )(list 0x00 0x04 )
|
|
group.long ($2+0x1DC)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "88" "89" )(list 0x00 0x04 )
|
|
group.long ($2+0x1E0)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "RAMn89,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "EmbeddedRAM90,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "RAMn90,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "EmbeddedRAM91,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "RAMn91,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "EmbeddedRAM92,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "RAMn92,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "EmbeddedRAM93,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "93" "94" )(list 0x00 0x04 )
|
|
group.long ($2+0x1F4)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "94" "95" )(list 0x00 0x04 )
|
|
group.long ($2+0x1F8)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "95" "96" )(list 0x00 0x04 )
|
|
group.long ($2+0x1FC)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "96" "97" )(list 0x00 0x04 )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "97" "98" )(list 0x00 0x04 )
|
|
group.long ($2+0x204)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "98" "99" )(list 0x00 0x04 )
|
|
group.long ($2+0x208)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "RAMn99,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "EmbeddedRAM100,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "100" "101" )(list 0x00 0x04 )
|
|
group.long ($2+0x210)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "EmbeddedRAM101,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "RAMn102,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "102" "103" )(list 0x00 0x04 )
|
|
group.long ($2+0x218)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "103" "104" )(list 0x00 0x04 )
|
|
group.long ($2+0x21C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "EmbeddedRAM104,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "RAMn105,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "EmbeddedRAM105,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "RAMn106,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "106" "107" )(list 0x00 0x04 )
|
|
group.long ($2+0x228)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "107" "108" )(list 0x00 0x04 )
|
|
group.long ($2+0x22C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "EmbeddedRAM108,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "RAMn109,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "109" "110" )(list 0x00 0x04 )
|
|
group.long ($2+0x234)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "110" "111" )(list 0x00 0x04 )
|
|
group.long ($2+0x238)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 2. (strings "111" "112" )(list 0x00 0x04 )
|
|
group.long ($2+0x23C)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "112" "113" )(list 0x00 0x04 )
|
|
group.long ($2+0x240)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "EmbeddedRAM113,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "RAMn114,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "114" "115" )(list 0x00 0x04 )
|
|
group.long ($2+0x248)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "RAMn115,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "EmbeddedRAM116,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "RAMn116,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "EmbeddedRAM117,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "117" "118" )(list 0x00 0x04 )
|
|
group.long ($2+0x254)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "EmbeddedRAM118,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "RAMn119,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "119" "120" )(list 0x00 0x04 )
|
|
group.long ($2+0x25C)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "RAMn120,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "EmbeddedRAM121,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "RAMn121,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "EmbeddedRAM122,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "122" "123" )(list 0x00 0x04 )
|
|
group.long ($2+0x268)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "EmbeddedRAM123,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "RAMn124,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "EmbeddedRAM124,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "RAMn125,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
repeat 2. (strings "125" "126" )(list 0x00 0x04 )
|
|
group.long ($2+0x274)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K118")
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "RAMn126,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "EmbeddedRAM127,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
sif cpuis("S32K118")
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "RAMn127,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x880)++0x03
|
|
line.long 0x00 "RXIMR$1,Rx Individual Mask Registers"
|
|
hexmask.long 0x00 0.--31. 1. "MI,Individual Mask Bits"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x8C0)++0x03
|
|
line.long 0x00 "RXIMR$1,Rx Individual Mask Registers"
|
|
hexmask.long 0x00 0.--31. 1. "MI,Individual Mask Bits"
|
|
repeat.end
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "CTRL1_PN,Pretended Networking Control 1 Register"
|
|
bitfld.long 0x00 17. "WTOF_MSK,Wake Up by Timeout Flag Mask Bit" "0: Timeout wake up event is disabled,1: Timeout wake up event is enabled"
|
|
bitfld.long 0x00 16. "WUMF_MSK,Wake Up by Match Flag Mask Bit" "0: Wake up match event is disabled,1: Wake up match event is enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "NMATCH,Number of Messages Matching the Same Filtering Criteria"
|
|
bitfld.long 0x00 4.--5. "PLFS,Payload Filtering Selection" "0: Match upon a payload contents against an..,1: Match upon a payload value greater than or..,2: Match upon a payload value smaller than or..,3: Match upon a payload value inside a range.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "IDFS,ID Filtering Selection" "0: Match upon a ID contents against an exact..,1: Match upon a ID value greater than or equal..,2: Match upon a ID value smaller than or equal..,3: Match upon a ID value inside a range greater.."
|
|
bitfld.long 0x00 0.--1. "FCS,Filtering Combination Selection" "0: Message ID filtering only,1: Message ID filtering and payload filtering,2: Message ID filtering occurring a specified..,3: Message ID filtering and payload filtering a.."
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MATCHTO,Timeout for No Message Matching the Filtering Criteria"
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "WU_MTC,Pretended Networking Wake Up Match Register"
|
|
bitfld.long 0x00 17. "WTOF,Wake Up by Timeout Flag Bit" "0: No wake up by timeout event detected,1: Wake up by timeout event detected"
|
|
bitfld.long 0x00 16. "WUMF,Wake Up by Match Flag Bit" "0: No wake up by match event detected,1: Wake up by match event detected"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MCOUNTER,Number of Matches while in Pretended Networking"
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 30. "FLT_IDE,ID Extended Filter" "0: Accept standard frame format,1: Accept extended frame format"
|
|
bitfld.long 0x00 29. "FLT_RTR,Remote Transmission Request Filter" "0: Reject remote frame (accept data frame),1: Accept remote frame"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. "FLT_ID1,ID Filter 1 for Pretended Networking filtering"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "FLT_DLC,Pretended Networking DLC Filter Register"
|
|
bitfld.long 0x00 16.--19. "FLT_DLC_LO,Lower Limit for Length of Data Bytes Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "FLT_DLC_HI,Upper Limit for Length of Data Bytes Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 3"
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7"
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "FLT_ID2_IDMASK,Pretended Networking ID Filter 2 Register / ID Mask Register"
|
|
bitfld.long 0x00 30. "IDE_MSK,ID Extended Mask Bit" "0: The corresponding bit in the filter is don't..,1: The corresponding bit in the filter is checked"
|
|
bitfld.long 0x00 29. "RTR_MSK,Remote Transmission Request Mask Bit" "0: The corresponding bit in the filter is don't..,1: The corresponding bit in the filter is checked"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. "FLT_ID2_IDMASK,ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering"
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 3"
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 7"
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "WMB0_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB44++0x03
|
|
line.long 0x00 "WMB0_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "WMB0_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB4C++0x03
|
|
line.long 0x00 "WMB0_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "WMB1_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB54++0x03
|
|
line.long 0x00 "WMB1_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "WMB1_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB5C++0x03
|
|
line.long 0x00 "WMB1_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "WMB2_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB64++0x03
|
|
line.long 0x00 "WMB2_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "WMB2_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB6C++0x03
|
|
line.long 0x00 "WMB2_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "WMB3_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB74++0x03
|
|
line.long 0x00 "WMB3_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "WMB3_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB7C++0x03
|
|
line.long 0x00 "WMB3_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. "FDRATE,Bit Rate Switch Enable" "0: Transmit a frame in nominal rate,1: Transmit a frame with bit rate switching if.."
|
|
bitfld.long 0x00 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: Selects 8 bytes per Message Buffer,1: Selects 16 bytes per Message Buffer,2: Selects 32 bytes per Message Buffer,3: Selects 64 bytes per Message Buffer"
|
|
newline
|
|
bitfld.long 0x00 15. "TDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled"
|
|
bitfld.long 0x00 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: Measured loop delay is in range,1: Measured loop delay is out of range"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "TDCOFF,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 0.--5. "TDCVAL,Transceiver Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "FDCBT,CAN FD Bit Timing Register"
|
|
hexmask.long.word 0x00 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor"
|
|
bitfld.long 0x00 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 10.--14. "FPROPSEG,Fast Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "FDCRC,CAN FD CRC Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. "FD_MBCRC,CRC Mailbox Number for FD_TXCRC"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value"
|
|
endif
|
|
tree.end
|
|
tree "CAN1"
|
|
base ad:0x40025000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. "MDIS,Module Disable" "0: Enable the FlexCAN module,1: Disable the FlexCAN module"
|
|
bitfld.long 0x00 30. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode,1: Enabled to enter Freeze mode"
|
|
newline
|
|
bitfld.long 0x00 29. "RFEN,Rx FIFO Enable" "0: Rx FIFO not enabled,1: Rx FIFO enabled"
|
|
bitfld.long 0x00 28. "HALT,Halt FlexCAN" "0: No Freeze mode request,1: Enters Freeze mode if the FRZ bit is asserted"
|
|
newline
|
|
rbitfld.long 0x00 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN module is either in Normal mode..,?..."
|
|
bitfld.long 0x00 25. "SOFTRST,Soft Reset" "0: No reset request,1: Resets the registers affected by soft reset"
|
|
newline
|
|
rbitfld.long 0x00 24. "FRZACK,Freeze Mode Acknowledge" "0: FlexCAN not in Freeze mode prescaler running,1: FlexCAN in Freeze mode prescaler stopped"
|
|
bitfld.long 0x00 23. "SUPV,Supervisor Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WRNEN,Warning Interrupt Enable" "0: TWRNINT and RWRNINT bits are zero independent..,1: TWRNINT and RWRNINT bits are set when the.."
|
|
rbitfld.long 0x00 20. "LPMACK,Low-Power Mode Acknowledge" "0: FlexCAN is not in a low-power mode,1: FlexCAN is in a low-power mode"
|
|
newline
|
|
bitfld.long 0x00 17. "SRXDIS,Self Reception Disable" "0: Self reception enabled,1: Self reception disabled"
|
|
bitfld.long 0x00 16. "IRMQ,Individual Rx Masking And Queue Enable" "0: Individual Rx masking and queue feature are..,1: Individual Rx masking and queue feature are.."
|
|
newline
|
|
bitfld.long 0x00 15. "DMA,DMA Enable" "0: DMA feature for RX FIFO disabled,1: DMA feature for RX FIFO enabled"
|
|
bitfld.long 0x00 14. "PNET_EN,Pretended Networking Enable" "0: Pretended Networking mode is disabled,1: Pretended Networking mode is enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "LPRIOEN,Local Priority Enable" "0: Local Priority disabled,1: Local Priority enabled"
|
|
bitfld.long 0x00 12. "AEN,Abort Enable" "0: Abort disabled,1: Abort enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FDEN,CAN FD operation enable" "0: CAN FD is disabled,1: CAN FD is enabled"
|
|
bitfld.long 0x00 8.--9. "IDAM,ID Acceptance Mode" "0: Format A,1: Format B,2: Format C,3: Format D"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB,Number Of The Last Message Buffer"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRESDIV,Prescaler Division Factor"
|
|
bitfld.long 0x00 22.--23. "RJW,Resync Jump Width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Bus Off interrupt disabled,1: Bus Off interrupt enabled"
|
|
bitfld.long 0x00 14. "ERRMSK,Error Interrupt Mask" "0: Error interrupt disabled,1: Error interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "CLKSRC,CAN Engine Clock Source" "0: The CAN engine clock source is the oscillator..,1: The CAN engine clock source is the peripheral.."
|
|
bitfld.long 0x00 12. "LPB,Loop Back Mode" "0: Loop Back disabled,1: Loop Back enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TWRNMSK,Tx Warning Interrupt Mask" "0: Tx Warning Interrupt disabled,1: Tx Warning Interrupt enabled"
|
|
bitfld.long 0x00 10. "RWRNMSK,Rx Warning Interrupt Mask" "0: Rx Warning Interrupt disabled,1: Rx Warning Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SMP,CAN Bit Sampling" "0: Just one sample is used to determine the bit..,1: Three samples are used to determine the value.."
|
|
bitfld.long 0x00 6. "BOFFREC,Bus Off Recovery" "0: Automatic recovering from Bus Off state enabled,1: Automatic recovering from Bus Off state.."
|
|
newline
|
|
bitfld.long 0x00 5. "TSYN,Timer Sync" "0: Timer Sync feature disabled,1: Timer Sync feature enabled"
|
|
bitfld.long 0x00 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted..,1: Lowest number buffer is transmitted first"
|
|
newline
|
|
bitfld.long 0x00 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated,1: FlexCAN module operates in Listen-Only mode"
|
|
bitfld.long 0x00 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMER,Free Running Timer"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMER,Timer Value"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. "MG,Rx Mailboxes Global Mask Bits"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RX14MASK,Rx 14 Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "RX14M,Rx Buffer 14 Mask Bits"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RX15MASK,Rx 15 Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "RX15M,Rx Buffer 15 Mask Bits"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ECR,Error Counter"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for fast bits"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for fast bits"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXERRCNT,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXERRCNT,Transmit Error Counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ESR1,Error and Status 1 register"
|
|
rbitfld.long 0x00 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as recessive is.."
|
|
rbitfld.long 0x00 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as dominant is received.."
|
|
newline
|
|
rbitfld.long 0x00 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A CRC error occurred since last read of this.."
|
|
rbitfld.long 0x00 27. "FRMERR_FAST,Form Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A Form Error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A Stuffing Error occurred since last read of.."
|
|
bitfld.long 0x00 21. "ERROVR,Error Overrun bit" "0: Overrun has not occurred,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 20. "ERRINT_FAST,Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: Indicates setting of any Error Bit detected.."
|
|
bitfld.long 0x00 19. "BOFFDONEINT,Bus Off Done Interrupt" "0: No such occurrence,1: FlexCAN module has completed Bus Off process"
|
|
newline
|
|
rbitfld.long 0x00 18. "SYNCH,CAN Synchronization Status" "0: FlexCAN is not synchronized to the CAN bus,1: FlexCAN is synchronized to the CAN bus"
|
|
bitfld.long 0x00 17. "TWRNINT,Tx Warning Interrupt Flag" "0: No such occurrence,1: The Tx error counter transitioned from less.."
|
|
newline
|
|
bitfld.long 0x00 16. "RWRNINT,Rx Warning Interrupt Flag" "0: No such occurrence,1: The Rx error counter transitioned from less.."
|
|
rbitfld.long 0x00 15. "BIT1ERR,Bit1 Error" "0: No such occurrence,1: At least one bit sent as recessive is.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIT0ERR,Bit0 Error" "0: No such occurrence,1: At least one bit sent as dominant is received.."
|
|
rbitfld.long 0x00 13. "ACKERR,Acknowledge Error" "0: No such occurrence,1: An ACK error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 12. "CRCERR,Cyclic Redundancy Check Error" "0: No such occurrence,1: A CRC error occurred since last read of this.."
|
|
rbitfld.long 0x00 11. "FRMERR,Form Error" "0: No such occurrence,1: A Form Error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 10. "STFERR,Stuffing Error" "0: No such occurrence,1: A Stuffing Error occurred since last read of.."
|
|
rbitfld.long 0x00 9. "TXWRN,TX Error Warning" "0: No such occurrence,1: TXERRCNT is greater than or equal to 96"
|
|
newline
|
|
rbitfld.long 0x00 8. "RXWRN,Rx Error Warning" "0: No such occurrence,1: RXERRCNT is greater than or equal to 96"
|
|
rbitfld.long 0x00 7. "IDLE,IDLE" "0: No such occurrence,1: CAN bus is now IDLE"
|
|
newline
|
|
rbitfld.long 0x00 6. "TX,FlexCAN In Transmission" "0: FlexCAN is not transmitting a message,1: FlexCAN is transmitting a message"
|
|
rbitfld.long 0x00 4.--5. "FLTCONF,Fault Confinement State" "0: Error Active,1: Error Passive,2: Bus Off,3: Bus Off"
|
|
newline
|
|
rbitfld.long 0x00 3. "RX,FlexCAN In Reception" "0: FlexCAN is not receiving a message,1: FlexCAN is receiving a message"
|
|
bitfld.long 0x00 2. "BOFFINT,Bus Off Interrupt" "0: No such occurrence,1: FlexCAN module entered Bus Off state"
|
|
newline
|
|
bitfld.long 0x00 1. "ERRINT,Error Interrupt" "0: No such occurrence,1: Indicates setting of any Error Bit in the.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMASK1,Interrupt Masks 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "BUF31TO0M,Buffer MB i Mask"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IFLAG1,Interrupt Flags 1 register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt"
|
|
bitfld.long 0x00 7. "BUF7I,Buffer MB7 Interrupt Or Rx FIFO Overflow" "0: No occurrence of MB7 completing..,1: MB7 completed transmission/reception when.."
|
|
newline
|
|
bitfld.long 0x00 6. "BUF6I,Buffer MB6 Interrupt Or Rx FIFO Warning" "0: No occurrence of MB6 completing..,1: MB6 completed transmission/reception when.."
|
|
bitfld.long 0x00 5. "BUF5I,Buffer MB5 Interrupt Or Frames available in Rx FIFO" "0: No occurrence of MB5 completing..,1: MB5 completed transmission/reception when.."
|
|
newline
|
|
bitfld.long 0x00 1.--4. "BUF4TO1I,Buffer MB i Interrupt Or reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "BUF0I,Buffer MB0 Interrupt Or Clear FIFO bit" "0: The corresponding buffer has no occurrence of..,1: The corresponding buffer has successfully.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL2,Control 2 register"
|
|
bitfld.long 0x00 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames" "0: ERRINT_FAST Error interrupt disabled,1: ERRINT_FAST Error interrupt enabled"
|
|
bitfld.long 0x00 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Bus Off Done interrupt disabled,1: Bus Off Done interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "RFFN,Number Of Rx FIFO Filters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. "TASD,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 18. "MRP,Mailboxes Reception Priority" "0: Matching starts from Rx FIFO and continues on..,1: Matching starts from Mailboxes and continues.."
|
|
bitfld.long 0x00 17. "RRS,Remote Request Storing" "0: Remote Response Frame is generated,1: Remote Request Frame is stored"
|
|
newline
|
|
bitfld.long 0x00 16. "EACEN,Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes" "0: Rx Mailbox filter's IDE bit is always..,1: Enables the comparison of both Rx Mailbox.."
|
|
bitfld.long 0x00 15. "TIMER_SRC,Timer Source" "0: The Free Running Timer is clocked by the CAN..,1: The Free Running Timer is clocked by an.."
|
|
newline
|
|
bitfld.long 0x00 14. "PREXCEN,Protocol Exception Enable" "0: Protocol Exception is disabled,1: Protocol Exception is enabled"
|
|
bitfld.long 0x00 12. "ISOCANFDEN,ISO CAN FD Enable" "0: FlexCAN operates using the non-ISO CAN FD..,1: FlexCAN operates using the ISO CAN FD.."
|
|
newline
|
|
bitfld.long 0x00 11. "EDFLTDIS,Edge Filter Disable" "0: Edge Filter is enabled,1: Edge Filter is disabled"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "ESR2,Error and Status 2 register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "LPTM,Lowest Priority Tx Mailbox"
|
|
bitfld.long 0x00 14. "VPS,Valid Priority Status" "0: Contents of IMB and LPTM are invalid,1: Contents of IMB and LPTM are valid"
|
|
newline
|
|
bitfld.long 0x00 13. "IMB,Inactive Mailbox" "0: If ESR2[VPS] is asserted the ESR2[LPTM] is..,1: If ESR2[VPS] is asserted there is at least.."
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "MBCRC,CRC Mailbox"
|
|
hexmask.long.word 0x00 0.--14. 1. "TXCRC,Transmitted CRC value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "FGM,Rx FIFO Global Mask Bits"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. "BTF,Bit Timing Format Enable" "0: Extended bit time definitions disabled,1: Extended bit time definitions enabled"
|
|
hexmask.long.word 0x00 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "ERJW,Extended Resync Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--15. "EPROPSEG,Extended Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "EPSEG1,Extended Phase Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "EPSEG2,Extended Phase Segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xC0)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x140)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1C0)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
repeat 16. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" "107" "108" "109" "110" "111" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
repeat 16. (strings "112" "113" "114" "115" "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x240)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x880)++0x03
|
|
line.long 0x00 "RXIMR$1,Rx Individual Mask Registers"
|
|
hexmask.long 0x00 0.--31. 1. "MI,Individual Mask Bits"
|
|
repeat.end
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x8C0)++0x03
|
|
line.long 0x00 "RXIMR$1,Rx Individual Mask Registers"
|
|
hexmask.long 0x00 0.--31. 1. "MI,Individual Mask Bits"
|
|
repeat.end
|
|
endif
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "CTRL1_PN,Pretended Networking Control 1 Register"
|
|
bitfld.long 0x00 17. "WTOF_MSK,Wake Up by Timeout Flag Mask Bit" "0: Timeout wake up event is disabled,1: Timeout wake up event is enabled"
|
|
bitfld.long 0x00 16. "WUMF_MSK,Wake Up by Match Flag Mask Bit" "0: Wake up match event is disabled,1: Wake up match event is enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "NMATCH,Number of Messages Matching the Same Filtering Criteria"
|
|
bitfld.long 0x00 4.--5. "PLFS,Payload Filtering Selection" "0: Match upon a payload contents against an..,1: Match upon a payload value greater than or..,2: Match upon a payload value smaller than or..,3: Match upon a payload value inside a range.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "IDFS,ID Filtering Selection" "0: Match upon a ID contents against an exact..,1: Match upon a ID value greater than or equal..,2: Match upon a ID value smaller than or equal..,3: Match upon a ID value inside a range greater.."
|
|
bitfld.long 0x00 0.--1. "FCS,Filtering Combination Selection" "0: Message ID filtering only,1: Message ID filtering and payload filtering,2: Message ID filtering occurring a specified..,3: Message ID filtering and payload filtering a.."
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MATCHTO,Timeout for No Message Matching the Filtering Criteria"
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "WU_MTC,Pretended Networking Wake Up Match Register"
|
|
bitfld.long 0x00 17. "WTOF,Wake Up by Timeout Flag Bit" "0: No wake up by timeout event detected,1: Wake up by timeout event detected"
|
|
bitfld.long 0x00 16. "WUMF,Wake Up by Match Flag Bit" "0: No wake up by match event detected,1: Wake up by match event detected"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MCOUNTER,Number of Matches while in Pretended Networking"
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 30. "FLT_IDE,ID Extended Filter" "0: Accept standard frame format,1: Accept extended frame format"
|
|
bitfld.long 0x00 29. "FLT_RTR,Remote Transmission Request Filter" "0: Reject remote frame (accept data frame),1: Accept remote frame"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. "FLT_ID1,ID Filter 1 for Pretended Networking filtering"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "FLT_DLC,Pretended Networking DLC Filter Register"
|
|
bitfld.long 0x00 16.--19. "FLT_DLC_LO,Lower Limit for Length of Data Bytes Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "FLT_DLC_HI,Upper Limit for Length of Data Bytes Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 3"
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7"
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "FLT_ID2_IDMASK,Pretended Networking ID Filter 2 Register / ID Mask Register"
|
|
bitfld.long 0x00 30. "IDE_MSK,ID Extended Mask Bit" "0: The corresponding bit in the filter is don't..,1: The corresponding bit in the filter is checked"
|
|
bitfld.long 0x00 29. "RTR_MSK,Remote Transmission Request Mask Bit" "0: The corresponding bit in the filter is don't..,1: The corresponding bit in the filter is checked"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. "FLT_ID2_IDMASK,ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering"
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 3"
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 7"
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "WMB0_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB44++0x03
|
|
line.long 0x00 "WMB0_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "WMB0_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB4C++0x03
|
|
line.long 0x00 "WMB0_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "WMB1_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB54++0x03
|
|
line.long 0x00 "WMB1_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "WMB1_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB5C++0x03
|
|
line.long 0x00 "WMB1_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "WMB2_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB64++0x03
|
|
line.long 0x00 "WMB2_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "WMB2_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB6C++0x03
|
|
line.long 0x00 "WMB2_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "WMB3_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB74++0x03
|
|
line.long 0x00 "WMB3_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "WMB3_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB7C++0x03
|
|
line.long 0x00 "WMB3_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. "FDRATE,Bit Rate Switch Enable" "0: Transmit a frame in nominal rate,1: Transmit a frame with bit rate switching if.."
|
|
bitfld.long 0x00 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: Selects 8 bytes per Message Buffer,1: Selects 16 bytes per Message Buffer,2: Selects 32 bytes per Message Buffer,3: Selects 64 bytes per Message Buffer"
|
|
newline
|
|
bitfld.long 0x00 15. "TDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled"
|
|
bitfld.long 0x00 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: Measured loop delay is in range,1: Measured loop delay is out of range"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "TDCOFF,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 0.--5. "TDCVAL,Transceiver Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "FDCBT,CAN FD Bit Timing Register"
|
|
hexmask.long.word 0x00 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor"
|
|
bitfld.long 0x00 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 10.--14. "FPROPSEG,Fast Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "FDCRC,CAN FD CRC Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. "FD_MBCRC,CRC Mailbox Number for FD_TXCRC"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value"
|
|
tree.end
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
tree "CAN2"
|
|
base ad:0x4002B000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. "MDIS,Module Disable" "0: Enable the FlexCAN module,1: Disable the FlexCAN module"
|
|
bitfld.long 0x00 30. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode,1: Enabled to enter Freeze mode"
|
|
newline
|
|
bitfld.long 0x00 29. "RFEN,Rx FIFO Enable" "0: Rx FIFO not enabled,1: Rx FIFO enabled"
|
|
bitfld.long 0x00 28. "HALT,Halt FlexCAN" "0: No Freeze mode request,1: Enters Freeze mode if the FRZ bit is asserted"
|
|
newline
|
|
rbitfld.long 0x00 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN module is either in Normal mode..,?..."
|
|
bitfld.long 0x00 25. "SOFTRST,Soft Reset" "0: No reset request,1: Resets the registers affected by soft reset"
|
|
newline
|
|
rbitfld.long 0x00 24. "FRZACK,Freeze Mode Acknowledge" "0: FlexCAN not in Freeze mode prescaler running,1: FlexCAN in Freeze mode prescaler stopped"
|
|
bitfld.long 0x00 23. "SUPV,Supervisor Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WRNEN,Warning Interrupt Enable" "0: TWRNINT and RWRNINT bits are zero independent..,1: TWRNINT and RWRNINT bits are set when the.."
|
|
rbitfld.long 0x00 20. "LPMACK,Low-Power Mode Acknowledge" "0: FlexCAN is not in a low-power mode,1: FlexCAN is in a low-power mode"
|
|
newline
|
|
bitfld.long 0x00 17. "SRXDIS,Self Reception Disable" "0: Self reception enabled,1: Self reception disabled"
|
|
bitfld.long 0x00 16. "IRMQ,Individual Rx Masking And Queue Enable" "0: Individual Rx masking and queue feature are..,1: Individual Rx masking and queue feature are.."
|
|
newline
|
|
bitfld.long 0x00 15. "DMA,DMA Enable" "0: DMA feature for RX FIFO disabled,1: DMA feature for RX FIFO enabled"
|
|
bitfld.long 0x00 14. "PNET_EN,Pretended Networking Enable" "0: Pretended Networking mode is disabled,1: Pretended Networking mode is enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "LPRIOEN,Local Priority Enable" "0: Local Priority disabled,1: Local Priority enabled"
|
|
bitfld.long 0x00 12. "AEN,Abort Enable" "0: Abort disabled,1: Abort enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FDEN,CAN FD operation enable" "0: CAN FD is disabled,1: CAN FD is enabled"
|
|
bitfld.long 0x00 8.--9. "IDAM,ID Acceptance Mode" "0: Format A,1: Format B,2: Format C,3: Format D"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB,Number Of The Last Message Buffer"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRESDIV,Prescaler Division Factor"
|
|
bitfld.long 0x00 22.--23. "RJW,Resync Jump Width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Bus Off interrupt disabled,1: Bus Off interrupt enabled"
|
|
bitfld.long 0x00 14. "ERRMSK,Error Interrupt Mask" "0: Error interrupt disabled,1: Error interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "CLKSRC,CAN Engine Clock Source" "0: The CAN engine clock source is the oscillator..,1: The CAN engine clock source is the peripheral.."
|
|
bitfld.long 0x00 12. "LPB,Loop Back Mode" "0: Loop Back disabled,1: Loop Back enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TWRNMSK,Tx Warning Interrupt Mask" "0: Tx Warning Interrupt disabled,1: Tx Warning Interrupt enabled"
|
|
bitfld.long 0x00 10. "RWRNMSK,Rx Warning Interrupt Mask" "0: Rx Warning Interrupt disabled,1: Rx Warning Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SMP,CAN Bit Sampling" "0: Just one sample is used to determine the bit..,1: Three samples are used to determine the value.."
|
|
bitfld.long 0x00 6. "BOFFREC,Bus Off Recovery" "0: Automatic recovering from Bus Off state enabled,1: Automatic recovering from Bus Off state.."
|
|
newline
|
|
bitfld.long 0x00 5. "TSYN,Timer Sync" "0: Timer Sync feature disabled,1: Timer Sync feature enabled"
|
|
bitfld.long 0x00 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted..,1: Lowest number buffer is transmitted first"
|
|
newline
|
|
bitfld.long 0x00 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated,1: FlexCAN module operates in Listen-Only mode"
|
|
bitfld.long 0x00 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMER,Free Running Timer"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMER,Timer Value"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. "MG,Rx Mailboxes Global Mask Bits"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RX14MASK,Rx 14 Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "RX14M,Rx Buffer 14 Mask Bits"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RX15MASK,Rx 15 Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "RX15M,Rx Buffer 15 Mask Bits"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ECR,Error Counter"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for fast bits"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for fast bits"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXERRCNT,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXERRCNT,Transmit Error Counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ESR1,Error and Status 1 register"
|
|
rbitfld.long 0x00 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as recessive is.."
|
|
rbitfld.long 0x00 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as dominant is received.."
|
|
newline
|
|
rbitfld.long 0x00 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A CRC error occurred since last read of this.."
|
|
rbitfld.long 0x00 27. "FRMERR_FAST,Form Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A Form Error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A Stuffing Error occurred since last read of.."
|
|
bitfld.long 0x00 21. "ERROVR,Error Overrun bit" "0: Overrun has not occurred,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 20. "ERRINT_FAST,Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: Indicates setting of any Error Bit detected.."
|
|
bitfld.long 0x00 19. "BOFFDONEINT,Bus Off Done Interrupt" "0: No such occurrence,1: FlexCAN module has completed Bus Off process"
|
|
newline
|
|
rbitfld.long 0x00 18. "SYNCH,CAN Synchronization Status" "0: FlexCAN is not synchronized to the CAN bus,1: FlexCAN is synchronized to the CAN bus"
|
|
bitfld.long 0x00 17. "TWRNINT,Tx Warning Interrupt Flag" "0: No such occurrence,1: The Tx error counter transitioned from less.."
|
|
newline
|
|
bitfld.long 0x00 16. "RWRNINT,Rx Warning Interrupt Flag" "0: No such occurrence,1: The Rx error counter transitioned from less.."
|
|
rbitfld.long 0x00 15. "BIT1ERR,Bit1 Error" "0: No such occurrence,1: At least one bit sent as recessive is.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIT0ERR,Bit0 Error" "0: No such occurrence,1: At least one bit sent as dominant is received.."
|
|
rbitfld.long 0x00 13. "ACKERR,Acknowledge Error" "0: No such occurrence,1: An ACK error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 12. "CRCERR,Cyclic Redundancy Check Error" "0: No such occurrence,1: A CRC error occurred since last read of this.."
|
|
rbitfld.long 0x00 11. "FRMERR,Form Error" "0: No such occurrence,1: A Form Error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 10. "STFERR,Stuffing Error" "0: No such occurrence,1: A Stuffing Error occurred since last read of.."
|
|
rbitfld.long 0x00 9. "TXWRN,TX Error Warning" "0: No such occurrence,1: TXERRCNT is greater than or equal to 96"
|
|
newline
|
|
rbitfld.long 0x00 8. "RXWRN,Rx Error Warning" "0: No such occurrence,1: RXERRCNT is greater than or equal to 96"
|
|
rbitfld.long 0x00 7. "IDLE,IDLE" "0: No such occurrence,1: CAN bus is now IDLE"
|
|
newline
|
|
rbitfld.long 0x00 6. "TX,FlexCAN In Transmission" "0: FlexCAN is not transmitting a message,1: FlexCAN is transmitting a message"
|
|
rbitfld.long 0x00 4.--5. "FLTCONF,Fault Confinement State" "0: Error Active,1: Error Passive,2: Bus Off,3: Bus Off"
|
|
newline
|
|
rbitfld.long 0x00 3. "RX,FlexCAN In Reception" "0: FlexCAN is not receiving a message,1: FlexCAN is receiving a message"
|
|
bitfld.long 0x00 2. "BOFFINT,Bus Off Interrupt" "0: No such occurrence,1: FlexCAN module entered Bus Off state"
|
|
newline
|
|
bitfld.long 0x00 1. "ERRINT,Error Interrupt" "0: No such occurrence,1: Indicates setting of any Error Bit in the.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMASK1,Interrupt Masks 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "BUF31TO0M,Buffer MB i Mask"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IFLAG1,Interrupt Flags 1 register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt"
|
|
bitfld.long 0x00 7. "BUF7I,Buffer MB7 Interrupt Or Rx FIFO Overflow" "0: No occurrence of MB7 completing..,1: MB7 completed transmission/reception when.."
|
|
newline
|
|
bitfld.long 0x00 6. "BUF6I,Buffer MB6 Interrupt Or Rx FIFO Warning" "0: No occurrence of MB6 completing..,1: MB6 completed transmission/reception when.."
|
|
bitfld.long 0x00 5. "BUF5I,Buffer MB5 Interrupt Or Frames available in Rx FIFO" "0: No occurrence of MB5 completing..,1: MB5 completed transmission/reception when.."
|
|
newline
|
|
bitfld.long 0x00 1.--4. "BUF4TO1I,Buffer MB i Interrupt Or reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "BUF0I,Buffer MB0 Interrupt Or Clear FIFO bit" "0: The corresponding buffer has no occurrence of..,1: The corresponding buffer has successfully.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL2,Control 2 register"
|
|
bitfld.long 0x00 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames" "0: ERRINT_FAST Error interrupt disabled,1: ERRINT_FAST Error interrupt enabled"
|
|
bitfld.long 0x00 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Bus Off Done interrupt disabled,1: Bus Off Done interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "RFFN,Number Of Rx FIFO Filters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. "TASD,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 18. "MRP,Mailboxes Reception Priority" "0: Matching starts from Rx FIFO and continues on..,1: Matching starts from Mailboxes and continues.."
|
|
bitfld.long 0x00 17. "RRS,Remote Request Storing" "0: Remote Response Frame is generated,1: Remote Request Frame is stored"
|
|
newline
|
|
bitfld.long 0x00 16. "EACEN,Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes" "0: Rx Mailbox filter's IDE bit is always..,1: Enables the comparison of both Rx Mailbox.."
|
|
bitfld.long 0x00 15. "TIMER_SRC,Timer Source" "0: The Free Running Timer is clocked by the CAN..,1: The Free Running Timer is clocked by an.."
|
|
newline
|
|
bitfld.long 0x00 14. "PREXCEN,Protocol Exception Enable" "0: Protocol Exception is disabled,1: Protocol Exception is enabled"
|
|
bitfld.long 0x00 12. "ISOCANFDEN,ISO CAN FD Enable" "0: FlexCAN operates using the non-ISO CAN FD..,1: FlexCAN operates using the ISO CAN FD.."
|
|
newline
|
|
bitfld.long 0x00 11. "EDFLTDIS,Edge Filter Disable" "0: Edge Filter is enabled,1: Edge Filter is disabled"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "ESR2,Error and Status 2 register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "LPTM,Lowest Priority Tx Mailbox"
|
|
bitfld.long 0x00 14. "VPS,Valid Priority Status" "0: Contents of IMB and LPTM are invalid,1: Contents of IMB and LPTM are valid"
|
|
newline
|
|
bitfld.long 0x00 13. "IMB,Inactive Mailbox" "0: If ESR2[VPS] is asserted the ESR2[LPTM] is..,1: If ESR2[VPS] is asserted there is at least.."
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "MBCRC,CRC Mailbox"
|
|
hexmask.long.word 0x00 0.--14. 1. "TXCRC,Transmitted CRC value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "FGM,Rx FIFO Global Mask Bits"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. "BTF,Bit Timing Format Enable" "0: Extended bit time definitions disabled,1: Extended bit time definitions enabled"
|
|
hexmask.long.word 0x00 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "ERJW,Extended Resync Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--15. "EPROPSEG,Extended Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "EPSEG1,Extended Phase Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "EPSEG2,Extended Phase Segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x80)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0xC0)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
repeat 16. (strings "32" "33" "34" "35" "36" "37" "38" "39" "40" "41" "42" "43" "44" "45" "46" "47" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x100)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
repeat 16. (strings "48" "49" "50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "60" "61" "62" "63" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x140)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 16. (strings "64" "65" "66" "67" "68" "69" "70" "71" "72" "73" "74" "75" "76" "77" "78" "79" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x180)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
repeat 16. (strings "80" "81" "82" "83" "84" "85" "86" "87" "88" "89" "90" "91" "92" "93" "94" "95" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1C0)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
repeat 16. (strings "96" "97" "98" "99" "100" "101" "102" "103" "104" "105" "106" "107" "108" "109" "110" "111" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
repeat 16. (strings "112" "113" "114" "115" "116" "117" "118" "119" "120" "121" "122" "123" "124" "125" "126" "127" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x240)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x880)++0x03
|
|
line.long 0x00 "RXIMR$1,Rx Individual Mask Registers"
|
|
hexmask.long 0x00 0.--31. 1. "MI,Individual Mask Bits"
|
|
repeat.end
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x8C0)++0x03
|
|
line.long 0x00 "RXIMR$1,Rx Individual Mask Registers"
|
|
hexmask.long 0x00 0.--31. 1. "MI,Individual Mask Bits"
|
|
repeat.end
|
|
endif
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "CTRL1_PN,Pretended Networking Control 1 Register"
|
|
bitfld.long 0x00 17. "WTOF_MSK,Wake Up by Timeout Flag Mask Bit" "0: Timeout wake up event is disabled,1: Timeout wake up event is enabled"
|
|
bitfld.long 0x00 16. "WUMF_MSK,Wake Up by Match Flag Mask Bit" "0: Wake up match event is disabled,1: Wake up match event is enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "NMATCH,Number of Messages Matching the Same Filtering Criteria"
|
|
bitfld.long 0x00 4.--5. "PLFS,Payload Filtering Selection" "0: Match upon a payload contents against an..,1: Match upon a payload value greater than or..,2: Match upon a payload value smaller than or..,3: Match upon a payload value inside a range.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "IDFS,ID Filtering Selection" "0: Match upon a ID contents against an exact..,1: Match upon a ID value greater than or equal..,2: Match upon a ID value smaller than or equal..,3: Match upon a ID value inside a range greater.."
|
|
bitfld.long 0x00 0.--1. "FCS,Filtering Combination Selection" "0: Message ID filtering only,1: Message ID filtering and payload filtering,2: Message ID filtering occurring a specified..,3: Message ID filtering and payload filtering a.."
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MATCHTO,Timeout for No Message Matching the Filtering Criteria"
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "WU_MTC,Pretended Networking Wake Up Match Register"
|
|
bitfld.long 0x00 17. "WTOF,Wake Up by Timeout Flag Bit" "0: No wake up by timeout event detected,1: Wake up by timeout event detected"
|
|
bitfld.long 0x00 16. "WUMF,Wake Up by Match Flag Bit" "0: No wake up by match event detected,1: Wake up by match event detected"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MCOUNTER,Number of Matches while in Pretended Networking"
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 30. "FLT_IDE,ID Extended Filter" "0: Accept standard frame format,1: Accept extended frame format"
|
|
bitfld.long 0x00 29. "FLT_RTR,Remote Transmission Request Filter" "0: Reject remote frame (accept data frame),1: Accept remote frame"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. "FLT_ID1,ID Filter 1 for Pretended Networking filtering"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "FLT_DLC,Pretended Networking DLC Filter Register"
|
|
bitfld.long 0x00 16.--19. "FLT_DLC_LO,Lower Limit for Length of Data Bytes Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "FLT_DLC_HI,Upper Limit for Length of Data Bytes Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 3"
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7"
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "FLT_ID2_IDMASK,Pretended Networking ID Filter 2 Register / ID Mask Register"
|
|
bitfld.long 0x00 30. "IDE_MSK,ID Extended Mask Bit" "0: The corresponding bit in the filter is don't..,1: The corresponding bit in the filter is checked"
|
|
bitfld.long 0x00 29. "RTR_MSK,Remote Transmission Request Mask Bit" "0: The corresponding bit in the filter is don't..,1: The corresponding bit in the filter is checked"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. "FLT_ID2_IDMASK,ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering"
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 3"
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 7"
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "WMB0_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB44++0x03
|
|
line.long 0x00 "WMB0_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "WMB0_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB4C++0x03
|
|
line.long 0x00 "WMB0_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "WMB1_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB54++0x03
|
|
line.long 0x00 "WMB1_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "WMB1_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB5C++0x03
|
|
line.long 0x00 "WMB1_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "WMB2_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB64++0x03
|
|
line.long 0x00 "WMB2_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "WMB2_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB6C++0x03
|
|
line.long 0x00 "WMB2_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "WMB3_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB74++0x03
|
|
line.long 0x00 "WMB3_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "WMB3_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB7C++0x03
|
|
line.long 0x00 "WMB3_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. "FDRATE,Bit Rate Switch Enable" "0: Transmit a frame in nominal rate,1: Transmit a frame with bit rate switching if.."
|
|
bitfld.long 0x00 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: Selects 8 bytes per Message Buffer,1: Selects 16 bytes per Message Buffer,2: Selects 32 bytes per Message Buffer,3: Selects 64 bytes per Message Buffer"
|
|
newline
|
|
bitfld.long 0x00 15. "TDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled"
|
|
bitfld.long 0x00 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: Measured loop delay is in range,1: Measured loop delay is out of range"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "TDCOFF,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 0.--5. "TDCVAL,Transceiver Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "FDCBT,CAN FD Bit Timing Register"
|
|
hexmask.long.word 0x00 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor"
|
|
bitfld.long 0x00 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 10.--14. "FPROPSEG,Fast Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "FDCRC,CAN FD CRC Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. "FD_MBCRC,CRC Mailbox Number for FD_TXCRC"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
tree "FTM (FlexTimer Module)"
|
|
repeat 2. (list 0. 1.) (list ad:0x40038000 ad:0x40039000)
|
|
tree "FTM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC,Status And Control"
|
|
bitfld.long 0x00 24.--27. "FLTPS,Filter Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,8: Divide by 9,9: Divide by 10,10: Divide by 11,11: Divide by 12,12: Divide by 13,13: Divide by 14,14: Divide by 15,15: Divide by 16"
|
|
bitfld.long 0x00 23. "PWMEN7,Channel 7 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 22. "PWMEN6,Channel 6 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 21. "PWMEN5,Channel 5 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "PWMEN4,Channel 4 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 19. "PWMEN3,Channel 3 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "PWMEN2,Channel 2 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 17. "PWMEN1,Channel 1 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "PWMEN0,Channel 0 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
rbitfld.long 0x00 9. "TOF,Timer Overflow Flag" "0: FTM counter has not overflowed,1: FTM counter has overflowed"
|
|
newline
|
|
bitfld.long 0x00 8. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
|
|
rbitfld.long 0x00 7. "RF,Reload Flag" "0: A selected reload point did not happen,1: A selected reload point happened"
|
|
newline
|
|
bitfld.long 0x00 6. "RIE,Reload Point Interrupt Enable" "0: Reload point interrupt is disabled,1: Reload point interrupt is enabled"
|
|
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: FTM counter operates in Up Counting mode,1: FTM counter operates in Up-Down Counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CLKS,Clock Source Selection" "0: No clock selected,1: FTM input clock,2: Fixed frequency clock,3: External clock"
|
|
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Counter Value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MOD,Modulo"
|
|
hexmask.long.word 0x00 0.--15. 1. "MOD,MOD"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "C0SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "C0V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "C1SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "C1V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "C2SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "C2V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "C3SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "C3V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "C4SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "C4V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "C5SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "C5V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "C6SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "C6V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "C7SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "C7V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CNTIN,Counter Initial Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "INIT,INIT"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "STATUS,Capture And Compare Status"
|
|
bitfld.long 0x00 7. "CH7F,Channel 7 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 6. "CH6F,Channel 6 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. "FAULTIE,Fault Interrupt Enable" "0: Fault control interrupt is disabled,1: Fault control interrupt is enabled"
|
|
bitfld.long 0x00 5.--6. "FAULTM,Fault Control Mode" "0: Fault control is disabled for all channels,1: Fault control is enabled for even channels..,2: Fault control is enabled for all channels and..,3: Fault control is enabled for all channels and.."
|
|
newline
|
|
bitfld.long 0x00 4. "CAPTEST,Capture Test Mode Enable" "0: Capture test mode is disabled,1: Capture test mode is enabled"
|
|
bitfld.long 0x00 3. "PWMSYNC,PWM Synchronization Mode" "0: No restrictions,1: Software trigger can only be used by MOD and.."
|
|
newline
|
|
bitfld.long 0x00 2. "WPDIS,Write Protection Disable" "0: Write protection is enabled,1: Write protection is disabled"
|
|
bitfld.long 0x00 1. "INIT,Initialize The Channels Output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "FTMEN,FTM Enable" "0: TPM compatibility,1: Free running counter and synchronization are.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SYNC,Synchronization"
|
|
bitfld.long 0x00 7. "SWSYNC,PWM Synchronization Software Trigger" "0: Software trigger is not selected,1: Software trigger is selected"
|
|
bitfld.long 0x00 6. "TRIG2,PWM Synchronization Hardware Trigger 2" "0: Trigger is disabled,1: Trigger is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "TRIG1,PWM Synchronization Hardware Trigger 1" "0: Trigger is disabled,1: Trigger is enabled"
|
|
bitfld.long 0x00 4. "TRIG0,PWM Synchronization Hardware Trigger 0" "0: Trigger is disabled,1: Trigger is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "SYNCHOM,Output Mask Synchronization" "0: OUTMASK register is updated with the value of..,1: OUTMASK register is updated with the value of.."
|
|
bitfld.long 0x00 2. "REINIT,FTM Counter Reinitialization by Synchronization" "0: FTM counter continues to count normally,1: FTM counter is updated with its initial value.."
|
|
newline
|
|
bitfld.long 0x00 1. "CNTMAX,Maximum Loading Point Enable" "0: The maximum loading point is disabled,1: The maximum loading point is enabled"
|
|
bitfld.long 0x00 0. "CNTMIN,Minimum Loading Point Enable" "0: The minimum loading point is disabled,1: The minimum loading point is enabled"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "OUTINIT,Initial State For Channels Output"
|
|
bitfld.long 0x00 7. "CH7OI,Channel 7 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
bitfld.long 0x00 6. "CH6OI,Channel 6 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5OI,Channel 5 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
bitfld.long 0x00 4. "CH4OI,Channel 4 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3OI,Channel 3 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
bitfld.long 0x00 2. "CH2OI,Channel 2 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1OI,Channel 1 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
bitfld.long 0x00 0. "CH0OI,Channel 0 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OUTMASK,Output Mask"
|
|
bitfld.long 0x00 7. "CH7OM,Channel 7 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
bitfld.long 0x00 6. "CH6OM,Channel 6 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5OM,Channel 5 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
bitfld.long 0x00 4. "CH4OM,Channel 4 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3OM,Channel 3 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
bitfld.long 0x00 2. "CH2OM,Channel 2 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1OM,Channel 1 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
bitfld.long 0x00 0. "CH0OM,Channel 0 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "COMBINE,Function For Linked Channels"
|
|
bitfld.long 0x00 31. "MCOMBINE3,Modified Combine Mode For n = 6" "0,1"
|
|
bitfld.long 0x00 30. "FAULTEN3,Fault Control Enable For n = 6" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
|
|
newline
|
|
bitfld.long 0x00 29. "SYNCEN3,Synchronization Enable For n = 6" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
|
|
bitfld.long 0x00 28. "DTEN3,Deadtime Enable For n = 6" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
|
|
newline
|
|
bitfld.long 0x00 27. "DECAP3,Dual Edge Capture Mode Captures For n = 6" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 26. "DECAPEN3,Dual Edge Capture Mode Enable For n = 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "COMP3,Complement Of Channel (n) for n = 6" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
|
|
bitfld.long 0x00 24. "COMBINE3,Combine Channels For n = 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "MCOMBINE2,Modified Combine Mode For n = 4" "0,1"
|
|
bitfld.long 0x00 22. "FAULTEN2,Fault Control Enable For n = 4" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
|
|
newline
|
|
bitfld.long 0x00 21. "SYNCEN2,Synchronization Enable For n = 4" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
|
|
bitfld.long 0x00 20. "DTEN2,Deadtime Enable For n = 4" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
|
|
newline
|
|
bitfld.long 0x00 19. "DECAP2,Dual Edge Capture Mode Captures For n = 4" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 18. "DECAPEN2,Dual Edge Capture Mode Enable For n = 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "COMP2,Complement Of Channel (n) For n = 4" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
|
|
bitfld.long 0x00 16. "COMBINE2,Combine Channels For n = 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "MCOMBINE1,Modified Combine Mode For n = 2" "0,1"
|
|
bitfld.long 0x00 14. "FAULTEN1,Fault Control Enable For n = 2" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
|
|
newline
|
|
bitfld.long 0x00 13. "SYNCEN1,Synchronization Enable For n = 2" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
|
|
bitfld.long 0x00 12. "DTEN1,Deadtime Enable For n = 2" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
|
|
newline
|
|
bitfld.long 0x00 11. "DECAP1,Dual Edge Capture Mode Captures For n = 2" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 10. "DECAPEN1,Dual Edge Capture Mode Enable For n = 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "COMP1,Complement Of Channel (n) For n = 2" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
|
|
bitfld.long 0x00 8. "COMBINE1,Combine Channels For n = 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "MCOMBINE0,Modified Combine Mode For n = 0" "0,1"
|
|
bitfld.long 0x00 6. "FAULTEN0,Fault Control Enable For n = 0" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
|
|
newline
|
|
bitfld.long 0x00 5. "SYNCEN0,Synchronization Enable For n = 0" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
|
|
bitfld.long 0x00 4. "DTEN0,Deadtime Enable For n = 0" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
|
|
newline
|
|
bitfld.long 0x00 3. "DECAP0,Dual Edge Capture Mode Captures For n = 0" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 2. "DECAPEN0,Dual Edge Capture Mode Enable For n = 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "COMP0,Complement Of Channel (n) For n = 0" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
|
|
bitfld.long 0x00 0. "COMBINE0,Combine Channels For n = 0" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "DEADTIME,Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "EXTTRIG,FTM External Trigger"
|
|
bitfld.long 0x00 9. "CH7TRIG,Channel 7 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
bitfld.long 0x00 8. "CH6TRIG,Channel 6 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
newline
|
|
rbitfld.long 0x00 7. "TRIGF,Channel Trigger Flag" "0: No channel trigger was generated,1: A channel trigger was generated"
|
|
bitfld.long 0x00 6. "INITTRIGEN,Initialization Trigger Enable" "0: The generation of initialization trigger is..,1: The generation of initialization trigger is.."
|
|
newline
|
|
bitfld.long 0x00 5. "CH1TRIG,Channel 1 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
bitfld.long 0x00 4. "CH0TRIG,Channel 0 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
newline
|
|
bitfld.long 0x00 3. "CH5TRIG,Channel 5 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
bitfld.long 0x00 2. "CH4TRIG,Channel 4 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
newline
|
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bitfld.long 0x00 1. "CH3TRIG,Channel 3 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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|
bitfld.long 0x00 0. "CH2TRIG,Channel 2 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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|
group.long 0x70++0x03
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|
line.long 0x00 "POL,Channels Polarity"
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|
bitfld.long 0x00 7. "POL7,Channel 7 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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|
bitfld.long 0x00 6. "POL6,Channel 6 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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|
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bitfld.long 0x00 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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|
bitfld.long 0x00 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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|
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bitfld.long 0x00 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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|
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bitfld.long 0x00 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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|
bitfld.long 0x00 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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|
group.long 0x74++0x03
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|
line.long 0x00 "FMS,Fault Mode Status"
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|
rbitfld.long 0x00 7. "FAULTF,Fault Detection Flag" "0: No fault condition was detected,1: A fault condition was detected"
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|
bitfld.long 0x00 6. "WPEN,Write Protection Enable" "0: Write protection is disabled,1: Write protection is enabled"
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|
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rbitfld.long 0x00 5. "FAULTIN,Fault Inputs" "0: The logic OR of the enabled fault inputs is 0,1: The logic OR of the enabled fault inputs is 1"
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|
rbitfld.long 0x00 3. "FAULTF3,Fault Detection Flag 3" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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|
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rbitfld.long 0x00 2. "FAULTF2,Fault Detection Flag 2" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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rbitfld.long 0x00 1. "FAULTF1,Fault Detection Flag 1" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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|
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rbitfld.long 0x00 0. "FAULTF0,Fault Detection Flag 0" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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|
group.long 0x78++0x03
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|
line.long 0x00 "FILTER,Input Capture Filter Control"
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|
bitfld.long 0x00 12.--15. "CH3FVAL,Channel 3 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 8.--11. "CH2FVAL,Channel 2 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 4.--7. "CH1FVAL,Channel 1 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 0.--3. "CH0FVAL,Channel 0 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
group.long 0x7C++0x03
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line.long 0x00 "FLTCTRL,Fault Control"
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|
bitfld.long 0x00 15. "FSTATE,Fault output state" "0: FTM outputs will be placed into safe values..,1: FTM outputs will be tri-stated when fault.."
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|
bitfld.long 0x00 8.--11. "FFVAL,Fault Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
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bitfld.long 0x00 7. "FFLTR3EN,Fault Input 3 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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|
bitfld.long 0x00 6. "FFLTR2EN,Fault Input 2 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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|
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bitfld.long 0x00 5. "FFLTR1EN,Fault Input 1 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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|
bitfld.long 0x00 4. "FFLTR0EN,Fault Input 0 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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|
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bitfld.long 0x00 3. "FAULT3EN,Fault Input 3 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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|
bitfld.long 0x00 2. "FAULT2EN,Fault Input 2 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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|
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bitfld.long 0x00 1. "FAULT1EN,Fault Input 1 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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|
bitfld.long 0x00 0. "FAULT0EN,Fault Input 0 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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|
group.long 0x80++0x03
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line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status"
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|
bitfld.long 0x00 7. "PHAFLTREN,Phase A Input Filter Enable" "0: Phase A input filter is disabled,1: Phase A input filter is enabled"
|
|
bitfld.long 0x00 6. "PHBFLTREN,Phase B Input Filter Enable" "0: Phase B input filter is disabled,1: Phase B input filter is enabled"
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bitfld.long 0x00 5. "PHAPOL,Phase A Input Polarity" "0: Normal polarity,1: Inverted polarity"
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|
bitfld.long 0x00 4. "PHBPOL,Phase B Input Polarity" "0: Normal polarity,1: Inverted polarity"
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|
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bitfld.long 0x00 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase A and phase B encoding mode,1: Count and direction encoding mode"
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|
rbitfld.long 0x00 2. "QUADIR,FTM Counter Direction In Quadrature Decoder Mode" "0: Counting direction is decreasing (FTM counter..,1: Counting direction is increasing (FTM counter.."
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|
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rbitfld.long 0x00 1. "TOFDIR,Timer Overflow Direction In Quadrature Decoder Mode" "0: TOF bit was set on the bottom of counting,1: TOF bit was set on the top of counting"
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|
bitfld.long 0x00 0. "QUADEN,Quadrature Decoder Mode Enable" "0: Quadrature Decoder mode is disabled,1: Quadrature Decoder mode is enabled"
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|
group.long 0x84++0x03
|
|
line.long 0x00 "CONF,Configuration"
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|
bitfld.long 0x00 11. "ITRIGR,Initialization trigger on Reload Point" "0: Initialization trigger is generated on..,1: Initialization trigger is generated when a.."
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|
bitfld.long 0x00 10. "GTBEOUT,Global Time Base Output" "0,1"
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|
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bitfld.long 0x00 9. "GTBEEN,Global Time Base Enable" "0,1"
|
|
bitfld.long 0x00 6.--7. "BDMMODE,Debug Mode" "0,1,2,3"
|
|
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bitfld.long 0x00 0.--4. "LDFQ,Frequency of the Reload Opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FLTPOL,FTM Fault Input Polarity"
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|
bitfld.long 0x00 3. "FLT3POL,Fault Input 3 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
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|
bitfld.long 0x00 2. "FLT2POL,Fault Input 2 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
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|
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bitfld.long 0x00 1. "FLT1POL,Fault Input 1 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
|
|
bitfld.long 0x00 0. "FLT0POL,Fault Input 0 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SYNCONF,Synchronization Configuration"
|
|
bitfld.long 0x00 20. "HWSOC,Software output control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the SWOCTRL.."
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|
bitfld.long 0x00 19. "HWINVC,Inverting control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the INVCTRL.."
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bitfld.long 0x00 18. "HWOM,Output mask synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the OUTMASK.."
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|
bitfld.long 0x00 17. "HWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate MOD HCR..,1: A hardware trigger activates MOD HCR CNTIN.."
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bitfld.long 0x00 16. "HWRSTCNT,FTM counter synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the FTM..,1: A hardware trigger activates the FTM counter.."
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|
bitfld.long 0x00 12. "SWSOC,Software output control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the SWOCTRL.."
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|
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bitfld.long 0x00 11. "SWINVC,Inverting control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the INVCTRL.."
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|
bitfld.long 0x00 10. "SWOM,Output mask synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the OUTMASK.."
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bitfld.long 0x00 9. "SWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by the software trigger" "0: The software trigger does not activate MOD..,1: The software trigger activates MOD HCR CNTIN.."
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|
bitfld.long 0x00 8. "SWRSTCNT,FTM counter synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the FTM.."
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bitfld.long 0x00 7. "SYNCMODE,Synchronization Mode" "0: Legacy PWM synchronization is selected,1: Enhanced PWM synchronization is selected"
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|
bitfld.long 0x00 5. "SWOC,SWOCTRL Register Synchronization" "0: SWOCTRL register is updated with its buffer..,1: SWOCTRL register is updated with its buffer.."
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bitfld.long 0x00 4. "INVC,INVCTRL Register Synchronization" "0: INVCTRL register is updated with its buffer..,1: INVCTRL register is updated with its buffer.."
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|
bitfld.long 0x00 2. "CNTINC,CNTIN Register Synchronization" "0: CNTIN register is updated with its buffer..,1: CNTIN register is updated with its buffer.."
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bitfld.long 0x00 0. "HWTRIGMODE,Hardware Trigger Mode" "0: FTM clears the TRIGj bit when the hardware..,1: FTM does not clear the TRIGj bit when the.."
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|
group.long 0x90++0x03
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|
line.long 0x00 "INVCTRL,FTM Inverting Control"
|
|
bitfld.long 0x00 3. "INV3EN,Pair Channels 3 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
bitfld.long 0x00 2. "INV2EN,Pair Channels 2 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
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|
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bitfld.long 0x00 1. "INV1EN,Pair Channels 1 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
bitfld.long 0x00 0. "INV0EN,Pair Channels 0 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
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|
group.long 0x94++0x03
|
|
line.long 0x00 "SWOCTRL,FTM Software Output Control"
|
|
bitfld.long 0x00 15. "CH7OCV,Channel 7 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 14. "CH6OCV,Channel 6 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 13. "CH5OCV,Channel 5 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 12. "CH4OCV,Channel 4 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 11. "CH3OCV,Channel 3 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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|
bitfld.long 0x00 10. "CH2OCV,Channel 2 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 9. "CH1OCV,Channel 1 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 8. "CH0OCV,Channel 0 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 7. "CH7OC,Channel 7 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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|
bitfld.long 0x00 6. "CH6OC,Channel 6 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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|
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bitfld.long 0x00 5. "CH5OC,Channel 5 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 4. "CH4OC,Channel 4 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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bitfld.long 0x00 3. "CH3OC,Channel 3 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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|
bitfld.long 0x00 2. "CH2OC,Channel 2 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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|
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bitfld.long 0x00 1. "CH1OC,Channel 1 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 0. "CH0OC,Channel 0 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PWMLOAD,FTM PWM Load"
|
|
bitfld.long 0x00 11. "GLDOK,Global Load OK" "0: No action,1: LDOK bit is set"
|
|
bitfld.long 0x00 10. "GLEN,Global Load Enable" "0: Global Load Ok disabled,1: Global Load OK enabled"
|
|
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|
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bitfld.long 0x00 9. "LDOK,Load Enable" "0: Loading updated values is disabled,1: Loading updated values is enabled"
|
|
bitfld.long 0x00 8. "HCSEL,Half Cycle Select" "0: Half cycle reload is disabled and it is not..,1: Half cycle reload is enabled and it is.."
|
|
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|
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bitfld.long 0x00 7. "CH7SEL,Channel 7 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 6. "CH6SEL,Channel 6 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
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|
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bitfld.long 0x00 5. "CH5SEL,Channel 5 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 4. "CH4SEL,Channel 4 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
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|
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bitfld.long 0x00 3. "CH3SEL,Channel 3 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 2. "CH2SEL,Channel 2 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
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|
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bitfld.long 0x00 1. "CH1SEL,Channel 1 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 0. "CH0SEL,Channel 0 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "HCR,Half Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "HCVAL,Half Cycle Value"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PAIR0DEADTIME,Pair 0 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
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|
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|
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bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PAIR1DEADTIME,Pair 1 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
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bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PAIR2DEADTIME,Pair 2 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
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|
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bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PAIR3DEADTIME,Pair 3 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
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|
|
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MOD_MIRROR,Mirror of Modulo Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "MOD,Mirror of the Modulo Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACMOD,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "C0V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "C1V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "C2V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "C3V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "C4V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "C5V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "C6V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "C7V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (list 2. 3.) (list ad:0x4003A000 ad:0x40026000)
|
|
tree "FTM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC,Status And Control"
|
|
bitfld.long 0x00 24.--27. "FLTPS,Filter Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,8: Divide by 9,9: Divide by 10,10: Divide by 11,11: Divide by 12,12: Divide by 13,13: Divide by 14,14: Divide by 15,15: Divide by 16"
|
|
bitfld.long 0x00 23. "PWMEN7,Channel 7 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 22. "PWMEN6,Channel 6 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 21. "PWMEN5,Channel 5 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "PWMEN4,Channel 4 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 19. "PWMEN3,Channel 3 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "PWMEN2,Channel 2 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 17. "PWMEN1,Channel 1 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "PWMEN0,Channel 0 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
rbitfld.long 0x00 9. "TOF,Timer Overflow Flag" "0: FTM counter has not overflowed,1: FTM counter has overflowed"
|
|
newline
|
|
bitfld.long 0x00 8. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
|
|
rbitfld.long 0x00 7. "RF,Reload Flag" "0: A selected reload point did not happen,1: A selected reload point happened"
|
|
newline
|
|
bitfld.long 0x00 6. "RIE,Reload Point Interrupt Enable" "0: Reload point interrupt is disabled,1: Reload point interrupt is enabled"
|
|
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: FTM counter operates in Up Counting mode,1: FTM counter operates in Up-Down Counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CLKS,Clock Source Selection" "0: No clock selected,1: FTM input clock,2: Fixed frequency clock,3: External clock"
|
|
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Counter Value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MOD,Modulo"
|
|
hexmask.long.word 0x00 0.--15. 1. "MOD,MOD"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "C0SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "C0V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "C1SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "C1V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "C2SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "C2V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "C3SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "C3V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "C4SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "C4V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "C5SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "C5V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "C6SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "C6V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "C7SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "C7V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CNTIN,Counter Initial Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "INIT,INIT"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "STATUS,Capture And Compare Status"
|
|
bitfld.long 0x00 7. "CH7F,Channel 7 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 6. "CH6F,Channel 6 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. "FAULTIE,Fault Interrupt Enable" "0: Fault control interrupt is disabled,1: Fault control interrupt is enabled"
|
|
bitfld.long 0x00 5.--6. "FAULTM,Fault Control Mode" "0: Fault control is disabled for all channels,1: Fault control is enabled for even channels..,2: Fault control is enabled for all channels and..,3: Fault control is enabled for all channels and.."
|
|
newline
|
|
bitfld.long 0x00 4. "CAPTEST,Capture Test Mode Enable" "0: Capture test mode is disabled,1: Capture test mode is enabled"
|
|
bitfld.long 0x00 3. "PWMSYNC,PWM Synchronization Mode" "0: No restrictions,1: Software trigger can only be used by MOD and.."
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|
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bitfld.long 0x00 2. "WPDIS,Write Protection Disable" "0: Write protection is enabled,1: Write protection is disabled"
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|
bitfld.long 0x00 1. "INIT,Initialize The Channels Output" "0,1"
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|
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bitfld.long 0x00 0. "FTMEN,FTM Enable" "0: TPM compatibility,1: Free running counter and synchronization are.."
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|
group.long 0x58++0x03
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|
line.long 0x00 "SYNC,Synchronization"
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|
bitfld.long 0x00 7. "SWSYNC,PWM Synchronization Software Trigger" "0: Software trigger is not selected,1: Software trigger is selected"
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|
bitfld.long 0x00 6. "TRIG2,PWM Synchronization Hardware Trigger 2" "0: Trigger is disabled,1: Trigger is enabled"
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bitfld.long 0x00 5. "TRIG1,PWM Synchronization Hardware Trigger 1" "0: Trigger is disabled,1: Trigger is enabled"
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|
bitfld.long 0x00 4. "TRIG0,PWM Synchronization Hardware Trigger 0" "0: Trigger is disabled,1: Trigger is enabled"
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bitfld.long 0x00 3. "SYNCHOM,Output Mask Synchronization" "0: OUTMASK register is updated with the value of..,1: OUTMASK register is updated with the value of.."
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|
bitfld.long 0x00 2. "REINIT,FTM Counter Reinitialization by Synchronization" "0: FTM counter continues to count normally,1: FTM counter is updated with its initial value.."
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|
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bitfld.long 0x00 1. "CNTMAX,Maximum Loading Point Enable" "0: The maximum loading point is disabled,1: The maximum loading point is enabled"
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|
bitfld.long 0x00 0. "CNTMIN,Minimum Loading Point Enable" "0: The minimum loading point is disabled,1: The minimum loading point is enabled"
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|
group.long 0x5C++0x03
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line.long 0x00 "OUTINIT,Initial State For Channels Output"
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|
bitfld.long 0x00 7. "CH7OI,Channel 7 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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|
bitfld.long 0x00 6. "CH6OI,Channel 6 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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|
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bitfld.long 0x00 5. "CH5OI,Channel 5 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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bitfld.long 0x00 4. "CH4OI,Channel 4 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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|
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bitfld.long 0x00 3. "CH3OI,Channel 3 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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bitfld.long 0x00 2. "CH2OI,Channel 2 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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bitfld.long 0x00 1. "CH1OI,Channel 1 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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bitfld.long 0x00 0. "CH0OI,Channel 0 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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|
group.long 0x60++0x03
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line.long 0x00 "OUTMASK,Output Mask"
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|
bitfld.long 0x00 7. "CH7OM,Channel 7 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 6. "CH6OM,Channel 6 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 5. "CH5OM,Channel 5 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 4. "CH4OM,Channel 4 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 3. "CH3OM,Channel 3 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 2. "CH2OM,Channel 2 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 1. "CH1OM,Channel 1 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 0. "CH0OM,Channel 0 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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|
group.long 0x64++0x03
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line.long 0x00 "COMBINE,Function For Linked Channels"
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|
bitfld.long 0x00 31. "MCOMBINE3,Modified Combine Mode For n = 6" "0,1"
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|
bitfld.long 0x00 30. "FAULTEN3,Fault Control Enable For n = 6" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
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bitfld.long 0x00 29. "SYNCEN3,Synchronization Enable For n = 6" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
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|
bitfld.long 0x00 28. "DTEN3,Deadtime Enable For n = 6" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
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|
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bitfld.long 0x00 27. "DECAP3,Dual Edge Capture Mode Captures For n = 6" "0: The dual edge captures are inactive,1: The dual edge captures are active"
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|
bitfld.long 0x00 26. "DECAPEN3,Dual Edge Capture Mode Enable For n = 6" "0,1"
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|
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bitfld.long 0x00 25. "COMP3,Complement Of Channel (n) for n = 6" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
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bitfld.long 0x00 24. "COMBINE3,Combine Channels For n = 6" "0,1"
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|
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bitfld.long 0x00 23. "MCOMBINE2,Modified Combine Mode For n = 4" "0,1"
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|
bitfld.long 0x00 22. "FAULTEN2,Fault Control Enable For n = 4" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
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bitfld.long 0x00 21. "SYNCEN2,Synchronization Enable For n = 4" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
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bitfld.long 0x00 20. "DTEN2,Deadtime Enable For n = 4" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
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|
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bitfld.long 0x00 19. "DECAP2,Dual Edge Capture Mode Captures For n = 4" "0: The dual edge captures are inactive,1: The dual edge captures are active"
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|
bitfld.long 0x00 18. "DECAPEN2,Dual Edge Capture Mode Enable For n = 4" "0,1"
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|
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bitfld.long 0x00 17. "COMP2,Complement Of Channel (n) For n = 4" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
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bitfld.long 0x00 16. "COMBINE2,Combine Channels For n = 4" "0,1"
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|
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bitfld.long 0x00 15. "MCOMBINE1,Modified Combine Mode For n = 2" "0,1"
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|
bitfld.long 0x00 14. "FAULTEN1,Fault Control Enable For n = 2" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
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|
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bitfld.long 0x00 13. "SYNCEN1,Synchronization Enable For n = 2" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
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|
bitfld.long 0x00 12. "DTEN1,Deadtime Enable For n = 2" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
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|
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bitfld.long 0x00 11. "DECAP1,Dual Edge Capture Mode Captures For n = 2" "0: The dual edge captures are inactive,1: The dual edge captures are active"
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|
bitfld.long 0x00 10. "DECAPEN1,Dual Edge Capture Mode Enable For n = 2" "0,1"
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|
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bitfld.long 0x00 9. "COMP1,Complement Of Channel (n) For n = 2" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
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|
bitfld.long 0x00 8. "COMBINE1,Combine Channels For n = 2" "0,1"
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|
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bitfld.long 0x00 7. "MCOMBINE0,Modified Combine Mode For n = 0" "0,1"
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|
bitfld.long 0x00 6. "FAULTEN0,Fault Control Enable For n = 0" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
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|
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bitfld.long 0x00 5. "SYNCEN0,Synchronization Enable For n = 0" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
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|
bitfld.long 0x00 4. "DTEN0,Deadtime Enable For n = 0" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
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bitfld.long 0x00 3. "DECAP0,Dual Edge Capture Mode Captures For n = 0" "0: The dual edge captures are inactive,1: The dual edge captures are active"
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|
bitfld.long 0x00 2. "DECAPEN0,Dual Edge Capture Mode Enable For n = 0" "0,1"
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|
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|
|
bitfld.long 0x00 1. "COMP0,Complement Of Channel (n) For n = 0" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
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|
bitfld.long 0x00 0. "COMBINE0,Combine Channels For n = 0" "0,1"
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|
group.long 0x68++0x03
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line.long 0x00 "DEADTIME,Deadtime Configuration"
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bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
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|
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bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x6C++0x03
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line.long 0x00 "EXTTRIG,FTM External Trigger"
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bitfld.long 0x00 9. "CH7TRIG,Channel 7 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 8. "CH6TRIG,Channel 6 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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rbitfld.long 0x00 7. "TRIGF,Channel Trigger Flag" "0: No channel trigger was generated,1: A channel trigger was generated"
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bitfld.long 0x00 6. "INITTRIGEN,Initialization Trigger Enable" "0: The generation of initialization trigger is..,1: The generation of initialization trigger is.."
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bitfld.long 0x00 5. "CH1TRIG,Channel 1 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 4. "CH0TRIG,Channel 0 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 3. "CH5TRIG,Channel 5 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 2. "CH4TRIG,Channel 4 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 1. "CH3TRIG,Channel 3 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 0. "CH2TRIG,Channel 2 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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group.long 0x70++0x03
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line.long 0x00 "POL,Channels Polarity"
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bitfld.long 0x00 7. "POL7,Channel 7 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 6. "POL6,Channel 6 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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group.long 0x74++0x03
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line.long 0x00 "FMS,Fault Mode Status"
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|
rbitfld.long 0x00 7. "FAULTF,Fault Detection Flag" "0: No fault condition was detected,1: A fault condition was detected"
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bitfld.long 0x00 6. "WPEN,Write Protection Enable" "0: Write protection is disabled,1: Write protection is enabled"
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rbitfld.long 0x00 5. "FAULTIN,Fault Inputs" "0: The logic OR of the enabled fault inputs is 0,1: The logic OR of the enabled fault inputs is 1"
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rbitfld.long 0x00 3. "FAULTF3,Fault Detection Flag 3" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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rbitfld.long 0x00 2. "FAULTF2,Fault Detection Flag 2" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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rbitfld.long 0x00 1. "FAULTF1,Fault Detection Flag 1" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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rbitfld.long 0x00 0. "FAULTF0,Fault Detection Flag 0" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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group.long 0x78++0x03
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line.long 0x00 "FILTER,Input Capture Filter Control"
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|
bitfld.long 0x00 12.--15. "CH3FVAL,Channel 3 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "CH2FVAL,Channel 2 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "CH1FVAL,Channel 1 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "CH0FVAL,Channel 0 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x7C++0x03
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line.long 0x00 "FLTCTRL,Fault Control"
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bitfld.long 0x00 15. "FSTATE,Fault output state" "0: FTM outputs will be placed into safe values..,1: FTM outputs will be tri-stated when fault.."
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bitfld.long 0x00 8.--11. "FFVAL,Fault Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "FFLTR3EN,Fault Input 3 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
|
|
bitfld.long 0x00 6. "FFLTR2EN,Fault Input 2 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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bitfld.long 0x00 5. "FFLTR1EN,Fault Input 1 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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|
bitfld.long 0x00 4. "FFLTR0EN,Fault Input 0 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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newline
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bitfld.long 0x00 3. "FAULT3EN,Fault Input 3 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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|
bitfld.long 0x00 2. "FAULT2EN,Fault Input 2 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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bitfld.long 0x00 1. "FAULT1EN,Fault Input 1 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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|
bitfld.long 0x00 0. "FAULT0EN,Fault Input 0 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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group.long 0x80++0x03
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line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status"
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bitfld.long 0x00 7. "PHAFLTREN,Phase A Input Filter Enable" "0: Phase A input filter is disabled,1: Phase A input filter is enabled"
|
|
bitfld.long 0x00 6. "PHBFLTREN,Phase B Input Filter Enable" "0: Phase B input filter is disabled,1: Phase B input filter is enabled"
|
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bitfld.long 0x00 5. "PHAPOL,Phase A Input Polarity" "0: Normal polarity,1: Inverted polarity"
|
|
bitfld.long 0x00 4. "PHBPOL,Phase B Input Polarity" "0: Normal polarity,1: Inverted polarity"
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|
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bitfld.long 0x00 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase A and phase B encoding mode,1: Count and direction encoding mode"
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|
rbitfld.long 0x00 2. "QUADIR,FTM Counter Direction In Quadrature Decoder Mode" "0: Counting direction is decreasing (FTM counter..,1: Counting direction is increasing (FTM counter.."
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rbitfld.long 0x00 1. "TOFDIR,Timer Overflow Direction In Quadrature Decoder Mode" "0: TOF bit was set on the bottom of counting,1: TOF bit was set on the top of counting"
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|
bitfld.long 0x00 0. "QUADEN,Quadrature Decoder Mode Enable" "0: Quadrature Decoder mode is disabled,1: Quadrature Decoder mode is enabled"
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|
group.long 0x84++0x03
|
|
line.long 0x00 "CONF,Configuration"
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|
bitfld.long 0x00 11. "ITRIGR,Initialization trigger on Reload Point" "0: Initialization trigger is generated on..,1: Initialization trigger is generated when a.."
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|
bitfld.long 0x00 10. "GTBEOUT,Global Time Base Output" "0,1"
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|
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|
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bitfld.long 0x00 9. "GTBEEN,Global Time Base Enable" "0,1"
|
|
bitfld.long 0x00 6.--7. "BDMMODE,Debug Mode" "0,1,2,3"
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|
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|
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bitfld.long 0x00 0.--4. "LDFQ,Frequency of the Reload Opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FLTPOL,FTM Fault Input Polarity"
|
|
bitfld.long 0x00 3. "FLT3POL,Fault Input 3 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
|
|
bitfld.long 0x00 2. "FLT2POL,Fault Input 2 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
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|
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|
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bitfld.long 0x00 1. "FLT1POL,Fault Input 1 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
|
|
bitfld.long 0x00 0. "FLT0POL,Fault Input 0 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SYNCONF,Synchronization Configuration"
|
|
bitfld.long 0x00 20. "HWSOC,Software output control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the SWOCTRL.."
|
|
bitfld.long 0x00 19. "HWINVC,Inverting control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the INVCTRL.."
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|
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bitfld.long 0x00 18. "HWOM,Output mask synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the OUTMASK.."
|
|
bitfld.long 0x00 17. "HWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate MOD HCR..,1: A hardware trigger activates MOD HCR CNTIN.."
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|
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bitfld.long 0x00 16. "HWRSTCNT,FTM counter synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the FTM..,1: A hardware trigger activates the FTM counter.."
|
|
bitfld.long 0x00 12. "SWSOC,Software output control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the SWOCTRL.."
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|
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bitfld.long 0x00 11. "SWINVC,Inverting control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the INVCTRL.."
|
|
bitfld.long 0x00 10. "SWOM,Output mask synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the OUTMASK.."
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|
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|
bitfld.long 0x00 9. "SWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by the software trigger" "0: The software trigger does not activate MOD..,1: The software trigger activates MOD HCR CNTIN.."
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|
bitfld.long 0x00 8. "SWRSTCNT,FTM counter synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the FTM.."
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|
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|
|
bitfld.long 0x00 7. "SYNCMODE,Synchronization Mode" "0: Legacy PWM synchronization is selected,1: Enhanced PWM synchronization is selected"
|
|
bitfld.long 0x00 5. "SWOC,SWOCTRL Register Synchronization" "0: SWOCTRL register is updated with its buffer..,1: SWOCTRL register is updated with its buffer.."
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|
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|
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bitfld.long 0x00 4. "INVC,INVCTRL Register Synchronization" "0: INVCTRL register is updated with its buffer..,1: INVCTRL register is updated with its buffer.."
|
|
bitfld.long 0x00 2. "CNTINC,CNTIN Register Synchronization" "0: CNTIN register is updated with its buffer..,1: CNTIN register is updated with its buffer.."
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|
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|
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bitfld.long 0x00 0. "HWTRIGMODE,Hardware Trigger Mode" "0: FTM clears the TRIGj bit when the hardware..,1: FTM does not clear the TRIGj bit when the.."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "INVCTRL,FTM Inverting Control"
|
|
bitfld.long 0x00 3. "INV3EN,Pair Channels 3 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
bitfld.long 0x00 2. "INV2EN,Pair Channels 2 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "INV1EN,Pair Channels 1 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
bitfld.long 0x00 0. "INV0EN,Pair Channels 0 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "SWOCTRL,FTM Software Output Control"
|
|
bitfld.long 0x00 15. "CH7OCV,Channel 7 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
bitfld.long 0x00 14. "CH6OCV,Channel 6 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
newline
|
|
bitfld.long 0x00 13. "CH5OCV,Channel 5 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
bitfld.long 0x00 12. "CH4OCV,Channel 4 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
newline
|
|
bitfld.long 0x00 11. "CH3OCV,Channel 3 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
bitfld.long 0x00 10. "CH2OCV,Channel 2 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
newline
|
|
bitfld.long 0x00 9. "CH1OCV,Channel 1 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
bitfld.long 0x00 8. "CH0OCV,Channel 0 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
newline
|
|
bitfld.long 0x00 7. "CH7OC,Channel 7 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 6. "CH6OC,Channel 6 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
newline
|
|
bitfld.long 0x00 5. "CH5OC,Channel 5 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 4. "CH4OC,Channel 4 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
newline
|
|
bitfld.long 0x00 3. "CH3OC,Channel 3 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 2. "CH2OC,Channel 2 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
newline
|
|
bitfld.long 0x00 1. "CH1OC,Channel 1 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 0. "CH0OC,Channel 0 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PWMLOAD,FTM PWM Load"
|
|
bitfld.long 0x00 11. "GLDOK,Global Load OK" "0: No action,1: LDOK bit is set"
|
|
bitfld.long 0x00 10. "GLEN,Global Load Enable" "0: Global Load Ok disabled,1: Global Load OK enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "LDOK,Load Enable" "0: Loading updated values is disabled,1: Loading updated values is enabled"
|
|
bitfld.long 0x00 8. "HCSEL,Half Cycle Select" "0: Half cycle reload is disabled and it is not..,1: Half cycle reload is enabled and it is.."
|
|
newline
|
|
bitfld.long 0x00 7. "CH7SEL,Channel 7 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 6. "CH6SEL,Channel 6 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
newline
|
|
bitfld.long 0x00 5. "CH5SEL,Channel 5 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 4. "CH4SEL,Channel 4 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
newline
|
|
bitfld.long 0x00 3. "CH3SEL,Channel 3 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 2. "CH2SEL,Channel 2 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
newline
|
|
bitfld.long 0x00 1. "CH1SEL,Channel 1 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 0. "CH0SEL,Channel 0 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "HCR,Half Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "HCVAL,Half Cycle Value"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PAIR0DEADTIME,Pair 0 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PAIR1DEADTIME,Pair 1 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PAIR2DEADTIME,Pair 2 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PAIR3DEADTIME,Pair 3 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MOD_MIRROR,Mirror of Modulo Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "MOD,Mirror of the Modulo Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACMOD,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "C0V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "C1V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "C2V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "C3V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "C4V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "C5V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "C6V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "C7V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (list 4. 5.) (list ad:0x4006E000 ad:0x4006F000)
|
|
tree "FTM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC,Status And Control"
|
|
bitfld.long 0x00 24.--27. "FLTPS,Filter Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,8: Divide by 9,9: Divide by 10,10: Divide by 11,11: Divide by 12,12: Divide by 13,13: Divide by 14,14: Divide by 15,15: Divide by 16"
|
|
bitfld.long 0x00 23. "PWMEN7,Channel 7 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 22. "PWMEN6,Channel 6 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 21. "PWMEN5,Channel 5 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "PWMEN4,Channel 4 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 19. "PWMEN3,Channel 3 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "PWMEN2,Channel 2 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 17. "PWMEN1,Channel 1 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "PWMEN0,Channel 0 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
rbitfld.long 0x00 9. "TOF,Timer Overflow Flag" "0: FTM counter has not overflowed,1: FTM counter has overflowed"
|
|
newline
|
|
bitfld.long 0x00 8. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
|
|
rbitfld.long 0x00 7. "RF,Reload Flag" "0: A selected reload point did not happen,1: A selected reload point happened"
|
|
newline
|
|
bitfld.long 0x00 6. "RIE,Reload Point Interrupt Enable" "0: Reload point interrupt is disabled,1: Reload point interrupt is enabled"
|
|
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: FTM counter operates in Up Counting mode,1: FTM counter operates in Up-Down Counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CLKS,Clock Source Selection" "0: No clock selected,1: FTM input clock,2: Fixed frequency clock,3: External clock"
|
|
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Counter Value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MOD,Modulo"
|
|
hexmask.long.word 0x00 0.--15. 1. "MOD,MOD"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "C0SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "C0V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "C1SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "C1V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "C2SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
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bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "C2V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "C3SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
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bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "C3V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "C4SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "C4V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "C5SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
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bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "C5V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "C6SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "C6V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "C7SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "C7V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CNTIN,Counter Initial Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "INIT,INIT"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "STATUS,Capture And Compare Status"
|
|
bitfld.long 0x00 7. "CH7F,Channel 7 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 6. "CH6F,Channel 6 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. "FAULTIE,Fault Interrupt Enable" "0: Fault control interrupt is disabled,1: Fault control interrupt is enabled"
|
|
bitfld.long 0x00 5.--6. "FAULTM,Fault Control Mode" "0: Fault control is disabled for all channels,1: Fault control is enabled for even channels..,2: Fault control is enabled for all channels and..,3: Fault control is enabled for all channels and.."
|
|
newline
|
|
bitfld.long 0x00 4. "CAPTEST,Capture Test Mode Enable" "0: Capture test mode is disabled,1: Capture test mode is enabled"
|
|
bitfld.long 0x00 3. "PWMSYNC,PWM Synchronization Mode" "0: No restrictions,1: Software trigger can only be used by MOD and.."
|
|
newline
|
|
bitfld.long 0x00 2. "WPDIS,Write Protection Disable" "0: Write protection is enabled,1: Write protection is disabled"
|
|
bitfld.long 0x00 1. "INIT,Initialize The Channels Output" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "FTMEN,FTM Enable" "0: TPM compatibility,1: Free running counter and synchronization are.."
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "SYNC,Synchronization"
|
|
bitfld.long 0x00 7. "SWSYNC,PWM Synchronization Software Trigger" "0: Software trigger is not selected,1: Software trigger is selected"
|
|
bitfld.long 0x00 6. "TRIG2,PWM Synchronization Hardware Trigger 2" "0: Trigger is disabled,1: Trigger is enabled"
|
|
newline
|
|
bitfld.long 0x00 5. "TRIG1,PWM Synchronization Hardware Trigger 1" "0: Trigger is disabled,1: Trigger is enabled"
|
|
bitfld.long 0x00 4. "TRIG0,PWM Synchronization Hardware Trigger 0" "0: Trigger is disabled,1: Trigger is enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "SYNCHOM,Output Mask Synchronization" "0: OUTMASK register is updated with the value of..,1: OUTMASK register is updated with the value of.."
|
|
bitfld.long 0x00 2. "REINIT,FTM Counter Reinitialization by Synchronization" "0: FTM counter continues to count normally,1: FTM counter is updated with its initial value.."
|
|
newline
|
|
bitfld.long 0x00 1. "CNTMAX,Maximum Loading Point Enable" "0: The maximum loading point is disabled,1: The maximum loading point is enabled"
|
|
bitfld.long 0x00 0. "CNTMIN,Minimum Loading Point Enable" "0: The minimum loading point is disabled,1: The minimum loading point is enabled"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "OUTINIT,Initial State For Channels Output"
|
|
bitfld.long 0x00 7. "CH7OI,Channel 7 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
bitfld.long 0x00 6. "CH6OI,Channel 6 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5OI,Channel 5 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
bitfld.long 0x00 4. "CH4OI,Channel 4 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3OI,Channel 3 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
bitfld.long 0x00 2. "CH2OI,Channel 2 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1OI,Channel 1 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
bitfld.long 0x00 0. "CH0OI,Channel 0 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "OUTMASK,Output Mask"
|
|
bitfld.long 0x00 7. "CH7OM,Channel 7 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
bitfld.long 0x00 6. "CH6OM,Channel 6 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5OM,Channel 5 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
bitfld.long 0x00 4. "CH4OM,Channel 4 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3OM,Channel 3 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
bitfld.long 0x00 2. "CH2OM,Channel 2 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1OM,Channel 1 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
bitfld.long 0x00 0. "CH0OM,Channel 0 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "COMBINE,Function For Linked Channels"
|
|
bitfld.long 0x00 31. "MCOMBINE3,Modified Combine Mode For n = 6" "0,1"
|
|
bitfld.long 0x00 30. "FAULTEN3,Fault Control Enable For n = 6" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
|
|
newline
|
|
bitfld.long 0x00 29. "SYNCEN3,Synchronization Enable For n = 6" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
|
|
bitfld.long 0x00 28. "DTEN3,Deadtime Enable For n = 6" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
|
|
newline
|
|
bitfld.long 0x00 27. "DECAP3,Dual Edge Capture Mode Captures For n = 6" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 26. "DECAPEN3,Dual Edge Capture Mode Enable For n = 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 25. "COMP3,Complement Of Channel (n) for n = 6" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
|
|
bitfld.long 0x00 24. "COMBINE3,Combine Channels For n = 6" "0,1"
|
|
newline
|
|
bitfld.long 0x00 23. "MCOMBINE2,Modified Combine Mode For n = 4" "0,1"
|
|
bitfld.long 0x00 22. "FAULTEN2,Fault Control Enable For n = 4" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
|
|
newline
|
|
bitfld.long 0x00 21. "SYNCEN2,Synchronization Enable For n = 4" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
|
|
bitfld.long 0x00 20. "DTEN2,Deadtime Enable For n = 4" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
|
|
newline
|
|
bitfld.long 0x00 19. "DECAP2,Dual Edge Capture Mode Captures For n = 4" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 18. "DECAPEN2,Dual Edge Capture Mode Enable For n = 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 17. "COMP2,Complement Of Channel (n) For n = 4" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
|
|
bitfld.long 0x00 16. "COMBINE2,Combine Channels For n = 4" "0,1"
|
|
newline
|
|
bitfld.long 0x00 15. "MCOMBINE1,Modified Combine Mode For n = 2" "0,1"
|
|
bitfld.long 0x00 14. "FAULTEN1,Fault Control Enable For n = 2" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
|
|
newline
|
|
bitfld.long 0x00 13. "SYNCEN1,Synchronization Enable For n = 2" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
|
|
bitfld.long 0x00 12. "DTEN1,Deadtime Enable For n = 2" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
|
|
newline
|
|
bitfld.long 0x00 11. "DECAP1,Dual Edge Capture Mode Captures For n = 2" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 10. "DECAPEN1,Dual Edge Capture Mode Enable For n = 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 9. "COMP1,Complement Of Channel (n) For n = 2" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
|
|
bitfld.long 0x00 8. "COMBINE1,Combine Channels For n = 2" "0,1"
|
|
newline
|
|
bitfld.long 0x00 7. "MCOMBINE0,Modified Combine Mode For n = 0" "0,1"
|
|
bitfld.long 0x00 6. "FAULTEN0,Fault Control Enable For n = 0" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
|
|
newline
|
|
bitfld.long 0x00 5. "SYNCEN0,Synchronization Enable For n = 0" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
|
|
bitfld.long 0x00 4. "DTEN0,Deadtime Enable For n = 0" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
|
|
newline
|
|
bitfld.long 0x00 3. "DECAP0,Dual Edge Capture Mode Captures For n = 0" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 2. "DECAPEN0,Dual Edge Capture Mode Enable For n = 0" "0,1"
|
|
newline
|
|
bitfld.long 0x00 1. "COMP0,Complement Of Channel (n) For n = 0" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
|
|
bitfld.long 0x00 0. "COMBINE0,Combine Channels For n = 0" "0,1"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "DEADTIME,Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "EXTTRIG,FTM External Trigger"
|
|
bitfld.long 0x00 9. "CH7TRIG,Channel 7 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
bitfld.long 0x00 8. "CH6TRIG,Channel 6 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
|
|
newline
|
|
rbitfld.long 0x00 7. "TRIGF,Channel Trigger Flag" "0: No channel trigger was generated,1: A channel trigger was generated"
|
|
bitfld.long 0x00 6. "INITTRIGEN,Initialization Trigger Enable" "0: The generation of initialization trigger is..,1: The generation of initialization trigger is.."
|
|
newline
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bitfld.long 0x00 5. "CH1TRIG,Channel 1 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 4. "CH0TRIG,Channel 0 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 3. "CH5TRIG,Channel 5 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 2. "CH4TRIG,Channel 4 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 1. "CH3TRIG,Channel 3 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 0. "CH2TRIG,Channel 2 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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group.long 0x70++0x03
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line.long 0x00 "POL,Channels Polarity"
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bitfld.long 0x00 7. "POL7,Channel 7 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 6. "POL6,Channel 6 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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group.long 0x74++0x03
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line.long 0x00 "FMS,Fault Mode Status"
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rbitfld.long 0x00 7. "FAULTF,Fault Detection Flag" "0: No fault condition was detected,1: A fault condition was detected"
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bitfld.long 0x00 6. "WPEN,Write Protection Enable" "0: Write protection is disabled,1: Write protection is enabled"
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rbitfld.long 0x00 5. "FAULTIN,Fault Inputs" "0: The logic OR of the enabled fault inputs is 0,1: The logic OR of the enabled fault inputs is 1"
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rbitfld.long 0x00 3. "FAULTF3,Fault Detection Flag 3" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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rbitfld.long 0x00 2. "FAULTF2,Fault Detection Flag 2" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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rbitfld.long 0x00 1. "FAULTF1,Fault Detection Flag 1" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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rbitfld.long 0x00 0. "FAULTF0,Fault Detection Flag 0" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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group.long 0x78++0x03
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line.long 0x00 "FILTER,Input Capture Filter Control"
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bitfld.long 0x00 12.--15. "CH3FVAL,Channel 3 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "CH2FVAL,Channel 2 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "CH1FVAL,Channel 1 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "CH0FVAL,Channel 0 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x7C++0x03
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line.long 0x00 "FLTCTRL,Fault Control"
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bitfld.long 0x00 15. "FSTATE,Fault output state" "0: FTM outputs will be placed into safe values..,1: FTM outputs will be tri-stated when fault.."
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bitfld.long 0x00 8.--11. "FFVAL,Fault Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "FFLTR3EN,Fault Input 3 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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bitfld.long 0x00 6. "FFLTR2EN,Fault Input 2 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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bitfld.long 0x00 5. "FFLTR1EN,Fault Input 1 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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bitfld.long 0x00 4. "FFLTR0EN,Fault Input 0 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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bitfld.long 0x00 3. "FAULT3EN,Fault Input 3 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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bitfld.long 0x00 2. "FAULT2EN,Fault Input 2 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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bitfld.long 0x00 1. "FAULT1EN,Fault Input 1 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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bitfld.long 0x00 0. "FAULT0EN,Fault Input 0 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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group.long 0x80++0x03
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line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status"
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bitfld.long 0x00 7. "PHAFLTREN,Phase A Input Filter Enable" "0: Phase A input filter is disabled,1: Phase A input filter is enabled"
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bitfld.long 0x00 6. "PHBFLTREN,Phase B Input Filter Enable" "0: Phase B input filter is disabled,1: Phase B input filter is enabled"
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bitfld.long 0x00 5. "PHAPOL,Phase A Input Polarity" "0: Normal polarity,1: Inverted polarity"
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bitfld.long 0x00 4. "PHBPOL,Phase B Input Polarity" "0: Normal polarity,1: Inverted polarity"
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bitfld.long 0x00 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase A and phase B encoding mode,1: Count and direction encoding mode"
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rbitfld.long 0x00 2. "QUADIR,FTM Counter Direction In Quadrature Decoder Mode" "0: Counting direction is decreasing (FTM counter..,1: Counting direction is increasing (FTM counter.."
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rbitfld.long 0x00 1. "TOFDIR,Timer Overflow Direction In Quadrature Decoder Mode" "0: TOF bit was set on the bottom of counting,1: TOF bit was set on the top of counting"
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bitfld.long 0x00 0. "QUADEN,Quadrature Decoder Mode Enable" "0: Quadrature Decoder mode is disabled,1: Quadrature Decoder mode is enabled"
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group.long 0x84++0x03
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line.long 0x00 "CONF,Configuration"
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bitfld.long 0x00 11. "ITRIGR,Initialization trigger on Reload Point" "0: Initialization trigger is generated on..,1: Initialization trigger is generated when a.."
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bitfld.long 0x00 10. "GTBEOUT,Global Time Base Output" "0,1"
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bitfld.long 0x00 9. "GTBEEN,Global Time Base Enable" "0,1"
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bitfld.long 0x00 6.--7. "BDMMODE,Debug Mode" "0,1,2,3"
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bitfld.long 0x00 0.--4. "LDFQ,Frequency of the Reload Opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
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group.long 0x88++0x03
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line.long 0x00 "FLTPOL,FTM Fault Input Polarity"
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bitfld.long 0x00 3. "FLT3POL,Fault Input 3 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
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bitfld.long 0x00 2. "FLT2POL,Fault Input 2 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
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bitfld.long 0x00 1. "FLT1POL,Fault Input 1 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
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bitfld.long 0x00 0. "FLT0POL,Fault Input 0 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
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group.long 0x8C++0x03
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line.long 0x00 "SYNCONF,Synchronization Configuration"
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bitfld.long 0x00 20. "HWSOC,Software output control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the SWOCTRL.."
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bitfld.long 0x00 19. "HWINVC,Inverting control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the INVCTRL.."
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bitfld.long 0x00 18. "HWOM,Output mask synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the OUTMASK.."
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bitfld.long 0x00 17. "HWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate MOD HCR..,1: A hardware trigger activates MOD HCR CNTIN.."
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bitfld.long 0x00 16. "HWRSTCNT,FTM counter synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the FTM..,1: A hardware trigger activates the FTM counter.."
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bitfld.long 0x00 12. "SWSOC,Software output control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the SWOCTRL.."
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bitfld.long 0x00 11. "SWINVC,Inverting control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the INVCTRL.."
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bitfld.long 0x00 10. "SWOM,Output mask synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the OUTMASK.."
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bitfld.long 0x00 9. "SWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by the software trigger" "0: The software trigger does not activate MOD..,1: The software trigger activates MOD HCR CNTIN.."
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bitfld.long 0x00 8. "SWRSTCNT,FTM counter synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the FTM.."
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bitfld.long 0x00 7. "SYNCMODE,Synchronization Mode" "0: Legacy PWM synchronization is selected,1: Enhanced PWM synchronization is selected"
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bitfld.long 0x00 5. "SWOC,SWOCTRL Register Synchronization" "0: SWOCTRL register is updated with its buffer..,1: SWOCTRL register is updated with its buffer.."
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bitfld.long 0x00 4. "INVC,INVCTRL Register Synchronization" "0: INVCTRL register is updated with its buffer..,1: INVCTRL register is updated with its buffer.."
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bitfld.long 0x00 2. "CNTINC,CNTIN Register Synchronization" "0: CNTIN register is updated with its buffer..,1: CNTIN register is updated with its buffer.."
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bitfld.long 0x00 0. "HWTRIGMODE,Hardware Trigger Mode" "0: FTM clears the TRIGj bit when the hardware..,1: FTM does not clear the TRIGj bit when the.."
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group.long 0x90++0x03
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line.long 0x00 "INVCTRL,FTM Inverting Control"
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bitfld.long 0x00 3. "INV3EN,Pair Channels 3 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
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bitfld.long 0x00 2. "INV2EN,Pair Channels 2 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
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bitfld.long 0x00 1. "INV1EN,Pair Channels 1 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
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bitfld.long 0x00 0. "INV0EN,Pair Channels 0 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
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group.long 0x94++0x03
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line.long 0x00 "SWOCTRL,FTM Software Output Control"
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bitfld.long 0x00 15. "CH7OCV,Channel 7 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 14. "CH6OCV,Channel 6 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 13. "CH5OCV,Channel 5 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 12. "CH4OCV,Channel 4 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 11. "CH3OCV,Channel 3 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 10. "CH2OCV,Channel 2 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 9. "CH1OCV,Channel 1 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 8. "CH0OCV,Channel 0 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
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bitfld.long 0x00 7. "CH7OC,Channel 7 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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bitfld.long 0x00 6. "CH6OC,Channel 6 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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bitfld.long 0x00 5. "CH5OC,Channel 5 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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bitfld.long 0x00 4. "CH4OC,Channel 4 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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bitfld.long 0x00 3. "CH3OC,Channel 3 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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bitfld.long 0x00 2. "CH2OC,Channel 2 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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bitfld.long 0x00 1. "CH1OC,Channel 1 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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bitfld.long 0x00 0. "CH0OC,Channel 0 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
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group.long 0x98++0x03
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line.long 0x00 "PWMLOAD,FTM PWM Load"
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bitfld.long 0x00 11. "GLDOK,Global Load OK" "0: No action,1: LDOK bit is set"
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bitfld.long 0x00 10. "GLEN,Global Load Enable" "0: Global Load Ok disabled,1: Global Load OK enabled"
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bitfld.long 0x00 9. "LDOK,Load Enable" "0: Loading updated values is disabled,1: Loading updated values is enabled"
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bitfld.long 0x00 8. "HCSEL,Half Cycle Select" "0: Half cycle reload is disabled and it is not..,1: Half cycle reload is enabled and it is.."
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bitfld.long 0x00 7. "CH7SEL,Channel 7 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
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bitfld.long 0x00 6. "CH6SEL,Channel 6 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
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bitfld.long 0x00 5. "CH5SEL,Channel 5 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
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bitfld.long 0x00 4. "CH4SEL,Channel 4 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
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bitfld.long 0x00 3. "CH3SEL,Channel 3 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
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bitfld.long 0x00 2. "CH2SEL,Channel 2 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
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bitfld.long 0x00 1. "CH1SEL,Channel 1 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
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bitfld.long 0x00 0. "CH0SEL,Channel 0 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
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group.long 0x9C++0x03
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line.long 0x00 "HCR,Half Cycle Register"
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hexmask.long.word 0x00 0.--15. 1. "HCVAL,Half Cycle Value"
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group.long 0xA0++0x03
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line.long 0x00 "PAIR0DEADTIME,Pair 0 Deadtime Configuration"
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bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
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bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0xA8++0x03
|
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line.long 0x00 "PAIR1DEADTIME,Pair 1 Deadtime Configuration"
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bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
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bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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|
group.long 0xB0++0x03
|
|
line.long 0x00 "PAIR2DEADTIME,Pair 2 Deadtime Configuration"
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|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
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bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PAIR3DEADTIME,Pair 3 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
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|
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bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MOD_MIRROR,Mirror of Modulo Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "MOD,Mirror of the Modulo Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACMOD,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "C0V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "C1V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "C2V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "C3V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "C4V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "C5V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "C6V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "C7V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K148")
|
|
repeat 2. (list 6. 7.) (list ad:0x40070000 ad:0x40071000)
|
|
tree "FTM$1"
|
|
base $2
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC,Status And Control"
|
|
bitfld.long 0x00 24.--27. "FLTPS,Filter Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 3,3: Divide by 4,4: Divide by 5,5: Divide by 6,6: Divide by 7,7: Divide by 8,8: Divide by 9,9: Divide by 10,10: Divide by 11,11: Divide by 12,12: Divide by 13,13: Divide by 14,14: Divide by 15,15: Divide by 16"
|
|
bitfld.long 0x00 23. "PWMEN7,Channel 7 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 22. "PWMEN6,Channel 6 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 21. "PWMEN5,Channel 5 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "PWMEN4,Channel 4 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 19. "PWMEN3,Channel 3 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 18. "PWMEN2,Channel 2 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
bitfld.long 0x00 17. "PWMEN1,Channel 1 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "PWMEN0,Channel 0 PWM enable bit" "0: Channel output port is disabled,1: Channel output port is enabled"
|
|
rbitfld.long 0x00 9. "TOF,Timer Overflow Flag" "0: FTM counter has not overflowed,1: FTM counter has overflowed"
|
|
newline
|
|
bitfld.long 0x00 8. "TOIE,Timer Overflow Interrupt Enable" "0: Disable TOF interrupts,1: Enable TOF interrupts"
|
|
rbitfld.long 0x00 7. "RF,Reload Flag" "0: A selected reload point did not happen,1: A selected reload point happened"
|
|
newline
|
|
bitfld.long 0x00 6. "RIE,Reload Point Interrupt Enable" "0: Reload point interrupt is disabled,1: Reload point interrupt is enabled"
|
|
bitfld.long 0x00 5. "CPWMS,Center-Aligned PWM Select" "0: FTM counter operates in Up Counting mode,1: FTM counter operates in Up-Down Counting mode"
|
|
newline
|
|
bitfld.long 0x00 3.--4. "CLKS,Clock Source Selection" "0: No clock selected,1: FTM input clock,2: Fixed frequency clock,3: External clock"
|
|
bitfld.long 0x00 0.--2. "PS,Prescale Factor Selection" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CNT,Counter"
|
|
hexmask.long.word 0x00 0.--15. 1. "COUNT,Counter Value"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "MOD,Modulo"
|
|
hexmask.long.word 0x00 0.--15. 1. "MOD,MOD"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "C0SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "C0V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "C1SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "C1V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "C2SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "C2V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "C3SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "C3V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "C4SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "C4V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "C5SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "C5V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "C6SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "C6V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "C7SC,Channel (n) Status And Control"
|
|
rbitfld.long 0x00 10. "CHOV,Channel (n) Output Value" "0: The channel (n) output is zero,1: The channel (n) output is one"
|
|
rbitfld.long 0x00 9. "CHIS,Channel (n) Input State" "0: The channel (n) input is zero,1: The channel (n) input is one"
|
|
newline
|
|
bitfld.long 0x00 8. "TRIGMODE,Trigger mode control" "0: Channel outputs will generate the normal PWM..,1: If a match in the channel occurs a trigger.."
|
|
rbitfld.long 0x00 7. "CHF,Channel (n) Flag" "0: No channel (n) event has occurred,1: A channel (n) event has occurred"
|
|
newline
|
|
bitfld.long 0x00 6. "CHIE,Channel (n) Interrupt Enable" "0: Disable channel (n) interrupt,1: Enable channel (n) interrupt"
|
|
bitfld.long 0x00 5. "MSB,Channel (n) Mode Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "MSA,Channel (n) Mode Select" "0,1"
|
|
bitfld.long 0x00 3. "ELSB,Channel (n) Edge or Level Select" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "ELSA,Channel (n) Edge or Level Select" "0,1"
|
|
bitfld.long 0x00 1. "ICRST,FTM counter reset by the selected input capture event" "0: FTM counter is not reset when the selected..,1: FTM counter is reset when the selected.."
|
|
newline
|
|
bitfld.long 0x00 0. "DMA,DMA Enable" "0: Disable DMA transfers,1: Enable DMA transfers"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "C7V,Channel (n) Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "VAL,Channel Value"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CNTIN,Counter Initial Value"
|
|
hexmask.long.word 0x00 0.--15. 1. "INIT,INIT"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "STATUS,Capture And Compare Status"
|
|
bitfld.long 0x00 7. "CH7F,Channel 7 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 6. "CH6F,Channel 6 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 5. "CH5F,Channel 5 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 4. "CH4F,Channel 4 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 3. "CH3F,Channel 3 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 2. "CH2F,Channel 2 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
newline
|
|
bitfld.long 0x00 1. "CH1F,Channel 1 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
bitfld.long 0x00 0. "CH0F,Channel 0 Flag" "0: No channel event has occurred,1: A channel event has occurred"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "MODE,Features Mode Selection"
|
|
bitfld.long 0x00 7. "FAULTIE,Fault Interrupt Enable" "0: Fault control interrupt is disabled,1: Fault control interrupt is enabled"
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|
bitfld.long 0x00 5.--6. "FAULTM,Fault Control Mode" "0: Fault control is disabled for all channels,1: Fault control is enabled for even channels..,2: Fault control is enabled for all channels and..,3: Fault control is enabled for all channels and.."
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bitfld.long 0x00 4. "CAPTEST,Capture Test Mode Enable" "0: Capture test mode is disabled,1: Capture test mode is enabled"
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bitfld.long 0x00 3. "PWMSYNC,PWM Synchronization Mode" "0: No restrictions,1: Software trigger can only be used by MOD and.."
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|
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bitfld.long 0x00 2. "WPDIS,Write Protection Disable" "0: Write protection is enabled,1: Write protection is disabled"
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|
bitfld.long 0x00 1. "INIT,Initialize The Channels Output" "0,1"
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|
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bitfld.long 0x00 0. "FTMEN,FTM Enable" "0: TPM compatibility,1: Free running counter and synchronization are.."
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group.long 0x58++0x03
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line.long 0x00 "SYNC,Synchronization"
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|
bitfld.long 0x00 7. "SWSYNC,PWM Synchronization Software Trigger" "0: Software trigger is not selected,1: Software trigger is selected"
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|
bitfld.long 0x00 6. "TRIG2,PWM Synchronization Hardware Trigger 2" "0: Trigger is disabled,1: Trigger is enabled"
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bitfld.long 0x00 5. "TRIG1,PWM Synchronization Hardware Trigger 1" "0: Trigger is disabled,1: Trigger is enabled"
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|
bitfld.long 0x00 4. "TRIG0,PWM Synchronization Hardware Trigger 0" "0: Trigger is disabled,1: Trigger is enabled"
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bitfld.long 0x00 3. "SYNCHOM,Output Mask Synchronization" "0: OUTMASK register is updated with the value of..,1: OUTMASK register is updated with the value of.."
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|
bitfld.long 0x00 2. "REINIT,FTM Counter Reinitialization by Synchronization" "0: FTM counter continues to count normally,1: FTM counter is updated with its initial value.."
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bitfld.long 0x00 1. "CNTMAX,Maximum Loading Point Enable" "0: The maximum loading point is disabled,1: The maximum loading point is enabled"
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|
bitfld.long 0x00 0. "CNTMIN,Minimum Loading Point Enable" "0: The minimum loading point is disabled,1: The minimum loading point is enabled"
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group.long 0x5C++0x03
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line.long 0x00 "OUTINIT,Initial State For Channels Output"
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|
bitfld.long 0x00 7. "CH7OI,Channel 7 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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|
bitfld.long 0x00 6. "CH6OI,Channel 6 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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|
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bitfld.long 0x00 5. "CH5OI,Channel 5 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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bitfld.long 0x00 4. "CH4OI,Channel 4 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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|
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bitfld.long 0x00 3. "CH3OI,Channel 3 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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bitfld.long 0x00 2. "CH2OI,Channel 2 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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bitfld.long 0x00 1. "CH1OI,Channel 1 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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bitfld.long 0x00 0. "CH0OI,Channel 0 Output Initialization Value" "0: The initialization value is 0,1: The initialization value is 1"
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group.long 0x60++0x03
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line.long 0x00 "OUTMASK,Output Mask"
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|
bitfld.long 0x00 7. "CH7OM,Channel 7 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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|
bitfld.long 0x00 6. "CH6OM,Channel 6 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 5. "CH5OM,Channel 5 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 4. "CH4OM,Channel 4 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 3. "CH3OM,Channel 3 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 2. "CH2OM,Channel 2 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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bitfld.long 0x00 1. "CH1OM,Channel 1 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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|
bitfld.long 0x00 0. "CH0OM,Channel 0 Output Mask" "0: Channel output is not masked,1: Channel output is masked"
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|
group.long 0x64++0x03
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line.long 0x00 "COMBINE,Function For Linked Channels"
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|
bitfld.long 0x00 31. "MCOMBINE3,Modified Combine Mode For n = 6" "0,1"
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bitfld.long 0x00 30. "FAULTEN3,Fault Control Enable For n = 6" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
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bitfld.long 0x00 29. "SYNCEN3,Synchronization Enable For n = 6" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
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bitfld.long 0x00 28. "DTEN3,Deadtime Enable For n = 6" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
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bitfld.long 0x00 27. "DECAP3,Dual Edge Capture Mode Captures For n = 6" "0: The dual edge captures are inactive,1: The dual edge captures are active"
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|
bitfld.long 0x00 26. "DECAPEN3,Dual Edge Capture Mode Enable For n = 6" "0,1"
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bitfld.long 0x00 25. "COMP3,Complement Of Channel (n) for n = 6" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
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bitfld.long 0x00 24. "COMBINE3,Combine Channels For n = 6" "0,1"
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|
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bitfld.long 0x00 23. "MCOMBINE2,Modified Combine Mode For n = 4" "0,1"
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bitfld.long 0x00 22. "FAULTEN2,Fault Control Enable For n = 4" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
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bitfld.long 0x00 21. "SYNCEN2,Synchronization Enable For n = 4" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
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bitfld.long 0x00 20. "DTEN2,Deadtime Enable For n = 4" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
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bitfld.long 0x00 19. "DECAP2,Dual Edge Capture Mode Captures For n = 4" "0: The dual edge captures are inactive,1: The dual edge captures are active"
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|
bitfld.long 0x00 18. "DECAPEN2,Dual Edge Capture Mode Enable For n = 4" "0,1"
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|
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bitfld.long 0x00 17. "COMP2,Complement Of Channel (n) For n = 4" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
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bitfld.long 0x00 16. "COMBINE2,Combine Channels For n = 4" "0,1"
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bitfld.long 0x00 15. "MCOMBINE1,Modified Combine Mode For n = 2" "0,1"
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|
bitfld.long 0x00 14. "FAULTEN1,Fault Control Enable For n = 2" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
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bitfld.long 0x00 13. "SYNCEN1,Synchronization Enable For n = 2" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
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|
bitfld.long 0x00 12. "DTEN1,Deadtime Enable For n = 2" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
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|
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|
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bitfld.long 0x00 11. "DECAP1,Dual Edge Capture Mode Captures For n = 2" "0: The dual edge captures are inactive,1: The dual edge captures are active"
|
|
bitfld.long 0x00 10. "DECAPEN1,Dual Edge Capture Mode Enable For n = 2" "0,1"
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|
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|
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bitfld.long 0x00 9. "COMP1,Complement Of Channel (n) For n = 2" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
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bitfld.long 0x00 8. "COMBINE1,Combine Channels For n = 2" "0,1"
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bitfld.long 0x00 7. "MCOMBINE0,Modified Combine Mode For n = 0" "0,1"
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bitfld.long 0x00 6. "FAULTEN0,Fault Control Enable For n = 0" "0: The fault control in this pair of channels is..,1: The fault control in this pair of channels is.."
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bitfld.long 0x00 5. "SYNCEN0,Synchronization Enable For n = 0" "0: The PWM synchronization in this pair of..,1: The PWM synchronization in this pair of.."
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bitfld.long 0x00 4. "DTEN0,Deadtime Enable For n = 0" "0: The deadtime insertion in this pair of..,1: The deadtime insertion in this pair of.."
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|
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bitfld.long 0x00 3. "DECAP0,Dual Edge Capture Mode Captures For n = 0" "0: The dual edge captures are inactive,1: The dual edge captures are active"
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|
bitfld.long 0x00 2. "DECAPEN0,Dual Edge Capture Mode Enable For n = 0" "0,1"
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bitfld.long 0x00 1. "COMP0,Complement Of Channel (n) For n = 0" "0: The channel (n+1) output is the same as the..,1: The channel (n+1) output is the complement of.."
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bitfld.long 0x00 0. "COMBINE0,Combine Channels For n = 0" "0,1"
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group.long 0x68++0x03
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line.long 0x00 "DEADTIME,Deadtime Configuration"
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bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
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bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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group.long 0x6C++0x03
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line.long 0x00 "EXTTRIG,FTM External Trigger"
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bitfld.long 0x00 9. "CH7TRIG,Channel 7 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 8. "CH6TRIG,Channel 6 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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rbitfld.long 0x00 7. "TRIGF,Channel Trigger Flag" "0: No channel trigger was generated,1: A channel trigger was generated"
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bitfld.long 0x00 6. "INITTRIGEN,Initialization Trigger Enable" "0: The generation of initialization trigger is..,1: The generation of initialization trigger is.."
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bitfld.long 0x00 5. "CH1TRIG,Channel 1 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 4. "CH0TRIG,Channel 0 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 3. "CH5TRIG,Channel 5 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 2. "CH4TRIG,Channel 4 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 1. "CH3TRIG,Channel 3 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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bitfld.long 0x00 0. "CH2TRIG,Channel 2 External Trigger Enable" "0: The generation of this external trigger is..,1: The generation of this external trigger is.."
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group.long 0x70++0x03
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line.long 0x00 "POL,Channels Polarity"
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bitfld.long 0x00 7. "POL7,Channel 7 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 6. "POL6,Channel 6 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 5. "POL5,Channel 5 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 4. "POL4,Channel 4 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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|
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bitfld.long 0x00 3. "POL3,Channel 3 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 2. "POL2,Channel 2 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 1. "POL1,Channel 1 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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bitfld.long 0x00 0. "POL0,Channel 0 Polarity" "0: The channel polarity is active high,1: The channel polarity is active low"
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group.long 0x74++0x03
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line.long 0x00 "FMS,Fault Mode Status"
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rbitfld.long 0x00 7. "FAULTF,Fault Detection Flag" "0: No fault condition was detected,1: A fault condition was detected"
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bitfld.long 0x00 6. "WPEN,Write Protection Enable" "0: Write protection is disabled,1: Write protection is enabled"
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|
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|
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rbitfld.long 0x00 5. "FAULTIN,Fault Inputs" "0: The logic OR of the enabled fault inputs is 0,1: The logic OR of the enabled fault inputs is 1"
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|
rbitfld.long 0x00 3. "FAULTF3,Fault Detection Flag 3" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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|
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rbitfld.long 0x00 2. "FAULTF2,Fault Detection Flag 2" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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rbitfld.long 0x00 1. "FAULTF1,Fault Detection Flag 1" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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rbitfld.long 0x00 0. "FAULTF0,Fault Detection Flag 0" "0: No fault condition was detected at the fault..,1: A fault condition was detected at the fault.."
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group.long 0x78++0x03
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line.long 0x00 "FILTER,Input Capture Filter Control"
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|
bitfld.long 0x00 12.--15. "CH3FVAL,Channel 3 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 8.--11. "CH2FVAL,Channel 2 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 4.--7. "CH1FVAL,Channel 1 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 0.--3. "CH0FVAL,Channel 0 Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x7C++0x03
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line.long 0x00 "FLTCTRL,Fault Control"
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|
bitfld.long 0x00 15. "FSTATE,Fault output state" "0: FTM outputs will be placed into safe values..,1: FTM outputs will be tri-stated when fault.."
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bitfld.long 0x00 8.--11. "FFVAL,Fault Input Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x00 7. "FFLTR3EN,Fault Input 3 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
|
|
bitfld.long 0x00 6. "FFLTR2EN,Fault Input 2 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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bitfld.long 0x00 5. "FFLTR1EN,Fault Input 1 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
|
|
bitfld.long 0x00 4. "FFLTR0EN,Fault Input 0 Filter Enable" "0: Fault input filter is disabled,1: Fault input filter is enabled"
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|
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bitfld.long 0x00 3. "FAULT3EN,Fault Input 3 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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|
bitfld.long 0x00 2. "FAULT2EN,Fault Input 2 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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bitfld.long 0x00 1. "FAULT1EN,Fault Input 1 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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|
bitfld.long 0x00 0. "FAULT0EN,Fault Input 0 Enable" "0: Fault input is disabled,1: Fault input is enabled"
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group.long 0x80++0x03
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line.long 0x00 "QDCTRL,Quadrature Decoder Control And Status"
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bitfld.long 0x00 7. "PHAFLTREN,Phase A Input Filter Enable" "0: Phase A input filter is disabled,1: Phase A input filter is enabled"
|
|
bitfld.long 0x00 6. "PHBFLTREN,Phase B Input Filter Enable" "0: Phase B input filter is disabled,1: Phase B input filter is enabled"
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|
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bitfld.long 0x00 5. "PHAPOL,Phase A Input Polarity" "0: Normal polarity,1: Inverted polarity"
|
|
bitfld.long 0x00 4. "PHBPOL,Phase B Input Polarity" "0: Normal polarity,1: Inverted polarity"
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|
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|
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bitfld.long 0x00 3. "QUADMODE,Quadrature Decoder Mode" "0: Phase A and phase B encoding mode,1: Count and direction encoding mode"
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|
rbitfld.long 0x00 2. "QUADIR,FTM Counter Direction In Quadrature Decoder Mode" "0: Counting direction is decreasing (FTM counter..,1: Counting direction is increasing (FTM counter.."
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rbitfld.long 0x00 1. "TOFDIR,Timer Overflow Direction In Quadrature Decoder Mode" "0: TOF bit was set on the bottom of counting,1: TOF bit was set on the top of counting"
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|
bitfld.long 0x00 0. "QUADEN,Quadrature Decoder Mode Enable" "0: Quadrature Decoder mode is disabled,1: Quadrature Decoder mode is enabled"
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|
group.long 0x84++0x03
|
|
line.long 0x00 "CONF,Configuration"
|
|
bitfld.long 0x00 11. "ITRIGR,Initialization trigger on Reload Point" "0: Initialization trigger is generated on..,1: Initialization trigger is generated when a.."
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|
bitfld.long 0x00 10. "GTBEOUT,Global Time Base Output" "0,1"
|
|
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|
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bitfld.long 0x00 9. "GTBEEN,Global Time Base Enable" "0,1"
|
|
bitfld.long 0x00 6.--7. "BDMMODE,Debug Mode" "0,1,2,3"
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|
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|
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bitfld.long 0x00 0.--4. "LDFQ,Frequency of the Reload Opportunities" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "FLTPOL,FTM Fault Input Polarity"
|
|
bitfld.long 0x00 3. "FLT3POL,Fault Input 3 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
|
|
bitfld.long 0x00 2. "FLT2POL,Fault Input 2 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
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|
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|
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bitfld.long 0x00 1. "FLT1POL,Fault Input 1 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
|
|
bitfld.long 0x00 0. "FLT0POL,Fault Input 0 Polarity" "0: The fault input polarity is active high,1: The fault input polarity is active low"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SYNCONF,Synchronization Configuration"
|
|
bitfld.long 0x00 20. "HWSOC,Software output control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the SWOCTRL.."
|
|
bitfld.long 0x00 19. "HWINVC,Inverting control synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the INVCTRL.."
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|
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bitfld.long 0x00 18. "HWOM,Output mask synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the..,1: A hardware trigger activates the OUTMASK.."
|
|
bitfld.long 0x00 17. "HWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate MOD HCR..,1: A hardware trigger activates MOD HCR CNTIN.."
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|
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bitfld.long 0x00 16. "HWRSTCNT,FTM counter synchronization is activated by a hardware trigger" "0: A hardware trigger does not activate the FTM..,1: A hardware trigger activates the FTM counter.."
|
|
bitfld.long 0x00 12. "SWSOC,Software output control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the SWOCTRL.."
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|
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bitfld.long 0x00 11. "SWINVC,Inverting control synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the INVCTRL.."
|
|
bitfld.long 0x00 10. "SWOM,Output mask synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the OUTMASK.."
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|
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bitfld.long 0x00 9. "SWWRBUF,MOD HCR CNTIN and CV registers synchronization is activated by the software trigger" "0: The software trigger does not activate MOD..,1: The software trigger activates MOD HCR CNTIN.."
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|
bitfld.long 0x00 8. "SWRSTCNT,FTM counter synchronization is activated by the software trigger" "0: The software trigger does not activate the..,1: The software trigger activates the FTM.."
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|
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|
|
bitfld.long 0x00 7. "SYNCMODE,Synchronization Mode" "0: Legacy PWM synchronization is selected,1: Enhanced PWM synchronization is selected"
|
|
bitfld.long 0x00 5. "SWOC,SWOCTRL Register Synchronization" "0: SWOCTRL register is updated with its buffer..,1: SWOCTRL register is updated with its buffer.."
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|
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|
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bitfld.long 0x00 4. "INVC,INVCTRL Register Synchronization" "0: INVCTRL register is updated with its buffer..,1: INVCTRL register is updated with its buffer.."
|
|
bitfld.long 0x00 2. "CNTINC,CNTIN Register Synchronization" "0: CNTIN register is updated with its buffer..,1: CNTIN register is updated with its buffer.."
|
|
newline
|
|
bitfld.long 0x00 0. "HWTRIGMODE,Hardware Trigger Mode" "0: FTM clears the TRIGj bit when the hardware..,1: FTM does not clear the TRIGj bit when the.."
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "INVCTRL,FTM Inverting Control"
|
|
bitfld.long 0x00 3. "INV3EN,Pair Channels 3 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
bitfld.long 0x00 2. "INV2EN,Pair Channels 2 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "INV1EN,Pair Channels 1 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
bitfld.long 0x00 0. "INV0EN,Pair Channels 0 Inverting Enable" "0: Inverting is disabled,1: Inverting is enabled"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "SWOCTRL,FTM Software Output Control"
|
|
bitfld.long 0x00 15. "CH7OCV,Channel 7 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
bitfld.long 0x00 14. "CH6OCV,Channel 6 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
newline
|
|
bitfld.long 0x00 13. "CH5OCV,Channel 5 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
bitfld.long 0x00 12. "CH4OCV,Channel 4 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
newline
|
|
bitfld.long 0x00 11. "CH3OCV,Channel 3 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
bitfld.long 0x00 10. "CH2OCV,Channel 2 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
newline
|
|
bitfld.long 0x00 9. "CH1OCV,Channel 1 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
bitfld.long 0x00 8. "CH0OCV,Channel 0 Software Output Control Value" "0: The software output control forces 0 to the..,1: The software output control forces 1 to the.."
|
|
newline
|
|
bitfld.long 0x00 7. "CH7OC,Channel 7 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 6. "CH6OC,Channel 6 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
newline
|
|
bitfld.long 0x00 5. "CH5OC,Channel 5 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 4. "CH4OC,Channel 4 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
newline
|
|
bitfld.long 0x00 3. "CH3OC,Channel 3 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 2. "CH2OC,Channel 2 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
newline
|
|
bitfld.long 0x00 1. "CH1OC,Channel 1 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
bitfld.long 0x00 0. "CH0OC,Channel 0 Software Output Control Enable" "0: The channel output is not affected by..,1: The channel output is affected by software.."
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "PWMLOAD,FTM PWM Load"
|
|
bitfld.long 0x00 11. "GLDOK,Global Load OK" "0: No action,1: LDOK bit is set"
|
|
bitfld.long 0x00 10. "GLEN,Global Load Enable" "0: Global Load Ok disabled,1: Global Load OK enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "LDOK,Load Enable" "0: Loading updated values is disabled,1: Loading updated values is enabled"
|
|
bitfld.long 0x00 8. "HCSEL,Half Cycle Select" "0: Half cycle reload is disabled and it is not..,1: Half cycle reload is enabled and it is.."
|
|
newline
|
|
bitfld.long 0x00 7. "CH7SEL,Channel 7 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 6. "CH6SEL,Channel 6 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
newline
|
|
bitfld.long 0x00 5. "CH5SEL,Channel 5 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 4. "CH4SEL,Channel 4 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
newline
|
|
bitfld.long 0x00 3. "CH3SEL,Channel 3 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 2. "CH2SEL,Channel 2 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
newline
|
|
bitfld.long 0x00 1. "CH1SEL,Channel 1 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
bitfld.long 0x00 0. "CH0SEL,Channel 0 Select" "0: Channel match is not included as a reload..,1: Channel match is included as a reload.."
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "HCR,Half Cycle Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "HCVAL,Half Cycle Value"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "PAIR0DEADTIME,Pair 0 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "PAIR1DEADTIME,Pair 1 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "PAIR2DEADTIME,Pair 2 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "PAIR3DEADTIME,Pair 3 Deadtime Configuration"
|
|
bitfld.long 0x00 16.--19. "DTVALEX,Extended Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 6.--7. "DTPS,Deadtime Prescaler Value" "0: Divide the FTM input clock by 1,1: Divide the FTM input clock by 1,2: Divide the FTM input clock by 4,3: Divide the FTM input clock by 16"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "DTVAL,Deadtime Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MOD_MIRROR,Mirror of Modulo Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "MOD,Mirror of the Modulo Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACMOD,Modulo Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "C0V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "C1V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "C2V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "C3V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "C4V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "C5V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "C6V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "C7V_MIRROR,Mirror of Channel (n) Match Value"
|
|
hexmask.long.word 0x00 16.--31. 1. "VAL,Mirror of the Channel (n) Match Integer Value"
|
|
bitfld.long 0x00 11.--15. "FRACVAL,Channel (n) Match Fractional Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
endif
|
|
tree.end
|
|
sif cpuis("S32K148")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")
|
|
tree "ADC (Analog-to-Digital Converter)"
|
|
repeat 2. (list 0. 1.) (list ad:0x4003B000 ad:0x40027000)
|
|
tree "ADC$1"
|
|
base $2
|
|
sif cpuis("S32K148")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC1A,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC1A,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC1A,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SC1B,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SC1B,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SC1B,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SC1C,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SC1C,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SC1C,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SC1D,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SC1D,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SC1D,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC1E,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC1E,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC1E,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC1F,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC1F,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC1F,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC1G,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC1G,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC1G,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC1H,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC1H,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC1H,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SC1I,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SC1I,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SC1I,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SC1J,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SC1J,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SC1J,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SC1K,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SC1K,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SC1K,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SC1L,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SC1L,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SC1L,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SC1M,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SC1M,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SC1M,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SC1N,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SC1N,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SC1N,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SC1O,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SC1O,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SC1O,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SC1P,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SC1P,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SC1P,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CFG1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 8. "CLRLTRG,Clear Latch Trigger in Trigger Handler Block" "0,1"
|
|
bitfld.long 0x00 5.--6. "ADIV,Clock Divide Select" "0: The divide ratio is 1 and the clock rate is..,1: The divide ratio is 2 and the clock rate is..,2: The divide ratio is 4 and the clock rate is..,3: The divide ratio is 8 and the clock rate is.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "MODE,Conversion mode selection" "0: 8-bit conversion,1: 12-bit conversion,2: 10-bit conversion,?..."
|
|
bitfld.long 0x00 0.--1. "ADICLK,Input Clock Select" "0: Alternate clock 1 (ADC_ALTCLK1),1: Alternate clock 2 (ADC_ALTCLK2),2: Alternate clock 3 (ADC_ALTCLK3),3: Alternate clock 4 (ADC_ALTCLK4)"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CFG2,ADC Configuration Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SMPLTS,Sample Time Select"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "RA,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "RB,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "RC,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "RD,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "RE,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "RF,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "RG,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "RH,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "RI,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "RJ,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RK,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RL,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "RM,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "RN,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "RO,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "RP,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x88)++0x03
|
|
line.long 0x00 "CV$1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. "CV,Compare Value"
|
|
repeat.end
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "SC2,Status and Control Register 2"
|
|
rbitfld.long 0x00 24.--27. "TRGSTERR,Error in Multiplexed Trigger Request" "0: No error has occurred,1: An error has occurred,?..."
|
|
rbitfld.long 0x00 16.--19. "TRGSTLAT,Trigger Status" "0: No trigger request has been latched,1: A trigger request has been latched,?..."
|
|
newline
|
|
rbitfld.long 0x00 13.--14. "TRGPRNUM,Trigger Process Number" "0,1,2,3"
|
|
rbitfld.long 0x00 7. "ADACT,Conversion Active" "0: Conversion not in progress,1: Conversion in progress"
|
|
newline
|
|
bitfld.long 0x00 6. "ADTRG,Conversion Trigger Select" "0: Software trigger selected,1: Hardware trigger selected"
|
|
bitfld.long 0x00 5. "ACFE,Compare Function Enable" "0: Compare function disabled,1: Compare function enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "ACFGT,Compare Function Greater Than Enable" "0,1"
|
|
bitfld.long 0x00 3. "ACREN,Compare Function Range Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DMAEN,DMA Enable" "0: DMA is disabled,1: DMA is enabled and will assert the ADC DMA.."
|
|
bitfld.long 0x00 0.--1. "REFSEL,Voltage Reference Selection" "0: Default voltage reference pin pair that is..,1: Alternate reference voltage that is VALTH,?..."
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "SC3,Status and Control Register 3"
|
|
bitfld.long 0x00 7. "CAL,Calibration" "0,1"
|
|
bitfld.long 0x00 3. "ADCO,Continuous Conversion Enable" "0: One conversion will be performed (or one set..,1: Continuous conversions will be performed (or.."
|
|
newline
|
|
bitfld.long 0x00 2. "AVGE,Hardware Average Enable" "0: Hardware average function disabled,1: Hardware average function enabled"
|
|
bitfld.long 0x00 0.--1. "AVGS,Hardware Average Select" "0: 4 samples averaged,1: 8 samples averaged,2: 16 samples averaged,3: 32 samples averaged"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "BASE_OFS,BASE Offset Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BA_OFS,Base Offset Error Correction Value"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "OFS,ADC Offset Correction Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "OFS,Offset Error Correction Value"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "USR_OFS,USER Offset Correction Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "USR_OFS,USER Offset Error Correction Value"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "XOFS,ADC X Offset Correction Register"
|
|
bitfld.long 0x00 0.--5. "XOFS,X offset error correction value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "YOFS,ADC Y Offset Correction Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "YOFS,Y offset error correction value"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "G,ADC Gain Register"
|
|
hexmask.long.word 0x00 0.--10. 1. "G,Gain error adjustment factor for the overall conversion"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "UG,ADC User Gain Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "UG,User gain error correction value"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CLPS,ADC General Calibration Value Register S"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CLPS,Calibration Value"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CLP3,ADC Plus-Side General Calibration Value Register 3"
|
|
hexmask.long.word 0x00 0.--9. 1. "CLP3,Calibration Value"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CLP2,ADC Plus-Side General Calibration Value Register 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "CLP2,Calibration Value"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CLP1,ADC Plus-Side General Calibration Value Register 1"
|
|
hexmask.long.word 0x00 0.--8. 1. "CLP1,Calibration Value"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CLP0,ADC Plus-Side General Calibration Value Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLP0,Calibration Value"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CLPX,ADC Plus-Side General Calibration Value Register X"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CLPX,Calibration Value"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CLP9,ADC Plus-Side General Calibration Value Register 9"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CLP9,Calibration Value"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CLPS_OFS,ADC General Calibration Offset Value Register S"
|
|
bitfld.long 0x00 0.--3. "CLPS_OFS,CLPS Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CLP3_OFS,ADC Plus-Side General Calibration Offset Value Register 3"
|
|
bitfld.long 0x00 0.--3. "CLP3_OFS,CLP3 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CLP2_OFS,ADC Plus-Side General Calibration Offset Value Register 2"
|
|
bitfld.long 0x00 0.--3. "CLP2_OFS,CLP2 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CLP1_OFS,ADC Plus-Side General Calibration Offset Value Register 1"
|
|
bitfld.long 0x00 0.--3. "CLP1_OFS,CLP1 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CLP0_OFS,ADC Plus-Side General Calibration Offset Value Register 0"
|
|
bitfld.long 0x00 0.--3. "CLP0_OFS,CLP0 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CLPX_OFS,ADC Plus-Side General Calibration Offset Value Register X"
|
|
hexmask.long.word 0x00 0.--11. 1. "CLPX_OFS,CLPX Offset"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CLP9_OFS,ADC Plus-Side General Calibration Offset Value Register 9"
|
|
hexmask.long.word 0x00 0.--11. 1. "CLP9_OFS,CLP9 Offset"
|
|
sif cpuis("S32K148")
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "aSC1A,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "aSC1A,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "aSC1B,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "aSC1B,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "aSC1C,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "aSC1C,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "aSC1D,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "aSC1D,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "aSC1E,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "aSC1E,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "aSC1F,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "aSC1F,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "aSC1G,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "aSC1G,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "aSC1H,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "aSC1H,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "aSC1I,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "aSC1I,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "aSC1J,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "aSC1J,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "aSC1K,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "aSC1K,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "aSC1L,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "aSC1L,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "aSC1M,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "aSC1M,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "aSC1N,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "aSC1N,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "aSC1O,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "aSC1O,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "aSC1P,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "aSC1P,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "SC1Q,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "SC1Q,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "SC1R,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "SC1R,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "SC1S,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "SC1S,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "SC1T,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "SC1T,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "SC1U,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "SC1U,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "SC1V,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "SC1V,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "SC1W,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "SC1W,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "SC1X,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "SC1X,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "SC1Y,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "SC1Z,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "SC1AA,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "SC1AB,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "SC1AC,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "SC1AD,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SC1AE,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SC1AF,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "aRA,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "aRB,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "aRC,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "aRD,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "aRE,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "aRF,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "aRG,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "aRH,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "aRI,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1AC++0x03
|
|
line.long 0x00 "aRJ,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "aRK,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "aRL,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "aRM,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "aRN,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "aRO,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "aRP,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1C8++0x03
|
|
line.long 0x00 "RQ,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "RR,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1D0++0x03
|
|
line.long 0x00 "RS,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1D4++0x03
|
|
line.long 0x00 "RT,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1D8++0x03
|
|
line.long 0x00 "RU,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1DC++0x03
|
|
line.long 0x00 "RV,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "RW,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1E4++0x03
|
|
line.long 0x00 "RX,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "RY,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "RZ,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1F0++0x03
|
|
line.long 0x00 "RAA,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1F4++0x03
|
|
line.long 0x00 "RAB,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1F8++0x03
|
|
line.long 0x00 "RAC,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1FC++0x03
|
|
line.long 0x00 "RAD,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x200++0x03
|
|
line.long 0x00 "RAE,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "RAF,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
endif
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
sif cpuis("S32K148")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")
|
|
tree "LPSPI (The LPSPI Memory Map/Register Definition can be found here.)"
|
|
repeat 2. (list 0. 1.) (list ad:0x4002C000 ad:0x4002D000)
|
|
tree "LPSPI$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Module Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Module is disabled in debug mode,1: Module is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Module is enabled in Doze mode,1: Module is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Module Enable" "0: Module is disabled,1: Module is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy"
|
|
bitfld.long 0x00 13. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
newline
|
|
bitfld.long 0x00 12. "REF,Receive Error Flag" "0: Receive FIFO has not overflowed,1: Receive FIFO has overflowed"
|
|
bitfld.long 0x00 11. "TEF,Transmit Error Flag" "0: Transmit FIFO underrun has not occurred,1: Transmit FIFO underrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 10. "TCF,Transfer Complete Flag" "0: All transfers have not completed,1: All transfers have completed"
|
|
bitfld.long 0x00 9. "FCF,Frame Complete Flag" "0: Frame transfer has not completed,1: Frame transfer has completed"
|
|
newline
|
|
bitfld.long 0x00 8. "WCF,Word Complete Flag" "0: Transfer word not completed,1: Transfer word completed"
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "REIE,Receive Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TEIE,Transmit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "TCIE,Transfer Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FCIE,Frame Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "WCIE,Word Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DER,DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the DMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPSPI_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request is disabled,1: Host request is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are enabled,1: PCS[3:2] are disabled"
|
|
bitfld.long 0x00 26. "OUTCFG,Output Config" "0: Output data retains last value when chip..,1: Output data is tristated when chip select is.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data and SOUT for..,1: SIN is used for both input and output data,2: SOUT is used for both input and output data,3: SOUT is used for input data and SIN for.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: 010b - Match is enabled if 1st data word..,3: 011b - Match is enabled if any data word..,4: 100b - Match is enabled if 1st data word..,5: 101b - Match is enabled if any data word..,6: 110b - Match is enabled if (1st data word AND..,7: 111b - Match is enabled if (any data word AND.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PCSPOL,Peripheral Chip Select Polarity" "0: The PCSx is active low,1: The PCSx is active high,?..."
|
|
bitfld.long 0x00 3. "NOSTALL,No Stall" "0: Transfers will stall when transmit FIFO is..,1: Transfers will not stall allowing transmit.."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTOPCS,Automatic PCS" "0: Automatic PCS generation disabled,1: Automatic PCS generation enabled"
|
|
bitfld.long 0x00 1. "SAMPLE,Sample Point" "0: Input data sampled on SCK edge,1: Input data sampled on delayed SCK edge"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH0,Match 0 Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMR1,Data Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH1,Match 1 Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCKPCS,SCK to PCS Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSSCK,PCS to SCK Delay"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DBT,Delay Between Transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCKDIV,SCK Divider"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
|
|
bitfld.long 0x00 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
|
|
newline
|
|
bitfld.long 0x00 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
bitfld.long 0x00 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using LPSPI_PCS[0],1: Transfer using LPSPI_PCS[1],2: Transfer using LPSPI_PCS[2],3: Transfer using LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
|
|
bitfld.long 0x00 22. "BYSW,Byte Swap" "0: Byte swap disabled,1: Byte swap enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CONT,Continuous Transfer" "0: Continuous transfer disabled,1: Continuous transfer enabled"
|
|
bitfld.long 0x00 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked"
|
|
bitfld.long 0x00 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "WIDTH,Transfer Width" "0: Single bit transfer,1: Two bit transfer,2: Four bit transfer,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. "FRAMESZ,Frame Size"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. "RXEMPTY,RX FIFO Empty" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
bitfld.long 0x00 0. "SOF,Start Of Frame" "0: Subsequent data word received after LPSPI_PCS..,1: First data word received after LPSPI_PCS.."
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Receive Data"
|
|
tree.end
|
|
repeat.end
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
tree "LPSPI2"
|
|
base ad:0x4002E000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Module Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Module is disabled in debug mode,1: Module is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Module is enabled in Doze mode,1: Module is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Module Enable" "0: Module is disabled,1: Module is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy"
|
|
bitfld.long 0x00 13. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
newline
|
|
bitfld.long 0x00 12. "REF,Receive Error Flag" "0: Receive FIFO has not overflowed,1: Receive FIFO has overflowed"
|
|
bitfld.long 0x00 11. "TEF,Transmit Error Flag" "0: Transmit FIFO underrun has not occurred,1: Transmit FIFO underrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 10. "TCF,Transfer Complete Flag" "0: All transfers have not completed,1: All transfers have completed"
|
|
bitfld.long 0x00 9. "FCF,Frame Complete Flag" "0: Frame transfer has not completed,1: Frame transfer has completed"
|
|
newline
|
|
bitfld.long 0x00 8. "WCF,Word Complete Flag" "0: Transfer word not completed,1: Transfer word completed"
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "REIE,Receive Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TEIE,Transmit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "TCIE,Transfer Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FCIE,Frame Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "WCIE,Word Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DER,DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the DMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPSPI_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request is disabled,1: Host request is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are enabled,1: PCS[3:2] are disabled"
|
|
bitfld.long 0x00 26. "OUTCFG,Output Config" "0: Output data retains last value when chip..,1: Output data is tristated when chip select is.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data and SOUT for..,1: SIN is used for both input and output data,2: SOUT is used for both input and output data,3: SOUT is used for input data and SIN for.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: 010b - Match is enabled if 1st data word..,3: 011b - Match is enabled if any data word..,4: 100b - Match is enabled if 1st data word..,5: 101b - Match is enabled if any data word..,6: 110b - Match is enabled if (1st data word AND..,7: 111b - Match is enabled if (any data word AND.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PCSPOL,Peripheral Chip Select Polarity" "0: The PCSx is active low,1: The PCSx is active high,?..."
|
|
bitfld.long 0x00 3. "NOSTALL,No Stall" "0: Transfers will stall when transmit FIFO is..,1: Transfers will not stall allowing transmit.."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTOPCS,Automatic PCS" "0: Automatic PCS generation disabled,1: Automatic PCS generation enabled"
|
|
bitfld.long 0x00 1. "SAMPLE,Sample Point" "0: Input data sampled on SCK edge,1: Input data sampled on delayed SCK edge"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH0,Match 0 Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMR1,Data Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH1,Match 1 Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCKPCS,SCK to PCS Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSSCK,PCS to SCK Delay"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DBT,Delay Between Transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCKDIV,SCK Divider"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
|
|
bitfld.long 0x00 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
|
|
newline
|
|
bitfld.long 0x00 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
bitfld.long 0x00 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using LPSPI_PCS[0],1: Transfer using LPSPI_PCS[1],2: Transfer using LPSPI_PCS[2],3: Transfer using LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
|
|
bitfld.long 0x00 22. "BYSW,Byte Swap" "0: Byte swap disabled,1: Byte swap enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CONT,Continuous Transfer" "0: Continuous transfer disabled,1: Continuous transfer enabled"
|
|
bitfld.long 0x00 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked"
|
|
bitfld.long 0x00 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "WIDTH,Transfer Width" "0: Single bit transfer,1: Two bit transfer,2: Four bit transfer,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. "FRAMESZ,Frame Size"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. "RXEMPTY,RX FIFO Empty" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
bitfld.long 0x00 0. "SOF,Start Of Frame" "0: Subsequent data word received after LPSPI_PCS..,1: First data word received after LPSPI_PCS.."
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Receive Data"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("S32K148")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")
|
|
tree "PDB (Programmable Delay Block)"
|
|
tree "PDB0"
|
|
base ad:0x40036000
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC,Status and Control register"
|
|
bitfld.long 0x00 18.--19. "LDMOD,Load Mode Select" "0: The internal registers are loaded with the..,1: The internal registers are loaded with the..,2: The internal registers are loaded with the..,3: The internal registers are loaded with the.."
|
|
bitfld.long 0x00 17. "PDBEIE,PDB Sequence Error Interrupt Enable" "0: PDB sequence error interrupt disabled,1: PDB sequence error interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "SWTRIG,Software Trigger" "0,1"
|
|
bitfld.long 0x00 15. "DMAEN,DMA Enable" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "PRESCALER,Prescaler Divider Select" "0: Counting uses the peripheral clock divided by..,1: Counting uses the peripheral clock divided by..,2: Counting uses the peripheral clock divided by..,3: Counting uses the peripheral clock divided by..,4: Counting uses the peripheral clock divided by..,5: Counting uses the peripheral clock divided by..,6: Counting uses the peripheral clock divided by..,7: Counting uses the peripheral clock divided by.."
|
|
bitfld.long 0x00 8.--11. "TRGSEL,Trigger Input Source Select" "0: Trigger-In 0 is selected,1: Trigger-In 1 is selected,2: Trigger-In 2 is selected,3: Trigger-In 3 is selected,4: Trigger-In 4 is selected,5: Trigger-In 5 is selected,6: Trigger-In 6 is selected,7: Trigger-In 7 is selected,8: Trigger-In 8 is selected,9: Trigger-In 9 is selected,10: Trigger-In 10 is selected,11: Trigger-In 11 is selected,12: Trigger-In 12 is selected,13: Trigger-In 13 is selected,14: Trigger-In 14 is selected,15: Software trigger is selected"
|
|
newline
|
|
bitfld.long 0x00 7. "PDBEN,PDB Enable" "0: PDB disabled,1: PDB enabled"
|
|
bitfld.long 0x00 6. "PDBIF,PDB Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PDBIE,PDB Interrupt Enable" "0: PDB interrupt disabled,1: PDB interrupt enabled"
|
|
bitfld.long 0x00 2.--3. "MULT,Multiplication Factor Select for Prescaler" "0: Multiplication factor is 1,1: Multiplication factor is 10,2: Multiplication factor is 20,3: Multiplication factor is 40"
|
|
newline
|
|
bitfld.long 0x00 1. "CONT,Continuous Mode Enable" "0: PDB operation in One-Shot mode,1: PDB operation in Continuous mode"
|
|
bitfld.long 0x00 0. "LDOK,Load OK" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MOD,Modulus register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MOD,PDB Modulus"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CNT,Counter register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,PDB Counter"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IDLY,Interrupt Delay register"
|
|
hexmask.long.word 0x00 0.--15. 1. "IDLY,PDB Interrupt Delay"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0C1,Channel n Control register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BB,PDB Channel Pre-Trigger Back-to-Back Operation Enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOS,PDB Channel Pre-Trigger Output Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EN,PDB Channel Pre-Trigger Enable"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CH1C1,Channel n Control register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BB,PDB Channel Pre-Trigger Back-to-Back Operation Enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOS,PDB Channel Pre-Trigger Output Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EN,PDB Channel Pre-Trigger Enable"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CH2C1,Channel n Control register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BB,PDB Channel Pre-Trigger Back-to-Back Operation Enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOS,PDB Channel Pre-Trigger Output Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EN,PDB Channel Pre-Trigger Enable"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CH3C1,Channel n Control register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BB,PDB Channel Pre-Trigger Back-to-Back Operation Enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOS,PDB Channel Pre-Trigger Output Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EN,PDB Channel Pre-Trigger Enable"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH0S,Channel n Status register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CF,PDB Channel Flags"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERR,PDB Channel Sequence Error Flags"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CH1S,Channel n Status register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CF,PDB Channel Flags"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERR,PDB Channel Sequence Error Flags"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CH2S,Channel n Status register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CF,PDB Channel Flags"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERR,PDB Channel Sequence Error Flags"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CH3S,Channel n Status register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CF,PDB Channel Flags"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERR,PDB Channel Sequence Error Flags"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CH0DLY0,Channel n Delay 0 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1DLY0,Channel n Delay 0 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CH2DLY0,Channel n Delay 0 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH3DLY0,Channel n Delay 0 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CH0DLY1,Channel n Delay 1 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CH1DLY1,Channel n Delay 1 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CH2DLY1,Channel n Delay 1 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CH3DLY1,Channel n Delay 1 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CH0DLY2,Channel n Delay 2 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CH1DLY2,Channel n Delay 2 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CH2DLY2,Channel n Delay 2 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CH3DLY2,Channel n Delay 2 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CH0DLY3,Channel n Delay 3 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CH1DLY3,Channel n Delay 3 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CH2DLY3,Channel n Delay 3 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CH3DLY3,Channel n Delay 3 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CH0DLY4,Channel n Delay 4 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH1DLY4,Channel n Delay 4 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CH2DLY4,Channel n Delay 4 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CH3DLY4,Channel n Delay 4 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CH0DLY5,Channel n Delay 5 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CH1DLY5,Channel n Delay 5 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CH2DLY5,Channel n Delay 5 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CH3DLY5,Channel n Delay 5 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CH0DLY6,Channel n Delay 6 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CH1DLY6,Channel n Delay 6 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH2DLY6,Channel n Delay 6 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CH3DLY6,Channel n Delay 6 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH0DLY7,Channel n Delay 7 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CH1DLY7,Channel n Delay 7 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CH2DLY7,Channel n Delay 7 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CH3DLY7,Channel n Delay 7 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "POEN,Pulse-Out n Enable register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "POEN,PDB Pulse-Out Enable"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "PODLY,Pulse-Out n Delay register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DLY1,PDB Pulse-Out Delay 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY2,PDB Pulse-Out Delay 2"
|
|
group.word 0x194++0x01
|
|
line.word 0x00 "DLY2,PDB0_DLY2 register"
|
|
hexmask.word 0x00 0.--15. 1. "DLY2,DLY2"
|
|
group.word 0x196++0x01
|
|
line.word 0x00 "DLY1,PDB0_DLY1 register"
|
|
hexmask.word 0x00 0.--15. 1. "DLY1,DLY1"
|
|
endif
|
|
tree.end
|
|
tree "PDB1"
|
|
base ad:0x40031000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC,Status and Control register"
|
|
bitfld.long 0x00 18.--19. "LDMOD,Load Mode Select" "0: The internal registers are loaded with the..,1: The internal registers are loaded with the..,2: The internal registers are loaded with the..,3: The internal registers are loaded with the.."
|
|
bitfld.long 0x00 17. "PDBEIE,PDB Sequence Error Interrupt Enable" "0: PDB sequence error interrupt disabled,1: PDB sequence error interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "SWTRIG,Software Trigger" "0,1"
|
|
bitfld.long 0x00 15. "DMAEN,DMA Enable" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "PRESCALER,Prescaler Divider Select" "0: Counting uses the peripheral clock divided by..,1: Counting uses the peripheral clock divided by..,2: Counting uses the peripheral clock divided by..,3: Counting uses the peripheral clock divided by..,4: Counting uses the peripheral clock divided by..,5: Counting uses the peripheral clock divided by..,6: Counting uses the peripheral clock divided by..,7: Counting uses the peripheral clock divided by.."
|
|
bitfld.long 0x00 8.--11. "TRGSEL,Trigger Input Source Select" "0: Trigger-In 0 is selected,1: Trigger-In 1 is selected,2: Trigger-In 2 is selected,3: Trigger-In 3 is selected,4: Trigger-In 4 is selected,5: Trigger-In 5 is selected,6: Trigger-In 6 is selected,7: Trigger-In 7 is selected,8: Trigger-In 8 is selected,9: Trigger-In 9 is selected,10: Trigger-In 10 is selected,11: Trigger-In 11 is selected,12: Trigger-In 12 is selected,13: Trigger-In 13 is selected,14: Trigger-In 14 is selected,15: Software trigger is selected"
|
|
newline
|
|
bitfld.long 0x00 7. "PDBEN,PDB Enable" "0: PDB disabled,1: PDB enabled"
|
|
bitfld.long 0x00 6. "PDBIF,PDB Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PDBIE,PDB Interrupt Enable" "0: PDB interrupt disabled,1: PDB interrupt enabled"
|
|
bitfld.long 0x00 2.--3. "MULT,Multiplication Factor Select for Prescaler" "0: Multiplication factor is 1,1: Multiplication factor is 10,2: Multiplication factor is 20,3: Multiplication factor is 40"
|
|
newline
|
|
bitfld.long 0x00 1. "CONT,Continuous Mode Enable" "0: PDB operation in One-Shot mode,1: PDB operation in Continuous mode"
|
|
bitfld.long 0x00 0. "LDOK,Load OK" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MOD,Modulus register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MOD,PDB Modulus"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CNT,Counter register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,PDB Counter"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IDLY,Interrupt Delay register"
|
|
hexmask.long.word 0x00 0.--15. 1. "IDLY,PDB Interrupt Delay"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0C1,Channel n Control register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BB,PDB Channel Pre-Trigger Back-to-Back Operation Enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOS,PDB Channel Pre-Trigger Output Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EN,PDB Channel Pre-Trigger Enable"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CH1C1,Channel n Control register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BB,PDB Channel Pre-Trigger Back-to-Back Operation Enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOS,PDB Channel Pre-Trigger Output Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EN,PDB Channel Pre-Trigger Enable"
|
|
sif cpuis("S32K148")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "CH2C1,Channel n Control register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BB,PDB Channel Pre-Trigger Back-to-Back Operation Enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOS,PDB Channel Pre-Trigger Output Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EN,PDB Channel Pre-Trigger Enable"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "CH3C1,Channel n Control register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BB,PDB Channel Pre-Trigger Back-to-Back Operation Enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOS,PDB Channel Pre-Trigger Output Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EN,PDB Channel Pre-Trigger Enable"
|
|
endif
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH0S,Channel n Status register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CF,PDB Channel Flags"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERR,PDB Channel Sequence Error Flags"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CH1S,Channel n Status register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CF,PDB Channel Flags"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERR,PDB Channel Sequence Error Flags"
|
|
sif cpuis("S32K148")
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "CH2S,Channel n Status register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CF,PDB Channel Flags"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERR,PDB Channel Sequence Error Flags"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "CH3S,Channel n Status register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CF,PDB Channel Flags"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERR,PDB Channel Sequence Error Flags"
|
|
endif
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CH0DLY0,Channel n Delay 0 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1DLY0,Channel n Delay 0 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
sif cpuis("S32K148")
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "CH2DLY0,Channel n Delay 0 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "CH3DLY0,Channel n Delay 0 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CH0DLY1,Channel n Delay 1 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CH1DLY1,Channel n Delay 1 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
sif cpuis("S32K148")
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "CH2DLY1,Channel n Delay 1 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "CH3DLY1,Channel n Delay 1 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CH0DLY2,Channel n Delay 2 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CH1DLY2,Channel n Delay 2 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
sif cpuis("S32K148")
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "CH2DLY2,Channel n Delay 2 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "CH3DLY2,Channel n Delay 2 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CH0DLY3,Channel n Delay 3 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CH1DLY3,Channel n Delay 3 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
sif cpuis("S32K148")
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "CH2DLY3,Channel n Delay 3 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "CH3DLY3,Channel n Delay 3 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CH0DLY4,Channel n Delay 4 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH1DLY4,Channel n Delay 4 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
sif cpuis("S32K148")
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "CH2DLY4,Channel n Delay 4 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "CH3DLY4,Channel n Delay 4 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CH0DLY5,Channel n Delay 5 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CH1DLY5,Channel n Delay 5 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
sif cpuis("S32K148")
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "CH2DLY5,Channel n Delay 5 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "CH3DLY5,Channel n Delay 5 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CH0DLY6,Channel n Delay 6 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CH1DLY6,Channel n Delay 6 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
sif cpuis("S32K148")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "CH2DLY6,Channel n Delay 6 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "CH3DLY6,Channel n Delay 6 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH0DLY7,Channel n Delay 7 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CH1DLY7,Channel n Delay 7 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
sif cpuis("S32K148")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "CH2DLY7,Channel n Delay 7 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "CH3DLY7,Channel n Delay 7 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
endif
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "POEN,Pulse-Out n Enable register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "POEN,PDB Pulse-Out Enable"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "PODLY,Pulse-Out n Delay register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DLY1,PDB Pulse-Out Delay 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY2,PDB Pulse-Out Delay 2"
|
|
group.word 0x194++0x01
|
|
line.word 0x00 "DLY2,PDB1_DLY2 register"
|
|
hexmask.word 0x00 0.--15. 1. "DLY2,DLY2"
|
|
group.word 0x196++0x01
|
|
line.word 0x00 "DLY1,PDB1_DLY1 register"
|
|
hexmask.word 0x00 0.--15. 1. "DLY1,DLY1"
|
|
tree.end
|
|
tree.end
|
|
endif
|
|
tree "PORT (Pin Control and Interrupts)"
|
|
tree "PORTA"
|
|
base ad:0x40049000
|
|
repeat 5. (strings "0" "1" "2" "3" "4" )(list 0x0 0x4 0x8 0xC 0x10 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "PCR5,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat 5. (strings "6" "7" "8" "9" "10" )(list 0x0 0x4 0x8 0xC 0x10 )
|
|
group.long ($2+0x18)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
repeat.end
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "PCR10,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
repeat 16. (strings "11" "12" "13" "14" "15" "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x2C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 5. (strings "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 )
|
|
group.long ($2+0x6C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
wgroup.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISF,Interrupt Status Flag"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DFER,Digital Filter Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "DFE,Digital Filter Enable"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x00 0. "CS,Clock Source" "0: Digital filters are clocked by the bus clock,1: Digital filters are clocked by the LPO clock"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x00 0.--4. "FILT,Filter Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "PORTB"
|
|
base ad:0x4004A000
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 2. (strings "4" "5" )(list 0x0 0x4 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PCR6,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "PCR6,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
repeat 16. (strings "7" "8" "9" "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "20" "21" "22" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x1C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 9. (strings "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 )
|
|
group.long ($2+0x5C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
wgroup.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISF,Interrupt Status Flag"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DFER,Digital Filter Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "DFE,Digital Filter Enable"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x00 0. "CS,Clock Source" "0: Digital filters are clocked by the bus clock,1: Digital filters are clocked by the LPO clock"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x00 0.--4. "FILT,Filter Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "PORTC"
|
|
base ad:0x4004B000
|
|
repeat 16. (strings "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 16. (strings "16" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x40)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
wgroup.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISF,Interrupt Status Flag"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DFER,Digital Filter Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "DFE,Digital Filter Enable"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x00 0. "CS,Clock Source" "0: Digital filters are clocked by the bus clock,1: Digital filters are clocked by the LPO clock"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x00 0.--4. "FILT,Filter Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "PORTD"
|
|
base ad:0x4004C000
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "PCR2,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PCR3,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 4. "PFE,Passive Filter Enable" "0: Passive input filter is disabled on the..,1: Passive input filter is enabled on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat 11. (strings "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 )
|
|
group.long ($2+0x10)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 2. (strings "15" "16" )(list 0x0 0x4 )
|
|
group.long ($2+0x3C)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 15. (strings "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x44)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
wgroup.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISF,Interrupt Status Flag"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DFER,Digital Filter Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "DFE,Digital Filter Enable"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x00 0. "CS,Clock Source" "0: Digital filters are clocked by the bus clock,1: Digital filters are clocked by the LPO clock"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x00 0.--4. "FILT,Filter Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree "PORTE"
|
|
base ad:0x4004D000
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x4 )
|
|
group.long ($2+0x00)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
repeat 3. (strings "2" "3" "4" )(list 0x0 0x4 0x8 )
|
|
group.long ($2+0x08)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
repeat.end
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "PCR4,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
repeat 15. (strings "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" "16" "17" "18" "19" )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 )
|
|
group.long ($2+0x14)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "PCR20,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "20" "21" )(list 0x0 0x4 )
|
|
group.long ($2+0x50)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")
|
|
repeat 2. (strings "21" "22" )(list 0x0 0x4 )
|
|
group.long ($2+0x54)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "PCR22,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PCR23,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "PCR23,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "PCR24,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "24" "25" )(list 0x0 0x4 )
|
|
group.long ($2+0x60)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "PCR25,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 6. "DSE,Drive Strength Enable" "0: Low drive strength is configured on the..,1: High drive strength is configured on the.."
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
newline
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
endif
|
|
repeat 6. (strings "26" "27" "28" "29" "30" "31" )(list 0x0 0x4 0x8 0xC 0x10 0x14 )
|
|
group.long ($2+0x68)++0x03
|
|
line.long 0x00 "PCR$1,Pin Control Register n"
|
|
bitfld.long 0x00 24. "ISF,Interrupt Status Flag" "0: Configured interrupt is not detected,1: Configured interrupt is detected"
|
|
bitfld.long 0x00 16.--19. "IRQC,Interrupt Configuration" "0: Interrupt Status Flag (ISF) is disabled,1: ISF flag and DMA request on rising edge,2: ISF flag and DMA request on falling edge,3: ISF flag and DMA request on either edge,?,?,?,?,8: ISF flag and Interrupt when logic 0,9: ISF flag and Interrupt on rising-edge,10: ISF flag and Interrupt on falling-edge,11: ISF flag and Interrupt on either edge,12: ISF flag and Interrupt when logic 1,?..."
|
|
newline
|
|
bitfld.long 0x00 15. "LK,Lock Register" "0: Pin Control Register fields [15:0] are not..,1: Pin Control Register fields [15:0] are locked.."
|
|
bitfld.long 0x00 8.--10. "MUX,Pin Mux Control" "0: Pin disabled (Alternative 0) (analog),1: Alternative 1 (GPIO),2: Alternative 2 (chip-specific),3: Alternative 3 (chip-specific),4: Alternative 4 (chip-specific),5: Alternative 5 (chip-specific),6: Alternative 6 (chip-specific),7: Alternative 7 (chip-specific)"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Pull Enable" "0: Internal pullup or pulldown resistor is not..,1: Internal pullup or pulldown resistor is.."
|
|
bitfld.long 0x00 0. "PS,Pull Select" "0: Internal pulldown resistor is enabled on the..,1: Internal pullup resistor is enabled on the.."
|
|
repeat.end
|
|
wgroup.long 0x80++0x03
|
|
line.long 0x00 "GPCLR,Global Pin Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
wgroup.long 0x84++0x03
|
|
line.long 0x00 "GPCHR,Global Pin Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GPWE,Global Pin Write Enable"
|
|
hexmask.long.word 0x00 0.--15. 1. "GPWD,Global Pin Write Data"
|
|
wgroup.long 0x88++0x03
|
|
line.long 0x00 "GICLR,Global Interrupt Control Low Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
wgroup.long 0x8C++0x03
|
|
line.long 0x00 "GICHR,Global Interrupt Control High Register"
|
|
hexmask.long.word 0x00 16.--31. 1. "GIWD,Global Interrupt Write Data"
|
|
hexmask.long.word 0x00 0.--15. 1. "GIWE,Global Interrupt Write Enable"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "ISFR,Interrupt Status Flag Register"
|
|
hexmask.long 0x00 0.--31. 1. "ISF,Interrupt Status Flag"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DFER,Digital Filter Enable Register"
|
|
hexmask.long 0x00 0.--31. 1. "DFE,Digital Filter Enable"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "DFCR,Digital Filter Clock Register"
|
|
bitfld.long 0x00 0. "CS,Clock Source" "0: Digital filters are clocked by the bus clock,1: Digital filters are clocked by the LPO clock"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "DFWR,Digital Filter Width Register"
|
|
bitfld.long 0x00 0.--4. "FILT,Filter Length" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
tree.end
|
|
tree.end
|
|
sif cpuis("S32K148")
|
|
tree "SAI (Synchronous Serial Interface)"
|
|
repeat 2. (list 0. 1.) (list ad:0x40054000 ad:0x40055000)
|
|
tree "SAI$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "SAI_VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "SAI_PARAM,Parameter Register"
|
|
bitfld.long 0x00 16.--19. "FRAME,Frame Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 8.--11. "FIFO,FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "DATALINE,Number of Datalines" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SAI_TCSR,SAI Transmit Control Register"
|
|
bitfld.long 0x00 31. "TE,Transmitter Enable" "0: Transmitter is disabled,1: Transmitter is enabled or transmitter has.."
|
|
bitfld.long 0x00 29. "DBGE,Debug Enable" "0: Transmitter is disabled in Debug mode after..,1: Transmitter is enabled in Debug mode"
|
|
newline
|
|
bitfld.long 0x00 28. "BCE,Bit Clock Enable" "0: Transmit bit clock is disabled,1: Transmit bit clock is enabled"
|
|
bitfld.long 0x00 25. "FR,FIFO Reset" "0: No effect,1: FIFO reset"
|
|
newline
|
|
bitfld.long 0x00 24. "SR,Software Reset" "0: No effect,1: Software reset"
|
|
bitfld.long 0x00 20. "WSF,Word Start Flag" "0: Start of word not detected,1: Start of word detected"
|
|
newline
|
|
bitfld.long 0x00 19. "SEF,Sync Error Flag" "0: Sync error not detected,1: Frame sync error detected"
|
|
bitfld.long 0x00 18. "FEF,FIFO Error Flag" "0: Transmit underrun not detected,1: Transmit underrun detected"
|
|
newline
|
|
rbitfld.long 0x00 17. "FWF,FIFO Warning Flag" "0: No enabled transmit FIFO is empty,1: Enabled transmit FIFO is empty"
|
|
rbitfld.long 0x00 16. "FRF,FIFO Request Flag" "0: Transmit FIFO watermark has not been reached,1: Transmit FIFO watermark has been reached"
|
|
newline
|
|
bitfld.long 0x00 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
bitfld.long 0x00 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
bitfld.long 0x00 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
bitfld.long 0x00 1. "FWDE,FIFO Warning DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
newline
|
|
bitfld.long 0x00 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SAI_TCR1,SAI Transmit Configuration 1 Register"
|
|
bitfld.long 0x00 0.--2. "TFW,Transmit FIFO Watermark" "0,1,2,3,4,5,6,7"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SAI_TCR2,SAI Transmit Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with receiver,?..."
|
|
bitfld.long 0x00 29. "BCS,Bit Clock Swap" "0: Use the normal bit clock source,1: Swap the bit clock source"
|
|
newline
|
|
bitfld.long 0x00 28. "BCI,Bit Clock Input" "0: No effect,1: Internal logic is clocked as if bit clock was.."
|
|
bitfld.long 0x00 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected,1: Master Clock (MCLK) 1 option selected,2: Master Clock (MCLK) 2 option selected,3: Master Clock (MCLK) 3 option selected"
|
|
newline
|
|
bitfld.long 0x00 25. "BCP,Bit Clock Polarity" "0: Bit clock is active high with drive outputs..,1: Bit clock is active low with drive outputs on.."
|
|
bitfld.long 0x00 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode,1: Bit clock is generated internally in Master.."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV,Bit Clock Divide"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SAI_TCR3,SAI Transmit Configuration 3 Register"
|
|
bitfld.long 0x00 24.--27. "CFR,Channel FIFO Reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "TCE,Transmit Channel Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "WDFL,Word Flag Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SAI_TCR4,SAI Transmit Configuration 4 Register"
|
|
bitfld.long 0x00 28. "FCONT,FIFO Continue on Error" "0: On FIFO error the SAI will continue from the..,1: On FIFO error the SAI will continue from the.."
|
|
bitfld.long 0x00 26.--27. "FCOMB,FIFO Combine Mode" "0: FIFO combine mode disabled,1: FIFO combine mode enabled on FIFO reads (from..,2: FIFO combine mode enabled on FIFO writes (by..,3: FIFO combine mode enabled on FIFO reads (from.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled,?,2: 8-bit FIFO packing is enabled,3: 16-bit FIFO packing is enabled"
|
|
bitfld.long 0x00 16.--19. "FRSZ,Frame size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "SYWD,Sync Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5. "CHMOD,Channel Mode" "0: TDM mode transmit data pins are tri-stated..,1: Output mode transmit data pins are never.."
|
|
newline
|
|
bitfld.long 0x00 4. "MF,MSB First" "0: LSB is transmitted first,1: MSB is transmitted first"
|
|
bitfld.long 0x00 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first.."
|
|
newline
|
|
bitfld.long 0x00 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously,1: Internal frame sync is generated when the.."
|
|
bitfld.long 0x00 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high,1: Frame sync is active low"
|
|
newline
|
|
bitfld.long 0x00 0. "FSD,Frame Sync Direction" "0: Frame sync is generated externally in Slave..,1: Frame sync is generated internally in Master.."
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SAI_TCR5,SAI Transmit Configuration 5 Register"
|
|
bitfld.long 0x00 24.--28. "WNW,Word N Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "W0W,Word 0 Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "FBT,First Bit Shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
wgroup.long ($2+0x20)++0x03
|
|
line.long 0x00 "SAI_TDR$1,SAI Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "TDR,Transmit Data Register"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
rgroup.long ($2+0x40)++0x03
|
|
line.long 0x00 "SAI_TFR$1,SAI Transmit FIFO Register"
|
|
bitfld.long 0x00 31. "WCP,Write Channel Pointer" "0: No effect,1: FIFO combine is enabled for FIFO writes and.."
|
|
bitfld.long 0x00 16.--19. "WFP,Write FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "RFP,Read FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "SAI_TMR,SAI Transmit Mask Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "TWM,Transmit Word Mask"
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "SAI_RCSR,SAI Receive Control Register"
|
|
bitfld.long 0x00 31. "RE,Receiver Enable" "0: Receiver is disabled,1: Receiver is enabled or receiver has been.."
|
|
bitfld.long 0x00 29. "DBGE,Debug Enable" "0: Receiver is disabled in Debug mode after..,1: Receiver is enabled in Debug mode"
|
|
newline
|
|
bitfld.long 0x00 28. "BCE,Bit Clock Enable" "0: Receive bit clock is disabled,1: Receive bit clock is enabled"
|
|
bitfld.long 0x00 25. "FR,FIFO Reset" "0: No effect,1: FIFO reset"
|
|
newline
|
|
bitfld.long 0x00 24. "SR,Software Reset" "0: No effect,1: Software reset"
|
|
bitfld.long 0x00 20. "WSF,Word Start Flag" "0: Start of word not detected,1: Start of word detected"
|
|
newline
|
|
bitfld.long 0x00 19. "SEF,Sync Error Flag" "0: Sync error not detected,1: Frame sync error detected"
|
|
bitfld.long 0x00 18. "FEF,FIFO Error Flag" "0: Receive overflow not detected,1: Receive overflow detected"
|
|
newline
|
|
rbitfld.long 0x00 17. "FWF,FIFO Warning Flag" "0: No enabled receive FIFO is full,1: Enabled receive FIFO is full"
|
|
rbitfld.long 0x00 16. "FRF,FIFO Request Flag" "0: Receive FIFO watermark not reached,1: Receive FIFO watermark has been reached"
|
|
newline
|
|
bitfld.long 0x00 12. "WSIE,Word Start Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
bitfld.long 0x00 11. "SEIE,Sync Error Interrupt Enable" "0: Disables interrupt,1: Enables interrupt"
|
|
newline
|
|
bitfld.long 0x00 10. "FEIE,FIFO Error Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
bitfld.long 0x00 9. "FWIE,FIFO Warning Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
newline
|
|
bitfld.long 0x00 8. "FRIE,FIFO Request Interrupt Enable" "0: Disables the interrupt,1: Enables the interrupt"
|
|
bitfld.long 0x00 1. "FWDE,FIFO Warning DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
newline
|
|
bitfld.long 0x00 0. "FRDE,FIFO Request DMA Enable" "0: Disables the DMA request,1: Enables the DMA request"
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "SAI_RCR1,SAI Receive Configuration 1 Register"
|
|
bitfld.long 0x00 0.--2. "RFW,Receive FIFO Watermark" "0,1,2,3,4,5,6,7"
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "SAI_RCR2,SAI Receive Configuration 2 Register"
|
|
bitfld.long 0x00 30.--31. "SYNC,Synchronous Mode" "0: Asynchronous mode,1: Synchronous with transmitter,?..."
|
|
bitfld.long 0x00 29. "BCS,Bit Clock Swap" "0: Use the normal bit clock source,1: Swap the bit clock source"
|
|
newline
|
|
bitfld.long 0x00 28. "BCI,Bit Clock Input" "0: No effect,1: Internal logic is clocked as if bit clock was.."
|
|
bitfld.long 0x00 26.--27. "MSEL,MCLK Select" "0: Bus Clock selected,1: Master Clock (MCLK) 1 option selected,2: Master Clock (MCLK) 2 option selected,3: Master Clock (MCLK) 3 option selected"
|
|
newline
|
|
bitfld.long 0x00 25. "BCP,Bit Clock Polarity" "0: Bit Clock is active high with drive outputs..,1: Bit Clock is active low with drive outputs on.."
|
|
bitfld.long 0x00 24. "BCD,Bit Clock Direction" "0: Bit clock is generated externally in Slave mode,1: Bit clock is generated internally in Master.."
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DIV,Bit Clock Divide"
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "SAI_RCR3,SAI Receive Configuration 3 Register"
|
|
bitfld.long 0x00 24.--27. "CFR,Channel FIFO Reset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "RCE,Receive Channel Enable" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 0.--3. "WDFL,Word Flag Configuration" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "SAI_RCR4,SAI Receive Configuration 4 Register"
|
|
bitfld.long 0x00 28. "FCONT,FIFO Continue on Error" "0: On FIFO error the SAI will continue from the..,1: On FIFO error the SAI will continue from the.."
|
|
bitfld.long 0x00 26.--27. "FCOMB,FIFO Combine Mode" "0: FIFO combine mode disabled,1: FIFO combine mode enabled on FIFO writes..,2: FIFO combine mode enabled on FIFO reads (by..,3: FIFO combine mode enabled on FIFO writes.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "FPACK,FIFO Packing Mode" "0: FIFO packing is disabled,?,2: 8-bit FIFO packing is enabled,3: 16-bit FIFO packing is enabled"
|
|
bitfld.long 0x00 16.--19. "FRSZ,Frame Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "SYWD,Sync Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 4. "MF,MSB First" "0: LSB is received first,1: MSB is received first"
|
|
newline
|
|
bitfld.long 0x00 3. "FSE,Frame Sync Early" "0: Frame sync asserts with the first bit of the..,1: Frame sync asserts one bit before the first.."
|
|
bitfld.long 0x00 2. "ONDEM,On Demand Mode" "0: Internal frame sync is generated continuously,1: Internal frame sync is generated when the.."
|
|
newline
|
|
bitfld.long 0x00 1. "FSP,Frame Sync Polarity" "0: Frame sync is active high,1: Frame sync is active low"
|
|
bitfld.long 0x00 0. "FSD,Frame Sync Direction" "0: Frame Sync is generated externally in Slave..,1: Frame Sync is generated internally in Master.."
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "SAI_RCR5,SAI Receive Configuration 5 Register"
|
|
bitfld.long 0x00 24.--28. "WNW,Word N Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 16.--20. "W0W,Word 0 Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "FBT,First Bit Shifted" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
rgroup.long ($2+0xA0)++0x03
|
|
line.long 0x00 "SAI_RDR$1,SAI Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "RDR,Receive Data Register"
|
|
repeat.end
|
|
repeat 4. (strings "0" "1" "2" "3" )(list 0x0 0x4 0x8 0xC )
|
|
rgroup.long ($2+0xC0)++0x03
|
|
line.long 0x00 "SAI_RFR$1,SAI Receive FIFO Register"
|
|
bitfld.long 0x00 16.--19. "WFP,Write FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 15. "RCP,Receive Channel Pointer" "0: No effect,1: FIFO combine is enabled for FIFO reads and.."
|
|
newline
|
|
bitfld.long 0x00 0.--3. "RFP,Read FIFO Pointer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
repeat.end
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "SAI_RMR,SAI Receive Mask Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "RWM,Receive Word Mask"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
tree "LPI2C (The LPI2C Memory Map/Register Definition can be found here.)"
|
|
repeat 2. (list 0. 1.) (list ad:0x40066000 ad:0x40067000)
|
|
tree "LPI2C$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
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|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
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|
bitfld.long 0x00 8.--11. "MRXFIFO,Master Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MTXFIFO,Master Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Master is disabled in debug mode,1: Master is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Master is enabled in Doze mode,1: Master is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Master Enable" "0: Master logic is disabled,1: Master logic is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MSR,Master Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "MBF,Master Busy Flag" "0: I2C Master is idle,1: I2C Master is busy"
|
|
newline
|
|
bitfld.long 0x00 14. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
bitfld.long 0x00 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout has not occurred or is disabled,1: Pin low timeout has occurred"
|
|
newline
|
|
bitfld.long 0x00 12. "FEF,FIFO Error Flag" "0: No error,1: Master sending or receiving data without.."
|
|
bitfld.long 0x00 11. "ALF,Arbitration Lost Flag" "0: Master has not lost arbitration,1: Master has lost arbitration"
|
|
newline
|
|
bitfld.long 0x00 10. "NDF,NACK Detect Flag" "0: Unexpected NACK not detected,1: Unexpected NACK was detected"
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Master has not generated a STOP condition,1: Master has generated a STOP condition"
|
|
newline
|
|
bitfld.long 0x00 8. "EPF,End Packet Flag" "0: Master has not generated a STOP or Repeated..,1: Master has generated a STOP or Repeated START.."
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 14. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt enabled,1: Interrupt disabled"
|
|
bitfld.long 0x00 11. "ALIE,Arbitration Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "NDIE,NACK Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "EPIE,End Packet Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the RMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request input is disabled,1: Host request input is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. "PINCFG,Pin Configuration" "0: LPI2C configured for 2-pin open drain mode,1: LPI2C configured for 2-pin output only mode..,2: LPI2C configured for 2-pin push-pull mode,3: LPI2C configured for 4-pin push-pull mode,4: LPI2C configured for 2-pin open drain mode..,5: LPI2C configured for 2-pin output only mode..,6: LPI2C configured for 2-pin push-pull mode..,7: LPI2C configured for 4-pin push-pull mode.."
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|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
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|
newline
|
|
bitfld.long 0x00 10. "TIMECFG,Timeout Configuration" "0: Pin Low Timeout Flag will set if SCL is low..,1: Pin Low Timeout Flag will set if either SCL.."
|
|
bitfld.long 0x00 9. "IGNACK,IGNACK" "0: LPI2C Master will receive ACK and NACK normally,1: LPI2C Master will treat a received NACK as if.."
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|
newline
|
|
bitfld.long 0x00 8. "AUTOSTOP,Automatic STOP Generation" "0: No effect,1: STOP condition is automatically generated.."
|
|
bitfld.long 0x00 0.--2. "PRESCALE,Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCFGR2,Master Configuration Register 2"
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|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BUSIDLE,Bus Idle Timeout"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x00 8.--19. 1. "PINLOW,Pin Low Timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MATCH1,Match 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MATCH0,Match 0 Value"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x8 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "MCCR$1,Master Clock Configuration Register $1"
|
|
bitfld.long 0x00 24.--29. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "SETHOLD,Setup Hold Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CLKHI,Clock High Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "CLKLO,Clock Low Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. "CMD,Command Data" "0: Transmit DATA[7:0],1: Receive (DATA[7:0] + 1) bytes,2: Generate STOP condition,3: Receive and discard (DATA[7:0] + 1) bytes,4: Generate (repeated) START and transmit..,5: Generate (repeated) START and transmit..,6: Generate (repeated) START and transmit..,7: Generate (repeated) START and transmit.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "MRDR,Master Receive Data Register"
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: Receive FIFO is not empty,1: Receive FIFO is empty"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 5. "FILTDZ,Filter Doze Enable" "0: Filter remains enabled in Doze mode,1: Filter is disabled in Doze mode"
|
|
bitfld.long 0x00 4. "FILTEN,Filter Enable" "0: Disable digital filter and output delay..,1: Enable digital filter and output delay.."
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Slave logic is not reset,1: Slave logic is reset"
|
|
bitfld.long 0x00 0. "SEN,Slave Enable" "0: Slave mode is disabled,1: Slave mode is enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "SBF,Slave Busy Flag" "0: I2C Slave is idle,1: I2C Slave is busy"
|
|
newline
|
|
rbitfld.long 0x00 15. "SARF,SMBus Alert Response Flag" "0: SMBus Alert Response disabled or not detected,1: SMBus Alert Response enabled and detected"
|
|
rbitfld.long 0x00 14. "GCF,General Call Flag" "0: Slave has not detected the General Call..,1: Slave has detected the General Call Address"
|
|
newline
|
|
rbitfld.long 0x00 13. "AM1F,Address Match 1 Flag" "0: Have not received ADDR1 or ADDR0/ADDR1 range..,1: Have received ADDR1 or ADDR0/ADDR1 range.."
|
|
rbitfld.long 0x00 12. "AM0F,Address Match 0 Flag" "0: Have not received ADDR0 matching address,1: Have received ADDR0 matching address"
|
|
newline
|
|
bitfld.long 0x00 11. "FEF,FIFO Error Flag" "0: FIFO underflow or overflow not detected,1: FIFO underflow or overflow detected"
|
|
bitfld.long 0x00 10. "BEF,Bit Error Flag" "0: Slave has not detected a bit error,1: Slave has detected a bit error"
|
|
newline
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Slave has not detected a STOP condition,1: Slave has detected a STOP condition"
|
|
bitfld.long 0x00 8. "RSF,Repeated Start Flag" "0: Slave has not detected a Repeated START..,1: Slave has detected a Repeated START condition"
|
|
newline
|
|
rbitfld.long 0x00 3. "TAF,Transmit ACK Flag" "0: Transmit ACK/NACK is not required,1: Transmit ACK/NACK is required"
|
|
rbitfld.long 0x00 2. "AVF,Address Valid Flag" "0: Address Status Register is not valid,1: Address Status Register is valid"
|
|
newline
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 14. "GCIE,General Call Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "AM1F,Address Match 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "AM0IE,Address Match 0 Interrupt Enable" "0: Interrupt enabled,1: Interrupt disabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "BEIE,Bit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "RSIE,Repeated Start Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "TAIE,Transmit ACK Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 2. "AVIE,Address Valid Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x00 2. "AVDE,Address Valid DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or Address match 1..,3: Address match 0 (10-bit) or Address match 1..,4: Address match 0 (7-bit) or Address match 1..,5: Address match 0 (10-bit) or Address match 1..,6: From Address match 0 (7-bit) to Address match..,7: From Address match 0 (10-bit) to Address.."
|
|
bitfld.long 0x00 13. "HSMEN,High Speed Mode Enable" "0: Disables detection of Hs-mode master code,1: Enables detection of Hs-mode master code"
|
|
newline
|
|
bitfld.long 0x00 12. "IGNACK,Ignore NACK" "0: Slave will end transfer when NACK detected,1: Slave will not end transfer when NACK detected"
|
|
bitfld.long 0x00 11. "RXCFG,Receive Data Configuration" "0: Reading the receive data register will return..,1: Reading the receive data register when the.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXCFG,Transmit Flag Configuration" "0: Transmit Data Flag will only assert during a..,1: Transmit Data Flag will assert whenever the.."
|
|
bitfld.long 0x00 9. "SAEN,SMBus Alert Enable" "0: Disables match on SMBus Alert,1: Enables match on SMBus Alert"
|
|
newline
|
|
bitfld.long 0x00 8. "GCEN,General Call Enable" "0: General Call address is disabled,1: General call address is enabled"
|
|
bitfld.long 0x00 3. "ACKSTALL,ACK SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXDSTALL,TX Data SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
bitfld.long 0x00 1. "RXSTALL,RX SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADRSTALL,Address SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--3. "CLKHOLD,Clock Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "SAMR,Slave Address Match Register"
|
|
hexmask.long.word 0x00 17.--26. 1. "ADDR1,Address 1 Value"
|
|
hexmask.long.word 0x00 1.--10. 1. "ADDR0,Address 0 Value"
|
|
rgroup.long 0x150++0x03
|
|
line.long 0x00 "SASR,Slave Address Status Register"
|
|
bitfld.long 0x00 14. "ANV,Address Not Valid" "0: RADDR is valid,1: RADDR is not valid"
|
|
hexmask.long.word 0x00 0.--10. 1. "RADDR,Received Address"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "STAR,Slave Transmit ACK Register"
|
|
bitfld.long 0x00 0. "TXNACK,Transmit NACK" "0: Transmit ACK for received word,1: Transmit NACK for received word"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "STDR,Slave Transmit Data Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x170++0x03
|
|
line.long 0x00 "SRDR,Slave Receive Data Register"
|
|
bitfld.long 0x00 15. "SOF,Start Of Frame" "0: Indicates this is not the first data word..,1: Indicates this is the first data word since a.."
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: The Receive Data Register is not empty,1: The Receive Data Register is empty"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
tree "LPUART (Universal Asynchronous Receiver/Transmitter)"
|
|
repeat 2. (list 0. 1.) (list ad:0x4006A000 ad:0x4006B000)
|
|
tree "LPUART$1"
|
|
base $2
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RXD pin input,2: Input trigger is used instead of CTS_B pin..,3: Input trigger is used to modulate the TXD pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 7-bit to 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0: Writing 0 to this field will result in an..,?,?,3: Oversampling ratio of 4 requires BOTHEDGE to..,4: Oversampling ratio of 5 requires BOTHEDGE to..,5: Oversampling ratio of 6 requires BOTHEDGE to..,6: Oversampling ratio of 7 requires BOTHEDGE to..,7: Oversampling ratio of 8,8: Oversampling ratio of 9,9: Oversampling ratio of 10,10: Oversampling ratio of 11,11: Oversampling ratio of 12,12: Oversampling ratio of 13,13: Oversampling ratio of 14,14: Oversampling ratio of 15,15: Oversampling ratio of 16,16: Oversampling ratio of 17,17: Oversampling ratio of 18,18: Oversampling ratio of 19,19: Oversampling ratio of 20,20: Oversampling ratio of 21,21: Oversampling ratio of 22,22: Oversampling ratio of 23,23: Oversampling ratio of 24,24: Oversampling ratio of 25,25: Oversampling ratio of 26,26: Oversampling ratio of 27,27: Oversampling ratio of 28,28: Oversampling ratio of 29,29: Oversampling ratio of 30,30: Oversampling ratio of 31,31: Oversampling ratio of 32"
|
|
newline
|
|
bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RIDMAE,Receiver Idle DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,?..."
|
|
newline
|
|
bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
newline
|
|
bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[LBKDIF]..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[RXEDGIF]..,1: Hardware interrupt requested when.."
|
|
newline
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
bitfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
bitfld.long 0x00 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
newline
|
|
bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
|
|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
|
|
bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
|
|
newline
|
|
bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: LIN break detect is disabled normal break..,1: LIN break detect is enabled"
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (RXD input not idle)"
|
|
newline
|
|
rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
|
|
rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
|
|
bitfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
|
|
newline
|
|
bitfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
|
|
bitfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
|
|
newline
|
|
bitfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
bitfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
|
|
bitfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
|
|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in single-wire mode,1: TXD pin is an output in single-wire mode"
|
|
bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
|
|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
|
|
newline
|
|
bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
|
|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
|
|
newline
|
|
bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
|
|
bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
|
|
newline
|
|
bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
|
|
bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
|
|
newline
|
|
bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
|
|
bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
|
|
bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
|
|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "M7,7-Bit Mode Select" "0: Receiver and transmitter use 8-bit to 10-bit..,1: Receiver and transmitter use 7-bit data.."
|
|
bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
|
|
newline
|
|
bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RXD and TXD use separate..,1: Loop mode or single-wire mode where.."
|
|
bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the TXD pin is.."
|
|
bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
|
|
newline
|
|
bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
|
|
bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
|
|
bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DATA,LPUART Data Register"
|
|
rbitfld.long 0x00 15. "NOISY,NOISY" "0: The dataword was received without noise,1: The data was received with noise"
|
|
rbitfld.long 0x00 14. "PARITYE,PARITYE" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
|
|
newline
|
|
bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
|
|
rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
|
|
newline
|
|
rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
|
|
bitfld.long 0x00 9. "R9T9,R9T9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "R8T8,R8T8" "0,1"
|
|
bitfld.long 0x00 7. "R7T7,R7T7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "R6T6,R6T6" "0,1"
|
|
bitfld.long 0x00 5. "R5T5,R5T5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "R4T4,R4T4" "0,1"
|
|
bitfld.long 0x00 3. "R3T3,R3T3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "R2T2,R2T2" "0,1"
|
|
bitfld.long 0x00 1. "R1T1,R1T1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "R0T0,R0T0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODIR,LPUART Modem IrDA Register"
|
|
bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
|
|
bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3"
|
|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the CTS_B pin,1: CTS input is the inverted Receiver Match result"
|
|
newline
|
|
bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
|
|
bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
bitfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
bitfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
|
|
bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
|
|
newline
|
|
bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO" "0: Transmit FIFO/Buffer depth = 1 dataword,1: Transmit FIFO/Buffer depth = 4 datawords,2: Transmit FIFO/Buffer depth = 8 datawords,3: Transmit FIFO/Buffer depth = 16 datawords,4: Transmit FIFO/Buffer depth = 32 datawords,5: Transmit FIFO/Buffer depth = 64 datawords,6: Transmit FIFO/Buffer depth = 128 datawords,7: Transmit FIFO/Buffer depth = 256 datawords"
|
|
bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO" "0: Receive FIFO/Buffer depth = 1 dataword,1: Receive FIFO/Buffer depth = 4 datawords,2: Receive FIFO/Buffer depth = 8 datawords,3: Receive FIFO/Buffer depth = 16 datawords,4: Receive FIFO/Buffer depth = 32 datawords,5: Receive FIFO/Buffer depth = 64 datawords,6: Receive FIFO/Buffer depth = 128 datawords,7: Receive FIFO/Buffer depth = 256 datawords"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
rbitfld.long 0x00 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. "RXWATER,Receive Watermark" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3"
|
|
tree.end
|
|
repeat.end
|
|
sif cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
tree "LPUART2"
|
|
base ad:0x4006C000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "GLOBAL,LPUART Global Register"
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Module is not reset,1: Module is reset"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "PINCFG,LPUART Pin Configuration Register"
|
|
bitfld.long 0x00 0.--1. "TRGSEL,Trigger Select" "0: Input trigger is disabled,1: Input trigger is used instead of RXD pin input,2: Input trigger is used instead of CTS_B pin..,3: Input trigger is used to modulate the TXD pin.."
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "BAUD,LPUART Baud Rate Register"
|
|
bitfld.long 0x00 31. "MAEN1,Match Address Mode Enable 1" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
bitfld.long 0x00 30. "MAEN2,Match Address Mode Enable 2" "0: Normal operation,1: Enables automatic address matching or data.."
|
|
newline
|
|
bitfld.long 0x00 29. "M10,10-bit Mode select" "0: Receiver and transmitter use 7-bit to 9-bit..,1: Receiver and transmitter use 10-bit data.."
|
|
bitfld.long 0x00 24.--28. "OSR,Oversampling Ratio" "0: Writing 0 to this field will result in an..,?,?,3: Oversampling ratio of 4 requires BOTHEDGE to..,4: Oversampling ratio of 5 requires BOTHEDGE to..,5: Oversampling ratio of 6 requires BOTHEDGE to..,6: Oversampling ratio of 7 requires BOTHEDGE to..,7: Oversampling ratio of 8,8: Oversampling ratio of 9,9: Oversampling ratio of 10,10: Oversampling ratio of 11,11: Oversampling ratio of 12,12: Oversampling ratio of 13,13: Oversampling ratio of 14,14: Oversampling ratio of 15,15: Oversampling ratio of 16,16: Oversampling ratio of 17,17: Oversampling ratio of 18,18: Oversampling ratio of 19,19: Oversampling ratio of 20,20: Oversampling ratio of 21,21: Oversampling ratio of 22,22: Oversampling ratio of 23,23: Oversampling ratio of 24,24: Oversampling ratio of 25,25: Oversampling ratio of 26,26: Oversampling ratio of 27,27: Oversampling ratio of 28,28: Oversampling ratio of 29,29: Oversampling ratio of 30,30: Oversampling ratio of 31,31: Oversampling ratio of 32"
|
|
newline
|
|
bitfld.long 0x00 23. "TDMAE,Transmitter DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 21. "RDMAE,Receiver Full DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 20. "RIDMAE,Receiver Idle DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 18.--19. "MATCFG,Match Configuration" "0: Address Match Wakeup,1: Idle Match Wakeup,2: Match On and Match Off,?..."
|
|
newline
|
|
bitfld.long 0x00 17. "BOTHEDGE,Both Edge Sampling" "0: Receiver samples input data using the rising..,1: Receiver samples input data using the rising.."
|
|
bitfld.long 0x00 16. "RESYNCDIS,Resynchronization Disable" "0: Resynchronization during received data word..,1: Resynchronization during received data word.."
|
|
newline
|
|
bitfld.long 0x00 15. "LBKDIE,LIN Break Detect Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[LBKDIF]..,1: Hardware interrupt requested when.."
|
|
bitfld.long 0x00 14. "RXEDGIE,RX Input Active Edge Interrupt Enable" "0: Hardware interrupts from LPUART_STAT[RXEDGIF]..,1: Hardware interrupt requested when.."
|
|
newline
|
|
bitfld.long 0x00 13. "SBNS,Stop Bit Number Select" "0: One stop bit,1: Two stop bits"
|
|
hexmask.long.word 0x00 0.--12. 1. "SBR,Baud Rate Modulo Divisor"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "STAT,LPUART Status Register"
|
|
bitfld.long 0x00 31. "LBKDIF,LIN Break Detect Interrupt Flag" "0: No LIN break character has been detected,1: LIN break character has been detected"
|
|
bitfld.long 0x00 30. "RXEDGIF,RXD Pin Active Edge Interrupt Flag" "0: No active edge on the receive pin has occurred,1: An active edge on the receive pin has occurred"
|
|
newline
|
|
bitfld.long 0x00 29. "MSBF,MSB First" "0: LSB (bit0) is the first bit that is..,1: MSB (bit9 bit8 bit7 or bit6) is the first bit.."
|
|
bitfld.long 0x00 28. "RXINV,Receive Data Inversion" "0: Receive data not inverted,1: Receive data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "RWUID,Receive Wake Up Idle Detect" "0: During receive standby state (RWU = 1) the..,1: During receive standby state (RWU = 1) the.."
|
|
bitfld.long 0x00 26. "BRK13,Break Character Generation Length" "0: Break character is transmitted with length of..,1: Break character is transmitted with length of.."
|
|
newline
|
|
bitfld.long 0x00 25. "LBKDE,LIN Break Detection Enable" "0: LIN break detect is disabled normal break..,1: LIN break detect is enabled"
|
|
rbitfld.long 0x00 24. "RAF,Receiver Active Flag" "0: LPUART receiver idle waiting for a start bit,1: LPUART receiver active (RXD input not idle)"
|
|
newline
|
|
rbitfld.long 0x00 23. "TDRE,Transmit Data Register Empty Flag" "0: Transmit data buffer full,1: Transmit data buffer empty"
|
|
rbitfld.long 0x00 22. "TC,Transmission Complete Flag" "0: Transmitter active (sending data a preamble..,1: Transmitter idle (transmission activity.."
|
|
newline
|
|
rbitfld.long 0x00 21. "RDRF,Receive Data Register Full Flag" "0: Receive data buffer empty,1: Receive data buffer full"
|
|
bitfld.long 0x00 20. "IDLE,Idle Line Flag" "0: No idle line detected,1: Idle line was detected"
|
|
newline
|
|
bitfld.long 0x00 19. "OR,Receiver Overrun Flag" "0: No overrun,1: Receive overrun (new LPUART data lost)"
|
|
bitfld.long 0x00 18. "NF,Noise Flag" "0: No noise detected,1: Noise detected in the received character in.."
|
|
newline
|
|
bitfld.long 0x00 17. "FE,Framing Error Flag" "0: No framing error detected,1: Framing error"
|
|
bitfld.long 0x00 16. "PF,Parity Error Flag" "0: No parity error,1: Parity error"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1F,Match 1 Flag" "0: Received data is not equal to MA1,1: Received data is equal to MA1"
|
|
bitfld.long 0x00 14. "MA2F,Match 2 Flag" "0: Received data is not equal to MA2,1: Received data is equal to MA2"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CTRL,LPUART Control Register"
|
|
bitfld.long 0x00 31. "R8T9,Receive Bit 8 / Transmit Bit 9" "0,1"
|
|
bitfld.long 0x00 30. "R9T8,Receive Bit 9 / Transmit Bit 8" "0,1"
|
|
newline
|
|
bitfld.long 0x00 29. "TXDIR,TXD Pin Direction in Single-Wire Mode" "0: TXD pin is an input in single-wire mode,1: TXD pin is an output in single-wire mode"
|
|
bitfld.long 0x00 28. "TXINV,Transmit Data Inversion" "0: Transmit data not inverted,1: Transmit data inverted"
|
|
newline
|
|
bitfld.long 0x00 27. "ORIE,Overrun Interrupt Enable" "0: OR interrupts disabled use polling,1: Hardware interrupt requested when OR is set"
|
|
bitfld.long 0x00 26. "NEIE,Noise Error Interrupt Enable" "0: NF interrupts disabled use polling,1: Hardware interrupt requested when NF is set"
|
|
newline
|
|
bitfld.long 0x00 25. "FEIE,Framing Error Interrupt Enable" "0: FE interrupts disabled use polling,1: Hardware interrupt requested when FE is set"
|
|
bitfld.long 0x00 24. "PEIE,Parity Error Interrupt Enable" "0: PF interrupts disabled use polling),1: Hardware interrupt requested when PF is set"
|
|
newline
|
|
bitfld.long 0x00 23. "TIE,Transmit Interrupt Enable" "0: Hardware interrupts from TDRE disabled use..,1: Hardware interrupt requested when TDRE flag.."
|
|
bitfld.long 0x00 22. "TCIE,Transmission Complete Interrupt Enable for" "0: Hardware interrupts from TC disabled use..,1: Hardware interrupt requested when TC flag is 1"
|
|
newline
|
|
bitfld.long 0x00 21. "RIE,Receiver Interrupt Enable" "0: Hardware interrupts from RDRF disabled use..,1: Hardware interrupt requested when RDRF flag.."
|
|
bitfld.long 0x00 20. "ILIE,Idle Line Interrupt Enable" "0: Hardware interrupts from IDLE disabled use..,1: Hardware interrupt requested when IDLE flag.."
|
|
newline
|
|
bitfld.long 0x00 19. "TE,Transmitter Enable" "0: Transmitter disabled,1: Transmitter enabled"
|
|
bitfld.long 0x00 18. "RE,Receiver Enable" "0: Receiver disabled,1: Receiver enabled"
|
|
newline
|
|
bitfld.long 0x00 17. "RWU,Receiver Wakeup Control" "0: Normal receiver operation,1: LPUART receiver in standby waiting for wakeup.."
|
|
bitfld.long 0x00 16. "SBK,Send Break" "0: Normal transmitter operation,1: Queue break character(s) to be sent"
|
|
newline
|
|
bitfld.long 0x00 15. "MA1IE,Match 1 Interrupt Enable" "0: MA1F interrupt disabled,1: MA1F interrupt enabled"
|
|
bitfld.long 0x00 14. "MA2IE,Match 2 Interrupt Enable" "0: MA2F interrupt disabled,1: MA2F interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "M7,7-Bit Mode Select" "0: Receiver and transmitter use 8-bit to 10-bit..,1: Receiver and transmitter use 7-bit data.."
|
|
bitfld.long 0x00 8.--10. "IDLECFG,Idle Configuration" "0: 1 idle character,1: 2 idle characters,2: 4 idle characters,3: 8 idle characters,4: 16 idle characters,5: 32 idle characters,6: 64 idle characters,7: 128 idle characters"
|
|
newline
|
|
bitfld.long 0x00 7. "LOOPS,Loop Mode Select" "0: Normal operation - RXD and TXD use separate..,1: Loop mode or single-wire mode where.."
|
|
bitfld.long 0x00 6. "DOZEEN,Doze Enable" "0: LPUART is enabled in Doze mode,1: LPUART is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 5. "RSRC,Receiver Source Select" "0: Provided LOOPS is set RSRC is cleared selects..,1: Single-wire LPUART mode where the TXD pin is.."
|
|
bitfld.long 0x00 4. "M,9-Bit or 8-Bit Mode Select" "0: Receiver and transmitter use 8-bit data..,1: Receiver and transmitter use 9-bit data.."
|
|
newline
|
|
bitfld.long 0x00 3. "WAKE,Receiver Wakeup Method Select" "0: Configures RWU for idle-line wakeup,1: Configures RWU with address-mark wakeup"
|
|
bitfld.long 0x00 2. "ILT,Idle Line Type Select" "0: Idle character bit count starts after start bit,1: Idle character bit count starts after stop bit"
|
|
newline
|
|
bitfld.long 0x00 1. "PE,Parity Enable" "0: No hardware parity generation or checking,1: Parity enabled"
|
|
bitfld.long 0x00 0. "PT,Parity Type" "0: Even parity,1: Odd parity"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DATA,LPUART Data Register"
|
|
rbitfld.long 0x00 15. "NOISY,NOISY" "0: The dataword was received without noise,1: The data was received with noise"
|
|
rbitfld.long 0x00 14. "PARITYE,PARITYE" "0: The dataword was received without a parity..,1: The dataword was received with a parity error"
|
|
newline
|
|
bitfld.long 0x00 13. "FRETSC,Frame Error / Transmit Special Character" "0: The dataword was received without a frame..,1: The dataword was received with a frame error.."
|
|
rbitfld.long 0x00 12. "RXEMPT,Receive Buffer Empty" "0: Receive buffer contains valid data,1: Receive buffer is empty data returned on read.."
|
|
newline
|
|
rbitfld.long 0x00 11. "IDLINE,Idle Line" "0: Receiver was not idle before receiving this..,1: Receiver was idle before receiving this.."
|
|
bitfld.long 0x00 9. "R9T9,R9T9" "0,1"
|
|
newline
|
|
bitfld.long 0x00 8. "R8T8,R8T8" "0,1"
|
|
bitfld.long 0x00 7. "R7T7,R7T7" "0,1"
|
|
newline
|
|
bitfld.long 0x00 6. "R6T6,R6T6" "0,1"
|
|
bitfld.long 0x00 5. "R5T5,R5T5" "0,1"
|
|
newline
|
|
bitfld.long 0x00 4. "R4T4,R4T4" "0,1"
|
|
bitfld.long 0x00 3. "R3T3,R3T3" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "R2T2,R2T2" "0,1"
|
|
bitfld.long 0x00 1. "R1T1,R1T1" "0,1"
|
|
newline
|
|
bitfld.long 0x00 0. "R0T0,R0T0" "0,1"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MATCH,LPUART Match Address Register"
|
|
hexmask.long.word 0x00 16.--25. 1. "MA2,Match Address 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "MA1,Match Address 1"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MODIR,LPUART Modem IrDA Register"
|
|
bitfld.long 0x00 18. "IREN,Infrared enable" "0: IR disabled,1: IR enabled"
|
|
bitfld.long 0x00 16.--17. "TNP,Transmitter narrow pulse" "0: 1/OSR,1: 2/OSR,2: 3/OSR,3: 4/OSR"
|
|
newline
|
|
bitfld.long 0x00 8.--9. "RTSWATER,Receive RTS Configuration" "0,1,2,3"
|
|
bitfld.long 0x00 5. "TXCTSSRC,Transmit CTS Source" "0: CTS input is the CTS_B pin,1: CTS input is the inverted Receiver Match result"
|
|
newline
|
|
bitfld.long 0x00 4. "TXCTSC,Transmit CTS Configuration" "0: CTS input is sampled at the start of each..,1: CTS input is sampled when the transmitter is.."
|
|
bitfld.long 0x00 3. "RXRTSE,Receiver request-to-send enable" "0: The receiver has no effect on RTS,?..."
|
|
newline
|
|
bitfld.long 0x00 2. "TXRTSPOL,Transmitter request-to-send polarity" "0: Transmitter RTS is active low,1: Transmitter RTS is active high"
|
|
bitfld.long 0x00 1. "TXRTSE,Transmitter request-to-send enable" "0: The transmitter has no effect on RTS,1: When a character is placed into an empty.."
|
|
newline
|
|
bitfld.long 0x00 0. "TXCTSE,Transmitter clear-to-send enable" "0: CTS has no effect on the transmitter,1: Enables clear-to-send operation"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "FIFO,LPUART FIFO Register"
|
|
rbitfld.long 0x00 23. "TXEMPT,Transmit Buffer/FIFO Empty" "0: Transmit buffer is not empty,1: Transmit buffer is empty"
|
|
rbitfld.long 0x00 22. "RXEMPT,Receive Buffer/FIFO Empty" "0: Receive buffer is not empty,1: Receive buffer is empty"
|
|
newline
|
|
bitfld.long 0x00 17. "TXOF,Transmitter Buffer Overflow Flag" "0: No transmit buffer overflow has occurred..,1: At least one transmit buffer overflow has.."
|
|
bitfld.long 0x00 16. "RXUF,Receiver Buffer Underflow Flag" "0: No receive buffer underflow has occurred..,1: At least one receive buffer underflow has.."
|
|
newline
|
|
bitfld.long 0x00 15. "TXFLUSH,Transmit FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the transmit FIFO/Buffer is.."
|
|
bitfld.long 0x00 14. "RXFLUSH,Receive FIFO/Buffer Flush" "0: No flush operation occurs,1: All data in the receive FIFO/buffer is.."
|
|
newline
|
|
bitfld.long 0x00 10.--12. "RXIDEN,Receiver Idle Empty Enable" "0: Disable RDRF assertion due to partially..,1: Enable RDRF assertion due to partially filled..,2: Enable RDRF assertion due to partially filled..,3: Enable RDRF assertion due to partially filled..,4: Enable RDRF assertion due to partially filled..,5: Enable RDRF assertion due to partially filled..,6: Enable RDRF assertion due to partially filled..,7: Enable RDRF assertion due to partially filled.."
|
|
bitfld.long 0x00 9. "TXOFE,Transmit FIFO Overflow Interrupt Enable" "0: TXOF flag does not generate an interrupt to..,1: TXOF flag generates an interrupt to the host"
|
|
newline
|
|
bitfld.long 0x00 8. "RXUFE,Receive FIFO Underflow Interrupt Enable" "0: RXUF flag does not generate an interrupt to..,1: RXUF flag generates an interrupt to the host"
|
|
bitfld.long 0x00 7. "TXFE,Transmit FIFO Enable" "0: Transmit FIFO is not enabled,1: Transmit FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 4.--6. "TXFIFOSIZE,Transmit FIFO" "0: Transmit FIFO/Buffer depth = 1 dataword,1: Transmit FIFO/Buffer depth = 4 datawords,2: Transmit FIFO/Buffer depth = 8 datawords,3: Transmit FIFO/Buffer depth = 16 datawords,4: Transmit FIFO/Buffer depth = 32 datawords,5: Transmit FIFO/Buffer depth = 64 datawords,6: Transmit FIFO/Buffer depth = 128 datawords,7: Transmit FIFO/Buffer depth = 256 datawords"
|
|
bitfld.long 0x00 3. "RXFE,Receive FIFO Enable" "0: Receive FIFO is not enabled,1: Receive FIFO is enabled"
|
|
newline
|
|
rbitfld.long 0x00 0.--2. "RXFIFOSIZE,Receive FIFO" "0: Receive FIFO/Buffer depth = 1 dataword,1: Receive FIFO/Buffer depth = 4 datawords,2: Receive FIFO/Buffer depth = 8 datawords,3: Receive FIFO/Buffer depth = 16 datawords,4: Receive FIFO/Buffer depth = 32 datawords,5: Receive FIFO/Buffer depth = 64 datawords,6: Receive FIFO/Buffer depth = 128 datawords,7: Receive FIFO/Buffer depth = 256 datawords"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "WATER,LPUART Watermark Register"
|
|
rbitfld.long 0x00 24.--26. "RXCOUNT,Receive Counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--17. "RXWATER,Receive Watermark" "0,1,2,3"
|
|
newline
|
|
rbitfld.long 0x00 8.--10. "TXCOUNT,Transmit Counter" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--1. "TXWATER,Transmit Watermark" "0,1,2,3"
|
|
tree.end
|
|
endif
|
|
tree.end
|
|
tree "GPIO (General Purpose I/O Ports And Peripheral I/O Lines)"
|
|
tree "PTA"
|
|
base ad:0x400FF000
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR_SET/CLR,Port Data Output Register"
|
|
sif cpuis("S32K148*")
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. "PDO[31],Port data output bit 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. "[30],Port data output bit 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. "[29],Port data output bit 29" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. "[28],Port data output bit 28" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. "[27],Port data output bit 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. "[26],Port data output bit 26" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. "[25],Port data output bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. "[24],Port data output bit 24" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. "[23],Port data output bit 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. "[22],Port data output bit 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. "[21],Port data output bit 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. "[20],Port data output bit 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. "[19],Port data output bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. "[18],Port data output bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "[17],Port data output bit 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K146*")
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. "PDO[24],Port data output bit 24" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. "[23],Port data output bit 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. "[22],Port data output bit 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. "[21],Port data output bit 21" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. "[20],Port data output bit 20" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. "[19],Port data output bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. "[18],Port data output bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "[17],Port data output bit 17" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "PDO[17],Port data output bit 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K118*")
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "PDO[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "PDO[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
endif
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 31. "PTTO[31],Port toggle output bit 31" "No effect,Toggle"
|
|
bitfld.long 0x00 30. "[30],Port toggle output bit 30" "No effect,Toggle"
|
|
bitfld.long 0x00 29. "[29],Port toggle output bit 29" "No effect,Toggle"
|
|
bitfld.long 0x00 28. "[28],Port toggle output bit 28" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 27. "[27],Port toggle output bit 27" "No effect,Toggle"
|
|
bitfld.long 0x00 26. "[26],Port toggle output bit 26" "No effect,Toggle"
|
|
bitfld.long 0x00 25. "[25],Port toggle output bit 25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. "[24],Port toggle output bit 24" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port toggle output bit 23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. "[22],Port toggle output bit 22" "No effect,Toggle"
|
|
bitfld.long 0x00 21. "[21],Port toggle output bit 21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. "[20],Port toggle output bit 20" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port toggle output bit 19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. "[18],Port toggle output bit 18" "No effect,Toggle"
|
|
bitfld.long 0x00 17. "[17],Port toggle output bit 17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 24. "PTTO[24],Port toggle output bit 24" "No effect,Toggle"
|
|
bitfld.long 0x00 23. "[23],Port toggle output bit 23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. "[22],Port toggle output bit 22" "No effect,Toggle"
|
|
bitfld.long 0x00 21. "[21],Port toggle output bit 21" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. "[20],Port toggle output bit 20" "No effect,Toggle"
|
|
bitfld.long 0x00 19. "[19],Port toggle output bit 19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. "[18],Port toggle output bit 18" "No effect,Toggle"
|
|
bitfld.long 0x00 17. "[17],Port toggle output bit 17" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PTTO[17],Port toggle output bit 17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 11. "PTTO[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 10. "PTTO[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 31. "PDI[31],Port data input output bit 31" "Low,High"
|
|
bitfld.long 0x00 30. "[30],Port data input output bit 30" "Low,High"
|
|
bitfld.long 0x00 29. "[29],Port data input output bit 29" "Low,High"
|
|
bitfld.long 0x00 28. "[28],Port data input output bit 28" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. "[27],Port data input output bit 27" "Low,High"
|
|
bitfld.long 0x00 26. "[26],Port data input output bit 26" "Low,High"
|
|
bitfld.long 0x00 25. "[25],Port data input output bit 25" "Low,High"
|
|
bitfld.long 0x00 24. "[24],Port data input output bit 24" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port data input output bit 23" "Low,High"
|
|
bitfld.long 0x00 22. "[22],Port data input output bit 22" "Low,High"
|
|
bitfld.long 0x00 21. "[21],Port data input output bit 21" "Low,High"
|
|
bitfld.long 0x00 20. "[20],Port data input output bit 20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port data input output bit 19" "Low,High"
|
|
bitfld.long 0x00 18. "[18],Port data input output bit 18" "Low,High"
|
|
bitfld.long 0x00 17. "[17],Port data input output bit 17" "Low,High"
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 24. "PDI[24],Port data input output bit 24" "Low,High"
|
|
bitfld.long 0x00 23. "[23],Port data input output bit 23" "Low,High"
|
|
bitfld.long 0x00 22. "[22],Port data input output bit 22" "Low,High"
|
|
bitfld.long 0x00 21. "[21],Port data input output bit 21" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. "[20],Port data input output bit 20" "Low,High"
|
|
bitfld.long 0x00 19. "[19],Port data input output bit 19" "Low,High"
|
|
bitfld.long 0x00 18. "[18],Port data input output bit 18" "Low,High"
|
|
bitfld.long 0x00 17. "[17],Port data input output bit 17" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PDI[17],Port data input output bit 17" "Low,High"
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 11. "PDI[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
else
|
|
bitfld.long 0x00 10. "PDI[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
endif
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 31. "PDD[31],Port data direction bit 31" "Input,Output"
|
|
bitfld.long 0x00 30. "[30],Port data direction bit 30" "Input,Output"
|
|
bitfld.long 0x00 29. "[29],Port data direction bit 29" "Input,Output"
|
|
bitfld.long 0x00 28. "[28],Port data direction bit 28" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 27. "[27],Port data direction bit 27" "Input,Output"
|
|
bitfld.long 0x00 26. "[26],Port data direction bit 26" "Input,Output"
|
|
bitfld.long 0x00 25. "[25],Port data direction bit 25" "Input,Output"
|
|
bitfld.long 0x00 24. "[24],Port data direction bit 24" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port data direction bit 23" "Input,Output"
|
|
bitfld.long 0x00 22. "[22],Port data direction bit 22" "Input,Output"
|
|
bitfld.long 0x00 21. "[21],Port data direction bit 21" "Input,Output"
|
|
bitfld.long 0x00 20. "[20],Port data direction bit 20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port data direction bit 19" "Input,Output"
|
|
bitfld.long 0x00 18. "[18],Port data direction bit 18" "Input,Output"
|
|
bitfld.long 0x00 17. "[17],Port data direction bit 17" "Input,Output"
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 24. "PDD[24],Port data direction bit 24" "Input,Output"
|
|
bitfld.long 0x00 23. "[23],Port data direction bit 23" "Input,Output"
|
|
bitfld.long 0x00 22. "[22],Port data direction bit 22" "Input,Output"
|
|
bitfld.long 0x00 21. "[21],Port data direction bit 21" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. "[20],Port data direction bit 20" "Input,Output"
|
|
bitfld.long 0x00 19. "[19],Port data direction bit 19" "Input,Output"
|
|
bitfld.long 0x00 18. "[18],Port data direction bit 18" "Input,Output"
|
|
bitfld.long 0x00 17. "[17],Port data direction bit 17" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PDD[17],Port data direction bit 17" "Input,Output"
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 11. "PDD[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 10. "PDD[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
endif
|
|
line.long 0x04 "PIDR,Port Input Disable Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x04 31. "PID[31],Port input disable bit 31" "No,Yes"
|
|
bitfld.long 0x04 30. "[30],Port input disable bit 30" "No,Yes"
|
|
bitfld.long 0x04 29. "[29],Port input disable bit 29" "No,Yes"
|
|
bitfld.long 0x04 28. "[28],Port input disable bit 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 27. "[27],Port input disable bit 27" "No,Yes"
|
|
bitfld.long 0x04 26. "[26],Port input disable bit 26" "No,Yes"
|
|
bitfld.long 0x04 25. "[25],Port input disable bit 25" "No,Yes"
|
|
bitfld.long 0x04 24. "[24],Port input disable bit 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 23. "[23],Port input disable bit 23" "No,Yes"
|
|
bitfld.long 0x04 22. "[22],Port input disable bit 22" "No,Yes"
|
|
bitfld.long 0x04 21. "[21],Port input disable bit 21" "No,Yes"
|
|
bitfld.long 0x04 20. "[20],Port input disable bit 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. "[19],Port input disable bit 19" "No,Yes"
|
|
bitfld.long 0x04 18. "[18],Port input disable bit 18" "No,Yes"
|
|
bitfld.long 0x04 17. "[17],Port input disable bit 17" "No,Yes"
|
|
bitfld.long 0x04 16. "[16],Port input disable bit 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x04 24. "PID[24],Port input disable bit 24" "No,Yes"
|
|
bitfld.long 0x04 23. "[23],Port input disable bit 23" "No,Yes"
|
|
bitfld.long 0x04 22. "[22],Port input disable bit 22" "No,Yes"
|
|
bitfld.long 0x04 21. "[21],Port input disable bit 21" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 20. "[20],Port input disable bit 20" "No,Yes"
|
|
bitfld.long 0x04 19. "[19],Port input disable bit 19" "No,Yes"
|
|
bitfld.long 0x04 18. "[18],Port input disable bit 18" "No,Yes"
|
|
bitfld.long 0x04 17. "[17],Port input disable bit 17" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 16. "[16],Port input disable bit 16" "No,Yes"
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x04 17. "PID[17],Port input disable bit 17" "No,Yes"
|
|
bitfld.long 0x04 16. "[16],Port input disable bit 16" "No,Yes"
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x04 11. "PID[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
else
|
|
bitfld.long 0x04 10. "PID[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
endif
|
|
tree.end
|
|
tree "PTB"
|
|
base ad:0x400FF040
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR_SET/CLR,Port Data Output Register"
|
|
sif cpuis("S32K148*")
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. "PDO[31],Port data output bit 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. "[30],Port data output bit 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. "[29],Port data output bit 29" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. "[28],Port data output bit 28" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. "[27],Port data output bit 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. "[26],Port data output bit 26" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. "[25],Port data output bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. "[24],Port data output bit 24" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. "[23],Port data output bit 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. "[22],Port data output bit 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. "[21],Port data output bit 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. "[20],Port data output bit 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. "[19],Port data output bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. "[18],Port data output bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "[17],Port data output bit 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K146*")
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. "PDO[26],Port data output bit 26" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. "[25],Port data output bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. "[24],Port data output bit 24" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. "[23],Port data output bit 23" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. "[22],Port data output bit 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. "[21],Port data output bit 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. "[20],Port data output bit 20" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. "[19],Port data output bit 19" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. "[18],Port data output bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "[17],Port data output bit 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "PDO[17],Port data output bit 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K118*")
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "PDO[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "PDO[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
endif
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 31. "PTTO[31],Port toggle output bit 31" "No effect,Toggle"
|
|
bitfld.long 0x00 30. "[30],Port toggle output bit 30" "No effect,Toggle"
|
|
bitfld.long 0x00 29. "[29],Port toggle output bit 29" "No effect,Toggle"
|
|
bitfld.long 0x00 28. "[28],Port toggle output bit 28" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 27. "[27],Port toggle output bit 27" "No effect,Toggle"
|
|
bitfld.long 0x00 26. "[26],Port toggle output bit 26" "No effect,Toggle"
|
|
bitfld.long 0x00 25. "[25],Port toggle output bit 25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. "[24],Port toggle output bit 24" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port toggle output bit 23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. "[22],Port toggle output bit 22" "No effect,Toggle"
|
|
bitfld.long 0x00 21. "[21],Port toggle output bit 21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. "[20],Port toggle output bit 20" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port toggle output bit 19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. "[18],Port toggle output bit 18" "No effect,Toggle"
|
|
bitfld.long 0x00 17. "[17],Port toggle output bit 17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 26. "PTTO[26],Port toggle output bit 26" "No effect,Toggle"
|
|
bitfld.long 0x00 25. "[25],Port toggle output bit 25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. "[24],Port toggle output bit 24" "No effect,Toggle"
|
|
bitfld.long 0x00 23. "[23],Port toggle output bit 23" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. "[22],Port toggle output bit 22" "No effect,Toggle"
|
|
bitfld.long 0x00 21. "[21],Port toggle output bit 21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. "[20],Port toggle output bit 20" "No effect,Toggle"
|
|
bitfld.long 0x00 19. "[19],Port toggle output bit 19" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 18. "[18],Port toggle output bit 18" "No effect,Toggle"
|
|
bitfld.long 0x00 17. "[17],Port toggle output bit 17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PTTO[17],Port toggle output bit 17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 9. "PTTO[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 8. "PTTO[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 31. "PDI[31],Port data input output bit 31" "Low,High"
|
|
bitfld.long 0x00 30. "[30],Port data input output bit 30" "Low,High"
|
|
bitfld.long 0x00 29. "[29],Port data input output bit 29" "Low,High"
|
|
bitfld.long 0x00 28. "[28],Port data input output bit 28" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. "[27],Port data input output bit 27" "Low,High"
|
|
bitfld.long 0x00 26. "[26],Port data input output bit 26" "Low,High"
|
|
bitfld.long 0x00 25. "[25],Port data input output bit 25" "Low,High"
|
|
bitfld.long 0x00 24. "[24],Port data input output bit 24" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port data input output bit 23" "Low,High"
|
|
bitfld.long 0x00 22. "[22],Port data input output bit 22" "Low,High"
|
|
bitfld.long 0x00 21. "[21],Port data input output bit 21" "Low,High"
|
|
bitfld.long 0x00 20. "[20],Port data input output bit 20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port data input output bit 19" "Low,High"
|
|
bitfld.long 0x00 18. "[18],Port data input output bit 18" "Low,High"
|
|
bitfld.long 0x00 17. "[17],Port data input output bit 17" "Low,High"
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 26. "PDI[26],Port data input output bit 26" "Low,High"
|
|
bitfld.long 0x00 25. "[25],Port data input output bit 25" "Low,High"
|
|
bitfld.long 0x00 24. "[24],Port data input output bit 24" "Low,High"
|
|
bitfld.long 0x00 23. "[23],Port data input output bit 23" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. "[22],Port data input output bit 22" "Low,High"
|
|
bitfld.long 0x00 21. "[21],Port data input output bit 21" "Low,High"
|
|
bitfld.long 0x00 20. "[20],Port data input output bit 20" "Low,High"
|
|
bitfld.long 0x00 19. "[19],Port data input output bit 19" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. "[18],Port data input output bit 18" "Low,High"
|
|
bitfld.long 0x00 17. "[17],Port data input output bit 17" "Low,High"
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PDI[17],Port data input output bit 17" "Low,High"
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 9. "PDI[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
else
|
|
bitfld.long 0x00 8. "PDI[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
endif
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 31. "PDD[31],Port data direction bit 31" "Input,Output"
|
|
bitfld.long 0x00 30. "[30],Port data direction bit 30" "Input,Output"
|
|
bitfld.long 0x00 29. "[29],Port data direction bit 29" "Input,Output"
|
|
bitfld.long 0x00 28. "[28],Port data direction bit 28" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 27. "[27],Port data direction bit 27" "Input,Output"
|
|
bitfld.long 0x00 26. "[26],Port data direction bit 26" "Input,Output"
|
|
bitfld.long 0x00 25. "[25],Port data direction bit 25" "Input,Output"
|
|
bitfld.long 0x00 24. "[24],Port data direction bit 24" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port data direction bit 23" "Input,Output"
|
|
bitfld.long 0x00 22. "[22],Port data direction bit 22" "Input,Output"
|
|
bitfld.long 0x00 21. "[21],Port data direction bit 21" "Input,Output"
|
|
bitfld.long 0x00 20. "[20],Port data direction bit 20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port data direction bit 19" "Input,Output"
|
|
bitfld.long 0x00 18. "[18],Port data direction bit 18" "Input,Output"
|
|
bitfld.long 0x00 17. "[17],Port data direction bit 17" "Input,Output"
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 26. "PDD[26],Port data direction bit 26" "Input,Output"
|
|
bitfld.long 0x00 25. "[25],Port data direction bit 25" "Input,Output"
|
|
bitfld.long 0x00 24. "[24],Port data direction bit 24" "Input,Output"
|
|
bitfld.long 0x00 23. "[23],Port data direction bit 23" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. "[22],Port data direction bit 22" "Input,Output"
|
|
bitfld.long 0x00 21. "[21],Port data direction bit 21" "Input,Output"
|
|
bitfld.long 0x00 20. "[20],Port data direction bit 20" "Input,Output"
|
|
bitfld.long 0x00 19. "[19],Port data direction bit 19" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 18. "[18],Port data direction bit 18" "Input,Output"
|
|
bitfld.long 0x00 17. "[17],Port data direction bit 17" "Input,Output"
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PDD[17],Port data direction bit 17" "Input,Output"
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 9. "PDD[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 8. "PDD[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
endif
|
|
line.long 0x04 "PIDR,Port Input Disable Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x04 31. "PID[31],Port input disable bit 31" "No,Yes"
|
|
bitfld.long 0x04 30. "[30],Port input disable bit 30" "No,Yes"
|
|
bitfld.long 0x04 29. "[29],Port input disable bit 29" "No,Yes"
|
|
bitfld.long 0x04 28. "[28],Port input disable bit 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 27. "[27],Port input disable bit 27" "No,Yes"
|
|
bitfld.long 0x04 26. "[26],Port input disable bit 26" "No,Yes"
|
|
bitfld.long 0x04 25. "[25],Port input disable bit 25" "No,Yes"
|
|
bitfld.long 0x04 24. "[24],Port input disable bit 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 23. "[23],Port input disable bit 23" "No,Yes"
|
|
bitfld.long 0x04 22. "[22],Port input disable bit 22" "No,Yes"
|
|
bitfld.long 0x04 21. "[21],Port input disable bit 21" "No,Yes"
|
|
bitfld.long 0x04 20. "[20],Port input disable bit 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. "[19],Port input disable bit 19" "No,Yes"
|
|
bitfld.long 0x04 18. "[18],Port input disable bit 18" "No,Yes"
|
|
bitfld.long 0x04 17. "[17],Port input disable bit 17" "No,Yes"
|
|
bitfld.long 0x04 16. "[16],Port input disable bit 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x04 26. "PID[26],Port input disable bit 26" "No,Yes"
|
|
bitfld.long 0x04 25. "[25],Port input disable bit 25" "No,Yes"
|
|
bitfld.long 0x04 24. "[24],Port input disable bit 24" "No,Yes"
|
|
bitfld.long 0x04 23. "[23],Port input disable bit 23" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 22. "[22],Port input disable bit 22" "No,Yes"
|
|
bitfld.long 0x04 21. "[21],Port input disable bit 21" "No,Yes"
|
|
bitfld.long 0x04 20. "[20],Port input disable bit 20" "No,Yes"
|
|
bitfld.long 0x04 19. "[19],Port input disable bit 19" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 18. "[18],Port input disable bit 18" "No,Yes"
|
|
bitfld.long 0x04 17. "[17],Port input disable bit 17" "No,Yes"
|
|
bitfld.long 0x04 16. "[16],Port input disable bit 16" "No,Yes"
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x04 17. "PID[17],Port input disable bit 17" "No,Yes"
|
|
bitfld.long 0x04 16. "[16],Port input disable bit 16" "No,Yes"
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x04 9. "PID[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
else
|
|
bitfld.long 0x04 8. "PID[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
endif
|
|
tree.end
|
|
tree "PTC"
|
|
base ad:0x400FF080
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR_SET/CLR,Port Data Output Register"
|
|
sif cpuis("S32K148*")
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. "PDO[31],Port data output bit 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. "[30],Port data output bit 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. "[29],Port data output bit 29" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. "[28],Port data output bit 28" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. "[27],Port data output bit 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. "[26],Port data output bit 26" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. "[25],Port data output bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. "[24],Port data output bit 24" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. "[23],Port data output bit 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. "[22],Port data output bit 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. "[21],Port data output bit 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. "[20],Port data output bit 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. "[19],Port data output bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. "[18],Port data output bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "[17],Port data output bit 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K146*")
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. "PDO[24],Port data output bit 24" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. "[23],Port data output bit 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. "[22],Port data output bit 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. "[21],Port data output bit 21" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. "[20],Port data output bit 20" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. "[19],Port data output bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. "[18],Port data output bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "[17],Port data output bit 17" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "PDO[17],Port data output bit 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K118*")
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "PDO[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "PDO[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
endif
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 31. "PTTO[31],Port toggle output bit 31" "No effect,Toggle"
|
|
bitfld.long 0x00 30. "[30],Port toggle output bit 30" "No effect,Toggle"
|
|
bitfld.long 0x00 29. "[29],Port toggle output bit 29" "No effect,Toggle"
|
|
bitfld.long 0x00 28. "[28],Port toggle output bit 28" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 27. "[27],Port toggle output bit 27" "No effect,Toggle"
|
|
bitfld.long 0x00 26. "[26],Port toggle output bit 26" "No effect,Toggle"
|
|
bitfld.long 0x00 25. "[25],Port toggle output bit 25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. "[24],Port toggle output bit 24" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port toggle output bit 23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. "[22],Port toggle output bit 22" "No effect,Toggle"
|
|
bitfld.long 0x00 21. "[21],Port toggle output bit 21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. "[20],Port toggle output bit 20" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port toggle output bit 19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. "[18],Port toggle output bit 18" "No effect,Toggle"
|
|
bitfld.long 0x00 17. "[17],Port toggle output bit 17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 24. "PTTO[24],Port toggle output bit 24" "No effect,Toggle"
|
|
bitfld.long 0x00 23. "[23],Port toggle output bit 23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. "[22],Port toggle output bit 22" "No effect,Toggle"
|
|
bitfld.long 0x00 21. "[21],Port toggle output bit 21" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 20. "[20],Port toggle output bit 20" "No effect,Toggle"
|
|
bitfld.long 0x00 19. "[19],Port toggle output bit 19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. "[18],Port toggle output bit 18" "No effect,Toggle"
|
|
bitfld.long 0x00 17. "[17],Port toggle output bit 17" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PTTO[17],Port toggle output bit 17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 13. "PTTO[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 11. "PTTO[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 31. "PDI[31],Port data input output bit 31" "Low,High"
|
|
bitfld.long 0x00 30. "[30],Port data input output bit 30" "Low,High"
|
|
bitfld.long 0x00 29. "[29],Port data input output bit 29" "Low,High"
|
|
bitfld.long 0x00 28. "[28],Port data input output bit 28" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. "[27],Port data input output bit 27" "Low,High"
|
|
bitfld.long 0x00 26. "[26],Port data input output bit 26" "Low,High"
|
|
bitfld.long 0x00 25. "[25],Port data input output bit 25" "Low,High"
|
|
bitfld.long 0x00 24. "[24],Port data input output bit 24" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port data input output bit 23" "Low,High"
|
|
bitfld.long 0x00 22. "[22],Port data input output bit 22" "Low,High"
|
|
bitfld.long 0x00 21. "[21],Port data input output bit 21" "Low,High"
|
|
bitfld.long 0x00 20. "[20],Port data input output bit 20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port data input output bit 19" "Low,High"
|
|
bitfld.long 0x00 18. "[18],Port data input output bit 18" "Low,High"
|
|
bitfld.long 0x00 17. "[17],Port data input output bit 17" "Low,High"
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 24. "PDI[24],Port data input output bit 24" "Low,High"
|
|
bitfld.long 0x00 23. "[23],Port data input output bit 23" "Low,High"
|
|
bitfld.long 0x00 22. "[22],Port data input output bit 22" "Low,High"
|
|
bitfld.long 0x00 21. "[21],Port data input output bit 21" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 20. "[20],Port data input output bit 20" "Low,High"
|
|
bitfld.long 0x00 19. "[19],Port data input output bit 19" "Low,High"
|
|
bitfld.long 0x00 18. "[18],Port data input output bit 18" "Low,High"
|
|
bitfld.long 0x00 17. "[17],Port data input output bit 17" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PDI[17],Port data input output bit 17" "Low,High"
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 13. "PDI[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
else
|
|
bitfld.long 0x00 11. "PDI[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
endif
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 31. "PDD[31],Port data direction bit 31" "Input,Output"
|
|
bitfld.long 0x00 30. "[30],Port data direction bit 30" "Input,Output"
|
|
bitfld.long 0x00 29. "[29],Port data direction bit 29" "Input,Output"
|
|
bitfld.long 0x00 28. "[28],Port data direction bit 28" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 27. "[27],Port data direction bit 27" "Input,Output"
|
|
bitfld.long 0x00 26. "[26],Port data direction bit 26" "Input,Output"
|
|
bitfld.long 0x00 25. "[25],Port data direction bit 25" "Input,Output"
|
|
bitfld.long 0x00 24. "[24],Port data direction bit 24" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port data direction bit 23" "Input,Output"
|
|
bitfld.long 0x00 22. "[22],Port data direction bit 22" "Input,Output"
|
|
bitfld.long 0x00 21. "[21],Port data direction bit 21" "Input,Output"
|
|
bitfld.long 0x00 20. "[20],Port data direction bit 20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port data direction bit 19" "Input,Output"
|
|
bitfld.long 0x00 18. "[18],Port data direction bit 18" "Input,Output"
|
|
bitfld.long 0x00 17. "[17],Port data direction bit 17" "Input,Output"
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 24. "PDD[24],Port data direction bit 24" "Input,Output"
|
|
bitfld.long 0x00 23. "[23],Port data direction bit 23" "Input,Output"
|
|
bitfld.long 0x00 22. "[22],Port data direction bit 22" "Input,Output"
|
|
bitfld.long 0x00 21. "[21],Port data direction bit 21" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 20. "[20],Port data direction bit 20" "Input,Output"
|
|
bitfld.long 0x00 19. "[19],Port data direction bit 19" "Input,Output"
|
|
bitfld.long 0x00 18. "[18],Port data direction bit 18" "Input,Output"
|
|
bitfld.long 0x00 17. "[17],Port data direction bit 17" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PDD[17],Port data direction bit 17" "Input,Output"
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 13. "PDD[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 11. "PDD[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
endif
|
|
line.long 0x04 "PIDR,Port Input Disable Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x04 31. "PID[31],Port input disable bit 31" "No,Yes"
|
|
bitfld.long 0x04 30. "[30],Port input disable bit 30" "No,Yes"
|
|
bitfld.long 0x04 29. "[29],Port input disable bit 29" "No,Yes"
|
|
bitfld.long 0x04 28. "[28],Port input disable bit 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 27. "[27],Port input disable bit 27" "No,Yes"
|
|
bitfld.long 0x04 26. "[26],Port input disable bit 26" "No,Yes"
|
|
bitfld.long 0x04 25. "[25],Port input disable bit 25" "No,Yes"
|
|
bitfld.long 0x04 24. "[24],Port input disable bit 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 23. "[23],Port input disable bit 23" "No,Yes"
|
|
bitfld.long 0x04 22. "[22],Port input disable bit 22" "No,Yes"
|
|
bitfld.long 0x04 21. "[21],Port input disable bit 21" "No,Yes"
|
|
bitfld.long 0x04 20. "[20],Port input disable bit 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. "[19],Port input disable bit 19" "No,Yes"
|
|
bitfld.long 0x04 18. "[18],Port input disable bit 18" "No,Yes"
|
|
bitfld.long 0x04 17. "[17],Port input disable bit 17" "No,Yes"
|
|
bitfld.long 0x04 16. "[16],Port input disable bit 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 24. "PID[24],Port input disable bit 24" "No,Yes"
|
|
bitfld.long 0x00 23. "[23],Port input disable bit 23" "No,Yes"
|
|
bitfld.long 0x00 22. "[22],Port input disable bit 22" "No,Yes"
|
|
bitfld.long 0x00 21. "[21],Port input disable bit 21" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 20. "[20],Port input disable bit 20" "No,Yes"
|
|
bitfld.long 0x00 19. "[19],Port input disable bit 19" "No,Yes"
|
|
bitfld.long 0x00 18. "[18],Port input disable bit 18" "No,Yes"
|
|
bitfld.long 0x00 17. "[17],Port input disable bit 17" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 16. "[16],Port input disable bit 16" "No,Yes"
|
|
bitfld.long 0x00 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x00 14. "[14],Port input disable bit 14" "No,Yes"
|
|
bitfld.long 0x00 13. "[13],Port input disable bit 13" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 12. "[12],Port input disable bit 12" "No,Yes"
|
|
bitfld.long 0x00 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x00 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x00 9. "[9],Port input disable bit 9" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x00 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x00 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x00 5. "[5],Port input disable bit 5" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x00 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x00 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x00 1. "[1],Port input disable bit 1" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PID[17],Port input disable bit 17" "No,Yes"
|
|
bitfld.long 0x00 16. "[16],Port input disable bit 16" "No,Yes"
|
|
bitfld.long 0x00 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x00 14. "[14],Port input disable bit 14" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x00 12. "[12],Port input disable bit 12" "No,Yes"
|
|
bitfld.long 0x00 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x00 10. "[10],Port input disable bit 10" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x00 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x00 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x00 6. "[6],Port input disable bit 6" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x00 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x00 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x00 2. "[2],Port input disable bit 2" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x00 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 13. "PID[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x00 12. "[12],Port input disable bit 12" "No,Yes"
|
|
bitfld.long 0x00 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x00 10. "[10],Port input disable bit 10" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x00 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x00 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x00 6. "[6],Port input disable bit 6" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x00 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x00 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x00 2. "[2],Port input disable bit 2" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x00 0. "[0],Port input disable bit 0" "No,Yes"
|
|
else
|
|
bitfld.long 0x00 11. "PID[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x00 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x00 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x00 8. "[8],Port input disable bit 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x00 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x00 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x00 4. "[4],Port input disable bit 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x00 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x00 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x00 0. "[0],Port input disable bit 0" "No,Yes"
|
|
endif
|
|
tree.end
|
|
tree "PTD"
|
|
base ad:0x400FF0C0
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR_SET/CLR,Port Data Output Register"
|
|
sif cpuis("S32K148*")
|
|
setclrfld.long 0x00 31. 0x04 31. 0x08 31. "PDO[31],Port data output bit 31" "Low,High"
|
|
setclrfld.long 0x00 30. 0x04 30. 0x08 30. "[30],Port data output bit 30" "Low,High"
|
|
setclrfld.long 0x00 29. 0x04 29. 0x08 29. "[29],Port data output bit 29" "Low,High"
|
|
setclrfld.long 0x00 28. 0x04 28. 0x08 28. "[28],Port data output bit 28" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. "[27],Port data output bit 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. "[26],Port data output bit 26" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. "[25],Port data output bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. "[24],Port data output bit 24" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. "[23],Port data output bit 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. "[22],Port data output bit 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. "[21],Port data output bit 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. "[20],Port data output bit 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. "[19],Port data output bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. "[18],Port data output bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "[17],Port data output bit 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K146*")
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. "PDO[26],Port data output bit 26" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. "[25],Port data output bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. "[24],Port data output bit 24" "Low,High"
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. "[23],Port data output bit 23" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. "[22],Port data output bit 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. "[21],Port data output bit 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. "[20],Port data output bit 20" "Low,High"
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. "[19],Port data output bit 19" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. "[18],Port data output bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "[17],Port data output bit 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "PDO[17],Port data output bit 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K118*")
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "PDO[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "PDO[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
endif
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 31. "PTTO[31],Port toggle output bit 31" "No effect,Toggle"
|
|
bitfld.long 0x00 30. "[30],Port toggle output bit 30" "No effect,Toggle"
|
|
bitfld.long 0x00 29. "[29],Port toggle output bit 29" "No effect,Toggle"
|
|
bitfld.long 0x00 28. "[28],Port toggle output bit 28" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 27. "[27],Port toggle output bit 27" "No effect,Toggle"
|
|
bitfld.long 0x00 26. "[26],Port toggle output bit 26" "No effect,Toggle"
|
|
bitfld.long 0x00 25. "[25],Port toggle output bit 25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. "[24],Port toggle output bit 24" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port toggle output bit 23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. "[22],Port toggle output bit 22" "No effect,Toggle"
|
|
bitfld.long 0x00 21. "[21],Port toggle output bit 21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. "[20],Port toggle output bit 20" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port toggle output bit 19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. "[18],Port toggle output bit 18" "No effect,Toggle"
|
|
bitfld.long 0x00 17. "[17],Port toggle output bit 17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 26. "PTTO[26],Port toggle output bit 26" "No effect,Toggle"
|
|
bitfld.long 0x00 25. "[25],Port toggle output bit 25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. "[24],Port toggle output bit 24" "No effect,Toggle"
|
|
bitfld.long 0x00 23. "[23],Port toggle output bit 23" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 22. "[22],Port toggle output bit 22" "No effect,Toggle"
|
|
bitfld.long 0x00 21. "[21],Port toggle output bit 21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. "[20],Port toggle output bit 20" "No effect,Toggle"
|
|
bitfld.long 0x00 19. "[19],Port toggle output bit 19" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 18. "[18],Port toggle output bit 18" "No effect,Toggle"
|
|
bitfld.long 0x00 17. "[17],Port toggle output bit 17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PTTO[17],Port toggle output bit 17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 9. "PTTO[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 6. "PTTO[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 31. "PDI[31],Port data input output bit 31" "Low,High"
|
|
bitfld.long 0x00 30. "[30],Port data input output bit 30" "Low,High"
|
|
bitfld.long 0x00 29. "[29],Port data input output bit 29" "Low,High"
|
|
bitfld.long 0x00 28. "[28],Port data input output bit 28" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 27. "[27],Port data input output bit 27" "Low,High"
|
|
bitfld.long 0x00 26. "[26],Port data input output bit 26" "Low,High"
|
|
bitfld.long 0x00 25. "[25],Port data input output bit 25" "Low,High"
|
|
bitfld.long 0x00 24. "[24],Port data input output bit 24" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port data input output bit 23" "Low,High"
|
|
bitfld.long 0x00 22. "[22],Port data input output bit 22" "Low,High"
|
|
bitfld.long 0x00 21. "[21],Port data input output bit 21" "Low,High"
|
|
bitfld.long 0x00 20. "[20],Port data input output bit 20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port data input output bit 19" "Low,High"
|
|
bitfld.long 0x00 18. "[18],Port data input output bit 18" "Low,High"
|
|
bitfld.long 0x00 17. "[17],Port data input output bit 17" "Low,High"
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 26. "PDI[26],Port data input output bit 26" "Low,High"
|
|
bitfld.long 0x00 25. "[25],Port data input output bit 25" "Low,High"
|
|
bitfld.long 0x00 24. "[24],Port data input output bit 24" "Low,High"
|
|
bitfld.long 0x00 23. "[23],Port data input output bit 23" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 22. "[22],Port data input output bit 22" "Low,High"
|
|
bitfld.long 0x00 21. "[21],Port data input output bit 21" "Low,High"
|
|
bitfld.long 0x00 20. "[20],Port data input output bit 20" "Low,High"
|
|
bitfld.long 0x00 19. "[19],Port data input output bit 19" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 18. "[18],Port data input output bit 18" "Low,High"
|
|
bitfld.long 0x00 17. "[17],Port data input output bit 17" "Low,High"
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PDI[17],Port data input output bit 17" "Low,High"
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 9. "PDI[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
else
|
|
bitfld.long 0x00 6. "PDI[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
endif
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 31. "PDD[31],Port data direction bit 31" "Input,Output"
|
|
bitfld.long 0x00 30. "[30],Port data direction bit 30" "Input,Output"
|
|
bitfld.long 0x00 29. "[29],Port data direction bit 29" "Input,Output"
|
|
bitfld.long 0x00 28. "[28],Port data direction bit 28" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 27. "[27],Port data direction bit 27" "Input,Output"
|
|
bitfld.long 0x00 26. "[26],Port data direction bit 26" "Input,Output"
|
|
bitfld.long 0x00 25. "[25],Port data direction bit 25" "Input,Output"
|
|
bitfld.long 0x00 24. "[24],Port data direction bit 24" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port data direction bit 23" "Input,Output"
|
|
bitfld.long 0x00 22. "[22],Port data direction bit 22" "Input,Output"
|
|
bitfld.long 0x00 21. "[21],Port data direction bit 21" "Input,Output"
|
|
bitfld.long 0x00 20. "[20],Port data direction bit 20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port data direction bit 19" "Input,Output"
|
|
bitfld.long 0x00 18. "[18],Port data direction bit 18" "Input,Output"
|
|
bitfld.long 0x00 17. "[17],Port data direction bit 17" "Input,Output"
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 26. "PDD[26],Port data direction bit 26" "Input,Output"
|
|
bitfld.long 0x00 25. "[25],Port data direction bit 25" "Input,Output"
|
|
bitfld.long 0x00 24. "[24],Port data direction bit 24" "Input,Output"
|
|
bitfld.long 0x00 23. "[23],Port data direction bit 23" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 22. "[22],Port data direction bit 22" "Input,Output"
|
|
bitfld.long 0x00 21. "[21],Port data direction bit 21" "Input,Output"
|
|
bitfld.long 0x00 20. "[20],Port data direction bit 20" "Input,Output"
|
|
bitfld.long 0x00 19. "[19],Port data direction bit 19" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 18. "[18],Port data direction bit 18" "Input,Output"
|
|
bitfld.long 0x00 17. "[17],Port data direction bit 17" "Input,Output"
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 17. "PDD[17],Port data direction bit 17" "Input,Output"
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 9. "PDD[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 6. "PDD[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
endif
|
|
line.long 0x04 "PIDR,Port Input Disable Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x04 31. "PID[31],Port input disable bit 31" "No,Yes"
|
|
bitfld.long 0x04 30. "[30],Port input disable bit 30" "No,Yes"
|
|
bitfld.long 0x04 29. "[29],Port input disable bit 29" "No,Yes"
|
|
bitfld.long 0x04 28. "[28],Port input disable bit 28" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 27. "[27],Port input disable bit 27" "No,Yes"
|
|
bitfld.long 0x04 26. "[26],Port input disable bit 26" "No,Yes"
|
|
bitfld.long 0x04 25. "[25],Port input disable bit 25" "No,Yes"
|
|
bitfld.long 0x04 24. "[24],Port input disable bit 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 23. "[23],Port input disable bit 23" "No,Yes"
|
|
bitfld.long 0x04 22. "[22],Port input disable bit 22" "No,Yes"
|
|
bitfld.long 0x04 21. "[21],Port input disable bit 21" "No,Yes"
|
|
bitfld.long 0x04 20. "[20],Port input disable bit 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. "[19],Port input disable bit 19" "No,Yes"
|
|
bitfld.long 0x04 18. "[18],Port input disable bit 18" "No,Yes"
|
|
bitfld.long 0x04 17. "[17],Port input disable bit 17" "No,Yes"
|
|
bitfld.long 0x04 16. "[16],Port input disable bit 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x04 26. "PID[26],Port input disable bit 26" "No,Yes"
|
|
bitfld.long 0x04 25. "[25],Port input disable bit 25" "No,Yes"
|
|
bitfld.long 0x04 24. "[24],Port input disable bit 24" "No,Yes"
|
|
bitfld.long 0x04 23. "[23],Port input disable bit 23" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 22. "[22],Port input disable bit 22" "No,Yes"
|
|
bitfld.long 0x04 21. "[21],Port input disable bit 21" "No,Yes"
|
|
bitfld.long 0x04 20. "[20],Port input disable bit 20" "No,Yes"
|
|
bitfld.long 0x04 19. "[19],Port input disable bit 19" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 18. "[18],Port input disable bit 18" "No,Yes"
|
|
bitfld.long 0x04 17. "[17],Port input disable bit 17" "No,Yes"
|
|
bitfld.long 0x04 16. "[16],Port input disable bit 16" "No,Yes"
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x04 17. "PID[17],Port input disable bit 17" "No,Yes"
|
|
bitfld.long 0x04 16. "[16],Port input disable bit 16" "No,Yes"
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x04 9. "PID[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
else
|
|
bitfld.long 0x04 6. "PID[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
endif
|
|
tree.end
|
|
tree "PTE"
|
|
base ad:0x400FF100
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PDOR_SET/CLR,Port Data Output Register"
|
|
sif cpuis("S32K148*")
|
|
setclrfld.long 0x00 27. 0x04 27. 0x08 27. "PDO[27],Port data output bit 27" "Low,High"
|
|
setclrfld.long 0x00 26. 0x04 26. 0x08 26. "[26],Port data output bit 26" "Low,High"
|
|
setclrfld.long 0x00 25. 0x04 25. 0x08 25. "[25],Port data output bit 25" "Low,High"
|
|
setclrfld.long 0x00 24. 0x04 24. 0x08 24. "[24],Port data output bit 24" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. "[23],Port data output bit 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. "[22],Port data output bit 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. "[21],Port data output bit 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. "[20],Port data output bit 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. "[19],Port data output bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. "[18],Port data output bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "[17],Port data output bit 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K146*")
|
|
setclrfld.long 0x00 23. 0x04 23. 0x08 23. "PDO[23],Port data output bit 23" "Low,High"
|
|
setclrfld.long 0x00 22. 0x04 22. 0x08 22. "[22],Port data output bit 22" "Low,High"
|
|
setclrfld.long 0x00 21. 0x04 21. 0x08 21. "[21],Port data output bit 21" "Low,High"
|
|
setclrfld.long 0x00 20. 0x04 20. 0x08 20. "[20],Port data output bit 20" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 19. 0x04 19. 0x08 19. "[19],Port data output bit 19" "Low,High"
|
|
setclrfld.long 0x00 18. 0x04 18. 0x08 18. "[18],Port data output bit 18" "Low,High"
|
|
setclrfld.long 0x00 17. 0x04 17. 0x08 17. "[17],Port data output bit 17" "Low,High"
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "[16],Port data output bit 16" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
setclrfld.long 0x00 16. 0x04 16. 0x08 16. "PDO[16],Port data output bit 16" "Low,High"
|
|
setclrfld.long 0x00 15. 0x04 15. 0x08 15. "[15],Port data output bit 15" "Low,High"
|
|
setclrfld.long 0x00 14. 0x04 14. 0x08 14. "[14],Port data output bit 14" "Low,High"
|
|
setclrfld.long 0x00 13. 0x04 13. 0x08 13. "[13],Port data output bit 13" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 12. 0x04 12. 0x08 12. "[12],Port data output bit 12" "Low,High"
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
elif cpuis("S32K118*")
|
|
setclrfld.long 0x00 11. 0x04 11. 0x08 11. "PDO[11],Port data output bit 11" "Low,High"
|
|
setclrfld.long 0x00 10. 0x04 10. 0x08 10. "[10],Port data output bit 10" "Low,High"
|
|
setclrfld.long 0x00 9. 0x04 9. 0x08 9. "[9],Port data output bit 9" "Low,High"
|
|
setclrfld.long 0x00 8. 0x04 8. 0x08 8. "[8],Port data output bit 8" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 7. 0x04 7. 0x08 7. "[7],Port data output bit 7" "Low,High"
|
|
setclrfld.long 0x00 6. 0x04 6. 0x08 6. "[6],Port data output bit 6" "Low,High"
|
|
setclrfld.long 0x00 5. 0x04 5. 0x08 5. "[5],Port data output bit 5" "Low,High"
|
|
setclrfld.long 0x00 4. 0x04 4. 0x08 4. "[4],Port data output bit 4" "Low,High"
|
|
newline
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
else
|
|
setclrfld.long 0x00 3. 0x04 3. 0x08 3. "PDO[3],Port data output bit 3" "Low,High"
|
|
setclrfld.long 0x00 2. 0x04 2. 0x08 2. "[2],Port data output bit 2" "Low,High"
|
|
setclrfld.long 0x00 1. 0x04 1. 0x08 1. "[1],Port data output bit 1" "Low,High"
|
|
setclrfld.long 0x00 0. 0x04 0. 0x08 0. "[0],Port data output bit 0" "Low,High"
|
|
endif
|
|
wgroup.long 0x0C++0x03
|
|
line.long 0x00 "PTOR,Port Toggle Output Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 27. "PTTO[27],Port toggle output bit 27" "No effect,Toggle"
|
|
bitfld.long 0x00 26. "[26],Port toggle output bit 26" "No effect,Toggle"
|
|
bitfld.long 0x00 25. "[25],Port toggle output bit 25" "No effect,Toggle"
|
|
bitfld.long 0x00 24. "[24],Port toggle output bit 24" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port toggle output bit 23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. "[22],Port toggle output bit 22" "No effect,Toggle"
|
|
bitfld.long 0x00 21. "[21],Port toggle output bit 21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. "[20],Port toggle output bit 20" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port toggle output bit 19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. "[18],Port toggle output bit 18" "No effect,Toggle"
|
|
bitfld.long 0x00 17. "[17],Port toggle output bit 17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 23. "PTTO[23],Port toggle output bit 23" "No effect,Toggle"
|
|
bitfld.long 0x00 22. "[22],Port toggle output bit 22" "No effect,Toggle"
|
|
bitfld.long 0x00 21. "[21],Port toggle output bit 21" "No effect,Toggle"
|
|
bitfld.long 0x00 20. "[20],Port toggle output bit 20" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port toggle output bit 19" "No effect,Toggle"
|
|
bitfld.long 0x00 18. "[18],Port toggle output bit 18" "No effect,Toggle"
|
|
bitfld.long 0x00 17. "[17],Port toggle output bit 17" "No effect,Toggle"
|
|
bitfld.long 0x00 16. "[16],Port toggle output bit 16" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 16. "PTTO[16],Port toggle output bit 16" "No effect,Toggle"
|
|
bitfld.long 0x00 15. "[15],Port toggle output bit 15" "No effect,Toggle"
|
|
bitfld.long 0x00 14. "[14],Port toggle output bit 14" "No effect,Toggle"
|
|
bitfld.long 0x00 13. "[13],Port toggle output bit 13" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 12. "[12],Port toggle output bit 12" "No effect,Toggle"
|
|
bitfld.long 0x00 11. "[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 11. "PTTO[11],Port toggle output bit 11" "No effect,Toggle"
|
|
bitfld.long 0x00 10. "[10],Port toggle output bit 10" "No effect,Toggle"
|
|
bitfld.long 0x00 9. "[9],Port toggle output bit 9" "No effect,Toggle"
|
|
bitfld.long 0x00 8. "[8],Port toggle output bit 8" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port toggle output bit 7" "No effect,Toggle"
|
|
bitfld.long 0x00 6. "[6],Port toggle output bit 6" "No effect,Toggle"
|
|
bitfld.long 0x00 5. "[5],Port toggle output bit 5" "No effect,Toggle"
|
|
bitfld.long 0x00 4. "[4],Port toggle output bit 4" "No effect,Toggle"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
else
|
|
bitfld.long 0x00 3. "PTTO[3],Port toggle output bit 3" "No effect,Toggle"
|
|
bitfld.long 0x00 2. "[2],Port toggle output bit 2" "No effect,Toggle"
|
|
bitfld.long 0x00 1. "[1],Port toggle output bit 1" "No effect,Toggle"
|
|
bitfld.long 0x00 0. "[0],Port toggle output bit 0" "No effect,Toggle"
|
|
endif
|
|
rgroup.long 0x10++0x03
|
|
line.long 0x00 "PDIR,Port Data Input Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 27. "PDI[27],Port data input output bit 27" "Low,High"
|
|
bitfld.long 0x00 26. "[26],Port data input output bit 26" "Low,High"
|
|
bitfld.long 0x00 25. "[25],Port data input output bit 25" "Low,High"
|
|
bitfld.long 0x00 24. "[24],Port data input output bit 24" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port data input output bit 23" "Low,High"
|
|
bitfld.long 0x00 22. "[22],Port data input output bit 22" "Low,High"
|
|
bitfld.long 0x00 21. "[21],Port data input output bit 21" "Low,High"
|
|
bitfld.long 0x00 20. "[20],Port data input output bit 20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port data input output bit 19" "Low,High"
|
|
bitfld.long 0x00 18. "[18],Port data input output bit 18" "Low,High"
|
|
bitfld.long 0x00 17. "[17],Port data input output bit 17" "Low,High"
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 23. "PDI[23],Port data input output bit 23" "Low,High"
|
|
bitfld.long 0x00 22. "[22],Port data input output bit 22" "Low,High"
|
|
bitfld.long 0x00 21. "[21],Port data input output bit 21" "Low,High"
|
|
bitfld.long 0x00 20. "[20],Port data input output bit 20" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port data input output bit 19" "Low,High"
|
|
bitfld.long 0x00 18. "[18],Port data input output bit 18" "Low,High"
|
|
bitfld.long 0x00 17. "[17],Port data input output bit 17" "Low,High"
|
|
bitfld.long 0x00 16. "[16],Port data input output bit 16" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 16. "PDI[16],Port data input output bit 16" "Low,High"
|
|
bitfld.long 0x00 15. "[15],Port data input output bit 15" "Low,High"
|
|
bitfld.long 0x00 14. "[14],Port data input output bit 14" "Low,High"
|
|
bitfld.long 0x00 13. "[13],Port data input output bit 13" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 12. "[12],Port data input output bit 12" "Low,High"
|
|
bitfld.long 0x00 11. "[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 11. "PDI[11],Port data input output bit 11" "Low,High"
|
|
bitfld.long 0x00 10. "[10],Port data input output bit 10" "Low,High"
|
|
bitfld.long 0x00 9. "[9],Port data input output bit 9" "Low,High"
|
|
bitfld.long 0x00 8. "[8],Port data input output bit 8" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data input output bit 7" "Low,High"
|
|
bitfld.long 0x00 6. "[6],Port data input output bit 6" "Low,High"
|
|
bitfld.long 0x00 5. "[5],Port data input output bit 5" "Low,High"
|
|
bitfld.long 0x00 4. "[4],Port data input output bit 4" "Low,High"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
else
|
|
bitfld.long 0x00 3. "PDI[3],Port data input output bit 3" "Low,High"
|
|
bitfld.long 0x00 2. "[2],Port data input output bit 2" "Low,High"
|
|
bitfld.long 0x00 1. "[1],Port data input output bit 1" "Low,High"
|
|
bitfld.long 0x00 0. "[0],Port data input output bit 0" "Low,High"
|
|
endif
|
|
group.long 0x14++0x07
|
|
line.long 0x00 "PDDR,Port Data Direction Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x00 27. "PDD[27],Port data direction bit 27" "Input,Output"
|
|
bitfld.long 0x00 26. "[26],Port data direction bit 26" "Input,Output"
|
|
bitfld.long 0x00 25. "[25],Port data direction bit 25" "Input,Output"
|
|
bitfld.long 0x00 24. "[24],Port data direction bit 24" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 23. "[23],Port data direction bit 23" "Input,Output"
|
|
bitfld.long 0x00 22. "[22],Port data direction bit 22" "Input,Output"
|
|
bitfld.long 0x00 21. "[21],Port data direction bit 21" "Input,Output"
|
|
bitfld.long 0x00 20. "[20],Port data direction bit 20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port data direction bit 19" "Input,Output"
|
|
bitfld.long 0x00 18. "[18],Port data direction bit 18" "Input,Output"
|
|
bitfld.long 0x00 17. "[17],Port data direction bit 17" "Input,Output"
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x00 23. "PDD[23],Port data direction bit 23" "Input,Output"
|
|
bitfld.long 0x00 22. "[22],Port data direction bit 22" "Input,Output"
|
|
bitfld.long 0x00 21. "[21],Port data direction bit 21" "Input,Output"
|
|
bitfld.long 0x00 20. "[20],Port data direction bit 20" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 19. "[19],Port data direction bit 19" "Input,Output"
|
|
bitfld.long 0x00 18. "[18],Port data direction bit 18" "Input,Output"
|
|
bitfld.long 0x00 17. "[17],Port data direction bit 17" "Input,Output"
|
|
bitfld.long 0x00 16. "[16],Port data direction bit 16" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x00 16. "PDD[16],Port data direction bit 16" "Input,Output"
|
|
bitfld.long 0x00 15. "[15],Port data direction bit 15" "Input,Output"
|
|
bitfld.long 0x00 14. "[14],Port data direction bit 14" "Input,Output"
|
|
bitfld.long 0x00 13. "[13],Port data direction bit 13" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 12. "[12],Port data direction bit 12" "Input,Output"
|
|
bitfld.long 0x00 11. "[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x00 11. "PDD[11],Port data direction bit 11" "Input,Output"
|
|
bitfld.long 0x00 10. "[10],Port data direction bit 10" "Input,Output"
|
|
bitfld.long 0x00 9. "[9],Port data direction bit 9" "Input,Output"
|
|
bitfld.long 0x00 8. "[8],Port data direction bit 8" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 7. "[7],Port data direction bit 7" "Input,Output"
|
|
bitfld.long 0x00 6. "[6],Port data direction bit 6" "Input,Output"
|
|
bitfld.long 0x00 5. "[5],Port data direction bit 5" "Input,Output"
|
|
bitfld.long 0x00 4. "[4],Port data direction bit 4" "Input,Output"
|
|
newline
|
|
bitfld.long 0x00 3. "[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
else
|
|
bitfld.long 0x00 3. "PDD[3],Port data direction bit 3" "Input,Output"
|
|
bitfld.long 0x00 2. "[2],Port data direction bit 2" "Input,Output"
|
|
bitfld.long 0x00 1. "[1],Port data direction bit 1" "Input,Output"
|
|
bitfld.long 0x00 0. "[0],Port data direction bit 0" "Input,Output"
|
|
endif
|
|
line.long 0x04 "PIDR,Port Input Disable Register"
|
|
sif cpuis("S32K148*")
|
|
bitfld.long 0x04 27. "PID[27],Port input disable bit 27" "No,Yes"
|
|
bitfld.long 0x04 26. "[26],Port input disable bit 26" "No,Yes"
|
|
bitfld.long 0x04 25. "[25],Port input disable bit 25" "No,Yes"
|
|
bitfld.long 0x04 24. "[24],Port input disable bit 24" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 23. "[23],Port input disable bit 23" "No,Yes"
|
|
bitfld.long 0x04 22. "[22],Port input disable bit 22" "No,Yes"
|
|
bitfld.long 0x04 21. "[21],Port input disable bit 21" "No,Yes"
|
|
bitfld.long 0x04 20. "[20],Port input disable bit 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. "[19],Port input disable bit 19" "No,Yes"
|
|
bitfld.long 0x04 18. "[18],Port input disable bit 18" "No,Yes"
|
|
bitfld.long 0x04 17. "[17],Port input disable bit 17" "No,Yes"
|
|
bitfld.long 0x04 16. "[16],Port input disable bit 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K146*")
|
|
bitfld.long 0x04 23. "PID[23],Port input disable bit 23" "No,Yes"
|
|
bitfld.long 0x04 22. "[22],Port input disable bit 22" "No,Yes"
|
|
bitfld.long 0x04 21. "[21],Port input disable bit 21" "No,Yes"
|
|
bitfld.long 0x04 20. "[20],Port input disable bit 20" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 19. "[19],Port input disable bit 19" "No,Yes"
|
|
bitfld.long 0x04 18. "[18],Port input disable bit 18" "No,Yes"
|
|
bitfld.long 0x04 17. "[17],Port input disable bit 17" "No,Yes"
|
|
bitfld.long 0x04 16. "[16],Port input disable bit 16" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K144*")||cpuis("S32K142*")
|
|
bitfld.long 0x04 16. "PID[16],Port input disable bit 16" "No,Yes"
|
|
bitfld.long 0x04 15. "[15],Port input disable bit 15" "No,Yes"
|
|
bitfld.long 0x04 14. "[14],Port input disable bit 14" "No,Yes"
|
|
bitfld.long 0x04 13. "[13],Port input disable bit 13" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 12. "[12],Port input disable bit 12" "No,Yes"
|
|
bitfld.long 0x04 11. "[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
elif cpuis("S32K118*")
|
|
bitfld.long 0x04 11. "PID[11],Port input disable bit 11" "No,Yes"
|
|
bitfld.long 0x04 10. "[10],Port input disable bit 10" "No,Yes"
|
|
bitfld.long 0x04 9. "[9],Port input disable bit 9" "No,Yes"
|
|
bitfld.long 0x04 8. "[8],Port input disable bit 8" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 7. "[7],Port input disable bit 7" "No,Yes"
|
|
bitfld.long 0x04 6. "[6],Port input disable bit 6" "No,Yes"
|
|
bitfld.long 0x04 5. "[5],Port input disable bit 5" "No,Yes"
|
|
bitfld.long 0x04 4. "[4],Port input disable bit 4" "No,Yes"
|
|
newline
|
|
bitfld.long 0x04 3. "[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
else
|
|
bitfld.long 0x04 3. "PID[3],Port input disable bit 3" "No,Yes"
|
|
bitfld.long 0x04 2. "[2],Port input disable bit 2" "No,Yes"
|
|
bitfld.long 0x04 1. "[1],Port input disable bit 1" "No,Yes"
|
|
bitfld.long 0x04 0. "[0],Port input disable bit 0" "No,Yes"
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
tree "MDM-AP"
|
|
base edp:0x0100
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "STATUS,MDM-AP Status Register"
|
|
bitfld.long 0x00 18. "CORE_SLEEPING,Indicates whether the core has entered a low power mode" "0: Not in low power mode,1: Low power mode"
|
|
bitfld.long 0x00 17. "CORE_SLEEPDEEP,Indicates whether the core has entered a debug halt mode" "0: Not in debug halt mode,1: Debug halt mode"
|
|
newline
|
|
bitfld.long 0x00 8. "VERY_LOW_POWER_MODE,Indicates that the current power mode is VLPx. This bit is not sticky and should always represent whether VLPx is enabled or not" "0: Not in VLPx power mode,1: VLPx power mode"
|
|
bitfld.long 0x00 7. "LP_ENABLED,Decode of LPLLSM control bits to indicate that VLPS is the selected power mode the next time the Arm core enters Deep Sleep. Low Power Stop Mode enable" "0: Low Power Stop Mode disabled,1: Low Power Stop Mode enabled"
|
|
newline
|
|
bitfld.long 0x00 6. "BACKDOOR_ACCESS_KEY_ENABLE,Indicates whether the MCU has the backdoor access key enabled" "0: Backdoor access key disabled,1: Backdoor access key enabled"
|
|
bitfld.long 0x00 5. "MASS_ERASE_ENABLE,Indicates whether the MCU can be mass erased" "0: Mass erase disabled,1: Mass erase enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "SYSTEM_RESET,Indicates the system reset state" "0: In reset,1: Not in reset"
|
|
bitfld.long 0x00 2. "SYSTEM_SECURITY,Indicates the security state. When secure the debugger does not have access to the system bus or any memory mapped peripherals" "0: Non-secure,1: Secure"
|
|
newline
|
|
bitfld.long 0x00 1. "FLASH_MEMORY_READY,Indicates whether flash memory has been initialized and the debugger can be configured even if the system is continuing to be held in reset via the debugger" "0: Not ready,1: Ready"
|
|
bitfld.long 0x00 0. "FLASH_MEMORY_MASS_ERASE_ACKNOWLEDGE,Cleared on debug reset. Also cleared at the launch of a mass erase command. Set after the flash memory control logic has started the mass erase operation" "0: Not pending,1: Pending"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CONTROL,MDM-AP Control Register"
|
|
bitfld.long 0x00 9. "TIMESTAMP_DISABLE,Set this bit to disable the 48-bit global trace timestamp counter during debug halt mode when the core is halted" "0: Counting continues,1: Timestamp counter freezes"
|
|
bitfld.long 0x00 4. "CORE_HOLD_RESET,Configuration bit to control core operation at the end of system reset sequencing" "0: Normal operation,1: Suspend operation"
|
|
newline
|
|
bitfld.long 0x00 3. "SYSTEM_RESET_REQUEST,Set to force a system reset. The system remains held in reset until this bit is cleared" "0: No reset,1: Reset"
|
|
bitfld.long 0x00 2. "DEBUG_REQUEST,Set to force the core to halt" "0: Not halted,1: Halted"
|
|
newline
|
|
bitfld.long 0x00 1. "DEBUG_DISABLE,Set to disable debug" "0: Debug enabled,1: Debug disabled"
|
|
bitfld.long 0x00 0. "FLASH_MEMORY_MASS_ERASE_IN_PROGRESS,Set to cause mass erase. Cleared by hardware after mass erase operation completes" "0: Not pending,1: Pending"
|
|
rgroup.long 0xFC++0x03
|
|
line.long 0x00 "ID,MDM-AP ID Register"
|
|
tree.end
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
tree "CAN0 (Flex Controller Area Network module)"
|
|
base ad:0x40024000
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "MCR,Module Configuration Register"
|
|
bitfld.long 0x00 31. "MDIS,Module Disable" "0: Enable the FlexCAN module,1: Disable the FlexCAN module"
|
|
bitfld.long 0x00 30. "FRZ,Freeze Enable" "0: Not enabled to enter Freeze mode,1: Enabled to enter Freeze mode"
|
|
newline
|
|
bitfld.long 0x00 29. "RFEN,Rx FIFO Enable" "0: Rx FIFO not enabled,1: Rx FIFO enabled"
|
|
bitfld.long 0x00 28. "HALT,Halt FlexCAN" "0: No Freeze mode request,1: Enters Freeze mode if the FRZ bit is asserted"
|
|
newline
|
|
rbitfld.long 0x00 27. "NOTRDY,FlexCAN Not Ready" "0: FlexCAN module is either in Normal mode..,?..."
|
|
bitfld.long 0x00 25. "SOFTRST,Soft Reset" "0: No reset request,1: Resets the registers affected by soft reset"
|
|
newline
|
|
rbitfld.long 0x00 24. "FRZACK,Freeze Mode Acknowledge" "0: FlexCAN not in Freeze mode prescaler running,1: FlexCAN in Freeze mode prescaler stopped"
|
|
bitfld.long 0x00 23. "SUPV,Supervisor Mode" "0,1"
|
|
newline
|
|
bitfld.long 0x00 21. "WRNEN,Warning Interrupt Enable" "0: TWRNINT and RWRNINT bits are zero independent..,1: TWRNINT and RWRNINT bits are set when the.."
|
|
rbitfld.long 0x00 20. "LPMACK,Low-Power Mode Acknowledge" "0: FlexCAN is not in a low-power mode,1: FlexCAN is in a low-power mode"
|
|
newline
|
|
bitfld.long 0x00 17. "SRXDIS,Self Reception Disable" "0: Self reception enabled,1: Self reception disabled"
|
|
bitfld.long 0x00 16. "IRMQ,Individual Rx Masking And Queue Enable" "0: Individual Rx masking and queue feature are..,1: Individual Rx masking and queue feature are.."
|
|
newline
|
|
bitfld.long 0x00 15. "DMA,DMA Enable" "0: DMA feature for RX FIFO disabled,1: DMA feature for RX FIFO enabled"
|
|
bitfld.long 0x00 14. "PNET_EN,Pretended Networking Enable" "0: Pretended Networking mode is disabled,1: Pretended Networking mode is enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "LPRIOEN,Local Priority Enable" "0: Local Priority disabled,1: Local Priority enabled"
|
|
bitfld.long 0x00 12. "AEN,Abort Enable" "0: Abort disabled,1: Abort enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FDEN,CAN FD operation enable" "0: CAN FD is disabled,1: CAN FD is enabled"
|
|
bitfld.long 0x00 8.--9. "IDAM,ID Acceptance Mode" "0: Format A,1: Format B,2: Format C,3: Format D"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--6. 1. "MAXMB,Number Of The Last Message Buffer"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "CTRL1,Control 1 register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "PRESDIV,Prescaler Division Factor"
|
|
bitfld.long 0x00 22.--23. "RJW,Resync Jump Width" "0,1,2,3"
|
|
newline
|
|
bitfld.long 0x00 19.--21. "PSEG1,Phase Segment 1" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 16.--18. "PSEG2,Phase Segment 2" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 15. "BOFFMSK,Bus Off Interrupt Mask" "0: Bus Off interrupt disabled,1: Bus Off interrupt enabled"
|
|
bitfld.long 0x00 14. "ERRMSK,Error Interrupt Mask" "0: Error interrupt disabled,1: Error interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "CLKSRC,CAN Engine Clock Source" "0: The CAN engine clock source is the oscillator..,1: The CAN engine clock source is the peripheral.."
|
|
bitfld.long 0x00 12. "LPB,Loop Back Mode" "0: Loop Back disabled,1: Loop Back enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TWRNMSK,Tx Warning Interrupt Mask" "0: Tx Warning Interrupt disabled,1: Tx Warning Interrupt enabled"
|
|
bitfld.long 0x00 10. "RWRNMSK,Rx Warning Interrupt Mask" "0: Rx Warning Interrupt disabled,1: Rx Warning Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 7. "SMP,CAN Bit Sampling" "0: Just one sample is used to determine the bit..,1: Three samples are used to determine the value.."
|
|
bitfld.long 0x00 6. "BOFFREC,Bus Off Recovery" "0: Automatic recovering from Bus Off state enabled,1: Automatic recovering from Bus Off state.."
|
|
newline
|
|
bitfld.long 0x00 5. "TSYN,Timer Sync" "0: Timer Sync feature disabled,1: Timer Sync feature enabled"
|
|
bitfld.long 0x00 4. "LBUF,Lowest Buffer Transmitted First" "0: Buffer with highest priority is transmitted..,1: Lowest number buffer is transmitted first"
|
|
newline
|
|
bitfld.long 0x00 3. "LOM,Listen-Only Mode" "0: Listen-Only mode is deactivated,1: FlexCAN module operates in Listen-Only mode"
|
|
bitfld.long 0x00 0.--2. "PROPSEG,Propagation Segment" "0,1,2,3,4,5,6,7"
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "TIMER,Free Running Timer"
|
|
hexmask.long.word 0x00 0.--15. 1. "TIMER,Timer Value"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "RXMGMASK,Rx Mailboxes Global Mask Register"
|
|
hexmask.long 0x00 0.--31. 1. "MG,Rx Mailboxes Global Mask Bits"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "RX14MASK,Rx 14 Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "RX14M,Rx Buffer 14 Mask Bits"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "RX15MASK,Rx 15 Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "RX15M,Rx Buffer 15 Mask Bits"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "ECR,Error Counter"
|
|
hexmask.long.byte 0x00 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for fast bits"
|
|
hexmask.long.byte 0x00 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for fast bits"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXERRCNT,Receive Error Counter"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXERRCNT,Transmit Error Counter"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "ESR1,Error and Status 1 register"
|
|
rbitfld.long 0x00 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as recessive is.."
|
|
rbitfld.long 0x00 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: At least one bit sent as dominant is received.."
|
|
newline
|
|
rbitfld.long 0x00 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A CRC error occurred since last read of this.."
|
|
rbitfld.long 0x00 27. "FRMERR_FAST,Form Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A Form Error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: A Stuffing Error occurred since last read of.."
|
|
bitfld.long 0x00 21. "ERROVR,Error Overrun bit" "0: Overrun has not occurred,1: Overrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 20. "ERRINT_FAST,Error Interrupt for errors detected in the Data Phase of CAN FD frames with the BRS bit set" "0: No such occurrence,1: Indicates setting of any Error Bit detected.."
|
|
bitfld.long 0x00 19. "BOFFDONEINT,Bus Off Done Interrupt" "0: No such occurrence,1: FlexCAN module has completed Bus Off process"
|
|
newline
|
|
rbitfld.long 0x00 18. "SYNCH,CAN Synchronization Status" "0: FlexCAN is not synchronized to the CAN bus,1: FlexCAN is synchronized to the CAN bus"
|
|
bitfld.long 0x00 17. "TWRNINT,Tx Warning Interrupt Flag" "0: No such occurrence,1: The Tx error counter transitioned from less.."
|
|
newline
|
|
bitfld.long 0x00 16. "RWRNINT,Rx Warning Interrupt Flag" "0: No such occurrence,1: The Rx error counter transitioned from less.."
|
|
rbitfld.long 0x00 15. "BIT1ERR,Bit1 Error" "0: No such occurrence,1: At least one bit sent as recessive is.."
|
|
newline
|
|
rbitfld.long 0x00 14. "BIT0ERR,Bit0 Error" "0: No such occurrence,1: At least one bit sent as dominant is received.."
|
|
rbitfld.long 0x00 13. "ACKERR,Acknowledge Error" "0: No such occurrence,1: An ACK error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 12. "CRCERR,Cyclic Redundancy Check Error" "0: No such occurrence,1: A CRC error occurred since last read of this.."
|
|
rbitfld.long 0x00 11. "FRMERR,Form Error" "0: No such occurrence,1: A Form Error occurred since last read of this.."
|
|
newline
|
|
rbitfld.long 0x00 10. "STFERR,Stuffing Error" "0: No such occurrence,1: A Stuffing Error occurred since last read of.."
|
|
rbitfld.long 0x00 9. "TXWRN,TX Error Warning" "0: No such occurrence,1: TXERRCNT is greater than or equal to 96"
|
|
newline
|
|
rbitfld.long 0x00 8. "RXWRN,Rx Error Warning" "0: No such occurrence,1: RXERRCNT is greater than or equal to 96"
|
|
rbitfld.long 0x00 7. "IDLE,IDLE" "0: No such occurrence,1: CAN bus is now IDLE"
|
|
newline
|
|
rbitfld.long 0x00 6. "TX,FlexCAN In Transmission" "0: FlexCAN is not transmitting a message,1: FlexCAN is transmitting a message"
|
|
rbitfld.long 0x00 4.--5. "FLTCONF,Fault Confinement State" "0: Error Active,1: Error Passive,2: Bus Off,3: Bus Off"
|
|
newline
|
|
rbitfld.long 0x00 3. "RX,FlexCAN In Reception" "0: FlexCAN is not receiving a message,1: FlexCAN is receiving a message"
|
|
bitfld.long 0x00 2. "BOFFINT,Bus Off Interrupt" "0: No such occurrence,1: FlexCAN module entered Bus Off state"
|
|
newline
|
|
bitfld.long 0x00 1. "ERRINT,Error Interrupt" "0: No such occurrence,1: Indicates setting of any Error Bit in the.."
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IMASK1,Interrupt Masks 1 register"
|
|
hexmask.long 0x00 0.--31. 1. "BUF31TO0M,Buffer MB i Mask"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IFLAG1,Interrupt Flags 1 register"
|
|
hexmask.long.tbyte 0x00 8.--31. 1. "BUF31TO8I,Buffer MBi Interrupt"
|
|
bitfld.long 0x00 7. "BUF7I,Buffer MB7 Interrupt Or Rx FIFO Overflow" "0: No occurrence of MB7 completing..,1: MB7 completed transmission/reception when.."
|
|
newline
|
|
bitfld.long 0x00 6. "BUF6I,Buffer MB6 Interrupt Or Rx FIFO Warning" "0: No occurrence of MB6 completing..,1: MB6 completed transmission/reception when.."
|
|
bitfld.long 0x00 5. "BUF5I,Buffer MB5 Interrupt Or Frames available in Rx FIFO" "0: No occurrence of MB5 completing..,1: MB5 completed transmission/reception when.."
|
|
newline
|
|
bitfld.long 0x00 1.--4. "BUF4TO1I,Buffer MB i Interrupt Or reserved" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. "BUF0I,Buffer MB0 Interrupt Or Clear FIFO bit" "0: The corresponding buffer has no occurrence of..,1: The corresponding buffer has successfully.."
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CTRL2,Control 2 register"
|
|
bitfld.long 0x00 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames" "0: ERRINT_FAST Error interrupt disabled,1: ERRINT_FAST Error interrupt enabled"
|
|
bitfld.long 0x00 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask" "0: Bus Off Done interrupt disabled,1: Bus Off Done interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 24.--27. "RFFN,Number Of Rx FIFO Filters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 19.--23. "TASD,Tx Arbitration Start Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
newline
|
|
bitfld.long 0x00 18. "MRP,Mailboxes Reception Priority" "0: Matching starts from Rx FIFO and continues on..,1: Matching starts from Mailboxes and continues.."
|
|
bitfld.long 0x00 17. "RRS,Remote Request Storing" "0: Remote Response Frame is generated,1: Remote Request Frame is stored"
|
|
newline
|
|
bitfld.long 0x00 16. "EACEN,Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes" "0: Rx Mailbox filter's IDE bit is always..,1: Enables the comparison of both Rx Mailbox.."
|
|
bitfld.long 0x00 15. "TIMER_SRC,Timer Source" "0: The Free Running Timer is clocked by the CAN..,1: The Free Running Timer is clocked by an.."
|
|
newline
|
|
bitfld.long 0x00 14. "PREXCEN,Protocol Exception Enable" "0: Protocol Exception is disabled,1: Protocol Exception is enabled"
|
|
bitfld.long 0x00 12. "ISOCANFDEN,ISO CAN FD Enable" "0: FlexCAN operates using the non-ISO CAN FD..,1: FlexCAN operates using the ISO CAN FD.."
|
|
newline
|
|
bitfld.long 0x00 11. "EDFLTDIS,Edge Filter Disable" "0: Edge Filter is enabled,1: Edge Filter is disabled"
|
|
rgroup.long 0x38++0x03
|
|
line.long 0x00 "ESR2,Error and Status 2 register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "LPTM,Lowest Priority Tx Mailbox"
|
|
bitfld.long 0x00 14. "VPS,Valid Priority Status" "0: Contents of IMB and LPTM are invalid,1: Contents of IMB and LPTM are valid"
|
|
newline
|
|
bitfld.long 0x00 13. "IMB,Inactive Mailbox" "0: If ESR2[VPS] is asserted the ESR2[LPTM] is..,1: If ESR2[VPS] is asserted there is at least.."
|
|
rgroup.long 0x44++0x03
|
|
line.long 0x00 "CRCR,CRC Register"
|
|
hexmask.long.byte 0x00 16.--22. 1. "MBCRC,CRC Mailbox"
|
|
hexmask.long.word 0x00 0.--14. 1. "TXCRC,Transmitted CRC value"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "RXFGMASK,Rx FIFO Global Mask register"
|
|
hexmask.long 0x00 0.--31. 1. "FGM,Rx FIFO Global Mask Bits"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "RXFIR,Rx FIFO Information Register"
|
|
hexmask.long.word 0x00 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CBT,CAN Bit Timing Register"
|
|
bitfld.long 0x00 31. "BTF,Bit Timing Format Enable" "0: Extended bit time definitions disabled,1: Extended bit time definitions enabled"
|
|
hexmask.long.word 0x00 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor"
|
|
newline
|
|
bitfld.long 0x00 16.--20. "ERJW,Extended Resync Jump Width" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 10.--15. "EPROPSEG,Extended Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 5.--9. "EPSEG1,Extended Phase Segment 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 0.--4. "EPSEG2,Extended Phase Segment 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "RAMn0,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "EmbeddedRAM0,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x84++0x03
|
|
line.long 0x00 "RAMn1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x84)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x88++0x03
|
|
line.long 0x00 "RAMn2,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x8C++0x03
|
|
line.long 0x00 "EmbeddedRAM3,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "4" )(list 0x0 0x4 )
|
|
group.long ($2+0x8C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "5" )(list 0x0 0x4 )
|
|
group.long ($2+0x90)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "RAMn5,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "EmbeddedRAM6,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "RAMn6,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "EmbeddedRAM7,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "8" )(list 0x0 0x4 )
|
|
group.long ($2+0x9C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "9" )(list 0x0 0x4 )
|
|
group.long ($2+0xA0)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "10" )(list 0x0 0x4 )
|
|
group.long ($2+0xA4)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "EmbeddedRAM10,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "RAMn11,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "12" )(list 0x0 0x4 )
|
|
group.long ($2+0xAC)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "RAMn12,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "EmbeddedRAM13,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "14" )(list 0x0 0x4 )
|
|
group.long ($2+0xB4)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "15" )(list 0x0 0x4 )
|
|
group.long ($2+0xB8)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "RAMn15,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "EmbeddedRAM16,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "RAMn16,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "EmbeddedRAM17,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "18" )(list 0x0 0x4 )
|
|
group.long ($2+0xC4)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "19" )(list 0x0 0x4 )
|
|
group.long ($2+0xC8)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "RAMn19,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "EmbeddedRAM20,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "RAMn20,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "EmbeddedRAM21,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "RAMn21,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "EmbeddedRAM22,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "23" )(list 0x0 0x4 )
|
|
group.long ($2+0xD8)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "EmbeddedRAM23,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "RAMn24,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "25" )(list 0x0 0x4 )
|
|
group.long ($2+0xE0)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "26" )(list 0x0 0x4 )
|
|
group.long ($2+0xE4)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "EmbeddedRAM26,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "RAMn27,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xEC++0x03
|
|
line.long 0x00 "EmbeddedRAM27,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "RAMn28,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "EmbeddedRAM28,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xF4++0x03
|
|
line.long 0x00 "RAMn29,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "30" )(list 0x0 0x4 )
|
|
group.long ($2+0xF4)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xF8++0x03
|
|
line.long 0x00 "RAMn30,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "EmbeddedRAM31,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "RAMn31,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "EmbeddedRAM32,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "RAMn32,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "EmbeddedRAM33,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "34" )(list 0x00 0x04 )
|
|
group.long ($2+0x104)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "35" )(list 0x00 0x04 )
|
|
group.long ($2+0x108)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "RAMn35,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "EmbeddedRAM36,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "RAMn36,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "EmbeddedRAM37,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "RAMn37,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "EmbeddedRAM38,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "RAMn38,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "EmbeddedRAM39,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "RAMn39,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "EmbeddedRAM40,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "41" )(list 0x00 0x04 )
|
|
group.long ($2+0x120)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "42" )(list 0x00 0x04 )
|
|
group.long ($2+0x124)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "43" )(list 0x00 0x04 )
|
|
group.long ($2+0x128)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "EmbeddedRAM43,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "RAMn44,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "EmbeddedRAM44,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "RAMn45,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "EmbeddedRAM45,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "RAMn46,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "47" )(list 0x00 0x04 )
|
|
group.long ($2+0x138)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "RAMn47,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "EmbeddedRAM48,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "RAMn48,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "EmbeddedRAM49,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "50" )(list 0x00 0x04 )
|
|
group.long ($2+0x144)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "EmbeddedRAM50,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "RAMn51,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "52" )(list 0x00 0x04 )
|
|
group.long ($2+0x14C)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "RAMn52,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "EmbeddedRAM53,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "54" )(list 0x00 0x04 )
|
|
group.long ($2+0x154)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "55" )(list 0x00 0x04 )
|
|
group.long ($2+0x158)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "56" )(list 0x00 0x04 )
|
|
group.long ($2+0x15C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "EmbeddedRAM56,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "RAMn57,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "58" )(list 0x00 0x04 )
|
|
group.long ($2+0x164)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "RAMn58,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "EmbeddedRAM59,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "60" )(list 0x00 0x04 )
|
|
group.long ($2+0x16C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "61" )(list 0x00 0x04 )
|
|
group.long ($2+0x170)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "RAMn61,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "EmbeddedRAM62,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "63" )(list 0x00 0x04 )
|
|
group.long ($2+0x178)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "64" )(list 0x00 0x04 )
|
|
group.long ($2+0x17C)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "RAMn64,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "EmbeddedRAM65,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "RAMn65,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "EmbeddedRAM66,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x188++0x03
|
|
line.long 0x00 "RAMn66,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x18C++0x03
|
|
line.long 0x00 "EmbeddedRAM67,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "68" )(list 0x00 0x04 )
|
|
group.long ($2+0x18C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "69" )(list 0x00 0x04 )
|
|
group.long ($2+0x190)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "70" )(list 0x00 0x04 )
|
|
group.long ($2+0x194)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "71" )(list 0x00 0x04 )
|
|
group.long ($2+0x198)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "72" )(list 0x00 0x04 )
|
|
group.long ($2+0x19C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "EmbeddedRAM72,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "RAMn73,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1A4++0x03
|
|
line.long 0x00 "EmbeddedRAM73,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1A8++0x03
|
|
line.long 0x00 "RAMn74,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "75" )(list 0x00 0x04 )
|
|
group.long ($2+0x1A8)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "76" )(list 0x00 0x04 )
|
|
group.long ($2+0x1AC)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1B0++0x03
|
|
line.long 0x00 "EmbeddedRAM76,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "RAMn77,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1B4++0x03
|
|
line.long 0x00 "EmbeddedRAM77,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1B8++0x03
|
|
line.long 0x00 "RAMn78,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "79" )(list 0x00 0x04 )
|
|
group.long ($2+0x1B8)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "80" )(list 0x00 0x04 )
|
|
group.long ($2+0x1BC)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1C0++0x03
|
|
line.long 0x00 "EmbeddedRAM80,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "RAMn81,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1C4++0x03
|
|
line.long 0x00 "EmbeddedRAM81,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "RAMn82,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1C8++0x03
|
|
line.long 0x00 "EmbeddedRAM82,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1CC++0x03
|
|
line.long 0x00 "RAMn83,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "84" )(list 0x00 0x04 )
|
|
group.long ($2+0x1CC)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1D0++0x03
|
|
line.long 0x00 "RAMn84,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "EmbeddedRAM85,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1D4++0x03
|
|
line.long 0x00 "RAMn85,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "EmbeddedRAM86,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1D8++0x03
|
|
line.long 0x00 "RAMn86,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1DC++0x03
|
|
line.long 0x00 "EmbeddedRAM87,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "88" )(list 0x00 0x04 )
|
|
group.long ($2+0x1DC)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "89" )(list 0x00 0x04 )
|
|
group.long ($2+0x1E0)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1E4++0x03
|
|
line.long 0x00 "RAMn89,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "EmbeddedRAM90,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1E8++0x03
|
|
line.long 0x00 "RAMn90,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "EmbeddedRAM91,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1EC++0x03
|
|
line.long 0x00 "RAMn91,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "EmbeddedRAM92,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x1F0++0x03
|
|
line.long 0x00 "RAMn92,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x1F4++0x03
|
|
line.long 0x00 "EmbeddedRAM93,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "94" )(list 0x00 0x04 )
|
|
group.long ($2+0x1F4)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "95" )(list 0x00 0x04 )
|
|
group.long ($2+0x1F8)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "96" )(list 0x00 0x04 )
|
|
group.long ($2+0x1FC)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "97" )(list 0x00 0x04 )
|
|
group.long ($2+0x200)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "98" )(list 0x00 0x04 )
|
|
group.long ($2+0x204)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "99" )(list 0x00 0x04 )
|
|
group.long ($2+0x208)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "RAMn99,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "EmbeddedRAM100,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "101" )(list 0x00 0x04 )
|
|
group.long ($2+0x210)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "EmbeddedRAM101,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "RAMn102,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "103" )(list 0x00 0x04 )
|
|
group.long ($2+0x218)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "104" )(list 0x00 0x04 )
|
|
group.long ($2+0x21C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "EmbeddedRAM104,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "RAMn105,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x224++0x03
|
|
line.long 0x00 "EmbeddedRAM105,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x228++0x03
|
|
line.long 0x00 "RAMn106,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "107" )(list 0x00 0x04 )
|
|
group.long ($2+0x228)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "108" )(list 0x00 0x04 )
|
|
group.long ($2+0x22C)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "EmbeddedRAM108,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x234++0x03
|
|
line.long 0x00 "RAMn109,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "110" )(list 0x00 0x04 )
|
|
group.long ($2+0x234)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "111" )(list 0x00 0x04 )
|
|
group.long ($2+0x238)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "112" )(list 0x00 0x04 )
|
|
group.long ($2+0x23C)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "113" )(list 0x00 0x04 )
|
|
group.long ($2+0x240)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x244++0x03
|
|
line.long 0x00 "EmbeddedRAM113,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x248++0x03
|
|
line.long 0x00 "RAMn114,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "115" )(list 0x00 0x04 )
|
|
group.long ($2+0x248)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x24C++0x03
|
|
line.long 0x00 "RAMn115,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "EmbeddedRAM116,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "RAMn116,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x254++0x03
|
|
line.long 0x00 "EmbeddedRAM117,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "118" )(list 0x00 0x04 )
|
|
group.long ($2+0x254)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x258++0x03
|
|
line.long 0x00 "EmbeddedRAM118,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x25C++0x03
|
|
line.long 0x00 "RAMn119,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "120" )(list 0x00 0x04 )
|
|
group.long ($2+0x25C)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "RAMn120,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "EmbeddedRAM121,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x264++0x03
|
|
line.long 0x00 "RAMn121,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x268++0x03
|
|
line.long 0x00 "EmbeddedRAM122,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
repeat 2. (strings "1" "123" )(list 0x00 0x04 )
|
|
group.long ($2+0x268)++0x03
|
|
line.long 0x00 "RAMn$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x26C++0x03
|
|
line.long 0x00 "EmbeddedRAM123,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "RAMn124,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "EmbeddedRAM124,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x274++0x03
|
|
line.long 0x00 "RAMn125,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 2. (strings "1" "126" )(list 0x00 0x04 )
|
|
group.long ($2+0x274)++0x03
|
|
line.long 0x00 "EmbeddedRAM$1,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
repeat.end
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x278++0x03
|
|
line.long 0x00 "RAMn126,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "EmbeddedRAM127,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")
|
|
group.long 0x27C++0x03
|
|
line.long 0x00 "RAMn127,Embedded RAM"
|
|
hexmask.long.byte 0x00 24.--31. 1. "DATA_BYTE_0,Data byte 0 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 16.--23. 1. "DATA_BYTE_1,Data byte 1 of Rx/Tx frame"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DATA_BYTE_2,Data byte 2 of Rx/Tx frame"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA_BYTE_3,Data byte 3 of Rx/Tx frame"
|
|
endif
|
|
sif cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")||cpuis("S32K148")
|
|
repeat 16. (strings "1" "1" "2" "3" "4" "5" "6" "7" "8" "9" "10" "11" "12" "13" "14" "15" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x880)++0x03
|
|
line.long 0x00 "RXIMR$1,Rx Individual Mask Registers"
|
|
hexmask.long 0x00 0.--31. 1. "MI,Individual Mask Bits"
|
|
repeat.end
|
|
repeat 16. (strings "1" "17" "18" "19" "20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "30" "31" )(list 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C )
|
|
group.long ($2+0x8C0)++0x03
|
|
line.long 0x00 "RXIMR$1,Rx Individual Mask Registers"
|
|
hexmask.long 0x00 0.--31. 1. "MI,Individual Mask Bits"
|
|
repeat.end
|
|
group.long 0xB00++0x03
|
|
line.long 0x00 "CTRL1_PN,Pretended Networking Control 1 Register"
|
|
bitfld.long 0x00 17. "WTOF_MSK,Wake Up by Timeout Flag Mask Bit" "0: Timeout wake up event is disabled,1: Timeout wake up event is enabled"
|
|
bitfld.long 0x00 16. "WUMF_MSK,Wake Up by Match Flag Mask Bit" "0: Wake up match event is disabled,1: Wake up match event is enabled"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "NMATCH,Number of Messages Matching the Same Filtering Criteria"
|
|
bitfld.long 0x00 4.--5. "PLFS,Payload Filtering Selection" "0: Match upon a payload contents against an..,1: Match upon a payload value greater than or..,2: Match upon a payload value smaller than or..,3: Match upon a payload value inside a range.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "IDFS,ID Filtering Selection" "0: Match upon a ID contents against an exact..,1: Match upon a ID value greater than or equal..,2: Match upon a ID value smaller than or equal..,3: Match upon a ID value inside a range greater.."
|
|
bitfld.long 0x00 0.--1. "FCS,Filtering Combination Selection" "0: Message ID filtering only,1: Message ID filtering and payload filtering,2: Message ID filtering occurring a specified..,3: Message ID filtering and payload filtering a.."
|
|
group.long 0xB04++0x03
|
|
line.long 0x00 "CTRL2_PN,Pretended Networking Control 2 Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MATCHTO,Timeout for No Message Matching the Filtering Criteria"
|
|
group.long 0xB08++0x03
|
|
line.long 0x00 "WU_MTC,Pretended Networking Wake Up Match Register"
|
|
bitfld.long 0x00 17. "WTOF,Wake Up by Timeout Flag Bit" "0: No wake up by timeout event detected,1: Wake up by timeout event detected"
|
|
bitfld.long 0x00 16. "WUMF,Wake Up by Match Flag Bit" "0: No wake up by match event detected,1: Wake up by match event detected"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "MCOUNTER,Number of Matches while in Pretended Networking"
|
|
group.long 0xB0C++0x03
|
|
line.long 0x00 "FLT_ID1,Pretended Networking ID Filter 1 Register"
|
|
bitfld.long 0x00 30. "FLT_IDE,ID Extended Filter" "0: Accept standard frame format,1: Accept extended frame format"
|
|
bitfld.long 0x00 29. "FLT_RTR,Remote Transmission Request Filter" "0: Reject remote frame (accept data frame),1: Accept remote frame"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. "FLT_ID1,ID Filter 1 for Pretended Networking filtering"
|
|
group.long 0xB10++0x03
|
|
line.long 0x00 "FLT_DLC,Pretended Networking DLC Filter Register"
|
|
bitfld.long 0x00 16.--19. "FLT_DLC_LO,Lower Limit for Length of Data Bytes Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "FLT_DLC_HI,Upper Limit for Length of Data Bytes Filter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xB14++0x03
|
|
line.long 0x00 "PL1_LO,Pretended Networking Payload Low Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Payload Filter 1 low order bits for Pretended Networking payload filtering corresponding to the data byte 3"
|
|
group.long 0xB18++0x03
|
|
line.long 0x00 "PL1_HI,Pretended Networking Payload High Filter 1 Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 5"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Payload Filter 1 high order bits for Pretended Networking payload filtering corresponding to the data byte 7"
|
|
group.long 0xB1C++0x03
|
|
line.long 0x00 "FLT_ID2_IDMASK,Pretended Networking ID Filter 2 Register / ID Mask Register"
|
|
bitfld.long 0x00 30. "IDE_MSK,ID Extended Mask Bit" "0: The corresponding bit in the filter is don't..,1: The corresponding bit in the filter is checked"
|
|
bitfld.long 0x00 29. "RTR_MSK,Remote Transmission Request Mask Bit" "0: The corresponding bit in the filter is don't..,1: The corresponding bit in the filter is checked"
|
|
newline
|
|
hexmask.long 0x00 0.--28. 1. "FLT_ID2_IDMASK,ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering"
|
|
group.long 0xB20++0x03
|
|
line.long 0x00 "PL2_PLMASK_LO,Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 0"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 1"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to the data byte 3"
|
|
group.long 0xB24++0x03
|
|
line.long 0x00 "PL2_PLMASK_HI,Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 4"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 5"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 6"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to the data byte 7"
|
|
rgroup.long 0xB40++0x03
|
|
line.long 0x00 "WMB0_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB44++0x03
|
|
line.long 0x00 "WMB0_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB48++0x03
|
|
line.long 0x00 "WMB0_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB4C++0x03
|
|
line.long 0x00 "WMB0_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
rgroup.long 0xB50++0x03
|
|
line.long 0x00 "WMB1_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB54++0x03
|
|
line.long 0x00 "WMB1_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB58++0x03
|
|
line.long 0x00 "WMB1_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB5C++0x03
|
|
line.long 0x00 "WMB1_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
rgroup.long 0xB60++0x03
|
|
line.long 0x00 "WMB2_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB64++0x03
|
|
line.long 0x00 "WMB2_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB68++0x03
|
|
line.long 0x00 "WMB2_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB6C++0x03
|
|
line.long 0x00 "WMB2_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
rgroup.long 0xB70++0x03
|
|
line.long 0x00 "WMB3_CS,Wake Up Message Buffer Register for C/S"
|
|
bitfld.long 0x00 22. "SRR,Substitute Remote Request" "0,1"
|
|
bitfld.long 0x00 21. "IDE,ID Extended Bit" "0: Frame format is standard,1: Frame format is extended"
|
|
newline
|
|
bitfld.long 0x00 20. "RTR,Remote Transmission Request Bit" "0: Frame is data one (not remote),1: Frame is a remote one"
|
|
bitfld.long 0x00 16.--19. "DLC,Length of Data in Bytes" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0xB74++0x03
|
|
line.long 0x00 "WMB3_ID,Wake Up Message Buffer Register for ID"
|
|
hexmask.long 0x00 0.--28. 1. "ID,Received ID under Pretended Networking mode"
|
|
rgroup.long 0xB78++0x03
|
|
line.long 0x00 "WMB3_D03,Wake Up Message Buffer Register for Data 0-3"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_0,Received payload corresponding to the data byte 0 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_1,Received payload corresponding to the data byte 1 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_2,Received payload corresponding to the data byte 2 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_3,Received payload corresponding to the data byte 3 under Pretended Networking mode"
|
|
rgroup.long 0xB7C++0x03
|
|
line.long 0x00 "WMB3_D47,Wake Up Message Buffer Register Data 4-7"
|
|
hexmask.long.byte 0x00 24.--31. 1. "Data_byte_4,Received payload corresponding to the data byte 4 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 16.--23. 1. "Data_byte_5,Received payload corresponding to the data byte 5 under Pretended Networking mode"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "Data_byte_6,Received payload corresponding to the data byte 6 under Pretended Networking mode"
|
|
hexmask.long.byte 0x00 0.--7. 1. "Data_byte_7,Received payload corresponding to the data byte 7 under Pretended Networking mode"
|
|
group.long 0xC00++0x03
|
|
line.long 0x00 "FDCTRL,CAN FD Control Register"
|
|
bitfld.long 0x00 31. "FDRATE,Bit Rate Switch Enable" "0: Transmit a frame in nominal rate,1: Transmit a frame with bit rate switching if.."
|
|
bitfld.long 0x00 16.--17. "MBDSR0,Message Buffer Data Size for Region 0" "0: Selects 8 bytes per Message Buffer,1: Selects 16 bytes per Message Buffer,2: Selects 32 bytes per Message Buffer,3: Selects 64 bytes per Message Buffer"
|
|
newline
|
|
bitfld.long 0x00 15. "TDCEN,Transceiver Delay Compensation Enable" "0: TDC is disabled,1: TDC is enabled"
|
|
bitfld.long 0x00 14. "TDCFAIL,Transceiver Delay Compensation Fail" "0: Measured loop delay is in range,1: Measured loop delay is out of range"
|
|
newline
|
|
bitfld.long 0x00 8.--12. "TDCOFF,Transceiver Delay Compensation Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
rbitfld.long 0x00 0.--5. "TDCVAL,Transceiver Delay Compensation Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xC04++0x03
|
|
line.long 0x00 "FDCBT,CAN FD Bit Timing Register"
|
|
hexmask.long.word 0x00 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor"
|
|
bitfld.long 0x00 16.--18. "FRJW,Fast Resync Jump Width" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 10.--14. "FPROPSEG,Fast Propagation Segment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 5.--7. "FPSEG1,Fast Phase Segment 1" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.long 0x00 0.--2. "FPSEG2,Fast Phase Segment 2" "0,1,2,3,4,5,6,7"
|
|
rgroup.long 0xC08++0x03
|
|
line.long 0x00 "FDCRC,CAN FD CRC Register"
|
|
hexmask.long.byte 0x00 24.--30. 1. "FD_MBCRC,CRC Mailbox Number for FD_TXCRC"
|
|
hexmask.long.tbyte 0x00 0.--20. 1. "FD_TXCRC,Extended Transmitted CRC value"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("S32K116")
|
|
tree "LPSPI0 (The LPSPI Memory Map/Register Definition can be found here.)"
|
|
base ad:0x4002C000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Module Identification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. "RXFIFO,Receive FIFO Size"
|
|
hexmask.long.byte 0x00 0.--7. 1. "TXFIFO,Transmit FIFO Size"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CR,Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Module is disabled in debug mode,1: Module is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Module is enabled in Doze mode,1: Module is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Module Enable" "0: Module is disabled,1: Module is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SR,Status Register"
|
|
rbitfld.long 0x00 24. "MBF,Module Busy Flag" "0: LPSPI is idle,1: LPSPI is busy"
|
|
bitfld.long 0x00 13. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
newline
|
|
bitfld.long 0x00 12. "REF,Receive Error Flag" "0: Receive FIFO has not overflowed,1: Receive FIFO has overflowed"
|
|
bitfld.long 0x00 11. "TEF,Transmit Error Flag" "0: Transmit FIFO underrun has not occurred,1: Transmit FIFO underrun has occurred"
|
|
newline
|
|
bitfld.long 0x00 10. "TCF,Transfer Complete Flag" "0: All transfers have not completed,1: All transfers have completed"
|
|
bitfld.long 0x00 9. "FCF,Frame Complete Flag" "0: Frame transfer has not completed,1: Frame transfer has completed"
|
|
newline
|
|
bitfld.long 0x00 8. "WCF,Word Complete Flag" "0: Transfer word not completed,1: Transfer word completed"
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IER,Interrupt Enable Register"
|
|
bitfld.long 0x00 13. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "REIE,Receive Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 11. "TEIE,Transmit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "TCIE,Transfer Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "FCIE,Frame Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "WCIE,Word Complete Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "DER,DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CFGR0,Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the DMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin LPSPI_HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request is disabled,1: Host request is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CFGR1,Configuration Register 1"
|
|
bitfld.long 0x00 27. "PCSCFG,Peripheral Chip Select Configuration" "0: PCS[3:2] are enabled,1: PCS[3:2] are disabled"
|
|
bitfld.long 0x00 26. "OUTCFG,Output Config" "0: Output data retains last value when chip..,1: Output data is tristated when chip select is.."
|
|
newline
|
|
bitfld.long 0x00 24.--25. "PINCFG,Pin Configuration" "0: SIN is used for input data and SOUT for..,1: SIN is used for both input and output data,2: SOUT is used for both input and output data,3: SOUT is used for input data and SIN for.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match is disabled,?,2: 010b - Match is enabled if 1st data word..,3: 011b - Match is enabled if any data word..,4: 100b - Match is enabled if 1st data word..,5: 101b - Match is enabled if any data word..,6: 110b - Match is enabled if (1st data word AND..,7: 111b - Match is enabled if (any data word AND.."
|
|
newline
|
|
bitfld.long 0x00 8.--11. "PCSPOL,Peripheral Chip Select Polarity" "0: The PCSx is active low,1: The PCSx is active high,?..."
|
|
bitfld.long 0x00 3. "NOSTALL,No Stall" "0: Transfers will stall when transmit FIFO is..,1: Transfers will not stall allowing transmit.."
|
|
newline
|
|
bitfld.long 0x00 2. "AUTOPCS,Automatic PCS" "0: Automatic PCS generation disabled,1: Automatic PCS generation enabled"
|
|
bitfld.long 0x00 1. "SAMPLE,Sample Point" "0: Input data sampled on SCK edge,1: Input data sampled on delayed SCK edge"
|
|
newline
|
|
bitfld.long 0x00 0. "MASTER,Master Mode" "0: Slave mode,1: Master mode"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DMR0,Data Match Register 0"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH0,Match 0 Value"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "DMR1,Data Match Register 1"
|
|
hexmask.long 0x00 0.--31. 1. "MATCH1,Match 1 Value"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CCR,Clock Configuration Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "SCKPCS,SCK to PCS Delay"
|
|
hexmask.long.byte 0x00 16.--23. 1. "PCSSCK,PCS to SCK Delay"
|
|
newline
|
|
hexmask.long.byte 0x00 8.--15. 1. "DBT,Delay Between Transfers"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SCKDIV,SCK Divider"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "FCR,FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "FSR,FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "TCR,Transmit Command Register"
|
|
bitfld.long 0x00 31. "CPOL,Clock Polarity" "0: The inactive state value of SCK is low,1: The inactive state value of SCK is high"
|
|
bitfld.long 0x00 30. "CPHA,Clock Phase" "0: Data is captured on the leading edge of SCK..,1: Data is changed on the leading edge of SCK.."
|
|
newline
|
|
bitfld.long 0x00 27.--29. "PRESCALE,Prescaler Value" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
bitfld.long 0x00 24.--25. "PCS,Peripheral Chip Select" "0: Transfer using LPSPI_PCS[0],1: Transfer using LPSPI_PCS[1],2: Transfer using LPSPI_PCS[2],3: Transfer using LPSPI_PCS[3]"
|
|
newline
|
|
bitfld.long 0x00 23. "LSBF,LSB First" "0: Data is transferred MSB first,1: Data is transferred LSB first"
|
|
bitfld.long 0x00 22. "BYSW,Byte Swap" "0: Byte swap disabled,1: Byte swap enabled"
|
|
newline
|
|
bitfld.long 0x00 21. "CONT,Continuous Transfer" "0: Continuous transfer disabled,1: Continuous transfer enabled"
|
|
bitfld.long 0x00 20. "CONTC,Continuing Command" "0: Command word for start of new transfer,1: Command word for continuing transfer"
|
|
newline
|
|
bitfld.long 0x00 19. "RXMSK,Receive Data Mask" "0: Normal transfer,1: Receive data is masked"
|
|
bitfld.long 0x00 18. "TXMSK,Transmit Data Mask" "0: Normal transfer,1: Mask transmit data"
|
|
newline
|
|
bitfld.long 0x00 16.--17. "WIDTH,Transfer Width" "0: Single bit transfer,1: Two bit transfer,2: Four bit transfer,?..."
|
|
hexmask.long.word 0x00 0.--11. 1. "FRAMESZ,Frame Size"
|
|
wgroup.long 0x64++0x03
|
|
line.long 0x00 "TDR,Transmit Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RSR,Receive Status Register"
|
|
bitfld.long 0x00 1. "RXEMPTY,RX FIFO Empty" "0: RX FIFO is not empty,1: RX FIFO is empty"
|
|
bitfld.long 0x00 0. "SOF,Start Of Frame" "0: Subsequent data word received after LPSPI_PCS..,1: First data word received after LPSPI_PCS.."
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RDR,Receive Data Register"
|
|
hexmask.long 0x00 0.--31. 1. "DATA,Receive Data"
|
|
tree.end
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")
|
|
tree "PDB0 (Programmable Delay Block)"
|
|
base ad:0x40036000
|
|
sif cpuis("S32K116")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC,Status and Control register"
|
|
bitfld.long 0x00 18.--19. "LDMOD,Load Mode Select" "0: The internal registers are loaded with the..,1: The internal registers are loaded with the..,2: The internal registers are loaded with the..,3: The internal registers are loaded with the.."
|
|
bitfld.long 0x00 17. "PDBEIE,PDB Sequence Error Interrupt Enable" "0: PDB sequence error interrupt disabled,1: PDB sequence error interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 16. "SWTRIG,Software Trigger" "0,1"
|
|
bitfld.long 0x00 15. "DMAEN,DMA Enable" "0: DMA disabled,1: DMA enabled"
|
|
newline
|
|
bitfld.long 0x00 12.--14. "PRESCALER,Prescaler Divider Select" "0: Counting uses the peripheral clock divided by..,1: Counting uses the peripheral clock divided by..,2: Counting uses the peripheral clock divided by..,3: Counting uses the peripheral clock divided by..,4: Counting uses the peripheral clock divided by..,5: Counting uses the peripheral clock divided by..,6: Counting uses the peripheral clock divided by..,7: Counting uses the peripheral clock divided by.."
|
|
bitfld.long 0x00 8.--11. "TRGSEL,Trigger Input Source Select" "0: Trigger-In 0 is selected,1: Trigger-In 1 is selected,2: Trigger-In 2 is selected,3: Trigger-In 3 is selected,4: Trigger-In 4 is selected,5: Trigger-In 5 is selected,6: Trigger-In 6 is selected,7: Trigger-In 7 is selected,8: Trigger-In 8 is selected,9: Trigger-In 9 is selected,10: Trigger-In 10 is selected,11: Trigger-In 11 is selected,12: Trigger-In 12 is selected,13: Trigger-In 13 is selected,14: Trigger-In 14 is selected,15: Software trigger is selected"
|
|
newline
|
|
bitfld.long 0x00 7. "PDBEN,PDB Enable" "0: PDB disabled,1: PDB enabled"
|
|
bitfld.long 0x00 6. "PDBIF,PDB Interrupt Flag" "0,1"
|
|
newline
|
|
bitfld.long 0x00 5. "PDBIE,PDB Interrupt Enable" "0: PDB interrupt disabled,1: PDB interrupt enabled"
|
|
bitfld.long 0x00 2.--3. "MULT,Multiplication Factor Select for Prescaler" "0: Multiplication factor is 1,1: Multiplication factor is 10,2: Multiplication factor is 20,3: Multiplication factor is 40"
|
|
newline
|
|
bitfld.long 0x00 1. "CONT,Continuous Mode Enable" "0: PDB operation in One-Shot mode,1: PDB operation in Continuous mode"
|
|
bitfld.long 0x00 0. "LDOK,Load OK" "0,1"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "MOD,Modulus register"
|
|
hexmask.long.word 0x00 0.--15. 1. "MOD,PDB Modulus"
|
|
rgroup.long 0x08++0x03
|
|
line.long 0x00 "CNT,Counter register"
|
|
hexmask.long.word 0x00 0.--15. 1. "CNT,PDB Counter"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "IDLY,Interrupt Delay register"
|
|
hexmask.long.word 0x00 0.--15. 1. "IDLY,PDB Interrupt Delay"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "CH0C1,Channel n Control register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BB,PDB Channel Pre-Trigger Back-to-Back Operation Enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOS,PDB Channel Pre-Trigger Output Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EN,PDB Channel Pre-Trigger Enable"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "CH1C1,Channel n Control register 1"
|
|
hexmask.long.byte 0x00 16.--23. 1. "BB,PDB Channel Pre-Trigger Back-to-Back Operation Enable"
|
|
hexmask.long.byte 0x00 8.--15. 1. "TOS,PDB Channel Pre-Trigger Output Select"
|
|
newline
|
|
hexmask.long.byte 0x00 0.--7. 1. "EN,PDB Channel Pre-Trigger Enable"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "CH0S,Channel n Status register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CF,PDB Channel Flags"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERR,PDB Channel Sequence Error Flags"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "CH1S,Channel n Status register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "CF,PDB Channel Flags"
|
|
hexmask.long.byte 0x00 0.--7. 1. "ERR,PDB Channel Sequence Error Flags"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "CH0DLY0,Channel n Delay 0 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CH1DLY0,Channel n Delay 0 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "CH0DLY1,Channel n Delay 1 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CH1DLY1,Channel n Delay 1 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "CH0DLY2,Channel n Delay 2 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "CH1DLY2,Channel n Delay 2 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "CH0DLY3,Channel n Delay 3 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "CH1DLY3,Channel n Delay 3 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "CH0DLY4,Channel n Delay 4 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "CH1DLY4,Channel n Delay 4 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "CH0DLY5,Channel n Delay 5 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "CH1DLY5,Channel n Delay 5 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "CH0DLY6,Channel n Delay 6 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "CH1DLY6,Channel n Delay 6 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "CH0DLY7,Channel n Delay 7 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "CH1DLY7,Channel n Delay 7 register"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY,PDB Channel Delay"
|
|
group.long 0x190++0x03
|
|
line.long 0x00 "POEN,Pulse-Out n Enable register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "POEN,PDB Pulse-Out Enable"
|
|
group.long 0x194++0x03
|
|
line.long 0x00 "PODLY,Pulse-Out n Delay register"
|
|
hexmask.long.word 0x00 16.--31. 1. "DLY1,PDB Pulse-Out Delay 1"
|
|
hexmask.long.word 0x00 0.--15. 1. "DLY2,PDB Pulse-Out Delay 2"
|
|
group.word 0x194++0x01
|
|
line.word 0x00 "DLY2,PDB0_DLY2 register"
|
|
hexmask.word 0x00 0.--15. 1. "DLY2,DLY2"
|
|
group.word 0x196++0x01
|
|
line.word 0x00 "DLY1,PDB0_DLY1 register"
|
|
hexmask.word 0x00 0.--15. 1. "DLY1,DLY1"
|
|
endif
|
|
tree.end
|
|
tree "ADC0 (Analog-to-Digital Converter)"
|
|
base ad:0x4003B000
|
|
sif cpuis("S32K148")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC1A,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC1A,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "SC1A,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SC1B,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SC1B,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "SC1B,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SC1C,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SC1C,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "SC1C,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SC1D,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SC1D,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "SC1D,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC1E,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC1E,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "SC1E,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC1F,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC1F,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "SC1F,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC1G,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC1G,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "SC1G,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC1H,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC1H,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "SC1H,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SC1I,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SC1I,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SC1I,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SC1J,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SC1J,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "SC1J,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SC1K,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SC1K,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "SC1K,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SC1L,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SC1L,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "SC1L,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SC1M,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SC1M,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "SC1M,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SC1N,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SC1N,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "SC1N,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SC1O,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SC1O,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K142")||cpuis("S32K144")
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "SC1O,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SC1P,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--4. "ADCH,Input channel select" "0: Exernal channel 0 is selected as input,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,18: Exernal channel 18 is selected as input,19: Exernal channel 19 is selected as input,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SC1P,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "SC1P,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "CFG1,ADC Configuration Register 1"
|
|
bitfld.long 0x00 8. "CLRLTRG,Clear Latch Trigger in Trigger Handler Block" "0,1"
|
|
bitfld.long 0x00 5.--6. "ADIV,Clock Divide Select" "0: The divide ratio is 1 and the clock rate is..,1: The divide ratio is 2 and the clock rate is..,2: The divide ratio is 4 and the clock rate is..,3: The divide ratio is 8 and the clock rate is.."
|
|
newline
|
|
bitfld.long 0x00 2.--3. "MODE,Conversion mode selection" "0: 8-bit conversion,1: 12-bit conversion,2: 10-bit conversion,?..."
|
|
bitfld.long 0x00 0.--1. "ADICLK,Input Clock Select" "0: Alternate clock 1 (ADC_ALTCLK1),1: Alternate clock 2 (ADC_ALTCLK2),2: Alternate clock 3 (ADC_ALTCLK3),3: Alternate clock 4 (ADC_ALTCLK4)"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "CFG2,ADC Configuration Register 2"
|
|
hexmask.long.byte 0x00 0.--7. 1. "SMPLTS,Sample Time Select"
|
|
rgroup.long 0x48++0x03
|
|
line.long 0x00 "RA,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x4C++0x03
|
|
line.long 0x00 "RB,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x50++0x03
|
|
line.long 0x00 "RC,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x54++0x03
|
|
line.long 0x00 "RD,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x58++0x03
|
|
line.long 0x00 "RE,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "RF,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x60++0x03
|
|
line.long 0x00 "RG,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x64++0x03
|
|
line.long 0x00 "RH,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x68++0x03
|
|
line.long 0x00 "RI,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x6C++0x03
|
|
line.long 0x00 "RJ,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "RK,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x74++0x03
|
|
line.long 0x00 "RL,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x78++0x03
|
|
line.long 0x00 "RM,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x7C++0x03
|
|
line.long 0x00 "RN,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x80++0x03
|
|
line.long 0x00 "RO,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x84++0x03
|
|
line.long 0x00 "RP,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
repeat 2. (strings "1" "2" )(list 0x0 0x4 )
|
|
group.long ($2+0x88)++0x03
|
|
line.long 0x00 "CV$1,Compare Value Registers"
|
|
hexmask.long.word 0x00 0.--15. 1. "CV,Compare Value"
|
|
repeat.end
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "SC2,Status and Control Register 2"
|
|
rbitfld.long 0x00 24.--27. "TRGSTERR,Error in Multiplexed Trigger Request" "0: No error has occurred,1: An error has occurred,?..."
|
|
rbitfld.long 0x00 16.--19. "TRGSTLAT,Trigger Status" "0: No trigger request has been latched,1: A trigger request has been latched,?..."
|
|
newline
|
|
rbitfld.long 0x00 13.--14. "TRGPRNUM,Trigger Process Number" "0,1,2,3"
|
|
rbitfld.long 0x00 7. "ADACT,Conversion Active" "0: Conversion not in progress,1: Conversion in progress"
|
|
newline
|
|
bitfld.long 0x00 6. "ADTRG,Conversion Trigger Select" "0: Software trigger selected,1: Hardware trigger selected"
|
|
bitfld.long 0x00 5. "ACFE,Compare Function Enable" "0: Compare function disabled,1: Compare function enabled"
|
|
newline
|
|
bitfld.long 0x00 4. "ACFGT,Compare Function Greater Than Enable" "0,1"
|
|
bitfld.long 0x00 3. "ACREN,Compare Function Range Enable" "0,1"
|
|
newline
|
|
bitfld.long 0x00 2. "DMAEN,DMA Enable" "0: DMA is disabled,1: DMA is enabled and will assert the ADC DMA.."
|
|
bitfld.long 0x00 0.--1. "REFSEL,Voltage Reference Selection" "0: Default voltage reference pin pair that is..,1: Alternate reference voltage that is VALTH,?..."
|
|
group.long 0x94++0x03
|
|
line.long 0x00 "SC3,Status and Control Register 3"
|
|
bitfld.long 0x00 7. "CAL,Calibration" "0,1"
|
|
bitfld.long 0x00 3. "ADCO,Continuous Conversion Enable" "0: One conversion will be performed (or one set..,1: Continuous conversions will be performed (or.."
|
|
newline
|
|
bitfld.long 0x00 2. "AVGE,Hardware Average Enable" "0: Hardware average function disabled,1: Hardware average function enabled"
|
|
bitfld.long 0x00 0.--1. "AVGS,Hardware Average Select" "0: 4 samples averaged,1: 8 samples averaged,2: 16 samples averaged,3: 32 samples averaged"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "BASE_OFS,BASE Offset Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "BA_OFS,Base Offset Error Correction Value"
|
|
group.long 0x9C++0x03
|
|
line.long 0x00 "OFS,ADC Offset Correction Register"
|
|
hexmask.long.word 0x00 0.--15. 1. "OFS,Offset Error Correction Value"
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "USR_OFS,USER Offset Correction Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "USR_OFS,USER Offset Error Correction Value"
|
|
group.long 0xA4++0x03
|
|
line.long 0x00 "XOFS,ADC X Offset Correction Register"
|
|
bitfld.long 0x00 0.--5. "XOFS,X offset error correction value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
group.long 0xA8++0x03
|
|
line.long 0x00 "YOFS,ADC Y Offset Correction Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. "YOFS,Y offset error correction value"
|
|
group.long 0xAC++0x03
|
|
line.long 0x00 "G,ADC Gain Register"
|
|
hexmask.long.word 0x00 0.--10. 1. "G,Gain error adjustment factor for the overall conversion"
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "UG,ADC User Gain Register"
|
|
hexmask.long.word 0x00 0.--9. 1. "UG,User gain error correction value"
|
|
group.long 0xB4++0x03
|
|
line.long 0x00 "CLPS,ADC General Calibration Value Register S"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CLPS,Calibration Value"
|
|
group.long 0xB8++0x03
|
|
line.long 0x00 "CLP3,ADC Plus-Side General Calibration Value Register 3"
|
|
hexmask.long.word 0x00 0.--9. 1. "CLP3,Calibration Value"
|
|
group.long 0xBC++0x03
|
|
line.long 0x00 "CLP2,ADC Plus-Side General Calibration Value Register 2"
|
|
hexmask.long.word 0x00 0.--9. 1. "CLP2,Calibration Value"
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "CLP1,ADC Plus-Side General Calibration Value Register 1"
|
|
hexmask.long.word 0x00 0.--8. 1. "CLP1,Calibration Value"
|
|
group.long 0xC4++0x03
|
|
line.long 0x00 "CLP0,ADC Plus-Side General Calibration Value Register 0"
|
|
hexmask.long.byte 0x00 0.--7. 1. "CLP0,Calibration Value"
|
|
group.long 0xC8++0x03
|
|
line.long 0x00 "CLPX,ADC Plus-Side General Calibration Value Register X"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CLPX,Calibration Value"
|
|
group.long 0xCC++0x03
|
|
line.long 0x00 "CLP9,ADC Plus-Side General Calibration Value Register 9"
|
|
hexmask.long.byte 0x00 0.--6. 1. "CLP9,Calibration Value"
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "CLPS_OFS,ADC General Calibration Offset Value Register S"
|
|
bitfld.long 0x00 0.--3. "CLPS_OFS,CLPS Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD4++0x03
|
|
line.long 0x00 "CLP3_OFS,ADC Plus-Side General Calibration Offset Value Register 3"
|
|
bitfld.long 0x00 0.--3. "CLP3_OFS,CLP3 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xD8++0x03
|
|
line.long 0x00 "CLP2_OFS,ADC Plus-Side General Calibration Offset Value Register 2"
|
|
bitfld.long 0x00 0.--3. "CLP2_OFS,CLP2 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xDC++0x03
|
|
line.long 0x00 "CLP1_OFS,ADC Plus-Side General Calibration Offset Value Register 1"
|
|
bitfld.long 0x00 0.--3. "CLP1_OFS,CLP1 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "CLP0_OFS,ADC Plus-Side General Calibration Offset Value Register 0"
|
|
bitfld.long 0x00 0.--3. "CLP0_OFS,CLP0 Offset" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0xE4++0x03
|
|
line.long 0x00 "CLPX_OFS,ADC Plus-Side General Calibration Offset Value Register X"
|
|
hexmask.long.word 0x00 0.--11. 1. "CLPX_OFS,CLPX Offset"
|
|
group.long 0xE8++0x03
|
|
line.long 0x00 "CLP9_OFS,ADC Plus-Side General Calibration Offset Value Register 9"
|
|
hexmask.long.word 0x00 0.--11. 1. "CLP9_OFS,CLP9 Offset"
|
|
sif cpuis("S32K148")
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "aSC1A,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "aSC1A,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "aSC1B,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "aSC1B,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "aSC1C,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "aSC1C,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "aSC1D,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "aSC1D,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "aSC1E,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "aSC1E,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "aSC1F,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "aSC1F,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "aSC1G,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x120++0x03
|
|
line.long 0x00 "aSC1G,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "aSC1H,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "aSC1H,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "aSC1I,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "aSC1I,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "aSC1J,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x12C++0x03
|
|
line.long 0x00 "aSC1J,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "aSC1K,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x130++0x03
|
|
line.long 0x00 "aSC1K,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "aSC1L,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x134++0x03
|
|
line.long 0x00 "aSC1L,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "aSC1M,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x138++0x03
|
|
line.long 0x00 "aSC1M,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "aSC1N,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x13C++0x03
|
|
line.long 0x00 "aSC1N,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "aSC1O,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x140++0x03
|
|
line.long 0x00 "aSC1O,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "aSC1P,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x144++0x03
|
|
line.long 0x00 "aSC1P,ADC Status and Control Register 1 (alias)"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "SC1Q,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x148++0x03
|
|
line.long 0x00 "SC1Q,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "SC1R,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x14C++0x03
|
|
line.long 0x00 "SC1R,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "SC1S,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x150++0x03
|
|
line.long 0x00 "SC1S,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "SC1T,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x154++0x03
|
|
line.long 0x00 "SC1T,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "SC1U,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x158++0x03
|
|
line.long 0x00 "SC1U,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "SC1V,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x15C++0x03
|
|
line.long 0x00 "SC1V,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "SC1W,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x160++0x03
|
|
line.long 0x00 "SC1W,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "SC1X,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")
|
|
group.long 0x164++0x03
|
|
line.long 0x00 "SC1X,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,?,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
group.long 0x168++0x03
|
|
line.long 0x00 "SC1Y,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x16C++0x03
|
|
line.long 0x00 "SC1Z,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x170++0x03
|
|
line.long 0x00 "SC1AA,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x174++0x03
|
|
line.long 0x00 "SC1AB,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x178++0x03
|
|
line.long 0x00 "SC1AC,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x17C++0x03
|
|
line.long 0x00 "SC1AD,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x180++0x03
|
|
line.long 0x00 "SC1AE,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
group.long 0x184++0x03
|
|
line.long 0x00 "SC1AF,ADC Status and Control Register 1"
|
|
rbitfld.long 0x00 7. "COCO,Conversion Complete Flag" "0: Conversion is not completed,1: Conversion is completed"
|
|
bitfld.long 0x00 6. "AIEN,Interrupt Enable" "0: Conversion complete interrupt is disabled,1: Conversion complete interrupt is enabled"
|
|
newline
|
|
bitfld.long 0x00 0.--5. "ADCH,Input channel select" "0: Exernal intput channel 0 is selected,1: Exernal channel 1 is selected as input,2: Exernal channel 2 is selected as input,3: Exernal channel 3 is selected as input,4: Exernal channel 4 is selected as input,5: Exernal channel 5 is selected as input,6: Exernal channel 6 is selected as input,7: Exernal channel 7 is selected as input,8: Exernal channel 8 is selected as input,9: Exernal channel 9 is selected as input,10: Exernal channel 10 is selected as input,11: Exernal channel 11 is selected as input,12: Exernal channel 12 is selected as input,13: Exernal channel 13 is selected as input,14: Exernal channel 14 is selected as input,15: Exernal channel 15 is selected as input,?,?,?,?,?,21: Internal channel 0 is selected as input,22: Internal channel 1 is selected as input,23: Internal channel 2 is selected as input,?,?,26: Temp Sensor,27: Band Gap,28: Internal channel 3 is selected as input,29: VREFSH is selected as input,30: VREFSL is selected as input,31: Module is disabled,32: Internal channel 16 is selected as input,33: Exernal channel 17 is selected as input,34: Exernal channel 18 is selected as input,35: Exernal channel 19 is selected as input,36: Exernal channel 20 is selected as input,37: Exernal channel 21 is selected as input,38: Exernal channel 22 is selected as input,39: Exernal channel 23 is selected as input,40: Exernal channel 24 is selected as input,41: Exernal channel 25 is selected as input,42: Exernal channel 26 is selected as input,43: Exernal channel 27 is selected as input,44: Exernal channel 28 is selected as input,45: Exernal channel 29 is selected as input,46: Exernal channel 30 is selected as input,47: Exernal channel 31 is selected as input,48: Module is disabled,49: Module is disabled,50: Module is disabled,51: Module is disabled,52: Module is disabled,53: Module is disabled,54: Module is disabled,55: Module is disabled,56: Module is disabled,57: Module is disabled,58: Module is disabled,59: Module is disabled,60: Module is disabled,61: Module is disabled,62: Module is disabled,63: Module is disabled"
|
|
endif
|
|
sif cpuis("S32K146")||cpuis("S32K148")
|
|
rgroup.long 0x188++0x03
|
|
line.long 0x00 "aRA,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x18C++0x03
|
|
line.long 0x00 "aRB,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x190++0x03
|
|
line.long 0x00 "aRC,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x194++0x03
|
|
line.long 0x00 "aRD,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x198++0x03
|
|
line.long 0x00 "aRE,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x19C++0x03
|
|
line.long 0x00 "aRF,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1A0++0x03
|
|
line.long 0x00 "aRG,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1A4++0x03
|
|
line.long 0x00 "aRH,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1A8++0x03
|
|
line.long 0x00 "aRI,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1AC++0x03
|
|
line.long 0x00 "aRJ,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1B0++0x03
|
|
line.long 0x00 "aRK,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1B4++0x03
|
|
line.long 0x00 "aRL,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1B8++0x03
|
|
line.long 0x00 "aRM,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1BC++0x03
|
|
line.long 0x00 "aRN,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1C0++0x03
|
|
line.long 0x00 "aRO,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1C4++0x03
|
|
line.long 0x00 "aRP,ADC Data Result Registers (alias)"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1C8++0x03
|
|
line.long 0x00 "RQ,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1CC++0x03
|
|
line.long 0x00 "RR,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1D0++0x03
|
|
line.long 0x00 "RS,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1D4++0x03
|
|
line.long 0x00 "RT,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1D8++0x03
|
|
line.long 0x00 "RU,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1DC++0x03
|
|
line.long 0x00 "RV,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1E0++0x03
|
|
line.long 0x00 "RW,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1E4++0x03
|
|
line.long 0x00 "RX,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
endif
|
|
sif cpuis("S32K148")
|
|
rgroup.long 0x1E8++0x03
|
|
line.long 0x00 "RY,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1EC++0x03
|
|
line.long 0x00 "RZ,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1F0++0x03
|
|
line.long 0x00 "RAA,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1F4++0x03
|
|
line.long 0x00 "RAB,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1F8++0x03
|
|
line.long 0x00 "RAC,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x1FC++0x03
|
|
line.long 0x00 "RAD,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x200++0x03
|
|
line.long 0x00 "RAE,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
rgroup.long 0x204++0x03
|
|
line.long 0x00 "RAF,ADC Data Result Registers"
|
|
hexmask.long.word 0x00 0.--11. 1. "D,Data result"
|
|
endif
|
|
tree.end
|
|
endif
|
|
sif cpuis("S32K116")||cpuis("S32K118")||cpuis("S32K142")||cpuis("S32K144")||cpuis("S32K146")
|
|
tree "LPI2C0 (The LPI2C Memory Map/Register Definition can be found here.)"
|
|
base ad:0x40066000
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "VERID,Version ID Register"
|
|
hexmask.long.byte 0x00 24.--31. 1. "MAJOR,Major Version Number"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MINOR,Minor Version Number"
|
|
newline
|
|
hexmask.long.word 0x00 0.--15. 1. "FEATURE,Feature Specification Number"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PARAM,Parameter Register"
|
|
bitfld.long 0x00 8.--11. "MRXFIFO,Master Receive FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0.--3. "MTXFIFO,Master Transmit FIFO Size" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "MCR,Master Control Register"
|
|
bitfld.long 0x00 9. "RRF,Reset Receive FIFO" "0: No effect,1: Receive FIFO is reset"
|
|
bitfld.long 0x00 8. "RTF,Reset Transmit FIFO" "0: No effect,1: Transmit FIFO is reset"
|
|
newline
|
|
bitfld.long 0x00 3. "DBGEN,Debug Enable" "0: Master is disabled in debug mode,1: Master is enabled in debug mode"
|
|
bitfld.long 0x00 2. "DOZEN,Doze mode enable" "0: Master is enabled in Doze mode,1: Master is disabled in Doze mode"
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Master logic is not reset,1: Master logic is reset"
|
|
bitfld.long 0x00 0. "MEN,Master Enable" "0: Master logic is disabled,1: Master logic is enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "MSR,Master Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "MBF,Master Busy Flag" "0: I2C Master is idle,1: I2C Master is busy"
|
|
newline
|
|
bitfld.long 0x00 14. "DMF,Data Match Flag" "0: Have not received matching data,1: Have received matching data"
|
|
bitfld.long 0x00 13. "PLTF,Pin Low Timeout Flag" "0: Pin low timeout has not occurred or is disabled,1: Pin low timeout has occurred"
|
|
newline
|
|
bitfld.long 0x00 12. "FEF,FIFO Error Flag" "0: No error,1: Master sending or receiving data without.."
|
|
bitfld.long 0x00 11. "ALF,Arbitration Lost Flag" "0: Master has not lost arbitration,1: Master has lost arbitration"
|
|
newline
|
|
bitfld.long 0x00 10. "NDF,NACK Detect Flag" "0: Unexpected NACK not detected,1: Unexpected NACK was detected"
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Master has not generated a STOP condition,1: Master has generated a STOP condition"
|
|
newline
|
|
bitfld.long 0x00 8. "EPF,End Packet Flag" "0: Master has not generated a STOP or Repeated..,1: Master has generated a STOP or Repeated START.."
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
newline
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "MIER,Master Interrupt Enable Register"
|
|
bitfld.long 0x00 14. "DMIE,Data Match Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 13. "PLTIE,Pin Low Timeout Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 12. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt enabled,1: Interrupt disabled"
|
|
bitfld.long 0x00 11. "ALIE,Arbitration Lost Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 10. "NDIE,NACK Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 8. "EPIE,End Packet Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MDER,Master DMA Enable Register"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "MCFGR0,Master Configuration Register 0"
|
|
bitfld.long 0x00 9. "RDMO,Receive Data Match Only" "0: Received data is stored in the receive FIFO..,1: Received data is discarded unless the RMF is.."
|
|
bitfld.long 0x00 8. "CIRFIFO,Circular FIFO Enable" "0: Circular FIFO is disabled,1: Circular FIFO is enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "HRSEL,Host Request Select" "0: Host request input is pin HREQ,1: Host request input is input trigger"
|
|
bitfld.long 0x00 1. "HRPOL,Host Request Polarity" "0: Active low,1: Active high"
|
|
newline
|
|
bitfld.long 0x00 0. "HREN,Host Request Enable" "0: Host request input is disabled,1: Host request input is enabled"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "MCFGR1,Master Configuration Register 1"
|
|
bitfld.long 0x00 24.--26. "PINCFG,Pin Configuration" "0: LPI2C configured for 2-pin open drain mode,1: LPI2C configured for 2-pin output only mode..,2: LPI2C configured for 2-pin push-pull mode,3: LPI2C configured for 4-pin push-pull mode,4: LPI2C configured for 2-pin open drain mode..,5: LPI2C configured for 2-pin output only mode..,6: LPI2C configured for 2-pin push-pull mode..,7: LPI2C configured for 4-pin push-pull mode.."
|
|
bitfld.long 0x00 16.--18. "MATCFG,Match Configuration" "0: Match disabled,?,2: Match enabled (1st data word equals MATCH0 OR..,3: Match enabled (any data word equals MATCH0 OR..,4: Match enabled (1st data word equals MATCH0..,5: Match enabled (any data word equals MATCH0..,6: Match enabled (1st data word AND MATCH1..,7: Match enabled (any data word AND MATCH1.."
|
|
newline
|
|
bitfld.long 0x00 10. "TIMECFG,Timeout Configuration" "0: Pin Low Timeout Flag will set if SCL is low..,1: Pin Low Timeout Flag will set if either SCL.."
|
|
bitfld.long 0x00 9. "IGNACK,IGNACK" "0: LPI2C Master will receive ACK and NACK normally,1: LPI2C Master will treat a received NACK as if.."
|
|
newline
|
|
bitfld.long 0x00 8. "AUTOSTOP,Automatic STOP Generation" "0: No effect,1: STOP condition is automatically generated.."
|
|
bitfld.long 0x00 0.--2. "PRESCALE,Prescaler" "0: Divide by 1,1: Divide by 2,2: Divide by 4,3: Divide by 8,4: Divide by 16,5: Divide by 32,6: Divide by 64,7: Divide by 128"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "MCFGR2,Master Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
hexmask.long.word 0x00 0.--11. 1. "BUSIDLE,Bus Idle Timeout"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "MCFGR3,Master Configuration Register 3"
|
|
hexmask.long.word 0x00 8.--19. 1. "PINLOW,Pin Low Timeout"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "MDMR,Master Data Match Register"
|
|
hexmask.long.byte 0x00 16.--23. 1. "MATCH1,Match 1 Value"
|
|
hexmask.long.byte 0x00 0.--7. 1. "MATCH0,Match 0 Value"
|
|
repeat 2. (strings "0" "1" )(list 0x0 0x8 )
|
|
group.long ($2+0x48)++0x03
|
|
line.long 0x00 "MCCR$1,Master Clock Configuration Register $1"
|
|
bitfld.long 0x00 24.--29. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 16.--21. "SETHOLD,Setup Hold Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "CLKHI,Clock High Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.long 0x00 0.--5. "CLKLO,Clock Low Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
repeat.end
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "MFCR,Master FIFO Control Register"
|
|
bitfld.long 0x00 16.--17. "RXWATER,Receive FIFO Watermark" "0,1,2,3"
|
|
bitfld.long 0x00 0.--1. "TXWATER,Transmit FIFO Watermark" "0,1,2,3"
|
|
rgroup.long 0x5C++0x03
|
|
line.long 0x00 "MFSR,Master FIFO Status Register"
|
|
bitfld.long 0x00 16.--18. "RXCOUNT,Receive FIFO Count" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0.--2. "TXCOUNT,Transmit FIFO Count" "0,1,2,3,4,5,6,7"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "MTDR,Master Transmit Data Register"
|
|
bitfld.long 0x00 8.--10. "CMD,Command Data" "0: Transmit DATA[7:0],1: Receive (DATA[7:0] + 1) bytes,2: Generate STOP condition,3: Receive and discard (DATA[7:0] + 1) bytes,4: Generate (repeated) START and transmit..,5: Generate (repeated) START and transmit..,6: Generate (repeated) START and transmit..,7: Generate (repeated) START and transmit.."
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
|
|
rgroup.long 0x70++0x03
|
|
line.long 0x00 "MRDR,Master Receive Data Register"
|
|
bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: Receive FIFO is not empty,1: Receive FIFO is empty"
|
|
hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "SCR,Slave Control Register"
|
|
bitfld.long 0x00 5. "FILTDZ,Filter Doze Enable" "0: Filter remains enabled in Doze mode,1: Filter is disabled in Doze mode"
|
|
bitfld.long 0x00 4. "FILTEN,Filter Enable" "0: Disable digital filter and output delay..,1: Enable digital filter and output delay.."
|
|
newline
|
|
bitfld.long 0x00 1. "RST,Software Reset" "0: Slave logic is not reset,1: Slave logic is reset"
|
|
bitfld.long 0x00 0. "SEN,Slave Enable" "0: Slave mode is disabled,1: Slave mode is enabled"
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "SSR,Slave Status Register"
|
|
rbitfld.long 0x00 25. "BBF,Bus Busy Flag" "0: I2C Bus is idle,1: I2C Bus is busy"
|
|
rbitfld.long 0x00 24. "SBF,Slave Busy Flag" "0: I2C Slave is idle,1: I2C Slave is busy"
|
|
newline
|
|
rbitfld.long 0x00 15. "SARF,SMBus Alert Response Flag" "0: SMBus Alert Response disabled or not detected,1: SMBus Alert Response enabled and detected"
|
|
rbitfld.long 0x00 14. "GCF,General Call Flag" "0: Slave has not detected the General Call..,1: Slave has detected the General Call Address"
|
|
newline
|
|
rbitfld.long 0x00 13. "AM1F,Address Match 1 Flag" "0: Have not received ADDR1 or ADDR0/ADDR1 range..,1: Have received ADDR1 or ADDR0/ADDR1 range.."
|
|
rbitfld.long 0x00 12. "AM0F,Address Match 0 Flag" "0: Have not received ADDR0 matching address,1: Have received ADDR0 matching address"
|
|
newline
|
|
bitfld.long 0x00 11. "FEF,FIFO Error Flag" "0: FIFO underflow or overflow not detected,1: FIFO underflow or overflow detected"
|
|
bitfld.long 0x00 10. "BEF,Bit Error Flag" "0: Slave has not detected a bit error,1: Slave has detected a bit error"
|
|
newline
|
|
bitfld.long 0x00 9. "SDF,STOP Detect Flag" "0: Slave has not detected a STOP condition,1: Slave has detected a STOP condition"
|
|
bitfld.long 0x00 8. "RSF,Repeated Start Flag" "0: Slave has not detected a Repeated START..,1: Slave has detected a Repeated START condition"
|
|
newline
|
|
rbitfld.long 0x00 3. "TAF,Transmit ACK Flag" "0: Transmit ACK/NACK is not required,1: Transmit ACK/NACK is required"
|
|
rbitfld.long 0x00 2. "AVF,Address Valid Flag" "0: Address Status Register is not valid,1: Address Status Register is valid"
|
|
newline
|
|
rbitfld.long 0x00 1. "RDF,Receive Data Flag" "0: Receive Data is not ready,1: Receive data is ready"
|
|
rbitfld.long 0x00 0. "TDF,Transmit Data Flag" "0: Transmit data not requested,1: Transmit data is requested"
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "SIER,Slave Interrupt Enable Register"
|
|
bitfld.long 0x00 15. "SARIE,SMBus Alert Response Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 14. "GCIE,General Call Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 13. "AM1F,Address Match 1 Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 12. "AM0IE,Address Match 0 Interrupt Enable" "0: Interrupt enabled,1: Interrupt disabled"
|
|
newline
|
|
bitfld.long 0x00 11. "FEIE,FIFO Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 10. "BEIE,Bit Error Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 9. "SDIE,STOP Detect Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 8. "RSIE,Repeated Start Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 3. "TAIE,Transmit ACK Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 2. "AVIE,Address Valid Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
newline
|
|
bitfld.long 0x00 1. "RDIE,Receive Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
bitfld.long 0x00 0. "TDIE,Transmit Data Interrupt Enable" "0: Interrupt disabled,1: Interrupt enabled"
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "SDER,Slave DMA Enable Register"
|
|
bitfld.long 0x00 2. "AVDE,Address Valid DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
bitfld.long 0x00 1. "RDDE,Receive Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "TDDE,Transmit Data DMA Enable" "0: DMA request disabled,1: DMA request enabled"
|
|
group.long 0x124++0x03
|
|
line.long 0x00 "SCFGR1,Slave Configuration Register 1"
|
|
bitfld.long 0x00 16.--18. "ADDRCFG,Address Configuration" "0: Address match 0 (7-bit),1: Address match 0 (10-bit),2: Address match 0 (7-bit) or Address match 1..,3: Address match 0 (10-bit) or Address match 1..,4: Address match 0 (7-bit) or Address match 1..,5: Address match 0 (10-bit) or Address match 1..,6: From Address match 0 (7-bit) to Address match..,7: From Address match 0 (10-bit) to Address.."
|
|
bitfld.long 0x00 13. "HSMEN,High Speed Mode Enable" "0: Disables detection of Hs-mode master code,1: Enables detection of Hs-mode master code"
|
|
newline
|
|
bitfld.long 0x00 12. "IGNACK,Ignore NACK" "0: Slave will end transfer when NACK detected,1: Slave will not end transfer when NACK detected"
|
|
bitfld.long 0x00 11. "RXCFG,Receive Data Configuration" "0: Reading the receive data register will return..,1: Reading the receive data register when the.."
|
|
newline
|
|
bitfld.long 0x00 10. "TXCFG,Transmit Flag Configuration" "0: Transmit Data Flag will only assert during a..,1: Transmit Data Flag will assert whenever the.."
|
|
bitfld.long 0x00 9. "SAEN,SMBus Alert Enable" "0: Disables match on SMBus Alert,1: Enables match on SMBus Alert"
|
|
newline
|
|
bitfld.long 0x00 8. "GCEN,General Call Enable" "0: General Call address is disabled,1: General call address is enabled"
|
|
bitfld.long 0x00 3. "ACKSTALL,ACK SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 2. "TXDSTALL,TX Data SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
bitfld.long 0x00 1. "RXSTALL,RX SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
newline
|
|
bitfld.long 0x00 0. "ADRSTALL,Address SCL Stall" "0: Clock stretching disabled,1: Clock stretching enabled"
|
|
group.long 0x128++0x03
|
|
line.long 0x00 "SCFGR2,Slave Configuration Register 2"
|
|
bitfld.long 0x00 24.--27. "FILTSDA,Glitch Filter SDA" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 16.--19. "FILTSCL,Glitch Filter SCL" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 8.--13. "DATAVD,Data Valid Delay" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
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bitfld.long 0x00 0.--3. "CLKHOLD,Clock Hold Time" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0x140++0x03
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line.long 0x00 "SAMR,Slave Address Match Register"
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hexmask.long.word 0x00 17.--26. 1. "ADDR1,Address 1 Value"
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hexmask.long.word 0x00 1.--10. 1. "ADDR0,Address 0 Value"
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rgroup.long 0x150++0x03
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line.long 0x00 "SASR,Slave Address Status Register"
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bitfld.long 0x00 14. "ANV,Address Not Valid" "0: RADDR is valid,1: RADDR is not valid"
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hexmask.long.word 0x00 0.--10. 1. "RADDR,Received Address"
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group.long 0x154++0x03
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line.long 0x00 "STAR,Slave Transmit ACK Register"
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bitfld.long 0x00 0. "TXNACK,Transmit NACK" "0: Transmit ACK for received word,1: Transmit NACK for received word"
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group.long 0x160++0x03
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line.long 0x00 "STDR,Slave Transmit Data Register"
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hexmask.long.byte 0x00 0.--7. 1. "DATA,Transmit Data"
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rgroup.long 0x170++0x03
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line.long 0x00 "SRDR,Slave Receive Data Register"
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bitfld.long 0x00 15. "SOF,Start Of Frame" "0: Indicates this is not the first data word..,1: Indicates this is the first data word since a.."
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bitfld.long 0x00 14. "RXEMPTY,RX Empty" "0: The Receive Data Register is not empty,1: The Receive Data Register is empty"
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newline
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hexmask.long.byte 0x00 0.--7. 1. "DATA,Receive Data"
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tree.end
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endif
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sif cpuis("S32K116")||cpuis("S32K118")
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tree "CMU_FC"
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repeat 2. (list 0. 1.) (list ad:0x4003E000 ad:0x4003F000)
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tree "CMU_FC_$1"
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base $2
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group.long 0x00++0x03
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line.long 0x00 "GCR,CMU Frequency Check Global Configuration Register"
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bitfld.long 0x00 0. "FCE,Frequency Check Enable" "0: Frequency Check Disabled,1: Frequency Check Enabled"
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group.long 0x04++0x03
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line.long 0x00 "RCCR,CMU Frequency Check Reference Count Configuration Register"
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hexmask.long.word 0x00 0.--15. 1. "REF_CNT,Reference Clock Count"
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|
group.long 0x08++0x03
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|
line.long 0x00 "HTCR,CMU Frequency Check High Threshold Configuration Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "HFREF,High Frequency Reference Threshold"
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group.long 0x0C++0x03
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line.long 0x00 "LTCR,CMU Frequency Check Low Threshold Configuration Register"
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hexmask.long.tbyte 0x00 0.--23. 1. "LFREF,Low Frequency Reference Threshold"
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group.long 0x10++0x03
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line.long 0x00 "SR,CMU Frequency Check Status Register"
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rbitfld.long 0x00 4. "RS,Run Status" "0: Frequency Check Stopped,1: Frequency Check Running"
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rbitfld.long 0x00 2.--3. "STATE,Module State" "0: Configure State- Configuration registers and..,1: Initialization State- Register configurations..,2: Initialization Wait State- The module stays..,3: Frequency Check State- The module is ready to.."
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|
newline
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bitfld.long 0x00 1. "FHH,Frequency Higher than High Frequency Reference Threshold Event Status" "0: No FHH Event,1: FHH Event Occured"
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|
bitfld.long 0x00 0. "FLL,Frequency Lower than Low Frequency Reference Threshold Event Status" "0: No FLL Event,1: FLL Event Occured"
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|
group.long 0x14++0x03
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|
line.long 0x00 "IER,CMU Frequency Check Interrupt/Event Enable Register"
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|
bitfld.long 0x00 3. "FHHAEE,Frequency Higher than High Frequency Reference Threshold Asynchronous Event Enable" "0: Asynchronous FHH Event is Disabled,1: Asynchronous FHH Event is Enabled"
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bitfld.long 0x00 2. "FLLAEE,Frequency Lower than Low Frequency Reference Threshold Asynchronous Event Enable" "0: Asynchronous FLL Event is Disabled,1: Asynchronous FLL Event is Enabled"
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|
newline
|
|
bitfld.long 0x00 1. "FHHIE,Frequency Higher than High Frequency Reference Threshold Interrupt Enable" "0: FHH Interrupt is Disabled,1: FHH Interrupt is Enabled"
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|
bitfld.long 0x00 0. "FLLIE,Frequency Lower than Low Frequency Reference Threshold Interrupt Enable" "0: FLL Interrupt is Disabled,1: FLL Interrupt is Enabled"
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|
tree.end
|
|
repeat.end
|
|
tree.end
|
|
endif
|
|
autoindent.off
|
|
newline
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