13246 lines
1.0 MiB
13246 lines
1.0 MiB
; --------------------------------------------------------------------------------
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; @Title: RA2L1 On-Chip Peripherals
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; @Props: Released
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; @Author: KWI, ADR, JDU, NEJ
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; @Changelog: 2021-02-11 KWI
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; 2022-01-28 ADR
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; 2023-03-13 JDU
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; 2023-09-11 NEJ
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; @Manufacturer: RENESAS - Renesas Technology, Corp.
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; @Doc: Generated (Trace32 Version S.2023.09.000162625M), based on: R7FA2L1AB.svd (Rev. 1.30.00)
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; @Core: Cortex-M23
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; @Chip: R7FA2L1A92DFL, R7FA2L1A92DFM, R7FA2L1A92DFN, R7FA2L1A92DFP,
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; R7FA2L1A92DNE, R7FA2L1A93CFL, R7FA2L1A93CFM, R7FA2L1A93CFN,
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; R7FA2L1A93CFP, R7FA2L1A93CNE, R7FA2L1AB2DFL, R7FA2L1AB2DFM,
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; R7FA2L1AB2DFN, R7FA2L1AB2DFP, R7FA2L1AB2DNE, R7FA2L1AB3CFL,
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; R7FA2L1AB3CFM, R7FA2L1AB3CFN, R7FA2L1AB3CFP, R7FA2L1AB3CNE
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; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perra2l1.per 16620 2023-09-14 10:36:24Z apopow $
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tree.close "Core Registers (Cortex-M23)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 12.
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group.long 0x08++0x03
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line.long 0x00 "ACTLR,Auxiliary Control Register"
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bitfld.long 0x00 29. " EXTEXCLALL ,LDREX and STREX instructions use the Global Exclusive Monitor" "Only on Shared regions,Always"
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newline
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group.long 0x10++0x03
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line.long 0x00 "SYST_CSR,SysTick Control and Status Register"
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rbitfld.long 0x00 16. " COUNTFLAG ,Counter Flag" "Not counted,Counted"
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bitfld.long 0x00 2. " CLKSOURCE ,SysTick clock source" "External,Core"
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bitfld.long 0x00 1. " TICKINT ,SysTick Handler" "No SysTick,SysTick"
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newline
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bitfld.long 0x00 0. " ENABLE ,Counter Enable" "Disabled,Enabled"
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group.long 0x14++0x07
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line.long 0x00 "SYST_RVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x00 0.--23. 1. " RELOAD ,The value to load into the SYST_CVR when the counter reaches 0"
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line.long 0x04 "SYST_CVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " CURRENT ,Current counter value"
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rgroup.long 0x1C++0x03
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line.long 0x00 "SYST_CALIB,SysTick Calibration value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the implementation defined reference clock is implemented" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing"
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rgroup.long 0xD00++0x03
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line.long 0x00 "CPUID,CPUID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Indicates implementer"
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bitfld.long 0x00 20.--23. " VARIANT ,Indicates processor revision" "Revision 0,Revision 1,?..."
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bitfld.long 0x00 16.--19. " ARCHITECTURE ,Architecture" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,ARMv8-M w/o Main extension,Reserved,Reserved,ARMv8-M w/ Main extension"
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newline
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hexmask.long.word 0x00 4.--15. 1. " PARTNO ,Indicates part number"
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bitfld.long 0x00 0.--3. " REVISION ,Indicates patch release" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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group.long 0xD04++0x13
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line.long 0x00 "ICSR,Interrupt Control and State Register"
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setclrfld.long 0x00 31. 0x00 31. 0x00 30. " PENDNMISET ,On writes allows the NMI exception to be set as pending. On reads indicates whether the NMI exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 28. 0x00 28. 0x00 27. " PENDSVSET ,On writes allows the PendSV exception for the selected Security state to be set as pending. On reads indicates whether the PendSV for the selected Security state exception is pending" "Not pending,Pending"
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setclrfld.long 0x00 26. 0x00 26. 0x00 25. " PENDSTSET ,On writes, sets the SysTick exception as pending. On reads, indicates the current state of the exception" "Not pending,Pending"
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newline
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bitfld.long 0x00 24. " STTNS ,Controls whether in a single SysTick implementation the SysTick is Secure or Non-secure" "Secure,Non-secure"
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rbitfld.long 0x00 23. " ISRPREEMPT ,Indicates whether a pending exception will be serviced on exit from debug halt state" "Disabled,Enabled"
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rbitfld.long 0x00 22. " ISRPENDING ,Indicates whether an external interrupt, generated by the NVIC, is pending" "Not pending,Pending"
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newline
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hexmask.long.word 0x00 12.--20. 1. " VECTPENDING ,The exception number of the highest priority pending and enabled interrupt"
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rbitfld.long 0x00 11. " RETTOBASE ,Indicates whether there is an active exception other than the exception indicated by the current value of the IPSR" "Present,Absent"
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hexmask.long.word 0x00 0.--8. 1. " VECTACTIVE ,The exception number of the current executing exception"
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line.long 0x04 "VTOR,Vector Table Offset Register"
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hexmask.long 0x04 7.--31. 0x80 " TBLOFF ,Bits[31:7] of the vector table address"
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line.long 0x08 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x08 16.--31. 1. " VECTKEYSTAT ,Vector Key"
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rbitfld.long 0x08 15. " ENDIANNESS ,Indicates the memory system endianness" "Little endian,Big endian"
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bitfld.long 0x08 14. " PRIS ,Prioritize Secure exceptions" "Disabled,Enabled"
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newline
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bitfld.long 0x08 13. " BFHFNMINS ,BusFault BusFault HardFault and NMI Non-secure enable" "Disabled,Enabled"
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bitfld.long 0x08 8.--10. " PRIGROUP ,Priority grouping. Group priority field bits/Subpriority field bits" "[7:1]/[0],[7:2]/[1:0],[7:3]/[2:0],[7:4]/[3:0],[7:5]/[4:0],[7:6]/[5:0],[7]/[6:0],-/[7:0]"
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bitfld.long 0x08 3. " SYSRESETREQS ,System reset request Secure only" "Both states,Secure only"
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newline
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bitfld.long 0x08 2. " SYSRESETREQ ,System reset request" "Not requested,Requested"
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bitfld.long 0x08 1. " VECTCLRACTIVE ,Writing 1 to this bit clears all active state information for fixed and configurable exceptions" "No effect,Clear"
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line.long 0x0C "SCR,System Control Register"
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bitfld.long 0x0C 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x0C 3. " SLEEPDEEPS ,Controls whether the SLEEPDEEP bit is only accessible from the secure state" "Both states,Secure only"
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bitfld.long 0x0C 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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newline
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bitfld.long 0x0C 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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line.long 0x10 "CCR,Configuration and Control Register"
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bitfld.long 0x10 18. " BP ,Branch prediction enable bit" "Disabled,Enabled"
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bitfld.long 0x10 17. " IC ,Instruction cache enable bit" "Disabled,Enabled"
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bitfld.long 0x10 16. " DC ,Cache enable bit" "Disabled,Enabled"
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newline
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bitfld.long 0x10 10. " STKOFHFNMIGN ,Controls the effect of a stack limit violation while executing at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 8. " BFHFNMIGN ,Determines the effect of precise busfaults on handlers running at a requested priority less than 0" "Not ignored,Ignored"
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bitfld.long 0x10 4. " DIV_0_TRP ,Controls the trap on divide by 0" "Disabled,Enabled"
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newline
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bitfld.long 0x10 3. " UNALIGN_TRP ,Controls the trapping of unaligned word or halfword accesses" "Disabled,Enabled"
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bitfld.long 0x10 1. " USERSETMPEND ,Controls whether unprivileged software can access the STIR" "Disabled,Enabled"
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group.long 0xD1C++0x0B
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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hexmask.long.byte 0x00 24.--31. 1. " PRI_11 ,Priority of system handler 11, SVCall"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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hexmask.long.byte 0x04 24.--31. 1. " PRI_15 ,Priority of system handler 15, SysTick"
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hexmask.long.byte 0x04 16.--23. 1. " PRI_14 ,Priority of system handler 14, PendSV"
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hexmask.long.byte 0x04 0.--7. 1. " PRI_12 ,Priority of system handler 12, DebugMonitor"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 21. " HARDFAULTPENDED ,HardFault exception status" "Not pending,Pending"
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bitfld.long 0x08 20. " SECUREFAULTPENDED ,SecureFault exception status" "Not pending,Pending"
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bitfld.long 0x08 19. " SECUREFAULTENA ,SecureFault exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 18. " USGFAULTENA ,UsageFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 17. " BUSFAULTENA ,BusFault exception enable" "Disabled,Enabled"
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bitfld.long 0x08 16. " MEMFAULTENA ,MemManage exception enable" "Disabled,Enabled"
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newline
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bitfld.long 0x08 15. " SVCALLPENDED ,SVCall exception status" "Not pending,Pending"
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bitfld.long 0x08 14. " BUSFAULTPENDED ,BusFault exception status" "Not pending,Pending"
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bitfld.long 0x08 13. " MEMFAULTPENDED ,MemManage exception status" "Not pending,Pending"
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newline
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bitfld.long 0x08 12. " USGFAULTPENDED ,UsageFault exception status" "Not pending,Pending"
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bitfld.long 0x08 11. " SYSTICKACT ,SysTick exception status" "Not active,Active"
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bitfld.long 0x08 10. " PENDSVACT ,PendSV exception status" "Not active,Active"
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newline
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bitfld.long 0x08 8. " MONITORACT ,Monitor exception status" "Not active,Active"
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bitfld.long 0x08 7. " SVCALLACT ,SVCall exception status" "Not active,Active"
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bitfld.long 0x08 5. " NMIACT ,NMI exception status" "Not active,Active"
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newline
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bitfld.long 0x08 4. " SECUREFAULTACT ,SecureFault exception status" "Not active,Active"
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bitfld.long 0x08 3. " USGFAULTACT ,UsageFault exception status" "Not active,Active"
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bitfld.long 0x08 2. " HARDFAULTACT ,HardFault exception status for the selected Security state" "Not active,Active"
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newline
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bitfld.long 0x08 1. " BUSFAULTACT ,BusFault exception status" "Not active,Active"
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bitfld.long 0x08 0. " MEMFAULTACT ,MemManage exception status" "Not active,Active"
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tree "Memory System"
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width 10.
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rgroup.long 0xD78++0x0B
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line.long 0x00 "CLIDR,Cache Level ID Register"
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bitfld.long 0x00 30.--31. " ICB ,Inner cache boundary" "Not disclosed,L1 cache highest,L2 cache highest,L3 cache highest"
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bitfld.long 0x00 27.--29. " LOU ,LOUU" "Level 1,Level 2,?..."
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bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,?..."
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textline " "
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bitfld.long 0x00 18.--20. " CL7 ,Cache type field level 7" "No cache,Instr. only,Data only,Data and Instr.,Unified cache,?..."
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line.long 0x04 "CTR,Cache Type Register"
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bitfld.long 0x04 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,?..."
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bitfld.long 0x04 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,?..."
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textline " "
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bitfld.long 0x04 16.--19. " DMINLINE ,Log 2 of the number of words in the smallest cache line of all the data caches and unified caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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bitfld.long 0x04 0.--3. " IMINLINE ,Log 2 of the number of words in the smallest cache line of all the instruction caches that are controlled by the processor" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
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line.long 0x08 "CCSIDR,Cache Size ID Register"
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bitfld.long 0x08 31. " WT ,Indicates support available for Write-Through" "Not supported,Supported"
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bitfld.long 0x08 30. " WB ,Indicates support available for Write-Back" "Not supported,Supported"
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bitfld.long 0x08 29. " RA ,Indicates support available for read allocation" "Not supported,Supported"
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textline " "
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bitfld.long 0x08 28. " WA ,Indicates support available for write allocation" "Not supported,Supported"
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hexmask.long.word 0x08 13.--27. 1. " NUMSETS ,Indicates the number of sets as (number of sets) - 1"
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hexmask.long.word 0x08 3.--12. 1. " ASSOCIATIVITY ,Indicates the number of ways as (number of ways) - 1"
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textline " "
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bitfld.long 0x08 0.--2. " LINESIZE ,Indicates the number of words in each cache line" "4,8,16,32,64,128,256,512"
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group.long 0xD84++0x03
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line.long 0x00 "CSSELR,Cache Size Selection Register"
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bitfld.long 0x00 1.--3. " LEVEL ,Identifies which cache level to select" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,?..."
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bitfld.long 0x00 0. " IND ,Identifies instruction or data cache to use" "Data/Unified,Instruction"
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wgroup.long 0xF50++0x03
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line.long 0x00 "ICIALLU,I-Cache Invalidate All to PoU"
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wgroup.long 0xF58++0x23
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line.long 0x00 "ICIMVAU,I-Cache Invalidate by MVA to PoU"
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line.long 0x04 "DCIMVAC,D-Cache Invalidate by MVA to PoC"
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line.long 0x08 "DCISW,D-Cache Invalidate by Set-Way"
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hexmask.long 0x08 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x08 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x0C "DCCMVAU,D-Cache Clean by MVA to PoU"
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line.long 0x10 "DCCMVAC,D-Cache Clean by MVA to PoC"
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line.long 0x14 "DCCSW,D-Cache Clean by Set-Way"
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hexmask.long 0x14 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x14 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x18 "DCCIMVAC,D-Cache Clean and Invalidate by MVA to PoC"
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line.long 0x1C "DCCISW,D-Cache Clean and Invalidate by Set-Way"
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hexmask.long 0x1C 4.--31. 1. " SETWAY ,Defines number of the way to operate on and number of the set to operate on"
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bitfld.long 0x1C 1.--3. " LEVEL ,Cache level to operate on, minus" "L1,L2,L3,L4,L5,L6,L7,L8"
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line.long 0x20 "BPIALL,Branch Predictor Invalidate All"
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tree.end
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width 11.
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tree "CoreSight Identification Registers"
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rgroup.long 0xFE0++0x0F
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line.long 0x00 "DPIDR0,Peripheral ID0"
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hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
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line.long 0x04 "DPIDR1,Peripheral ID1"
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hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
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hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
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line.long 0x08 "DPIDR2,Peripheral ID2"
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hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
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bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
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hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
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line.long 0x0c "DPIDR3,Peripheral ID3"
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hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
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hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
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rgroup.long 0xFD0++0x03
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line.long 0x00 "PID4,Peripheral Identification Register 4"
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hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
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hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
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rgroup.long 0xFF0++0x0F
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line.long 0x00 "DCIDR0,Component ID0 (Preamble)"
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hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
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line.long 0x04 "DCIDR1,Component ID1"
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hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
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hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
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line.long 0x08 "DCIDR2,Component ID2"
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hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
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line.long 0x0C "DCIDR3,Component ID3"
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hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
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tree.end
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width 0x0B
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. " DREGION ,Number of regions supported by the MPU" "0,,,,4,,,,8,,,,,,,,16,?..."
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bitfld.long 0x00 0. " SEPARATE ,Indicates support for separate instruction and data address maps" "Not supported,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
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bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
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bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
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newline
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bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
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hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
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bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
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bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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newline
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
|
|
hide.long 0x00 "MPU_RLAR0,MPU Region Attribute and Size Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
|
|
group.long 0xD9C++0x03 "Region 1"
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
line.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x1
|
|
hide.long 0x00 "MPU_RLAR1,MPU Region Attribute and Size Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
|
|
group.long 0xD9C++0x03 "Region 2"
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
line.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x2
|
|
hide.long 0x00 "MPU_RLAR2,MPU Region Attribute and Size Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
|
|
group.long 0xD9C++0x03 "Region 3"
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
line.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RLAR3,MPU Region Attribute and Size Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RLAR4,MPU Region Attribute and Size Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RLAR5,MPU Region Attribute and Size Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RLAR6,MPU Region Attribute and Size Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RLAR7,MPU Region Attribute and Size Register 7"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x8
|
|
group.long 0xD9C++0x03 "Region 8"
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
line.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 8 (not implemented)"
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RBAR8,MPU Region Base Address Register 8"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x8
|
|
hide.long 0x00 "MPU_RLAR8,MPU Region Attribute and Size Register 8"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x9
|
|
group.long 0xD9C++0x03 "Region 9"
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
line.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 9 (not implemented)"
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RBAR9,MPU Region Base Address Register 9"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x9
|
|
hide.long 0x00 "MPU_RLAR9,MPU Region Attribute and Size Register 9"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xA
|
|
group.long 0xD9C++0x03 "Region 10"
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
line.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 10 (not implemented)"
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RBAR10,MPU Region Base Address Register 10"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xA
|
|
hide.long 0x00 "MPU_RLAR10,MPU Region Attribute and Size Register 10"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xB
|
|
group.long 0xD9C++0x03 "Region 11"
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
line.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 11 (not implemented)"
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RBAR11,MPU Region Base Address Register 11"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xB
|
|
hide.long 0x00 "MPU_RLAR11,MPU Region Attribute and Size Register 11"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xC
|
|
group.long 0xD9C++0x03 "Region 12"
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
line.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 12 (not implemented)"
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RBAR12,MPU Region Base Address Register 12"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xC
|
|
hide.long 0x00 "MPU_RLAR12,MPU Region Attribute and Size Register 12"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xD
|
|
group.long 0xD9C++0x03 "Region 13"
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
line.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 13 (not implemented)"
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RBAR13,MPU Region Base Address Register 13"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xD
|
|
hide.long 0x00 "MPU_RLAR13,MPU Region Attribute and Size Register 13"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xE
|
|
group.long 0xD9C++0x03 "Region 14"
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
line.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 14 (not implemented)"
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RBAR14,MPU Region Base Address Register 14"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xE
|
|
hide.long 0x00 "MPU_RLAR14,MPU Region Attribute and Size Register 14"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0xF
|
|
group.long 0xD9C++0x03 "Region 15"
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
bitfld.long 0x00 3.--4. " SH ,Defines the shareability domain of this region for Normal memory" "Non-shareable,,Outer Shareable,Inner Shareable"
|
|
bitfld.long 0x00 1.--2. " AP ,Defines the access permissions for this region" "R/W privileged,R/W any,RO privileged,RO any"
|
|
newline
|
|
bitfld.long 0x00 0. " XN ,Defines whether code can be executed from this region" "Not permitted,Permitted"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
line.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
hexmask.long 0x00 5.--31. 0x20 " LIMIT ,Contains bits [31:5] of the upper inclusive limit of the selected MPU memory region"
|
|
bitfld.long 0x00 1.--3. " ATTRINDX ,Associates a set of attributes in the MPU_MAIR0 and MPU_MAIR1 fields" "0,1,2,3,4,5,6,7"
|
|
bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 15 (not implemented)"
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RBAR15,MPU Region Base Address Register 15"
|
|
newline
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0xF
|
|
hide.long 0x00 "MPU_RLAR15,MPU Region Attribute and Size Register 15"
|
|
endif
|
|
tree.end
|
|
newline
|
|
group.long 0xDC0++0x07
|
|
line.long 0x00 "MPU_MAIR0,MPU Memory Attribute Indirection Register 0"
|
|
hexmask.long.byte 0x00 24.--31. 1. " ATTR3 ,Memory attribute encoding for MPU regions with an AttrIndex of 3"
|
|
hexmask.long.byte 0x00 16.--23. 1. " ATTR2 ,Memory attribute encoding for MPU regions with an AttrIndex of 2"
|
|
hexmask.long.byte 0x00 8.--15. 1. " ATTR1 ,Memory attribute encoding for MPU regions with an AttrIndex of 1"
|
|
hexmask.long.byte 0x00 0.--7. 1. " ATTR0 ,Memory attribute encoding for MPU regions with an AttrIndex of 0"
|
|
line.long 0x04 "MPU_MAIR1,MPU Memory Attribute Indirection Register 1"
|
|
hexmask.long.byte 0x04 24.--31. 1. " ATTR7 ,Memory attribute encoding for MPU regions with an AttrIndex of 7"
|
|
hexmask.long.byte 0x04 16.--23. 1. " ATTR6 ,Memory attribute encoding for MPU regions with an AttrIndex of 6"
|
|
hexmask.long.byte 0x04 8.--15. 1. " ATTR5 ,Memory attribute encoding for MPU regions with an AttrIndex of 5"
|
|
hexmask.long.byte 0x04 0.--7. 1. " ATTR4 ,Memory attribute encoding for MPU regions with an AttrIndex of 4"
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Security Attribution Unit (SAU)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 15.
|
|
group.long 0xDD0++0x03
|
|
line.long 0x00 "SAU_CTRL,SAU Control Register"
|
|
bitfld.long 0x00 1. " ALLNS ,When SAU_CTRL.ENABLE is 0 this bit controls if the memory is marked as Non-secure or Secure" "Secure,Non-Secure"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables the SAU" "Disabled,Enabled"
|
|
rgroup.long 0xDD4++0x03
|
|
line.long 0x00 "SAU_TYPE,SAU Type Register"
|
|
bitfld.long 0x00 0.--7. " SREGION ,The number of implemented SAU regions" "0,,,,4,,,,8,?..."
|
|
group.long 0xDD8++0x03
|
|
line.long 0x00 "SAU_RNR,SAU Region Number Register"
|
|
hexmask.long.byte 0x00 0.--7. 1. " SAU_RNR ,Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR"
|
|
tree.close "SAU regions"
|
|
if ADDRESS.isSECUREEX(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD0)
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x0
|
|
group.long 0xDDC++0x03 "Region 0"
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
line.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not implemented)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x1
|
|
group.long 0xDDC++0x03 "Region 1"
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
line.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not implemented)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x2
|
|
group.long 0xDDC++0x03 "Region 2"
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
line.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not implemented)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x3
|
|
group.long 0xDDC++0x03 "Region 3"
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
line.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not implemented)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x4
|
|
group.long 0xDDC++0x03 "Region 4"
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
line.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not implemented)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x5
|
|
group.long 0xDDC++0x03 "Region 5"
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
line.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not implemented)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x6
|
|
group.long 0xDDC++0x03 "Region 6"
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
line.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not implemented)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDD4)&0xFF))>0x7
|
|
group.long 0xDDC++0x03 "Region 7"
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
line.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hexmask.long 0x00 5.--31. 0x20 " LADDR ,Holds bits [31:5] of the limit address for the selected SAU region"
|
|
bitfld.long 0x00 1. " NSC ,Controls whether Non-secure state is permitted to execute an SG instruction from this region" "Not permitted,Permitted"
|
|
bitfld.long 0x00 0. " ENABLE ,SAU region enable" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not implemented)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
endif
|
|
else
|
|
hgroup.long 0xDDC++0x03 "Region 0 (not accessible)"
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RBAR0,SAU Region Base Address Register 0"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x0
|
|
hide.long 0x00 "SAU_RLAR0,SAU Region Limit Address Register 0"
|
|
hgroup.long 0xDDC++0x03 "Region 1 (not accessible)"
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RBAR1,SAU Region Base Address Register 1"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x1
|
|
hide.long 0x00 "SAU_RLAR1,SAU Region Limit Address Register 1"
|
|
hgroup.long 0xDDC++0x03 "Region 2 (not accessible)"
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RBAR2,SAU Region Base Address Register 2"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x2
|
|
hide.long 0x00 "SAU_RLAR2,SAU Region Limit Address Register 2"
|
|
hgroup.long 0xDDC++0x03 "Region 3 (not accessible)"
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RBAR3,SAU Region Base Address Register 3"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x3
|
|
hide.long 0x00 "SAU_RLAR3,SAU Region Limit Address Register 3"
|
|
hgroup.long 0xDDC++0x03 "Region 4 (not accessible)"
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RBAR4,SAU Region Base Address Register 4"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x4
|
|
hide.long 0x00 "SAU_RLAR4,SAU Region Limit Address Register 4"
|
|
hgroup.long 0xDDC++0x03 "Region 5 (not accessible)"
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RBAR5,SAU Region Base Address Register 5"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x5
|
|
hide.long 0x00 "SAU_RLAR5,SAU Region Limit Address Register 5"
|
|
hgroup.long 0xDDC++0x03 "Region 6 (not accessible)"
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RBAR6,SAU Region Base Address Register 6"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x6
|
|
hide.long 0x00 "SAU_RLAR6,SAU Region Limit Address Register 6"
|
|
hgroup.long 0xDDC++0x03 "Region 7 (not accessible)"
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RBAR7,SAU Region Base Address Register 7"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x7
|
|
hide.long 0x00 "SAU_RLAR7,SAU Region Limit Address Register 7"
|
|
hgroup.long 0xDDC++0x03 "Region 8 (not accessible)"
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RBAR8,SAU Region Base Address Register 8"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x8
|
|
hide.long 0x00 "SAU_RLAR8,SAU Region Limit Address Register 8"
|
|
hgroup.long 0xDDC++0x03 "Region 9 (not accessible)"
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RBAR9,SAU Region Base Address Register 9"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0x9
|
|
hide.long 0x00 "SAU_RLAR9,SAU Region Limit Address Register 9"
|
|
hgroup.long 0xDDC++0x03 "Region 10 (not accessible)"
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RBAR10,SAU Region Base Address Register 10"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xA
|
|
hide.long 0x00 "SAU_RLAR10,SAU Region Limit Address Register 10"
|
|
hgroup.long 0xDDC++0x03 "Region 11 (not accessible)"
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RBAR11,SAU Region Base Address Register 11"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xB
|
|
hide.long 0x00 "SAU_RLAR11,SAU Region Limit Address Register 11"
|
|
hgroup.long 0xDDC++0x03 "Region 12 (not accessible)"
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RBAR12,SAU Region Base Address Register 12"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xC
|
|
hide.long 0x00 "SAU_RLAR12,SAU Region Limit Address Register 12"
|
|
hgroup.long 0xDDC++0x03 "Region 13 (not accessible)"
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RBAR13,SAU Region Base Address Register 13"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xD
|
|
hide.long 0x00 "SAU_RLAR13,SAU Region Limit Address Register 13"
|
|
hgroup.long 0xDDC++0x03 "Region 14 (not accessible)"
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RBAR14,SAU Region Base Address Register 14"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xE
|
|
hide.long 0x00 "SAU_RLAR14,SAU Region Limit Address Register 14"
|
|
hgroup.long 0xDDC++0x03 "Region 15 (not accessible)"
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RBAR15,SAU Region Base Address Register 15"
|
|
hgroup.long 0xDE0++0x03
|
|
saveout 0xDD8 %l 0xF
|
|
hide.long 0x00 "SAU_RLAR15,SAU Region Limit Address Register 15"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 6.
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "ICTR,Interrupt Controller Type Register"
|
|
bitfld.long 0x00 0.--3. " INTLINESNUM ,Total Number of Interrupt" "0-32,0-64,0-96,0-128,0-160,0-192,0-224,0-239,?..."
|
|
tree "Interrupt Enable Registers"
|
|
width 24.
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "IRQ0_31_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x104++0x03
|
|
line.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA63 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA62 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA61 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA60 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA59 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA58 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA57 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA56 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA55 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA54 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA53 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA52 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA51 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA50 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA49 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA48 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA47 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA46 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA45 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA44 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA43 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA42 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA41 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA40 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA39 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA38 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA37 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA36 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA35 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA34 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA33 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA32 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x104++0x03
|
|
hide.long 0x00 "IRQ32_63_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x108++0x03
|
|
line.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA95 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA94 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA93 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA92 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA91 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA90 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA89 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA88 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA87 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA86 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA85 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA84 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA83 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA82 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA81 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA80 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA79 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA78 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA77 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA76 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA75 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA74 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA73 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA72 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA71 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA70 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA69 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA68 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA67 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA66 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA65 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA64 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x108++0x03
|
|
hide.long 0x00 "IRQ64_95_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x10C++0x03
|
|
line.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA127 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA126 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA125 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA124 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA123 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA122 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA121 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA120 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA119 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA118 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA117 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA116 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA115 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA114 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA113 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA112 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA111 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA110 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA109 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA108 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA107 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA106 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA105 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA104 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA103 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA102 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA101 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA100 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA99 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA98 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA97 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA96 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x10C++0x03
|
|
hide.long 0x00 "IRQ96_127_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA159 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA158 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA157 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA156 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA155 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA154 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA153 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA152 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA151 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA150 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA149 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA148 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA147 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA146 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA145 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA144 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA143 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA142 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA141 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA140 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA139 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA138 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA137 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA136 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA135 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA134 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA133 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA132 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA131 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA130 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA129 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA128 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x110++0x03
|
|
hide.long 0x00 "IRQ128_159_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x114++0x03
|
|
line.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA191 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA190 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA189 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA188 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA187 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA186 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA185 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA184 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA183 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA182 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA181 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA180 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA179 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA178 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA177 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA176 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA175 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA174 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA173 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA172 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA171 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA170 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA169 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA168 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA167 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA166 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA165 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA164 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA163 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA162 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA161 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA160 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x114++0x03
|
|
hide.long 0x00 "IRQ160_191_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x118++0x03
|
|
line.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " ENA223 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " ENA222 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " ENA221 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " ENA220 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " ENA219 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " ENA218 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " ENA217 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " ENA216 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " ENA215 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " ENA214 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " ENA213 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " ENA212 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " ENA211 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " ENA210 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " ENA209 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " ENA208 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA207 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA206 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA205 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA204 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA203 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA202 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA201 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA200 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA199 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA198 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA197 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA196 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA195 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA194 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA193 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA192 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x118++0x03
|
|
hide.long 0x00 "IRQ192_223_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x11C++0x03
|
|
line.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " ENA239 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " ENA238 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " ENA237 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " ENA236 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " ENA235 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " ENA234 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " ENA233 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " ENA232 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " ENA231 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " ENA230 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " ENA229 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " ENA228 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " ENA227 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " ENA226 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " ENA225 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " ENA224 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0x11C++0x03
|
|
hide.long 0x00 "IRQ224_239_EN_SET/CLR,Interrupt Enable Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
width 24.
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "IRQ0_31_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x204++0x03
|
|
line.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN63 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN62 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN61 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN60 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN59 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN58 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN57 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN56 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN55 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN54 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN53 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN52 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN51 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN50 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN49 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN48 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN47 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN46 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN45 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN44 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN43 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN42 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN41 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN40 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN39 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN38 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN37 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN36 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN35 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN34 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN33 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN32 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x204++0x03
|
|
hide.long 0x00 "IRQ32_63_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x208++0x03
|
|
line.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN95 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN94 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN93 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN92 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN91 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN90 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN89 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN88 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN87 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN86 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN85 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN84 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN83 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN82 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN81 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN80 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN79 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN78 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN77 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN76 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN75 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN74 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN73 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN72 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN71 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN70 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN69 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN68 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN67 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN66 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN65 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN64 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x208++0x03
|
|
hide.long 0x00 "IRQ64_95_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x20C++0x03
|
|
line.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN127 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN126 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN125 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN124 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN123 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN122 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN121 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN120 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN119 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN118 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN117 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN116 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN115 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN114 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN113 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN112 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN111 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN110 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN109 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN108 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN107 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN106 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN105 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN104 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN103 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN102 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN101 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN100 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN99 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN98 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN97 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN96 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x20C++0x03
|
|
hide.long 0x00 "IRQ96_127_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN159 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN158 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN157 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN156 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN155 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN154 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN153 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN152 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN151 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN150 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN149 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN148 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN147 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN146 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN145 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN144 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN143 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN142 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN141 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN140 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN139 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN138 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN137 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN136 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN135 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN134 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN133 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN132 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN131 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN130 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN129 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN128 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x210++0x03
|
|
hide.long 0x00 "IRQ128_159_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x214++0x03
|
|
line.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN191 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN190 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN189 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN188 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN187 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN186 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN185 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN184 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN183 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN182 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN181 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN180 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN179 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN178 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN177 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN176 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN175 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN174 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN173 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN172 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN171 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN170 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN169 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN168 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN167 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN166 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN165 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN164 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN163 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN162 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN161 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN160 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x214++0x03
|
|
hide.long 0x00 "IRQ160_191_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x218++0x03
|
|
line.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " PEN223 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " PEN222 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " PEN221 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " PEN220 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " PEN219 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " PEN218 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " PEN217 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " PEN216 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " PEN215 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " PEN214 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " PEN213 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " PEN212 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " PEN211 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " PEN210 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " PEN209 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " PEN208 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN207 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN206 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN205 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN204 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN203 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN202 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN201 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN200 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN199 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN198 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN197 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN196 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN195 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN194 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN193 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN192 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x218++0x03
|
|
hide.long 0x00 "IRQ192_223_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x21C++0x03
|
|
line.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " PEN239 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " PEN238 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " PEN237 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " PEN236 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " PEN235 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " PEN234 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " PEN233 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " PEN232 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " PEN231 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " PEN230 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " PEN229 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " PEN228 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " PEN227 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " PEN226 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " PEN225 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " PEN224 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
else
|
|
hgroup.long 0x21C++0x03
|
|
hide.long 0x00 "IRQ224_239_PEN_SET/CLR,Interrupt Pending Register"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Active Bit Registers"
|
|
width 11.
|
|
rgroup.long 0x300++0x03
|
|
line.long 0x00 "ACTIVE0,Active Bit Register 0"
|
|
bitfld.long 0x00 31. " ACTIVE31 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE30 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE29 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE28 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE27 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE26 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE25 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE24 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE23 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE22 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE21 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE20 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE19 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE18 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE17 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE16 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE15 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE14 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE13 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE12 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE11 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE10 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE9 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE8 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE7 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE6 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE5 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE4 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE3 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE2 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE1 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE0 ,Interrupt Active Flag" "Not active,Active"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
rgroup.long 0x304++0x03
|
|
line.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
bitfld.long 0x00 31. " ACTIVE63 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE62 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE61 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE60 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE59 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE58 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE57 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE56 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE55 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE54 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE53 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE52 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE51 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE50 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE49 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE48 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE47 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE46 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE45 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE44 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE43 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE42 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE41 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE40 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE39 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE38 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE37 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE36 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE35 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE34 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE33 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE32 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x304++0x03
|
|
hide.long 0x00 "ACTIVE1,Active Bit Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
rgroup.long 0x308++0x03
|
|
line.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
bitfld.long 0x00 31. " ACTIVE95 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE94 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE93 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE92 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE91 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE90 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE89 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE88 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE87 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE86 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE85 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE84 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE83 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE82 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE81 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE80 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE79 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE78 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE77 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE76 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE75 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE74 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE73 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE72 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE71 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE70 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE69 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE68 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE67 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE66 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE65 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE64 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x308++0x03
|
|
hide.long 0x00 "ACTIVE2,Active Bit Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
rgroup.long 0x30C++0x03
|
|
line.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
bitfld.long 0x00 31. " ACTIVE127 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE126 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE125 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE124 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE123 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE122 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE121 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE120 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE119 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE118 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE117 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE116 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE115 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE114 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE113 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE112 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE111 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE110 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE109 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE108 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE107 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE106 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE105 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE104 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE103 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE102 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE101 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE100 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE99 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE98 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE97 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE96 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x30C++0x03
|
|
hide.long 0x00 "ACTIVE3,Active Bit Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
rgroup.long 0x310++0x03
|
|
line.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
bitfld.long 0x00 31. " ACTIVE159 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE158 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE157 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE156 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE155 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE154 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE153 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE152 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE151 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE150 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE149 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE148 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE147 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE146 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE145 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE144 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE143 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE142 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE141 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE140 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE139 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE138 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE137 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE136 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE135 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE134 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE133 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE132 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE131 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE130 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE129 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE128 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x310++0x03
|
|
hide.long 0x00 "ACTIVE4,Active Bit Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
rgroup.long 0x314++0x03
|
|
line.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
bitfld.long 0x00 31. " ACTIVE191 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE190 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE189 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE188 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE187 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE186 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE185 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE184 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE183 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE182 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE181 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE180 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE179 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE178 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE177 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE176 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE175 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE174 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE173 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE172 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE171 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE170 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE169 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE168 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE167 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE166 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE165 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE164 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE163 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE162 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE161 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE160 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x314++0x03
|
|
hide.long 0x00 "ACTIVE5,Active Bit Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
rgroup.long 0x318++0x03
|
|
line.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
bitfld.long 0x00 31. " ACTIVE223 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 30. " ACTIVE222 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 29. " ACTIVE221 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 28. " ACTIVE220 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 27. " ACTIVE219 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 26. " ACTIVE218 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ACTIVE217 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 24. " ACTIVE216 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 23. " ACTIVE215 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 22. " ACTIVE214 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 21. " ACTIVE213 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 20. " ACTIVE212 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ACTIVE211 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 18. " ACTIVE210 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 17. " ACTIVE209 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 16. " ACTIVE208 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 15. " ACTIVE207 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE206 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ACTIVE205 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE204 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE203 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE202 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 9. " ACTIVE201 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE200 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ACTIVE199 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE198 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE197 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE196 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 3. " ACTIVE195 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE194 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ACTIVE193 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE192 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x318++0x03
|
|
hide.long 0x00 "ACTIVE6,Active Bit Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
rgroup.long 0x31C++0x03
|
|
line.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
bitfld.long 0x00 15. " ACTIVE239 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 14. " ACTIVE238 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 13. " ACTIVE237 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 12. " ACTIVE236 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 11. " ACTIVE235 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 10. " ACTIVE234 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ACTIVE233 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 8. " ACTIVE232 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 7. " ACTIVE231 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 6. " ACTIVE230 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 5. " ACTIVE229 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 4. " ACTIVE228 ,Interrupt Active Flag" "Not active,Active"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ACTIVE227 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 2. " ACTIVE226 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 1. " ACTIVE225 ,Interrupt Active Flag" "Not active,Active"
|
|
bitfld.long 0x00 0. " ACTIVE224 ,Interrupt Active Flag" "Not active,Active"
|
|
else
|
|
hgroup.long 0x31C++0x03
|
|
hide.long 0x00 "ACTIVE7,Active Bit Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Target Non-Secure Registers"
|
|
width 13.
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "NVIC_ITNS0,Interrupt Target Non-Secure Register 0"
|
|
bitfld.long 0x00 31. " ITNS31 ,Interrupt Targets Non-secure 31" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS30 ,Interrupt Targets Non-secure 30" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS29 ,Interrupt Targets Non-secure 29" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS28 ,Interrupt Targets Non-secure 28" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS27 ,Interrupt Targets Non-secure 27" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS26 ,Interrupt Targets Non-secure 26" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS25 ,Interrupt Targets Non-secure 25" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS24 ,Interrupt Targets Non-secure 24" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS23 ,Interrupt Targets Non-secure 23" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS22 ,Interrupt Targets Non-secure 22" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS21 ,Interrupt Targets Non-secure 21" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS20 ,Interrupt Targets Non-secure 20" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS19 ,Interrupt Targets Non-secure 19" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS18 ,Interrupt Targets Non-secure 18" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS17 ,Interrupt Targets Non-secure 17" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS16 ,Interrupt Targets Non-secure 16" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS15 ,Interrupt Targets Non-secure 15" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS14 ,Interrupt Targets Non-secure 14" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS13 ,Interrupt Targets Non-secure 13" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS12 ,Interrupt Targets Non-secure 12" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS11 ,Interrupt Targets Non-secure 11" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS10 ,Interrupt Targets Non-secure 10" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS9 ,Interrupt Targets Non-secure 9" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS8 ,Interrupt Targets Non-secure 8" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS7 ,Interrupt Targets Non-secure 7" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS6 ,Interrupt Targets Non-secure 6" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS5 ,Interrupt Targets Non-secure 5" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS4 ,Interrupt Targets Non-secure 4" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS3 ,Interrupt Targets Non-secure 3" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS2 ,Interrupt Targets Non-secure 2" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS1 ,Interrupt Targets Non-secure 1" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS0 ,Interrupt Targets Non-secure 0" "Secure,Non-secure"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x384++0x03
|
|
line.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
bitfld.long 0x00 31. " ITNS63 ,Interrupt Targets Non-secure 63" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS62 ,Interrupt Targets Non-secure 62" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS61 ,Interrupt Targets Non-secure 61" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS60 ,Interrupt Targets Non-secure 60" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS59 ,Interrupt Targets Non-secure 59" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS58 ,Interrupt Targets Non-secure 58" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS57 ,Interrupt Targets Non-secure 57" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS56 ,Interrupt Targets Non-secure 56" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS55 ,Interrupt Targets Non-secure 55" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS54 ,Interrupt Targets Non-secure 54" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS53 ,Interrupt Targets Non-secure 53" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS52 ,Interrupt Targets Non-secure 52" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS51 ,Interrupt Targets Non-secure 51" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS50 ,Interrupt Targets Non-secure 50" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS49 ,Interrupt Targets Non-secure 49" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS48 ,Interrupt Targets Non-secure 48" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS47 ,Interrupt Targets Non-secure 47" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS46 ,Interrupt Targets Non-secure 46" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS45 ,Interrupt Targets Non-secure 45" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS44 ,Interrupt Targets Non-secure 44" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS43 ,Interrupt Targets Non-secure 43" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS42 ,Interrupt Targets Non-secure 42" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS41 ,Interrupt Targets Non-secure 41" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS40 ,Interrupt Targets Non-secure 40" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS39 ,Interrupt Targets Non-secure 39" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS38 ,Interrupt Targets Non-secure 38" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS37 ,Interrupt Targets Non-secure 37" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS36 ,Interrupt Targets Non-secure 36" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS35 ,Interrupt Targets Non-secure 35" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS34 ,Interrupt Targets Non-secure 34" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS33 ,Interrupt Targets Non-secure 33" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS32 ,Interrupt Targets Non-secure 32" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x384++0x03
|
|
hide.long 0x00 "NVIC_ITNS1,Interrupt Target Non-Secure Register 1"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x388++0x03
|
|
line.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
bitfld.long 0x00 31. " ITNS95 ,Interrupt Targets Non-secure 95" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS94 ,Interrupt Targets Non-secure 94" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS93 ,Interrupt Targets Non-secure 93" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS92 ,Interrupt Targets Non-secure 92" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS91 ,Interrupt Targets Non-secure 91" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS90 ,Interrupt Targets Non-secure 90" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS89 ,Interrupt Targets Non-secure 89" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS88 ,Interrupt Targets Non-secure 88" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS87 ,Interrupt Targets Non-secure 87" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS86 ,Interrupt Targets Non-secure 86" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS85 ,Interrupt Targets Non-secure 85" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS84 ,Interrupt Targets Non-secure 84" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS83 ,Interrupt Targets Non-secure 83" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS82 ,Interrupt Targets Non-secure 82" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS81 ,Interrupt Targets Non-secure 81" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS80 ,Interrupt Targets Non-secure 80" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS79 ,Interrupt Targets Non-secure 79" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS78 ,Interrupt Targets Non-secure 78" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS77 ,Interrupt Targets Non-secure 77" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS76 ,Interrupt Targets Non-secure 76" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS75 ,Interrupt Targets Non-secure 75" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS74 ,Interrupt Targets Non-secure 74" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS73 ,Interrupt Targets Non-secure 73" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS72 ,Interrupt Targets Non-secure 72" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS71 ,Interrupt Targets Non-secure 71" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS70 ,Interrupt Targets Non-secure 70" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS69 ,Interrupt Targets Non-secure 69" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS68 ,Interrupt Targets Non-secure 68" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS67 ,Interrupt Targets Non-secure 67" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS66 ,Interrupt Targets Non-secure 66" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS65 ,Interrupt Targets Non-secure 65" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS64 ,Interrupt Targets Non-secure 64" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x388++0x03
|
|
hide.long 0x00 "NVIC_ITNS2,Interrupt Target Non-Secure Register 2"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x38C++0x03
|
|
line.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
bitfld.long 0x00 31. " ITNS127 ,Interrupt Targets Non-secure 127" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS126 ,Interrupt Targets Non-secure 126" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS125 ,Interrupt Targets Non-secure 125" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS124 ,Interrupt Targets Non-secure 124" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS123 ,Interrupt Targets Non-secure 123" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS122 ,Interrupt Targets Non-secure 122" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS121 ,Interrupt Targets Non-secure 121" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS120 ,Interrupt Targets Non-secure 120" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS119 ,Interrupt Targets Non-secure 119" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS118 ,Interrupt Targets Non-secure 118" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS117 ,Interrupt Targets Non-secure 117" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS116 ,Interrupt Targets Non-secure 116" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS115 ,Interrupt Targets Non-secure 115" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS114 ,Interrupt Targets Non-secure 114" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS113 ,Interrupt Targets Non-secure 113" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS112 ,Interrupt Targets Non-secure 112" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS111 ,Interrupt Targets Non-secure 111" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS110 ,Interrupt Targets Non-secure 110" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS109 ,Interrupt Targets Non-secure 109" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS108 ,Interrupt Targets Non-secure 108" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS107 ,Interrupt Targets Non-secure 107" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS106 ,Interrupt Targets Non-secure 106" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS105 ,Interrupt Targets Non-secure 105" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS104 ,Interrupt Targets Non-secure 104" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS103 ,Interrupt Targets Non-secure 103" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS102 ,Interrupt Targets Non-secure 102" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS101 ,Interrupt Targets Non-secure 101" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS100 ,Interrupt Targets Non-secure 100" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS99 ,Interrupt Targets Non-secure 99" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS98 ,Interrupt Targets Non-secure 98" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS97 ,Interrupt Targets Non-secure 97" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS96 ,Interrupt Targets Non-secure 96" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x38C++0x03
|
|
hide.long 0x00 "NVIC_ITNS3,Interrupt Target Non-Secure Register 3"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
bitfld.long 0x00 31. " ITNS159 ,Interrupt Targets Non-secure 159" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS158 ,Interrupt Targets Non-secure 158" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS157 ,Interrupt Targets Non-secure 157" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS156 ,Interrupt Targets Non-secure 156" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS155 ,Interrupt Targets Non-secure 155" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS154 ,Interrupt Targets Non-secure 154" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS153 ,Interrupt Targets Non-secure 153" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS152 ,Interrupt Targets Non-secure 152" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS151 ,Interrupt Targets Non-secure 151" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS150 ,Interrupt Targets Non-secure 150" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS149 ,Interrupt Targets Non-secure 149" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS148 ,Interrupt Targets Non-secure 148" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS147 ,Interrupt Targets Non-secure 147" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS146 ,Interrupt Targets Non-secure 146" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS145 ,Interrupt Targets Non-secure 145" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS144 ,Interrupt Targets Non-secure 144" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS143 ,Interrupt Targets Non-secure 143" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS142 ,Interrupt Targets Non-secure 142" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS141 ,Interrupt Targets Non-secure 141" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS140 ,Interrupt Targets Non-secure 140" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS139 ,Interrupt Targets Non-secure 139" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS138 ,Interrupt Targets Non-secure 138" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS137 ,Interrupt Targets Non-secure 137" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS136 ,Interrupt Targets Non-secure 136" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS135 ,Interrupt Targets Non-secure 135" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS134 ,Interrupt Targets Non-secure 134" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS133 ,Interrupt Targets Non-secure 133" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS132 ,Interrupt Targets Non-secure 132" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS131 ,Interrupt Targets Non-secure 131" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS130 ,Interrupt Targets Non-secure 130" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS129 ,Interrupt Targets Non-secure 129" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS128 ,Interrupt Targets Non-secure 128" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x390++0x03
|
|
hide.long 0x00 "NVIC_ITNS4,Interrupt Target Non-Secure Register 4"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x394++0x03
|
|
line.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
bitfld.long 0x00 31. " ITNS191 ,Interrupt Targets Non-secure 191" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS190 ,Interrupt Targets Non-secure 190" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS189 ,Interrupt Targets Non-secure 189" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS188 ,Interrupt Targets Non-secure 188" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS187 ,Interrupt Targets Non-secure 187" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS186 ,Interrupt Targets Non-secure 186" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS185 ,Interrupt Targets Non-secure 185" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS184 ,Interrupt Targets Non-secure 184" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS183 ,Interrupt Targets Non-secure 183" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS182 ,Interrupt Targets Non-secure 182" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS181 ,Interrupt Targets Non-secure 181" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS180 ,Interrupt Targets Non-secure 180" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS179 ,Interrupt Targets Non-secure 179" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS178 ,Interrupt Targets Non-secure 178" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS177 ,Interrupt Targets Non-secure 177" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS176 ,Interrupt Targets Non-secure 176" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS175 ,Interrupt Targets Non-secure 175" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS174 ,Interrupt Targets Non-secure 174" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS173 ,Interrupt Targets Non-secure 173" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS172 ,Interrupt Targets Non-secure 172" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS171 ,Interrupt Targets Non-secure 171" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS170 ,Interrupt Targets Non-secure 170" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS169 ,Interrupt Targets Non-secure 169" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS168 ,Interrupt Targets Non-secure 168" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS167 ,Interrupt Targets Non-secure 167" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS166 ,Interrupt Targets Non-secure 166" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS165 ,Interrupt Targets Non-secure 165" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS164 ,Interrupt Targets Non-secure 164" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS163 ,Interrupt Targets Non-secure 163" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS162 ,Interrupt Targets Non-secure 162" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS161 ,Interrupt Targets Non-secure 161" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS160 ,Interrupt Targets Non-secure 160" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x394++0x03
|
|
hide.long 0x00 "NVIC_ITNS5,Interrupt Target Non-Secure Register 5"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x398++0x03
|
|
line.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
bitfld.long 0x00 31. " ITNS223 ,Interrupt Targets Non-secure 223" "Secure,Non-secure"
|
|
bitfld.long 0x00 30. " ITNS222 ,Interrupt Targets Non-secure 222" "Secure,Non-secure"
|
|
bitfld.long 0x00 29. " ITNS221 ,Interrupt Targets Non-secure 221" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 28. " ITNS220 ,Interrupt Targets Non-secure 220" "Secure,Non-secure"
|
|
bitfld.long 0x00 27. " ITNS219 ,Interrupt Targets Non-secure 219" "Secure,Non-secure"
|
|
bitfld.long 0x00 26. " ITNS218 ,Interrupt Targets Non-secure 218" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 25. " ITNS217 ,Interrupt Targets Non-secure 217" "Secure,Non-secure"
|
|
bitfld.long 0x00 24. " ITNS216 ,Interrupt Targets Non-secure 216" "Secure,Non-secure"
|
|
bitfld.long 0x00 23. " ITNS215 ,Interrupt Targets Non-secure 215" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 22. " ITNS214 ,Interrupt Targets Non-secure 214" "Secure,Non-secure"
|
|
bitfld.long 0x00 21. " ITNS213 ,Interrupt Targets Non-secure 213" "Secure,Non-secure"
|
|
bitfld.long 0x00 20. " ITNS212 ,Interrupt Targets Non-secure 212" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 19. " ITNS211 ,Interrupt Targets Non-secure 211" "Secure,Non-secure"
|
|
bitfld.long 0x00 18. " ITNS210 ,Interrupt Targets Non-secure 210" "Secure,Non-secure"
|
|
bitfld.long 0x00 17. " ITNS209 ,Interrupt Targets Non-secure 209" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 16. " ITNS208 ,Interrupt Targets Non-secure 208" "Secure,Non-secure"
|
|
bitfld.long 0x00 15. " ITNS207 ,Interrupt Targets Non-secure 207" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS206 ,Interrupt Targets Non-secure 206" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 13. " ITNS205 ,Interrupt Targets Non-secure 205" "Secure,Non-secure"
|
|
bitfld.long 0x00 12. " ITNS204 ,Interrupt Targets Non-secure 204" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS203 ,Interrupt Targets Non-secure 203" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 10. " ITNS202 ,Interrupt Targets Non-secure 202" "Secure,Non-secure"
|
|
bitfld.long 0x00 9. " ITNS201 ,Interrupt Targets Non-secure 201" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS200 ,Interrupt Targets Non-secure 200" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 7. " ITNS199 ,Interrupt Targets Non-secure 199" "Secure,Non-secure"
|
|
bitfld.long 0x00 6. " ITNS198 ,Interrupt Targets Non-secure 198" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS197 ,Interrupt Targets Non-secure 197" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 4. " ITNS196 ,Interrupt Targets Non-secure 196" "Secure,Non-secure"
|
|
bitfld.long 0x00 3. " ITNS195 ,Interrupt Targets Non-secure 195" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS194 ,Interrupt Targets Non-secure 194" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 1. " ITNS193 ,Interrupt Targets Non-secure 193" "Secure,Non-secure"
|
|
bitfld.long 0x00 0. " ITNS192 ,Interrupt Targets Non-secure 192" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x398++0x03
|
|
hide.long 0x00 "NVIC_ITNS6,Interrupt Target Non-Secure Register 6"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x39C++0x03
|
|
line.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
bitfld.long 0x00 15. " ITNS239 ,Interrupt Targets Non-secure 239" "Secure,Non-secure"
|
|
bitfld.long 0x00 14. " ITNS238 ,Interrupt Targets Non-secure 238" "Secure,Non-secure"
|
|
bitfld.long 0x00 13. " ITNS237 ,Interrupt Targets Non-secure 237" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 12. " ITNS236 ,Interrupt Targets Non-secure 236" "Secure,Non-secure"
|
|
bitfld.long 0x00 11. " ITNS235 ,Interrupt Targets Non-secure 235" "Secure,Non-secure"
|
|
bitfld.long 0x00 10. " ITNS234 ,Interrupt Targets Non-secure 234" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 9. " ITNS233 ,Interrupt Targets Non-secure 233" "Secure,Non-secure"
|
|
bitfld.long 0x00 8. " ITNS232 ,Interrupt Targets Non-secure 232" "Secure,Non-secure"
|
|
bitfld.long 0x00 7. " ITNS231 ,Interrupt Targets Non-secure 231" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 6. " ITNS230 ,Interrupt Targets Non-secure 230" "Secure,Non-secure"
|
|
bitfld.long 0x00 5. " ITNS229 ,Interrupt Targets Non-secure 229" "Secure,Non-secure"
|
|
bitfld.long 0x00 4. " ITNS228 ,Interrupt Targets Non-secure 228" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ITNS227 ,Interrupt Targets Non-secure 227" "Secure,Non-secure"
|
|
bitfld.long 0x00 2. " ITNS226 ,Interrupt Targets Non-secure 226" "Secure,Non-secure"
|
|
bitfld.long 0x00 1. " ITNS225 ,Interrupt Targets Non-secure 225" "Secure,Non-secure"
|
|
textline " "
|
|
bitfld.long 0x00 0. " ITNS224 ,Interrupt Targets Non-secure 224" "Secure,Non-secure"
|
|
else
|
|
hgroup.long 0x39C++0x03
|
|
hide.long 0x00 "NVIC_ITNS7,Interrupt Target Non-Secure Register 7"
|
|
endif
|
|
tree.end
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x0 "IPR0,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_3 ,Interrupt 3 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_2 ,Interrupt 2 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_1 ,Interrupt 1 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_0 ,Interrupt 0 Priority"
|
|
line.long 0x4 "IPR1,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_7 ,Interrupt 7 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_6 ,Interrupt 6 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_5 ,Interrupt 5 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_4 ,Interrupt 4 Priority"
|
|
line.long 0x8 "IPR2,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_11 ,Interrupt 11 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_10 ,Interrupt 10 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_9 ,Interrupt 9 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_8 ,Interrupt 8 Priority"
|
|
line.long 0xC "IPR3,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_15 ,Interrupt 15 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_14 ,Interrupt 14 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_13 ,Interrupt 13 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_12 ,Interrupt 12 Priority"
|
|
line.long 0x10 "IPR4,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_19 ,Interrupt 19 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_18 ,Interrupt 18 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_17 ,Interrupt 17 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_16 ,Interrupt 16 Priority"
|
|
line.long 0x14 "IPR5,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_23 ,Interrupt 23 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_22 ,Interrupt 22 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_21 ,Interrupt 21 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_20 ,Interrupt 20 Priority"
|
|
line.long 0x18 "IPR6,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_27 ,Interrupt 27 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_26 ,Interrupt 26 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_25 ,Interrupt 25 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_24 ,Interrupt 24 Priority"
|
|
line.long 0x1C "IPR7,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_31 ,Interrupt 31 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_30 ,Interrupt 30 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_29 ,Interrupt 29 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_28 ,Interrupt 28 Priority"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x01)
|
|
group.long 0x420++0x1F
|
|
line.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_35 ,Interrupt 35 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_34 ,Interrupt 34 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_33 ,Interrupt 33 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_32 ,Interrupt 32 Priority"
|
|
line.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_39 ,Interrupt 39 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_38 ,Interrupt 38 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_37 ,Interrupt 37 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_36 ,Interrupt 36 Priority"
|
|
line.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_43 ,Interrupt 43 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_42 ,Interrupt 42 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_41 ,Interrupt 41 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_40 ,Interrupt 40 Priority"
|
|
line.long 0xC "IPR11,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_47 ,Interrupt 47 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_46 ,Interrupt 46 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_45 ,Interrupt 45 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_44 ,Interrupt 44 Priority"
|
|
line.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_51 ,Interrupt 51 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_50 ,Interrupt 50 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_49 ,Interrupt 49 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_48 ,Interrupt 48 Priority"
|
|
line.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_55 ,Interrupt 55 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_54 ,Interrupt 54 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_53 ,Interrupt 53 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_52 ,Interrupt 52 Priority"
|
|
line.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_59 ,Interrupt 59 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_58 ,Interrupt 58 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_57 ,Interrupt 57 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_56 ,Interrupt 56 Priority"
|
|
line.long 0x1C "IPR15,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_63 ,Interrupt 63 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_62 ,Interrupt 62 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_61 ,Interrupt 61 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_60 ,Interrupt 60 Priority"
|
|
else
|
|
hgroup.long 0x420++0x1F
|
|
hide.long 0x0 "IPR8,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR9,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR10,Interrupt Priority Register"
|
|
hide.long 0xC "IPR11,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR12,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR13,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR14,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR15,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x02)
|
|
group.long 0x440++0x1F
|
|
line.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_67 ,Interrupt 67 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_66 ,Interrupt 66 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_65 ,Interrupt 65 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_64 ,Interrupt 64 Priority"
|
|
line.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_71 ,Interrupt 71 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_70 ,Interrupt 70 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_69 ,Interrupt 69 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_68 ,Interrupt 68 Priority"
|
|
line.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_75 ,Interrupt 75 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_74 ,Interrupt 74 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_73 ,Interrupt 73 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_72 ,Interrupt 72 Priority"
|
|
line.long 0xC "IPR19,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_79 ,Interrupt 79 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_78 ,Interrupt 78 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_77 ,Interrupt 77 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_76 ,Interrupt 76 Priority"
|
|
line.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_83 ,Interrupt 83 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_82 ,Interrupt 82 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_81 ,Interrupt 81 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_80 ,Interrupt 80 Priority"
|
|
line.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_87 ,Interrupt 87 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_86 ,Interrupt 86 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_85 ,Interrupt 85 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_84 ,Interrupt 84 Priority"
|
|
line.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_91 ,Interrupt 91 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_90 ,Interrupt 90 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_89 ,Interrupt 89 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_88 ,Interrupt 88 Priority"
|
|
line.long 0x1C "IPR23,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_95 ,Interrupt 95 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_94 ,Interrupt 94 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_93 ,Interrupt 93 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_92 ,Interrupt 92 Priority"
|
|
else
|
|
hgroup.long 0x440++0x1F
|
|
hide.long 0x0 "IPR16,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR17,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR18,Interrupt Priority Register"
|
|
hide.long 0xC "IPR19,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR20,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR21,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR22,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR23,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x03)
|
|
group.long 0x460++0x1F
|
|
line.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_99 ,Interrupt 99 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_98 ,Interrupt 98 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_97 ,Interrupt 97 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_96 ,Interrupt 96 Priority"
|
|
line.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_103 ,Interrupt 103 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_102 ,Interrupt 102 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_101 ,Interrupt 101 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_100 ,Interrupt 100 Priority"
|
|
line.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_107 ,Interrupt 107 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_106 ,Interrupt 106 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_105 ,Interrupt 105 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_104 ,Interrupt 104 Priority"
|
|
line.long 0xC "IPR27,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_111 ,Interrupt 111 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_110 ,Interrupt 110 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_109 ,Interrupt 109 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_108 ,Interrupt 108 Priority"
|
|
line.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_115 ,Interrupt 115 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_114 ,Interrupt 114 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_113 ,Interrupt 113 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_112 ,Interrupt 112 Priority"
|
|
line.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_119 ,Interrupt 119 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_118 ,Interrupt 118 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_117 ,Interrupt 117 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_116 ,Interrupt 116 Priority"
|
|
line.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_123 ,Interrupt 123 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_122 ,Interrupt 122 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_121 ,Interrupt 121 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_120 ,Interrupt 120 Priority"
|
|
line.long 0x1C "IPR31,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_127 ,Interrupt 127 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_126 ,Interrupt 126 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_125 ,Interrupt 125 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_124 ,Interrupt 124 Priority"
|
|
else
|
|
hgroup.long 0x460++0x1F
|
|
hide.long 0x0 "IPR24,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR25,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR26,Interrupt Priority Register"
|
|
hide.long 0xC "IPR27,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR28,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR29,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR30,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR31,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x04)
|
|
group.long 0x480++0x1F
|
|
line.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_131 ,Interrupt 131 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_130 ,Interrupt 130 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_129 ,Interrupt 129 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_128 ,Interrupt 128 Priority"
|
|
line.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_135 ,Interrupt 135 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_134 ,Interrupt 134 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_133 ,Interrupt 133 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_132 ,Interrupt 132 Priority"
|
|
line.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_139 ,Interrupt 139 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_138 ,Interrupt 138 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_137 ,Interrupt 137 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_136 ,Interrupt 136 Priority"
|
|
line.long 0xC "IPR35,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_143 ,Interrupt 143 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_142 ,Interrupt 142 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_141 ,Interrupt 141 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_140 ,Interrupt 140 Priority"
|
|
line.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_147 ,Interrupt 147 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_146 ,Interrupt 146 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_145 ,Interrupt 145 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_144 ,Interrupt 144 Priority"
|
|
line.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_151 ,Interrupt 151 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_150 ,Interrupt 150 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_149 ,Interrupt 149 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_148 ,Interrupt 148 Priority"
|
|
line.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_155 ,Interrupt 155 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_154 ,Interrupt 154 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_153 ,Interrupt 153 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_152 ,Interrupt 152 Priority"
|
|
line.long 0x1C "IPR39,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_159 ,Interrupt 159 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_158 ,Interrupt 158 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_157 ,Interrupt 157 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_156 ,Interrupt 156 Priority"
|
|
else
|
|
hgroup.long 0x480++0x1F
|
|
hide.long 0x0 "IPR32,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR33,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR34,Interrupt Priority Register"
|
|
hide.long 0xC "IPR35,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR36,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR37,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR38,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR39,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x05)
|
|
group.long 0x4A0++0x1F
|
|
line.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_163 ,Interrupt 163 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_162 ,Interrupt 162 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_161 ,Interrupt 161 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_160 ,Interrupt 160 Priority"
|
|
line.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_167 ,Interrupt 167 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_166 ,Interrupt 166 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_165 ,Interrupt 165 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_164 ,Interrupt 164 Priority"
|
|
line.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_171 ,Interrupt 171 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_170 ,Interrupt 170 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_169 ,Interrupt 169 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_168 ,Interrupt 168 Priority"
|
|
line.long 0xC "IPR43,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_175 ,Interrupt 175 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_174 ,Interrupt 174 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_173 ,Interrupt 173 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_172 ,Interrupt 172 Priority"
|
|
line.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_179 ,Interrupt 179 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_178 ,Interrupt 178 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_177 ,Interrupt 177 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_176 ,Interrupt 176 Priority"
|
|
line.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_183 ,Interrupt 183 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_182 ,Interrupt 182 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_181 ,Interrupt 181 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_180 ,Interrupt 180 Priority"
|
|
line.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_187 ,Interrupt 187 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_186 ,Interrupt 186 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_185 ,Interrupt 185 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_184 ,Interrupt 184 Priority"
|
|
line.long 0x1C "IPR47,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_191 ,Interrupt 191 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_190 ,Interrupt 190 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_189 ,Interrupt 189 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_188 ,Interrupt 188 Priority"
|
|
else
|
|
hgroup.long 0x4A0++0x1F
|
|
hide.long 0x0 "IPR40,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR41,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR42,Interrupt Priority Register"
|
|
hide.long 0xC "IPR43,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR44,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR45,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR46,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR47,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x06)
|
|
group.long 0x4C0++0x1F
|
|
line.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_195 ,Interrupt 195 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_194 ,Interrupt 194 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_193 ,Interrupt 193 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_192 ,Interrupt 192 Priority"
|
|
line.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_199 ,Interrupt 199 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_198 ,Interrupt 198 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_197 ,Interrupt 197 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_196 ,Interrupt 196 Priority"
|
|
line.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_203 ,Interrupt 203 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_202 ,Interrupt 202 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_201 ,Interrupt 201 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_200 ,Interrupt 200 Priority"
|
|
line.long 0xC "IPR51,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_207 ,Interrupt 207 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_206 ,Interrupt 206 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_205 ,Interrupt 205 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_204 ,Interrupt 204 Priority"
|
|
line.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hexmask.long.byte 0x10 24.--31. 1. " PRI_211 ,Interrupt 211 Priority"
|
|
hexmask.long.byte 0x10 16.--23. 1. " PRI_210 ,Interrupt 210 Priority"
|
|
hexmask.long.byte 0x10 8.--15. 1. " PRI_209 ,Interrupt 209 Priority"
|
|
hexmask.long.byte 0x10 0.--7. 1. " PRI_208 ,Interrupt 208 Priority"
|
|
line.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hexmask.long.byte 0x14 24.--31. 1. " PRI_215 ,Interrupt 215 Priority"
|
|
hexmask.long.byte 0x14 16.--23. 1. " PRI_214 ,Interrupt 214 Priority"
|
|
hexmask.long.byte 0x14 8.--15. 1. " PRI_213 ,Interrupt 213 Priority"
|
|
hexmask.long.byte 0x14 0.--7. 1. " PRI_212 ,Interrupt 212 Priority"
|
|
line.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hexmask.long.byte 0x18 24.--31. 1. " PRI_219 ,Interrupt 219 Priority"
|
|
hexmask.long.byte 0x18 16.--23. 1. " PRI_218 ,Interrupt 218 Priority"
|
|
hexmask.long.byte 0x18 8.--15. 1. " PRI_217 ,Interrupt 217 Priority"
|
|
hexmask.long.byte 0x18 0.--7. 1. " PRI_216 ,Interrupt 216 Priority"
|
|
line.long 0x1C "IPR55,Interrupt Priority Register"
|
|
hexmask.long.byte 0x1C 24.--31. 1. " PRI_223 ,Interrupt 223 Priority"
|
|
hexmask.long.byte 0x1C 16.--23. 1. " PRI_222 ,Interrupt 222 Priority"
|
|
hexmask.long.byte 0x1C 8.--15. 1. " PRI_221 ,Interrupt 221 Priority"
|
|
hexmask.long.byte 0x1C 0.--7. 1. " PRI_220 ,Interrupt 220 Priority"
|
|
else
|
|
hgroup.long 0x4C0++0x1F
|
|
hide.long 0x0 "IPR48,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR49,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR50,Interrupt Priority Register"
|
|
hide.long 0xC "IPR51,Interrupt Priority Register"
|
|
hide.long 0x10 "IPR52,Interrupt Priority Register"
|
|
hide.long 0x14 "IPR53,Interrupt Priority Register"
|
|
hide.long 0x18 "IPR54,Interrupt Priority Register"
|
|
hide.long 0x1C "IPR55,Interrupt Priority Register"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0x04))&0x0F)>=0x07)
|
|
group.long 0x4E0++0x0F
|
|
line.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. " PRI_227 ,Interrupt 227 Priority"
|
|
hexmask.long.byte 0x0 16.--23. 1. " PRI_226 ,Interrupt 226 Priority"
|
|
hexmask.long.byte 0x0 8.--15. 1. " PRI_225 ,Interrupt 225 Priority"
|
|
hexmask.long.byte 0x0 0.--7. 1. " PRI_224 ,Interrupt 224 Priority"
|
|
line.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hexmask.long.byte 0x4 24.--31. 1. " PRI_231 ,Interrupt 231 Priority"
|
|
hexmask.long.byte 0x4 16.--23. 1. " PRI_230 ,Interrupt 230 Priority"
|
|
hexmask.long.byte 0x4 8.--15. 1. " PRI_229 ,Interrupt 229 Priority"
|
|
hexmask.long.byte 0x4 0.--7. 1. " PRI_228 ,Interrupt 228 Priority"
|
|
line.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hexmask.long.byte 0x8 24.--31. 1. " PRI_235 ,Interrupt 235 Priority"
|
|
hexmask.long.byte 0x8 16.--23. 1. " PRI_234 ,Interrupt 234 Priority"
|
|
hexmask.long.byte 0x8 8.--15. 1. " PRI_233 ,Interrupt 233 Priority"
|
|
hexmask.long.byte 0x8 0.--7. 1. " PRI_232 ,Interrupt 232 Priority"
|
|
line.long 0xC "IPR59,Interrupt Priority Register"
|
|
hexmask.long.byte 0xC 24.--31. 1. " PRI_239 ,Interrupt 239 Priority"
|
|
hexmask.long.byte 0xC 16.--23. 1. " PRI_238 ,Interrupt 238 Priority"
|
|
hexmask.long.byte 0xC 8.--15. 1. " PRI_237 ,Interrupt 237 Priority"
|
|
hexmask.long.byte 0xC 0.--7. 1. " PRI_236 ,Interrupt 236 Priority"
|
|
else
|
|
hgroup.long 0x4E0++0x0F
|
|
hide.long 0x0 "IPR56,Interrupt Priority Register"
|
|
hide.long 0x4 "IPR57,Interrupt Priority Register"
|
|
hide.long 0x8 "IPR58,Interrupt Priority Register"
|
|
hide.long 0xC "IPR59,Interrupt Priority Register"
|
|
endif
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 7.
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Debug Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,Indicates a debug event generated because of the assertion of an external debug request" "Not generated,Generated"
|
|
eventfld.long 0x00 3. " VCATCH ,Indicates triggering of a Vector catch" "Not triggered,Triggered"
|
|
eventfld.long 0x00 2. " DWTTRAP ,Indicates a debug event generated by the DWT" "Not generated,Generated"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB" "Not generated,Generated"
|
|
eventfld.long 0x00 0. " HALTED ,Indicates a debug event generated by either a C_HALT or C_STEP request, triggered by a write to the DHCSR or a step request triggered by setting DEMCR.MON_STEP to 1" "Not generated,Generated"
|
|
hgroup.long 0xDF0++0x03
|
|
hide.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
in
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Register Selector Register"
|
|
bitfld.long 0x00 16. " REGWNR ,Specifies the access type for the transfer" "Read,Write"
|
|
hexmask.long.byte 0x00 0.--6. 1. " REGSEL ,Specifies the ARM core register, special-purpose register or Floating-point extension register"
|
|
group.long 0xDF8++0x03
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDFC))&0x10000)==0x10000)
|
|
group.long 0xFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MON_STEP ,Setting this bit to 1 makes the step request pending" "No step,Step"
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDFC++0x03
|
|
line.long 0x00 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x00 24. " TRCENA ,Global enable for all DWT and ITM features" "Disabled,Enabled"
|
|
rbitfld.long 0x00 20. " SDME ,Indicates whether the DebugMonitor targets the Secure or the Non-secure state" "Non-secure,Secure"
|
|
bitfld.long 0x00 19. " MON_REQ ,DebugMonitor semaphore bit" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " MON_PEND ,Sets or clears the pending state of the DebugMonitor exception" "Not pending,Pending"
|
|
bitfld.long 0x00 16. " MON_EN ,Enable the DebugMonitor exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " VC_SFERR ,SecureFault vector catch enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " VC_HARDERR ,Enable halting debug trap on a HardFault exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " VC_INTERR ,Enable halting debug trap on a fault occurring during exception entry or exception return" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " VC_BUSERR ,Enable halting debug trap on a BusFault exception" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " VC_STATERR ,Enable halting debug trap on a UsageFault exception caused by a state information error" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " VC_CHKERR ,Enable halting debug trap on a UsageFault exception caused by a checking error" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " VC_NOCPERR ,Enable halting debug trap on a UsageFault caused by an access to a Coprocessor" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " VC_MMERR ,Enable halting debug trap on a MemManage exception" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " VC_CORERESET ,Enable Reset Vector Catch" "Disabled,Enabled"
|
|
endif
|
|
newline
|
|
width 13.
|
|
group.long 0xE04++0x07
|
|
line.long 0x00 "DAUTHCTRL,Debug Authentication Control Register"
|
|
bitfld.long 0x00 3. " INTSPNIDEN ,Internal secure non-invasive debug enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SPNIDENSEL ,Secure non-invasive debug enable select.Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure non-invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPNIDEN"
|
|
bitfld.long 0x00 1. " INTSPIDEN ,Internal secure invasive debug enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SPIDENSEL ,Secure invasive debug enable select. Selects between DAUTHCTRL and the IMPLEMENTATION DEFINED external authentication interface for control of Secure invasive debug" "Ext. auth. interface,DAUTHCTRL.INTSPIDEN"
|
|
textline " "
|
|
line.long 0x04 "DSCSR,Debug Security Control and Status Register"
|
|
bitfld.long 0x04 17. " CDSKEY ,CDS write-enable key" "Not ignored,Ignored"
|
|
textline " "
|
|
bitfld.long 0x04 16. " CDS ,This field indicates the current security state of the processor" "Non-secure,Secure"
|
|
bitfld.long 0x04 1. " SBRSEL ,Secure banked register select" "Non-secure,Secure"
|
|
bitfld.long 0x04 0. " SBRSELEN ,Secure banked register select enable" "Disabled,Enabled"
|
|
rgroup.long 0xFB8++0x03
|
|
line.long 0x00 "DAUTHSTATUS,Debug Authentication Status Register"
|
|
bitfld.long 0x00 7. " SNI ,Secure non-invasive debug implemented" ",Implemented"
|
|
bitfld.long 0x00 6. " SNE ,Secure non-invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 5. " SI ,Secure invasive debug features implemented" ",Implemented"
|
|
textline " "
|
|
bitfld.long 0x00 4. " SE ,Secure invasive debug enabled" "0,1"
|
|
bitfld.long 0x00 3. " NSNI ,Non-secure non-invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 2. " NSNE ,Non-secure non-invasive debug enabled" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 1. " NSI ,Non-secure invasive debug features implemented" ",Implemented"
|
|
bitfld.long 0x00 0. " NSE ,Non-secure invasive debug enabled" "0,1"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Flash Patch and Breakpoint Unit (FPB)"
|
|
sif COMPonent.AVAILABLE("FPB")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))
|
|
width 12.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "FP_CTRL,Flash Patch Control Register"
|
|
rbitfld.long 0x00 28.--31. " REV ,Flash Patch Breakpoint architecture revision" "Reserved,Version 2,?..."
|
|
rbitfld.long 0x00 4.--7. 12.--14. " NUM_CODE ,The number of instruction address comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76,77,78,79,80,81,82,83,84,85,86,87,88,89,90,91,92,93,94,95,96,97,98,99,100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125,126,127"
|
|
rbitfld.long 0x00 8.--11. " NUM_LIT ,Number of literal comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 1. " KEY ,Key Field" "Low,High"
|
|
bitfld.long 0x00 0. " ENABLE ,Flash Patch Unit Enable" "Disabled,Enabled"
|
|
newline
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x8))&0x01)==0x00)
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "FP_COMP0,Flash Patch Comparator Register 0"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xC))&0x01)==0x00)
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "FP_COMP1,Flash Patch Comparator Register 1"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x10))&0x01)==0x00)
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "FP_COMP2,Flash Patch Comparator Register 2"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0x14))&0x01)==0x00)
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
bitfld.long 0x00 31. " FE ,Specifies if Flash Patch enabled" "Disabled,Enabled"
|
|
newline
|
|
hexmask.long 0x00 2.--28. 0x04 " FPADDR ,Specifies bits[28:2] of the Flash Patch address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
else
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "FP_COMP3,Flash Patch Comparator Register 3"
|
|
newline
|
|
hexmask.long 0x00 1.--31. 0x02 " BPADDR ,Breakpoint address"
|
|
bitfld.long 0x00 0. " BE ,Selects between flashpatch and breakpoint functionality" "FP mode,BP mode"
|
|
endif
|
|
tree "CoreSight Identification Registers"
|
|
width 12.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("FPB",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
newline
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "FP_DEVARCH,FPB CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "FP_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "FP_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "FP_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0C "FP_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "FP_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "FP_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "FP_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "FP_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0C "FP_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "FPB component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 16.
|
|
group.long 0x00++0x1B
|
|
line.long 0x00 "DWT_CTRL,Control Register"
|
|
bitfld.long 0x00 28.--31. " NUMCOMP ,Number of comparators implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 27. " NOTRCPKT ,Shows whether the implementation supports trace sampling and exception tracing" "Supported,Not supported"
|
|
bitfld.long 0x00 25. " NOCYCCNT ,Shows whether the implementation supports a cycle counter" "Supported,Not supported"
|
|
textline " "
|
|
bitfld.long 0x00 24. " NOPRFCNT ,Shows whether the implementation supports the profiling counters" "Supported,Not supported"
|
|
bitfld.long 0x00 23. " CYCDISS ,Controls whether the cycle counter is prevented from incrementing while the PE is in Secure state" "No,Yes"
|
|
bitfld.long 0x00 22. " CYCEVTENA ,Enables POSTCNT underflow Event counter packets generation" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " FOLDEVTENA ,Enables generation of the Folded-instruction counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " LSUEVTENA ,Enables generation of the LSU counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SLEEPEVTENA ,Enables generation of the Sleep counter overflow event" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " EXCEVTENA ,Enables generation of the Exception overhead counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CPIEVTENA ,Enables generation of the CPI counter overflow event" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EXCTRCENA ,Enables generation of exception trace" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PCSAMPLENA ,Enables use of POSTCNT counter as a timer for Periodic PC sample packet generation" "Disabled,Enabled"
|
|
bitfld.long 0x00 10.--11. " SYNCTAP ,Selects the position of the synchronization packet counter tap on the CYCCNT counter" "Disabled,CYCCNT[24],CYCCNT[26],CYCCNT[28]"
|
|
bitfld.long 0x00 9. " CYCTAP ,Selects the position of the POSTCNT tap on the CYCCNT counter" "CYCCNT[6],CYCCNT[10]"
|
|
textline " "
|
|
bitfld.long 0x00 5.--8. " POSTINIT ,Initial value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1.--4. " POSTPRESET ,Reload value for the POSTCNT counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 0. " CYCCNTENA ,Enables CYCCNT" "Disabled,Enabled"
|
|
line.long 0x04 "DWT_CYCCNT,Cycle Count register"
|
|
line.long 0x08 "DWT_CPICNT,CPI Count register"
|
|
hexmask.long.byte 0x08 0.--7. 1. " CPICNT ,Base instruction overhead counter"
|
|
line.long 0x0c "DWT_EXCCNT,Exception Overhead Count Register"
|
|
hexmask.long.byte 0x0c 0.--7. 1. " EXCCNT ,The exception overhead counter"
|
|
line.long 0x10 "DWT_SLEEPCNT,Sleep Count Register"
|
|
hexmask.long.byte 0x10 0.--7. 1. " SLEEPCNT ,Sleep Counter"
|
|
line.long 0x14 "DWT_LSUCNT,LSU Count Register"
|
|
hexmask.long.byte 0x14 0.--7. 1. " LSUCNT ,Load-store overhead counter"
|
|
line.long 0x18 "DWT_FOLDCNT,Folded-instruction Count register"
|
|
hexmask.long.byte 0x18 0.--7. 1. " FOLDCNT ,Folded-instruction counter"
|
|
rgroup.long 0x1C++0x03
|
|
line.long 0x00 "DWT_PCSR,Program Counter Sample register"
|
|
textline " "
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)==0x1)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x4)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xC)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x20+0x08)&0xF)<0xF)
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "DWT_COMP0,DWT Comparator Register 0"
|
|
endif
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION0,DWT Function Register 0"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)==0x1)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x4)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xC)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x30+0x08)&0xF)<0xF)
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "DWT_COMP1,DWT Comparator Register 1"
|
|
endif
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION1,DWT Function Register 1"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)==0x1)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x4)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xC)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x40+0x08)&0xF)<0xF)
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "DWT_COMP2,DWT Comparator Register 2"
|
|
endif
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION2,DWT Function Register 2"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)==0x1)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x4)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xC)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x50+0x08)&0xF)<0xF)
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "DWT_COMP3,DWT Comparator Register 3"
|
|
endif
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION3,DWT Function Register 3"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)==0x1)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x4)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xC)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x60+0x08)&0xF)<0xF)
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "DWT_COMP4,DWT Comparator Register 4"
|
|
endif
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION4,DWT Function Register 4"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)==0x1)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x4)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xC)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x70+0x08)&0xF)<0xF)
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "DWT_COMP5,DWT Comparator Register 5"
|
|
endif
|
|
group.long (0x70+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION5,DWT Function Register 5"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)==0x1)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x4)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xC)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x80+0x08)&0xF)<0xF)
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x80++0x03
|
|
line.long 0x00 "DWT_COMP6,DWT Comparator Register 6"
|
|
endif
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION6,DWT Function Register 6"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)==0x1)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x4)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xC)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x90+0x08)&0xF)<0xF)
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x90++0x03
|
|
line.long 0x00 "DWT_COMP7,DWT Comparator Register 7"
|
|
endif
|
|
group.long (0x90+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION7,DWT Function Register 7"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)==0x1)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x4)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xC)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xA0+0x08)&0xF)<0xF)
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xA0++0x03
|
|
line.long 0x00 "DWT_COMP8,DWT Comparator Register 8"
|
|
endif
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION8,DWT Function Register 8"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)==0x1)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x4)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xC)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xB0+0x08)&0xF)<0xF)
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xB0++0x03
|
|
line.long 0x00 "DWT_COMP9,DWT Comparator Register 9"
|
|
endif
|
|
group.long (0xB0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION9,DWT Function Register 9"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)==0x1)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x4)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xC)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xC0+0x08)&0xF)<0xF)
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xC0++0x03
|
|
line.long 0x00 "DWT_COMP10,DWT Comparator Register 10"
|
|
endif
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION10,DWT Function Register 10"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)==0x1)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x4)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xC)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xD0+0x08)&0xF)<0xF)
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xD0++0x03
|
|
line.long 0x00 "DWT_COMP11,DWT Comparator Register 11"
|
|
endif
|
|
group.long (0xD0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION11,DWT Function Register 11"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)==0x1)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x4)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xC)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xE0+0x08)&0xF)<0xF)
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xE0++0x03
|
|
line.long 0x00 "DWT_COMP12,DWT Comparator Register 12"
|
|
endif
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION12,DWT Function Register 12"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)==0x1)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x4)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xC)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xF0+0x08)&0xF)<0xF)
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0xF0++0x03
|
|
line.long 0x00 "DWT_COMP13,DWT Comparator Register 13"
|
|
endif
|
|
group.long (0xF0+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION13,DWT Function Register 13"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)==0x1)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x4)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xC)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x100+0x08)&0xF)<0xF)
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "DWT_COMP14,DWT Comparator Register 14"
|
|
endif
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION14,DWT Function Register 14"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)==0x1)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " CYCVALUE ,Cycle value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x2&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x4)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 1.--31. 1. " PCVALUE ,PC value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x8&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xC)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 1. " DVALUE ,Data1 value"
|
|
elif ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0x4&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0x8||(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)>=0xC&&(per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0x110+0x08)&0xF)<0xF)
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
hexmask.long 0x00 0.--31. 0x01 " DADDR ,Data address"
|
|
else
|
|
group.long 0x110++0x03
|
|
line.long 0x00 "DWT_COMP15,DWT Comparator Register 15"
|
|
endif
|
|
group.long (0x110+0x08)++0x03
|
|
line.long 0x00 "DWT_FUNCTION15,DWT Function Register 15"
|
|
bitfld.long 0x00 27.--31. " ID ,Identifies the capabilities of comparator" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.long 0x00 24. " MATCHED ,Comparator match" "Not matched,Matched"
|
|
bitfld.long 0x00 10.--11. " DATAVSIZE ,Data Value Size" "8-bit,16-bit,32-bit,Reserved"
|
|
textline " "
|
|
bitfld.long 0x00 4.--5. " ACTION ,These bits are ignored and the comparator generates no actions if it is disabled by MATCH" "Trigger only,Generate debug event,Trace data value,Trace address"
|
|
bitfld.long 0x00 0.--3. " MATCH ,Defines what this comparator matches against" "Disabled,Cycle counter,Instruction address,Instruction address limit,Data address (RW),Data address (W),Data address (R),Data address limit,Data value (RW),Data value (W),Data value (R),Linked data value,Data address/Data value (RW),Data address/Data value (W),Data address/Data value limit (R),?..."
|
|
tree "CoreSight Identification Registers"
|
|
width 13.
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))+0xFBC))&0x100000)==0x100000)
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
hexmask.long.word 0x00 21.--31. 1. " ARCHITECT ,Component architect"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
bitfld.long 0x00 16.--19. " REVISION ,Architecture revision" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.long 0x00 12.--15. " ARCHVER ,Architecture version" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
hexmask.long.word 0x00 0.--11. 1. " ARCHPART ,Architecture part"
|
|
else
|
|
rgroup.long 0xFBC++0x03
|
|
line.long 0x00 "DWT_DEVARCH,DWT CoreSight Device Architecture Register"
|
|
bitfld.long 0x00 20. " PRESENT ,Register present" "Not present,Present"
|
|
endif
|
|
rgroup.long 0xFE0++0x0F
|
|
line.long 0x00 "DWT_PIDR0,Peripheral ID0"
|
|
hexmask.long.byte 0x00 0.--7. 1. " Part_Num[7:0] ,Part Number bits[7:0]"
|
|
line.long 0x04 "DWT_PIDR1,Peripheral ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " JEP106ID[3:0] ,JEP106 ID code bits[3:0]"
|
|
hexmask.long.byte 0x04 0.--3. 1. " Part_Num[11:8] ,Part Number bits[11:8]"
|
|
line.long 0x08 "DWT_PIDR2,Peripheral ID2"
|
|
hexmask.long.byte 0x08 4.--7. 1. " Revision ,Revision"
|
|
bitfld.long 0x08 3. " JEDEC ,JEDEC assigned ID fields" "0,JEDEC"
|
|
hexmask.long.byte 0x08 0.--2. 1. " JEP106ID[6:4] ,JEP106 ID code bits[6:4]"
|
|
line.long 0x0c "DWT_PIDR3,Peripheral ID3"
|
|
hexmask.long.byte 0x0C 4.--7. 1. " RevAnd ,Minor revision field"
|
|
hexmask.long.byte 0x0C 0.--3. 1. " CMB ,Customer-modified block"
|
|
rgroup.long 0xFD0++0x03
|
|
line.long 0x00 "DWT_PIDR4,Peripheral Identification Register 4"
|
|
hexmask.long.byte 0x00 4.--7. 1. " Count ,4KB count"
|
|
hexmask.long.byte 0x00 0.--3. 1. " JEP106_CC ,JEP106 continuation code"
|
|
rgroup.long 0xFF0++0x0F
|
|
line.long 0x00 "DWT_CIDR0,Component ID0 (Preamble)"
|
|
hexmask.long.byte 0x00 0.--7. 1. " PRMBL_0 ,CoreSight component identification preamble"
|
|
line.long 0x04 "DWT_CIDR1,Component ID1"
|
|
hexmask.long.byte 0x04 4.--7. 1. " CC ,Component Class"
|
|
hexmask.long.byte 0x04 0.--3. 1. " PRMBL_1 ,CoreSight component class"
|
|
line.long 0x08 "DWT_CIDR2,Component ID2"
|
|
hexmask.long.byte 0x08 0.--7. 1. " PRMBL_2 ,CoreSight component identification preamble"
|
|
line.long 0x0c "DWT_CIDR3,Component ID3"
|
|
hexmask.long.byte 0x0C 0.--7. 1. " PRMBL_3 ,CoreSight component identification preamble"
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
AUTOINDENT.ON CENTER TREE
|
|
ENUMDELIMITER ","
|
|
base ad:0x0
|
|
tree "ACMPLP (Low-Power Analog Comparator)"
|
|
base ad:0x40085E00
|
|
group.byte 0x0++0x2
|
|
line.byte 0x0 "COMPMDR,ACMPLP Mode Setting Register"
|
|
rbitfld.byte 0x0 7. "C1MON,ACMPLP1 Monitor Flag" "0,1"
|
|
bitfld.byte 0x0 6. "C1VRF,ACMPLP1 Reference Voltage Selection" "0: Select CMPREF1 input as ACMPLP1 reference voltage.,1: Select internal reference voltage (Vref) as.."
|
|
newline
|
|
bitfld.byte 0x0 5. "C1WDE,ACMPLP1 Window Function Mode Enable" "0: Disable ACMPLP1 window function mode,1: Enable ACMPLP1 window function mode"
|
|
bitfld.byte 0x0 4. "C1ENB,ACMPLP1 Operation Enable" "0: Disable ACMPLP1 operation,1: Enable ACMPLP1 operation"
|
|
newline
|
|
rbitfld.byte 0x0 3. "C0MON,ACMPLP0 Monitor Flag" "0,1"
|
|
bitfld.byte 0x0 2. "C0VRF,ACMPLP0 Reference Voltage Selection" "0: Select CMPREF0 input as ACMPLP0 reference voltage.,1: Select internal reference voltage (Vref) as.."
|
|
newline
|
|
bitfld.byte 0x0 1. "C0WDE,ACMPLP0 Window Function Mode Enable" "0: Disable window function for ACMPLP0,1: Enable window function for ACMPLP0"
|
|
bitfld.byte 0x0 0. "C0ENB,ACMPLP0 Operation Enable" "0: Disable comparator channel ACMPLP0,1: Enable comparator channel ACMPLP0"
|
|
line.byte 0x1 "COMPFIR,ACMPLP Filter Control Register"
|
|
bitfld.byte 0x1 7. "C1EDG,ACMPLP1 Edge Detection Selection" "0: Interrupt and ELC event request by one-edge..,1: Interrupt and ELC event request by both-edge.."
|
|
bitfld.byte 0x1 6. "C1EPO,ACMPLP1 Edge Polarity Switching" "0: Interrupt and ELC event request on rising edge,1: Interrupt and ELC event request on falling edge"
|
|
newline
|
|
bitfld.byte 0x1 4.--5. "C1FCK,ACMPLP1 Filter Select" "0: No Sampling (bypass),1: Sampling at PCLKB,?,?"
|
|
bitfld.byte 0x1 3. "C0EDG,ACMPLP0 Edge Detection Selection" "0: Interrupt and ELC event request by one-edge..,1: Interrupt and ELC event request by both-edge.."
|
|
newline
|
|
bitfld.byte 0x1 2. "C0EPO,ACMPLP0 Edge Polarity Switching" "0: Interrupt and ELC event request on rising edge,1: Interrupt and ELC event request on falling edge"
|
|
bitfld.byte 0x1 0.--1. "C0FCK,ACMPLP0 Filter Select" "0: No Sampling (bypass),1: Sampling at PCLKB,?,?"
|
|
line.byte 0x2 "COMPOCR,ACMPLP Output Control Register"
|
|
bitfld.byte 0x2 7. "SPDMD,ACMPLP0/ACMPLP1 Speed Selection" "0: Low-speed mode,1: High-speed mode"
|
|
bitfld.byte 0x2 6. "C1OP,ACMPLP1 VCOUT Output Polarity Selection" "0: Non-inverted,1: Inverted"
|
|
newline
|
|
bitfld.byte 0x2 5. "C1OE,ACMPLP1 VCOUT Pin Output Enable" "0: Disabled,1: Enabled"
|
|
bitfld.byte 0x2 2. "C0OP,ACMPLP0 VCOUT Output Polarity Selection" "0: Non-inverted,1: Inverted"
|
|
newline
|
|
bitfld.byte 0x2 1. "C0OE,ACMPLP0 VCOUT Pin Output Enable" "0: Disabled,1: Enabled"
|
|
tree.end
|
|
tree "ADC12 (12-bit A/D Converter)"
|
|
base ad:0x4005C000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "ADCSR,A/D Control Register"
|
|
bitfld.word 0x0 15. "ADST,A/D Conversion Start" "0: Stop A/D conversion process.,1: Start A/D conversion process."
|
|
bitfld.word 0x0 13.--14. "ADCS,Scan Mode Select" "0: Single scan mode,1: Group scan mode,?,?"
|
|
newline
|
|
bitfld.word 0x0 10. "ADHSC,A/D Conversion Mode Select" "0: High-speed A/D conversion mode,1: Low-power A/D conversion mode"
|
|
bitfld.word 0x0 9. "TRGE,Trigger Start Enable" "0: Disable A/D conversion to be started by the..,1: Enable A/D conversion to be started by the.."
|
|
newline
|
|
bitfld.word 0x0 8. "EXTRG,Trigger Select" "0: Start A/D conversion by the synchronous trigger..,1: Start A/D conversion by the asynchronous trigger.."
|
|
bitfld.word 0x0 7. "DBLE,Double Trigger Mode Select" "0: Deselect double-trigger mode.,1: Select double-trigger mode."
|
|
newline
|
|
bitfld.word 0x0 6. "GBADIE,Group B Scan End Interrupt and ELC Event Enable" "0: Disable ADC120_GBADI interrupt generation on..,1: Enable ADC120_GBADI interrupt generation on.."
|
|
hexmask.word.byte 0x0 0.--4. 1. "DBLANS,Double Trigger Channel Select"
|
|
group.word 0x4++0x7
|
|
line.word 0x0 "ADANSA0,A/D Channel Select Register A0"
|
|
bitfld.word 0x0 15. "ANSA15,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x0 14. "ANSA14,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x0 13. "ANSA13,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x0 12. "ANSA12,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x0 11. "ANSA11,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x0 10. "ANSA10,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x0 9. "ANSA09,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x0 8. "ANSA08,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x0 7. "ANSA07,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x0 6. "ANSA06,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x0 5. "ANSA05,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x0 4. "ANSA04,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x0 3. "ANSA03,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x0 2. "ANSA02,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x0 1. "ANSA01,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x0 0. "ANSA00,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
line.word 0x2 "ADANSA1,A/D Channel Select Register A1"
|
|
bitfld.word 0x2 15. "ANSA31,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x2 14. "ANSA30,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x2 13. "ANSA29,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x2 12. "ANSA28,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x2 11. "ANSA27,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x2 10. "ANSA26,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x2 9. "ANSA25,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x2 8. "ANSA24,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x2 7. "ANSA23,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x2 6. "ANSA22,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x2 5. "ANSA21,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x2 4. "ANSA20,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x2 3. "ANSA19,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x2 2. "ANSA18,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x2 1. "ANSA17,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x2 0. "ANSA16,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
line.word 0x4 "ADADS0,A/D-Converted Value Addition/Average Channel Select Register 0"
|
|
bitfld.word 0x4 15. "ADS15,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x4 14. "ADS14,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x4 13. "ADS13,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x4 12. "ADS12,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x4 11. "ADS11,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x4 10. "ADS10,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x4 9. "ADS09,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x4 8. "ADS08,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x4 7. "ADS07,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x4 6. "ADS06,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x4 5. "ADS05,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x4 4. "ADS04,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x4 3. "ADS03,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x4 2. "ADS02,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x4 1. "ADS01,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x4 0. "ADS00,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
line.word 0x6 "ADADS1,A/D-Converted Value Addition/Average Channel Select Register 1"
|
|
bitfld.word 0x6 15. "ADS31,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 14. "ADS30,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 13. "ADS29,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 12. "ADS28,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 11. "ADS27,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 10. "ADS26,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 9. "ADS25,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 8. "ADS24,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 7. "ADS23,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 6. "ADS22,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 5. "ADS21,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 4. "ADS20,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 3. "ADS19,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 2. "ADS18,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 1. "ADS17,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 0. "ADS16,A/D-Converted Value Addition/Average Channel Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "ADADC,A/D-Converted Value Addition/Average Count Select Register"
|
|
bitfld.byte 0x0 7. "AVEE,Average Mode Select" "0: Enable addition mode,1: Enable average mode"
|
|
bitfld.byte 0x0 0.--2. "ADC,Addition/Average Count Select" "0: Setting prohibited,1: 2-time conversion (1 addition),?,?,?,?,?,?"
|
|
group.word 0xE++0x9
|
|
line.word 0x0 "ADCER,A/D Control Extended Register"
|
|
bitfld.word 0x0 15. "ADRFMT,A/D Data Register Format Select" "0: Select right-justified for the A/D data register..,1: Select left-justified for the A/D data register.."
|
|
bitfld.word 0x0 11. "DIAGM,Self-Diagnosis Enable" "0: Disable ADC12 self-diagnosis,1: Enable ADC12 self-diagnosis"
|
|
newline
|
|
bitfld.word 0x0 10. "DIAGLD,Self-Diagnosis Mode Select" "0: Select rotation mode for self-diagnosis voltage,1: Select mixed mode for self-diagnosis voltage"
|
|
bitfld.word 0x0 8.--9. "DIAGVAL,Self-Diagnosis Conversion Voltage Select" "0: Setting prohibited when self-diagnosis is enabled,1: 0 volts,?,?"
|
|
newline
|
|
bitfld.word 0x0 5. "ACE,A/D Data Register Automatic Clearing Enable" "0: Disable automatic clearing,1: Enable automatic clearing"
|
|
line.word 0x2 "ADSTRGR,A/D Conversion Start Trigger Select Register"
|
|
hexmask.word.byte 0x2 8.--13. 1. "TRSA,A/D Conversion Start Trigger Select"
|
|
hexmask.word.byte 0x2 0.--5. 1. "TRSB,A/D Conversion Start Trigger Select for Group B"
|
|
line.word 0x4 "ADEXICR,A/D Conversion Extended Input Control Registers"
|
|
bitfld.word 0x4 9. "OCSA,Internal Reference Voltage A/D Conversion Select" "0: Disable A/D conversion of internal reference..,1: Enable A/D conversion of internal reference.."
|
|
bitfld.word 0x4 8. "TSSA,Temperature Sensor Output A/D Conversion Select" "0: Disable A/D conversion of temperature sensor..,1: Enable A/D conversion of temperature sensor output"
|
|
newline
|
|
bitfld.word 0x4 1. "OCSAD,Internal Reference Voltage A/D-Converted Value Addition/Average Mode Select" "0: Do not select addition/average mode for internal..,1: Select addition/average mode for internal.."
|
|
bitfld.word 0x4 0. "TSSAD,Temperature Sensor Output A/D-Converted Value Addition/Average Mode Select" "0: Do not select addition/average mode for..,1: Select addition/average mode for temperature.."
|
|
line.word 0x6 "ADANSB0,A/D Channel Select Register B0"
|
|
bitfld.word 0x6 15. "ANSB15,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 14. "ANSB14,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 13. "ANSB13,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 12. "ANSB12,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 11. "ANSB11,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 10. "ANSB10,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 9. "ANSB09,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 8. "ANSB08,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 7. "ANSB07,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 6. "ANSB06,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 5. "ANSB05,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 4. "ANSB04,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 3. "ANSB03,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 2. "ANSB02,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x6 1. "ANSB01,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x6 0. "ANSB00,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
line.word 0x8 "ADANSB1,A/D Channel Select Register B1"
|
|
bitfld.word 0x8 15. "ANSB31,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x8 14. "ANSB30,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x8 13. "ANSB29,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x8 12. "ANSB28,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x8 11. "ANSB27,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x8 10. "ANSB26,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x8 9. "ANSB25,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x8 8. "ANSB24,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x8 7. "ANSB23,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x8 6. "ANSB22,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x8 5. "ANSB21,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x8 4. "ANSB20,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x8 3. "ANSB19,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x8 2. "ANSB18,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
newline
|
|
bitfld.word 0x8 1. "ANSB17,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
bitfld.word 0x8 0. "ANSB16,A/D Conversion Channels Select" "0: Do not select associated input channel.,1: Select associated input channel."
|
|
rgroup.word 0x18++0x7
|
|
line.word 0x0 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x0 0.--15. 1. "ADDBLDR,Converted Value 15 to 0"
|
|
line.word 0x2 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x2 0.--15. 1. "ADTSDR,Converted Value 15 to 0"
|
|
line.word 0x4 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x4 0.--15. 1. "ADOCDR,Converted Value 15 to 0"
|
|
line.word 0x6 "ADRD,A/D Self-Diagnosis Data Register"
|
|
bitfld.word 0x6 14.--15. "DIAGST,Self-Diagnosis Status" "0: Self-diagnosis not executed after power-on.,1: Self-diagnosis was executed using the 0 V voltage.,?,?"
|
|
hexmask.word 0x6 0.--11. 1. "AD,Converted Value 11 to 0"
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
rgroup.word ($2+0x20)++0x1
|
|
line.word 0x0 "ADDR$1,A/D Data Registers %s"
|
|
hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0"
|
|
repeat.end
|
|
rgroup.word 0x40++0x1
|
|
line.word 0x0 "ADCTDR,A/D CTSU TSCAP Voltage Data Register"
|
|
hexmask.word 0x0 0.--15. 1. "ADCTDR,Converted Value 15 to 0"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
rgroup.word ($2+0x42)++0x1
|
|
line.word 0x0 "ADDR$1,A/D Data Registers %s"
|
|
hexmask.word 0x0 0.--15. 1. "ADDR,Converted Value 15 to 0"
|
|
repeat.end
|
|
group.byte 0x7A++0x0
|
|
line.byte 0x0 "ADDISCR,A/D Disconnection Detection Control Register"
|
|
bitfld.byte 0x0 4. "PCHG,Precharge/discharge select" "0: Discharge,1: Precharge"
|
|
hexmask.byte 0x0 0.--3. 1. "ADNDIS,Disconnection Detection Assist Setting"
|
|
group.byte 0x7E++0x0
|
|
line.byte 0x0 "ADACSR,A/D Conversion Operation Mode Select Register"
|
|
bitfld.byte 0x0 1. "ADSAC,Successive Approximation Control Setting" "0: Normal conversion mode (default),1: Fast conversion mode"
|
|
group.word 0x80++0x1
|
|
line.word 0x0 "ADGSPCR,A/D Group Scan Priority Control Register"
|
|
bitfld.word 0x0 15. "GBRP,Single Scan Continuous Start" "0: Single scan is not continuously activated.,1: Single scan for the group with the.."
|
|
bitfld.word 0x0 1. "GBRSCN,Lower-Priority Group Restart Setting" "0: Disable rescanning of the group that was stopped..,1: Enable rescanning of the group that was stopped.."
|
|
newline
|
|
bitfld.word 0x0 0. "PGS,Group Priority Operation Setting" "0: Operate without group priority control.,1: Operate with group priority control."
|
|
rgroup.word 0x84++0x3
|
|
line.word 0x0 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x0 0.--15. 1. "ADDBLDR,Converted Value 15 to 0"
|
|
line.word 0x2 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x2 0.--15. 1. "ADDBLDR,Converted Value 15 to 0"
|
|
group.byte 0x8A++0x0
|
|
line.byte 0x0 "ADHVREFCNT,A/D High-Potential/Low-Potential Reference Voltage Control Register"
|
|
bitfld.byte 0x0 7. "ADSLP,Sleep" "0: Normal operation,1: Standby state"
|
|
bitfld.byte 0x0 4. "LVSEL,Low-Potential Reference Voltage Select" "0: AVSS0 is selected as the low-potential reference..,1: VREFL0 is selected as the low-potential.."
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "HVSEL,High-Potential Reference Voltage Select" "0: AVCC0 is selected as the high-potential..,1: VREFH0 is selected as the high-potential..,?,?"
|
|
rgroup.byte 0x8C++0x0
|
|
line.byte 0x0 "ADWINMON,A/D Compare Function Window A/B Status Monitor Register"
|
|
bitfld.byte 0x0 5. "MONCMPB,Comparison Result Monitor B" "0: Window B comparison conditions are not met.,1: Window B comparison conditions are met."
|
|
bitfld.byte 0x0 4. "MONCMPA,Comparison Result Monitor A" "0: Window A comparison conditions are not met.,1: Window A comparison conditions are met."
|
|
newline
|
|
bitfld.byte 0x0 0. "MONCOMB,Combination Result Monitor" "0: Window A/B composite conditions are not met.,1: Window A/B composite conditions are met."
|
|
group.word 0x90++0x1
|
|
line.word 0x0 "ADCMPCR,A/D Compare Function Control Register"
|
|
bitfld.word 0x0 15. "CMPAIE,Compare A Interrupt Enable" "0: Disable ADC120_CMPAI interrupt when comparison..,1: Enable ADC120_CMPAI interrupt when comparison.."
|
|
bitfld.word 0x0 14. "WCMPE,Window Function Setting" "0: Disable window function Window A and window B..,1: Enable window function Window A and window B.."
|
|
newline
|
|
bitfld.word 0x0 13. "CMPBIE,Compare B Interrupt Enable" "0: Disable ADC120_CMPBI interrupt when comparison..,1: Enable ADC120_CMPBI interrupt when comparison.."
|
|
bitfld.word 0x0 11. "CMPAE,Compare Window A Operation Enable" "0: Disable compare window A operation. Disable..,1: Enable compare window A operation."
|
|
newline
|
|
bitfld.word 0x0 9. "CMPBE,Compare Window B Operation Enable" "0: Disable compare window B operation. Disable..,1: Enable compare window B operation."
|
|
bitfld.word 0x0 0.--1. "CMPAB,Window A/B Composite Conditions Setting" "0: Output ADC120_WCMPM when window A OR window B..,1: Output ADC120_WCMPM when window A EXOR window B..,?,?"
|
|
group.byte 0x92++0x1
|
|
line.byte 0x0 "ADCMPANSER,A/D Compare Function Window A Extended Input Select Register"
|
|
bitfld.byte 0x0 1. "CMPOCA,Internal Reference Voltage Compare Select" "0: Exclude the internal reference voltage from the..,1: Include the internal reference voltage in the.."
|
|
bitfld.byte 0x0 0. "CMPTSA,Temperature Sensor Output Compare Select" "0: Exclude the temperature sensor output from the..,1: Include the temperature sensor output in the.."
|
|
line.byte 0x1 "ADCMPLER,A/D Compare Function Window A Extended Input Comparison Condition Setting Register"
|
|
bitfld.byte 0x1 1. "CMPLOCA,Compare Window A Internal Reference Voltage Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.byte 0x1 0. "CMPLTSA,Compare Window A Temperature Sensor Output Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
group.word 0x94++0x7
|
|
line.word 0x0 "ADCMPANSR0,A/D Compare Function Window A Channel Select Register 0"
|
|
bitfld.word 0x0 15. "CMPCHA15,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x0 14. "CMPCHA14,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x0 13. "CMPCHA13,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x0 12. "CMPCHA12,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x0 11. "CMPCHA11,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x0 10. "CMPCHA10,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x0 9. "CMPCHA09,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x0 8. "CMPCHA08,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x0 7. "CMPCHA07,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x0 6. "CMPCHA06,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x0 5. "CMPCHA05,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x0 4. "CMPCHA04,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x0 3. "CMPCHA03,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x0 2. "CMPCHA02,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x0 1. "CMPCHA01,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x0 0. "CMPCHA00,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
line.word 0x2 "ADCMPANSR1,A/D Compare Function Window A Channel Select Register 1"
|
|
bitfld.word 0x2 15. "CMPCHA31,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x2 14. "CMPCHA30,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x2 13. "CMPCHA29,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x2 12. "CMPCHA28,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x2 11. "CMPCHA27,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x2 10. "CMPCHA26,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x2 9. "CMPCHA25,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x2 8. "CMPCHA24,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x2 7. "CMPCHA23,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x2 6. "CMPCHA22,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x2 5. "CMPCHA21,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x2 4. "CMPCHA20,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x2 3. "CMPCHA19,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x2 2. "CMPCHA18,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
newline
|
|
bitfld.word 0x2 1. "CMPCHA17,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
bitfld.word 0x2 0. "CMPCHA16,Compare Window A Channel Select" "0: Disable compare function for associated input..,1: Enable compare function for associated input.."
|
|
line.word 0x4 "ADCMPLR0,A/D Compare Function Window A Comparison Condition Setting Register 0"
|
|
bitfld.word 0x4 15. "CMPLCHA15,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x4 14. "CMPLCHA14,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x4 13. "CMPLCHA13,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x4 12. "CMPLCHA12,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x4 11. "CMPLCHA11,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x4 10. "CMPLCHA10,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x4 9. "CMPLCHA09,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x4 8. "CMPLCHA08,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x4 7. "CMPLCHA07,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x4 6. "CMPLCHA06,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x4 5. "CMPLCHA05,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x4 4. "CMPLCHA04,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x4 3. "CMPLCHA03,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x4 2. "CMPLCHA02,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x4 1. "CMPLCHA01,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x4 0. "CMPLCHA00,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
line.word 0x6 "ADCMPLR1,A/D Compare Function Window A Comparison Condition Setting Register 1"
|
|
bitfld.word 0x6 15. "CMPLCHA31,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x6 14. "CMPLCHA30,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x6 13. "CMPLCHA29,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x6 12. "CMPLCHA28,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x6 11. "CMPLCHA27,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x6 10. "CMPLCHA26,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x6 9. "CMPLCHA25,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x6 8. "CMPLCHA24,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x6 7. "CMPLCHA23,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x6 6. "CMPLCHA22,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x6 5. "CMPLCHA21,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x6 4. "CMPLCHA20,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x6 3. "CMPLCHA19,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x6 2. "CMPLCHA18,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
newline
|
|
bitfld.word 0x6 1. "CMPLCHA17,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
bitfld.word 0x6 0. "CMPLCHA16,Compare Window A Comparison Condition Select" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.word ($2+0x9C)++0x1
|
|
line.word 0x0 "ADCMPDR$1,A/D Compare Function Window A Lower-Side/Upper-Side Level Setting Register"
|
|
repeat.end
|
|
group.word 0xA0++0x3
|
|
line.word 0x0 "ADCMPSR0,A/D Compare Function Window A Channel Status Register 0"
|
|
bitfld.word 0x0 15. "CMPSTCHA15,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x0 14. "CMPSTCHA14,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x0 13. "CMPSTCHA13,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x0 12. "CMPSTCHA12,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x0 11. "CMPSTCHA11,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x0 10. "CMPSTCHA10,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x0 9. "CMPSTCHA09,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x0 8. "CMPSTCHA08,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x0 7. "CMPSTCHA07,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x0 6. "CMPSTCHA06,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x0 5. "CMPSTCHA05,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x0 4. "CMPSTCHA04,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x0 3. "CMPSTCHA03,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x0 2. "CMPSTCHA02,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x0 1. "CMPSTCHA01,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x0 0. "CMPSTCHA00,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
line.word 0x2 "ADCMPSR1,A/D Compare Function Window A Channel Status Register1"
|
|
bitfld.word 0x2 15. "CMPSTCHA31,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x2 14. "CMPSTCHA30,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x2 13. "CMPSTCHA29,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x2 12. "CMPSTCHA28,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x2 11. "CMPSTCHA27,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x2 10. "CMPSTCHA26,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x2 9. "CMPSTCHA25,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x2 8. "CMPSTCHA24,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x2 7. "CMPSTCHA23,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x2 6. "CMPSTCHA22,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x2 5. "CMPSTCHA21,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x2 4. "CMPSTCHA20,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x2 3. "CMPSTCHA19,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x2 2. "CMPSTCHA18,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
newline
|
|
bitfld.word 0x2 1. "CMPSTCHA17,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.word 0x2 0. "CMPSTCHA16,Compare Window A Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
group.byte 0xA4++0x0
|
|
line.byte 0x0 "ADCMPSER,A/D Compare Function Window A Extended Input Channel Status Register"
|
|
bitfld.byte 0x0 1. "CMPSTOCA,Compare Window A Internal Reference Voltage Compare Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
bitfld.byte 0x0 0. "CMPSTTSA,Compare Window A Temperature Sensor Output Compare Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
group.byte 0xA6++0x0
|
|
line.byte 0x0 "ADCMPBNSR,A/D Compare Function Window B Channel Select Register"
|
|
bitfld.byte 0x0 7. "CMPLB,Compare Window B Comparison Condition Setting" "0: When window function is disabled (ADCMPCR.WCMPE..,1: When window function is disabled (ADCMPCR.WCMPE.."
|
|
hexmask.byte 0x0 0.--5. 1. "CMPCHB,Compare Window B Channel Select"
|
|
group.word 0xA8++0x3
|
|
line.word 0x0 "ADWINLLB,A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register"
|
|
line.word 0x2 "ADWINULB,A/D Compare Function Window B Lower-Side/Upper-Side Level Setting Register"
|
|
group.byte 0xAC++0x0
|
|
line.byte 0x0 "ADCMPBSR,A/D Compare Function Window B Status Register"
|
|
bitfld.byte 0x0 0. "CMPSTB,Compare Window B Flag" "0: Comparison conditions are not met.,1: Comparison conditions are met."
|
|
group.byte 0xDD++0x2
|
|
line.byte 0x0 "ADSSTRL,A/D Sampling State Register"
|
|
hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting"
|
|
line.byte 0x1 "ADSSTRT,A/D Sampling State Register"
|
|
hexmask.byte 0x1 0.--7. 1. "SST,Sampling Time Setting"
|
|
line.byte 0x2 "ADSSTRO,A/D Sampling State Register"
|
|
hexmask.byte 0x2 0.--7. 1. "SST,Sampling Time Setting"
|
|
repeat 15. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2+0xE0)++0x0
|
|
line.byte 0x0 "ADSSTR$1,A/D Sampling State Register"
|
|
hexmask.byte 0x0 0.--7. 1. "SST,Sampling Time Setting"
|
|
repeat.end
|
|
tree.end
|
|
tree "AGT (Low Power Asynchronous General Purpose Timer)"
|
|
tree "AGT0"
|
|
base ad:0x40084000
|
|
group.word 0x0++0x5
|
|
line.word 0x0 "AGT,AGT Counter Register"
|
|
line.word 0x2 "AGTCMA,AGT Compare Match A Register"
|
|
line.word 0x4 "AGTCMB,AGT Compare Match B Register"
|
|
group.byte 0x8++0x2
|
|
line.byte 0x0 "AGTCR,AGT Control Register"
|
|
bitfld.byte 0x0 7. "TCMBF,Compare Match B Flag" "0: No match,1: Match"
|
|
bitfld.byte 0x0 6. "TCMAF,Compare Match A Flag" "0: No match,1: Match"
|
|
newline
|
|
bitfld.byte 0x0 5. "TUNDF,Underflow Flag" "0: No underflow,1: Underflow"
|
|
bitfld.byte 0x0 4. "TEDGF,Active Edge Judgment Flag" "0: No active edge received,1: Active edge received"
|
|
newline
|
|
bitfld.byte 0x0 2. "TSTOP,AGT Count Forced Stop" "0: Writing is invalid,1: The count is forcibly stopped"
|
|
rbitfld.byte 0x0 1. "TCSTF,AGT Count Status Flag" "0: Count stopped,1: Count in progress"
|
|
newline
|
|
bitfld.byte 0x0 0. "TSTART,AGT Count Start" "0: Count stops,1: Count starts"
|
|
line.byte 0x1 "AGTMR1,AGT Mode Register 1"
|
|
bitfld.byte 0x1 4.--6. "TCK,Count Source" "0: Setting prohibited,1: PCLKB/8,?,?,?,?,?,?"
|
|
bitfld.byte 0x1 3. "TEDGPL,Edge Polarity" "0: Single-edge,1: Both-edge"
|
|
newline
|
|
bitfld.byte 0x1 0.--2. "TMOD,Operating Mode" "0: Setting prohibited,1: Pulse output mode,?,?,?,?,?,?"
|
|
line.byte 0x2 "AGTMR2,AGT Mode Register 2"
|
|
bitfld.byte 0x2 7. "LPM,Low Power Mode" "0: Normal mode,1: Low power mode"
|
|
bitfld.byte 0x2 0.--2. "CKS,AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio" "0: 1/1,1: 1/2,?,?,?,?,?,?"
|
|
group.byte 0xC++0x3
|
|
line.byte 0x0 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x0 6.--7. "TIOGT,Count Control" "0: Setting prohibited,1: Event is counted during polarity period..,?,?"
|
|
bitfld.byte 0x0 4.--5. "TIPF,Input Filter" "0: No filter,1: Filter sampled at PCLKB,?,?"
|
|
newline
|
|
bitfld.byte 0x0 2. "TOE,AGTOn pin Output Enable" "0: AGTOn pin output disabled,1: AGTOn pin output enabled"
|
|
bitfld.byte 0x0 0. "TEDGSEL,I/O Polarity Switch" "0,1"
|
|
line.byte 0x1 "AGTISR,AGT Event Pin Select Register"
|
|
bitfld.byte 0x1 2. "EEPS,AGTEEn Polarity Selection" "0: An event is counted during the low-level period,1: An event is counted during the high-level period"
|
|
line.byte 0x2 "AGTCMSR,AGT Compare Match Function Select Register"
|
|
bitfld.byte 0x2 6. "TOPOLB,AGTOBn Pin Polarity Select" "0: AGTOBn pin output is started on low. i.e. normal..,1: AGTOBn pin output is started on high. i.e."
|
|
bitfld.byte 0x2 5. "TOEB,AGTOBn Pin Output Enable" "0: AGTOBn pin output disabled,1: AGTOBn pin output enabled"
|
|
newline
|
|
bitfld.byte 0x2 4. "TCMEB,AGT Compare Match B Register Enable" "0: Compare match B register disabled,1: Compare match B register enabled"
|
|
bitfld.byte 0x2 2. "TOPOLA,AGTOAn Pin Polarity Select" "0: AGTOAn pin output is started on low. i.e. normal..,1: AGTOAn pin output is started on high. i.e."
|
|
newline
|
|
bitfld.byte 0x2 1. "TOEA,AGTOAn Pin Output Enable" "0: AGTOAn pin output disabled,1: AGTOAn pin output enabled"
|
|
bitfld.byte 0x2 0. "TCMEA,AGT Compare Match A Register Enable" "0: AGT Compare match A register disabled,1: AGT Compare match A register enabled"
|
|
line.byte 0x3 "AGTIOSEL,AGT Pin Select Register"
|
|
bitfld.byte 0x3 4. "TIES,AGTIOn Pin Input Enable" "0: External event input is disabled during Software..,1: External event input is enabled during Software.."
|
|
bitfld.byte 0x3 0.--1. "SEL,AGTIOn Pin Select" "0: Select the AGTIOn except for the following pins,1: Setting prohibited,?,?"
|
|
tree.end
|
|
tree "AGT1"
|
|
base ad:0x40084100
|
|
group.word 0x0++0x5
|
|
line.word 0x0 "AGT,AGT Counter Register"
|
|
line.word 0x2 "AGTCMA,AGT Compare Match A Register"
|
|
line.word 0x4 "AGTCMB,AGT Compare Match B Register"
|
|
group.byte 0x8++0x2
|
|
line.byte 0x0 "AGTCR,AGT Control Register"
|
|
bitfld.byte 0x0 7. "TCMBF,Compare Match B Flag" "0: No match,1: Match"
|
|
bitfld.byte 0x0 6. "TCMAF,Compare Match A Flag" "0: No match,1: Match"
|
|
newline
|
|
bitfld.byte 0x0 5. "TUNDF,Underflow Flag" "0: No underflow,1: Underflow"
|
|
bitfld.byte 0x0 4. "TEDGF,Active Edge Judgment Flag" "0: No active edge received,1: Active edge received"
|
|
newline
|
|
bitfld.byte 0x0 2. "TSTOP,AGT Count Forced Stop" "0: Writing is invalid,1: The count is forcibly stopped"
|
|
rbitfld.byte 0x0 1. "TCSTF,AGT Count Status Flag" "0: Count stopped,1: Count in progress"
|
|
newline
|
|
bitfld.byte 0x0 0. "TSTART,AGT Count Start" "0: Count stops,1: Count starts"
|
|
line.byte 0x1 "AGTMR1,AGT Mode Register 1"
|
|
bitfld.byte 0x1 4.--6. "TCK,Count Source" "0: Setting prohibited,1: PCLKB/8,?,?,?,?,?,?"
|
|
bitfld.byte 0x1 3. "TEDGPL,Edge Polarity" "0: Single-edge,1: Both-edge"
|
|
newline
|
|
bitfld.byte 0x1 0.--2. "TMOD,Operating Mode" "0: Setting prohibited,1: Pulse output mode,?,?,?,?,?,?"
|
|
line.byte 0x2 "AGTMR2,AGT Mode Register 2"
|
|
bitfld.byte 0x2 7. "LPM,Low Power Mode" "0: Normal mode,1: Low power mode"
|
|
bitfld.byte 0x2 0.--2. "CKS,AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio" "0: 1/1,1: 1/2,?,?,?,?,?,?"
|
|
group.byte 0xC++0x3
|
|
line.byte 0x0 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x0 6.--7. "TIOGT,Count Control" "0: Setting prohibited,1: Event is counted during polarity period..,?,?"
|
|
bitfld.byte 0x0 4.--5. "TIPF,Input Filter" "0: No filter,1: Filter sampled at PCLKB,?,?"
|
|
newline
|
|
bitfld.byte 0x0 2. "TOE,AGTOn pin Output Enable" "0: AGTOn pin output disabled,1: AGTOn pin output enabled"
|
|
bitfld.byte 0x0 0. "TEDGSEL,I/O Polarity Switch" "0,1"
|
|
line.byte 0x1 "AGTISR,AGT Event Pin Select Register"
|
|
bitfld.byte 0x1 2. "EEPS,AGTEEn Polarity Selection" "0: An event is counted during the low-level period,1: An event is counted during the high-level period"
|
|
line.byte 0x2 "AGTCMSR,AGT Compare Match Function Select Register"
|
|
bitfld.byte 0x2 6. "TOPOLB,AGTOBn Pin Polarity Select" "0: AGTOBn pin output is started on low. i.e. normal..,1: AGTOBn pin output is started on high. i.e."
|
|
bitfld.byte 0x2 5. "TOEB,AGTOBn Pin Output Enable" "0: AGTOBn pin output disabled,1: AGTOBn pin output enabled"
|
|
newline
|
|
bitfld.byte 0x2 4. "TCMEB,AGT Compare Match B Register Enable" "0: Compare match B register disabled,1: Compare match B register enabled"
|
|
bitfld.byte 0x2 2. "TOPOLA,AGTOAn Pin Polarity Select" "0: AGTOAn pin output is started on low. i.e. normal..,1: AGTOAn pin output is started on high. i.e."
|
|
newline
|
|
bitfld.byte 0x2 1. "TOEA,AGTOAn Pin Output Enable" "0: AGTOAn pin output disabled,1: AGTOAn pin output enabled"
|
|
bitfld.byte 0x2 0. "TCMEA,AGT Compare Match A Register Enable" "0: AGT Compare match A register disabled,1: AGT Compare match A register enabled"
|
|
line.byte 0x3 "AGTIOSEL,AGT Pin Select Register"
|
|
bitfld.byte 0x3 4. "TIES,AGTIOn Pin Input Enable" "0: External event input is disabled during Software..,1: External event input is enabled during Software.."
|
|
bitfld.byte 0x3 0.--1. "SEL,AGTIOn Pin Select" "0: Select the AGTIOn except for the following pins,1: Setting prohibited,?,?"
|
|
tree.end
|
|
tree.end
|
|
tree "BUS (BUS Control)"
|
|
base ad:0x40003000
|
|
group.word 0x1008++0x1
|
|
line.word 0x0 "BUSMCNTSYS,Master Bus Control Register SYS"
|
|
bitfld.word 0x0 15. "IERES,Ignore Error Responses" "0: A bus error is reported.,1: A bus error is not reported."
|
|
group.word 0x100C++0x1
|
|
line.word 0x0 "BUSMCNTDMA,Master Bus Control Register DMA"
|
|
bitfld.word 0x0 15. "IERES,Ignore Error Responses" "0: A bus error is reported.,1: A bus error is not reported."
|
|
rgroup.long 0x1820++0x3
|
|
line.long 0x0 "BUS3ERRADD,Bus Error Address Register 3"
|
|
hexmask.long 0x0 0.--31. 1. "BERAD,Bus Error Address"
|
|
rgroup.byte 0x1824++0x0
|
|
line.byte 0x0 "BUS3ERRSTAT,BUS Error Status Register 3"
|
|
bitfld.byte 0x0 7. "ERRSTAT,Bus Error Status flag" "0: No bus error occurred.,1: Bus error occurred."
|
|
bitfld.byte 0x0 0. "ACCSTAT,Error Access Status flag" "0: Read access,1: Write access"
|
|
rgroup.long 0x1830++0x3
|
|
line.long 0x0 "BUS4ERRADD,Bus Error Address Register 4"
|
|
hexmask.long 0x0 0.--31. 1. "BERAD,Bus Error Address"
|
|
rgroup.byte 0x1834++0x0
|
|
line.byte 0x0 "BUS4ERRSTAT,BUS Error Status Register 4"
|
|
bitfld.byte 0x0 7. "ERRSTAT,Bus Error Status flag" "0: No bus error occurred.,1: Bus error occurred."
|
|
bitfld.byte 0x0 0. "ACCSTAT,Error Access Status flag" "0: Read access,1: Write access"
|
|
tree.end
|
|
tree "CAC (Clock Frequency Accuracy Measurement Circuit)"
|
|
base ad:0x40044600
|
|
group.byte 0x0++0x3
|
|
line.byte 0x0 "CACR0,CAC Control Register 0"
|
|
bitfld.byte 0x0 0. "CFME,Clock Frequency Measurement Enable" "0: Disable,1: Enable"
|
|
line.byte 0x1 "CACR1,CAC Control Register 1"
|
|
bitfld.byte 0x1 6.--7. "EDGES,Valid Edge Select" "0: Rising edge,1: Falling edge,?,?"
|
|
bitfld.byte 0x1 4.--5. "TCSS,Timer Count Clock Source Select" "0: No division,1: x 1/4 clock,?,?"
|
|
newline
|
|
bitfld.byte 0x1 1.--3. "FMCS,Measurement Target Clock Select" "0: Main clock oscillator,1: Sub-clock oscillator,?,?,?,?,?,?"
|
|
bitfld.byte 0x1 0. "CACREFE,CACREF Pin Input Enable" "0: Disable,1: Enable"
|
|
line.byte 0x2 "CACR2,CAC Control Register 2"
|
|
bitfld.byte 0x2 6.--7. "DFS,Digital Filter Select" "0: Disable digital filtering,1: Use sampling clock for the digital filter as the..,?,?"
|
|
bitfld.byte 0x2 4.--5. "RCDS,Measurement Reference Clock Frequency Division Ratio Select" "0: x 1/32 clock,1: x 1/128 clock,?,?"
|
|
newline
|
|
bitfld.byte 0x2 1.--3. "RSCS,Measurement Reference Clock Select" "0: Main clock oscillator,1: Sub-clock oscillator,?,?,?,?,?,?"
|
|
bitfld.byte 0x2 0. "RPS,Reference Signal Select" "0: CACREF pin input,1: Internal clock (internally generated signal)"
|
|
line.byte 0x3 "CAICR,CAC Interrupt Control Register"
|
|
bitfld.byte 0x3 6. "OVFFCL,OVFF Clear" "0: No effect,1: The CASTR.OVFF flag is cleared."
|
|
bitfld.byte 0x3 5. "MENDFCL,MENDF Clear" "0: No effect,1: The CASTR.MENDF flag is cleared"
|
|
newline
|
|
bitfld.byte 0x3 4. "FERRFCL,FERRF Clear" "0: No effect,1: The CASTR.FERRF flag is cleared"
|
|
bitfld.byte 0x3 2. "OVFIE,Overflow Interrupt Request Enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.byte 0x3 1. "MENDIE,Measurement End Interrupt Request Enable" "0: Disable,1: Enable"
|
|
bitfld.byte 0x3 0. "FERRIE,Frequency Error Interrupt Request Enable" "0: Disable,1: Enable"
|
|
rgroup.byte 0x4++0x0
|
|
line.byte 0x0 "CASTR,CAC Status Register"
|
|
bitfld.byte 0x0 2. "OVFF,Overflow Flag" "0: Counter has not overflowed,1: Counter overflowed"
|
|
bitfld.byte 0x0 1. "MENDF,Measurement End Flag" "0: Measurement is in progress,1: Measurement ended"
|
|
newline
|
|
bitfld.byte 0x0 0. "FERRF,Frequency Error Flag" "0: Clock frequency is within the allowable range,1: Clock frequency has deviated beyond the.."
|
|
group.word 0x6++0x3
|
|
line.word 0x0 "CAULVR,CAC Upper-Limit Value Setting Register"
|
|
line.word 0x2 "CALLVR,CAC Lower-Limit Value Setting Register"
|
|
rgroup.word 0xA++0x1
|
|
line.word 0x0 "CACNTBR,CAC Counter Buffer Register"
|
|
tree.end
|
|
tree "CAN (Controller Area Network)"
|
|
base ad:0x40050000
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.long ($2+0x200)++0x3
|
|
line.long 0x0 "MB$1_ID,Mailbox ID Register %s"
|
|
bitfld.long 0x0 31. "IDE,ID Extension" "0: Standard ID,1: Extended ID"
|
|
bitfld.long 0x0 30. "RTR,Remote Transmission Request" "0: Data frame,1: Remote frame"
|
|
newline
|
|
hexmask.long.word 0x0 18.--28. 1. "SID,Standard ID of data and remote frames"
|
|
hexmask.long.tbyte 0x0 0.--17. 1. "EID,Extended ID of data and remote frames"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.word ($2+0x204)++0x1
|
|
line.word 0x0 "MB$1_DL,Mailbox Data Length Register %s"
|
|
hexmask.word.byte 0x0 0.--3. 1. "DLC,Data Length Code"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.byte ($2+0x206)++0x0
|
|
line.byte 0x0 "MB$1_D0,Mailbox Data Register %s"
|
|
hexmask.byte 0x0 0.--7. 1. "DATA0,Data Bytes 0"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.byte ($2+0x207)++0x0
|
|
line.byte 0x0 "MB$1_D1,Mailbox Data Register %s"
|
|
hexmask.byte 0x0 0.--7. 1. "DATA1,Data Bytes 1"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.byte ($2+0x208)++0x0
|
|
line.byte 0x0 "MB$1_D2,Mailbox Data Register %s"
|
|
hexmask.byte 0x0 0.--7. 1. "DATA2,Data Bytes 2"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.byte ($2+0x209)++0x0
|
|
line.byte 0x0 "MB$1_D3,Mailbox Data Register %s"
|
|
hexmask.byte 0x0 0.--7. 1. "DATA3,Data Bytes 3"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.byte ($2+0x20A)++0x0
|
|
line.byte 0x0 "MB$1_D4,Mailbox Data Register %s"
|
|
hexmask.byte 0x0 0.--7. 1. "DATA4,Data Bytes 4"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.byte ($2+0x20B)++0x0
|
|
line.byte 0x0 "MB$1_D5,Mailbox Data Register %s"
|
|
hexmask.byte 0x0 0.--7. 1. "DATA5,Data Bytes 5"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.byte ($2+0x20C)++0x0
|
|
line.byte 0x0 "MB$1_D6,Mailbox Data Register %s"
|
|
hexmask.byte 0x0 0.--7. 1. "DATA6,Data Bytes 6"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.byte ($2+0x20D)++0x0
|
|
line.byte 0x0 "MB$1_D7,Mailbox Data Register %s"
|
|
hexmask.byte 0x0 0.--7. 1. "DATA7,Data Bytes 7"
|
|
repeat.end
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.word ($2+0x20E)++0x1
|
|
line.word 0x0 "MB$1_TS,Mailbox Time Stamp Register %s"
|
|
hexmask.word.byte 0x0 8.--15. 1. "TSH,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x0 0.--7. 1. "TSL,Time Stamp Lower Byte"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x400)++0x3
|
|
line.long 0x0 "MKR[$1],Mask Register %s"
|
|
hexmask.long.word 0x0 18.--28. 1. "SID,Standard ID"
|
|
hexmask.long.tbyte 0x0 0.--17. 1. "EID,Extended ID"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x420)++0x3
|
|
line.long 0x0 "FIDCR$1,FIFO Received ID Compare Register %s"
|
|
bitfld.long 0x0 31. "IDE,ID Extension" "0: Standard ID,1: Extended ID"
|
|
bitfld.long 0x0 30. "RTR,Remote Transmission Request" "0: Data frame,1: Remote frame"
|
|
newline
|
|
hexmask.long.word 0x0 18.--28. 1. "SID,Standard ID of data and remote frames"
|
|
hexmask.long.tbyte 0x0 0.--17. 1. "EID,Extended ID of data and remote frames"
|
|
repeat.end
|
|
group.long 0x428++0x7
|
|
line.long 0x0 "MKIVLR,Mask Invalid Register"
|
|
bitfld.long 0x0 31. "MB31,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 30. "MB30,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 29. "MB29,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 28. "MB28,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 27. "MB27,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 26. "MB26,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 25. "MB25,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 24. "MB24,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 23. "MB23,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 22. "MB22,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 21. "MB21,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 20. "MB20,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 19. "MB19,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 18. "MB18,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 17. "MB17,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 16. "MB16,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 15. "MB15,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 14. "MB14,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 13. "MB13,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 12. "MB12,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 11. "MB11,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 10. "MB10,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 9. "MB09,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 8. "MB08,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 7. "MB07,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 6. "MB06,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 5. "MB05,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 4. "MB04,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 3. "MB03,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 2. "MB02,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
newline
|
|
bitfld.long 0x0 1. "MB01,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
bitfld.long 0x0 0. "MB00,Mask Invalid" "0: Mask valid,1: Mask invalid"
|
|
line.long 0x4 "MIER,Mailbox Interrupt Enable Register"
|
|
bitfld.long 0x4 31. "MB31,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 30. "MB30,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
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bitfld.long 0x4 29. "MB29,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 28. "MB28,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x4 27. "MB27,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 26. "MB26,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x4 25. "MB25,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 24. "MB24,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x4 23. "MB23,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 22. "MB22,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
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bitfld.long 0x4 21. "MB21,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 20. "MB20,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
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bitfld.long 0x4 19. "MB19,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 18. "MB18,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
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bitfld.long 0x4 17. "MB17,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 16. "MB16,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
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bitfld.long 0x4 15. "MB15,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 14. "MB14,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
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bitfld.long 0x4 13. "MB13,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 12. "MB12,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
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|
newline
|
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bitfld.long 0x4 11. "MB11,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 10. "MB10,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
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|
newline
|
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bitfld.long 0x4 9. "MB09,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 8. "MB08,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
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newline
|
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bitfld.long 0x4 7. "MB07,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 6. "MB06,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
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bitfld.long 0x4 5. "MB05,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 4. "MB04,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
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newline
|
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bitfld.long 0x4 3. "MB03,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 2. "MB02,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
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newline
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bitfld.long 0x4 1. "MB01,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x4 0. "MB00,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
group.long 0x42C++0x3
|
|
line.long 0x0 "MIER_FIFO,Mailbox Interrupt Enable Register for FIFO Mailbox Mode"
|
|
bitfld.long 0x0 29. "MB29,Receive FIFO Interrupt Generation Timing Control" "0: Generate every time reception completes,1: Generate when the receive FIFO becomes a buffer.."
|
|
bitfld.long 0x0 28. "MB28,Receive FIFO Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
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|
newline
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bitfld.long 0x0 25. "MB25,Transmit FIFO Interrupt Generation Timing Control" "0: Generate every time transmission completes,1: Generate when the transmit FIFO empties on.."
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|
bitfld.long 0x0 24. "MB24,Transmit FIFO Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
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bitfld.long 0x0 23. "MB23,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x0 22. "MB22,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
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bitfld.long 0x0 21. "MB21,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x0 20. "MB20,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x0 19. "MB19,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x0 18. "MB18,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x0 17. "MB17,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x0 16. "MB16,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x0 15. "MB15,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x0 14. "MB14,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
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bitfld.long 0x0 13. "MB13,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x0 12. "MB12,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x0 11. "MB11,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x0 10. "MB10,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x0 9. "MB09,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x0 8. "MB08,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.long 0x0 7. "MB07,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x0 6. "MB06,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
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bitfld.long 0x0 5. "MB05,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.long 0x0 4. "MB04,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
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|
newline
|
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bitfld.long 0x0 3. "MB03,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
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bitfld.long 0x0 2. "MB02,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
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newline
|
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bitfld.long 0x0 1. "MB01,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
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bitfld.long 0x0 0. "MB00,Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
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repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
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group.byte ($2+0x820)++0x0
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line.byte 0x0 "MCTL_RX[$1],Message Control Register for Receive"
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bitfld.byte 0x0 7. "TRMREQ,Transmit Mailbox Request" "0: Do not configure for transmission,1: Configure for transmission"
|
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bitfld.byte 0x0 6. "RECREQ,Receive Mailbox Request" "0: Do not configure for reception,1: Configure for reception"
|
|
newline
|
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bitfld.byte 0x0 4. "ONESHOT,One-Shot Enable" "0: Disable one-shot reception,1: Enable one-shot reception"
|
|
bitfld.byte 0x0 2. "MSGLOST,Message Lost Flag" "0: Message not overwritten or overrun,1: Message overwritten or overrun"
|
|
newline
|
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rbitfld.byte 0x0 1. "INVALDATA,Reception-in-Progress Status Flag" "0: Message valid,1: Message being updated"
|
|
bitfld.byte 0x0 0. "NEWDATA,Reception Complete Flag" "0: No data received or 0 was written to the flag,1: New message being stored or was stored in the.."
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repeat.end
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repeat 32. (increment 0x0 0x1)(increment 0x0 0x1)
|
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group.byte ($2+0x820)++0x0
|
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line.byte 0x0 "MCTL_TX[$1],Message Control Register for Transmit"
|
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bitfld.byte 0x0 7. "TRMREQ,Transmit Mailbox Request" "0: Do not configure for transmission,1: Configure for transmission"
|
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bitfld.byte 0x0 6. "RECREQ,Receive Mailbox Request" "0: Do not configure for reception,1: Configure for reception"
|
|
newline
|
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bitfld.byte 0x0 4. "ONESHOT,One-Shot Enable" "0: Disable one-shot transmission,1: Enable one-shot transmission"
|
|
bitfld.byte 0x0 2. "TRMABT,Transmission Abort Complete Flag" "0: Transmission started transmission abort failed..,1: Transmission abort complete"
|
|
newline
|
|
rbitfld.byte 0x0 1. "TRMACTIVE,Transmission-in-Progress Status Flag" "0: Transmission pending or not requested,1: Transmission in progress"
|
|
bitfld.byte 0x0 0. "SENTDATA,Transmission Complete Flag" "0: Transmission not complete,1: Transmission complete"
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repeat.end
|
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group.word 0x840++0x1
|
|
line.word 0x0 "CTLR,Control Register"
|
|
bitfld.word 0x0 13. "RBOC,Forcible Return from Bus-Off" "0: No return occurred,1: Forced return from bus-off state"
|
|
bitfld.word 0x0 11.--12. "BOM,Bus-Off Recovery Mode" "0: Normal mode (ISO11898-1-compliant),1: Enter CAN halt mode automatically on entering..,?,?"
|
|
newline
|
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bitfld.word 0x0 10. "SLPM,CAN Sleep Mode" "0: All other modes,1: CAN sleep mode"
|
|
bitfld.word 0x0 8.--9. "CANM,CAN Operating Mode Select" "0: CAN operation mode,1: CAN reset mode,?,?"
|
|
newline
|
|
bitfld.word 0x0 6.--7. "TSPS,Time Stamp Prescaler Select" "0: Every 1-bit time,1: Every 2-bit time,?,?"
|
|
bitfld.word 0x0 5. "TSRC,Time Stamp Counter Reset Command" "0: Do not reset time stamp counter,1: Reset time stamp counter"
|
|
newline
|
|
bitfld.word 0x0 4. "TPM,Transmission Priority Mode Select" "0: ID priority transmit mode,1: Mailbox number priority transmit mode"
|
|
bitfld.word 0x0 3. "MLM,Message Lost Mode Select" "0: Overwrite mode,1: Overrun mode"
|
|
newline
|
|
bitfld.word 0x0 1.--2. "IDFM,ID Format Mode Select" "0: Standard ID mode All mailboxes including FIFO..,1: Extended ID mode All mailboxes including FIFO..,?,?"
|
|
bitfld.word 0x0 0. "MBM,CAN Mailbox Mode Select" "0: Normal mailbox mode,1: FIFO mailbox mode"
|
|
rgroup.word 0x842++0x1
|
|
line.word 0x0 "STR,Status Register"
|
|
bitfld.word 0x0 14. "RECST,Receive Status Flag" "0: Bus idle or transmission in progress,1: Reception in progress"
|
|
bitfld.word 0x0 13. "TRMST,Transmit Status Flag" "0: Bus idle or reception in progress,1: Transmission in progress or module in bus-off.."
|
|
newline
|
|
bitfld.word 0x0 12. "BOST,Bus-Off Status Flag" "0: Not in bus-off state,1: In bus-off state"
|
|
bitfld.word 0x0 11. "EPST,Error-Passive Status Flag" "0: Not in error-passive state,1: In error-passive state"
|
|
newline
|
|
bitfld.word 0x0 10. "SLPST,CAN Sleep Status Flag" "0: Not in CAN sleep mode,1: In CAN sleep mode"
|
|
bitfld.word 0x0 9. "HLTST,CAN Halt Status Flag" "0: Not in CAN halt mode,1: In CAN halt mode"
|
|
newline
|
|
bitfld.word 0x0 8. "RSTST,CAN Reset Status Flag" "0: Not in CAN reset mode,1: In CAN reset mode"
|
|
bitfld.word 0x0 7. "EST,Error Status Flag" "0: No error occurred,1: Error occurred"
|
|
newline
|
|
bitfld.word 0x0 6. "TABST,Transmission Abort Status Flag" "0: No mailbox with TRMABT = 1,1: One or more mailboxes with TRMABT = 1"
|
|
bitfld.word 0x0 5. "FMLST,FIFO Mailbox Message Lost Status Flag" "0: RFMLF = 0,1: RFMLF = 1"
|
|
newline
|
|
bitfld.word 0x0 4. "NMLST,Normal Mailbox Message Lost Status Flag" "0: No mailbox with MSGLOST = 1,1: One or more mailboxes with MSGLOST = 1"
|
|
bitfld.word 0x0 3. "TFST,Transmit FIFO Status Flag" "0: Transmit FIFO is full,1: Transmit FIFO is not full"
|
|
newline
|
|
bitfld.word 0x0 2. "RFST,Receive FIFO Status Flag" "0: Receive FIFO empty,1: Message in receive FIFO"
|
|
bitfld.word 0x0 1. "SDST,SENTDATA Status Flag" "0: No mailbox with SENTDATA = 1,1: One or more mailboxes with SENTDATA = 1"
|
|
newline
|
|
bitfld.word 0x0 0. "NDST,NEWDATA Status Flag" "0: No mailbox with NEWDATA = 1,1: One or more mailboxes with NEWDATA = 1"
|
|
group.long 0x844++0x3
|
|
line.long 0x0 "BCR,Bit Configuration Register"
|
|
hexmask.long.byte 0x0 28.--31. 1. "TSEG1,Time Segment 1 Control"
|
|
hexmask.long.word 0x0 16.--25. 1. "BRP,Baud Rate Prescaler Select"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "SJW,Synchronization Jump Width Control" "0: 1 Tq,1: 2 Tq,?,?"
|
|
bitfld.long 0x0 8.--10. "TSEG2,Time Segment 2 Control" "0: Setting prohibited,1: 2 Tq,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x0 0. "CCLKS,CAN Clock Source Selection" "0: Reserved,1: CANMCLK (generated by the main clock oscillator)"
|
|
group.byte 0x848++0x0
|
|
line.byte 0x0 "RFCR,Receive FIFO Control Register"
|
|
rbitfld.byte 0x0 7. "RFEST,Receive FIFO Empty Status Flag" "0: Unread message in receive FIFO,1: No unread message in receive FIFO"
|
|
rbitfld.byte 0x0 6. "RFWST,Receive FIFO Buffer Warning Status Flag" "0: Receive FIFO is not buffer warning,1: Receive FIFO is buffer warning (3 unread messages)"
|
|
newline
|
|
rbitfld.byte 0x0 5. "RFFST,Receive FIFO Full Status Flag" "0: Receive FIFO not full,1: Receive FIFO full (4 unread messages)"
|
|
bitfld.byte 0x0 4. "RFMLF,Receive FIFO Message Lost Flag" "0: Receive FIFO message not lost,1: Receive FIFO message lost"
|
|
newline
|
|
rbitfld.byte 0x0 1.--3. "RFUST,Receive FIFO Unread Message Number Status" "0: No unread message,1: 1 unread message,?,?,?,?,?,?"
|
|
bitfld.byte 0x0 0. "RFE,Receive FIFO Enable" "0: Disable receive FIFO,1: Enable receive FIFO"
|
|
wgroup.byte 0x849++0x0
|
|
line.byte 0x0 "RFPCR,Receive FIFO Pointer Control Register"
|
|
group.byte 0x84A++0x0
|
|
line.byte 0x0 "TFCR,Transmit FIFO Control Register"
|
|
rbitfld.byte 0x0 7. "TFEST,Transmit FIFO Empty Status" "0: Unsent message in transmit FIFO,1: No unsent message in transmit FIFO"
|
|
rbitfld.byte 0x0 6. "TFFST,Transmit FIFO Full Status" "0: Transmit FIFO not full,1: Transmit FIFO full (4 unsent messages)"
|
|
newline
|
|
rbitfld.byte 0x0 1.--3. "TFUST,Transmit FIFO Unsent Message Number Status" "0: 0 unsent messages,1: 1 unsent message,?,?,?,?,?,?"
|
|
bitfld.byte 0x0 0. "TFE,Transmit FIFO Enable" "0: Disable transmit FIFO,1: Enable transmit FIFO"
|
|
wgroup.byte 0x84B++0x0
|
|
line.byte 0x0 "TFPCR,Transmit FIFO Pointer Control Register"
|
|
group.byte 0x84C++0x1
|
|
line.byte 0x0 "EIER,Error Interrupt Enable Register"
|
|
bitfld.byte 0x0 7. "BLIE,Bus Lock Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.byte 0x0 6. "OLIE,Overload Frame Transmit Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.byte 0x0 5. "ORIE,Overrun Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.byte 0x0 4. "BORIE,Bus-Off Recovery Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.byte 0x0 3. "BOEIE,Bus-Off Entry Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.byte 0x0 2. "EPIE,Error-Passive Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
newline
|
|
bitfld.byte 0x0 1. "EWIE,Error-Warning Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
bitfld.byte 0x0 0. "BEIE,Bus Error Interrupt Enable" "0: Disable interrupt,1: Enable interrupt"
|
|
line.byte 0x1 "EIFR,Error Interrupt Factor Judge Register"
|
|
bitfld.byte 0x1 7. "BLIF,Bus Lock Detect Flag" "0: No bus lock detected,1: Bus lock detected"
|
|
bitfld.byte 0x1 6. "OLIF,Overload Frame Transmission Detect Flag" "0: No overload frame transmission detected,1: Overload frame transmission detected"
|
|
newline
|
|
bitfld.byte 0x1 5. "ORIF,Receive Overrun Detect Flag" "0: No receive overrun detected,1: Receive overrun detected"
|
|
bitfld.byte 0x1 4. "BORIF,Bus-Off Recovery Detect Flag" "0: No bus-off recovery detected,1: Bus-off recovery detected"
|
|
newline
|
|
bitfld.byte 0x1 3. "BOEIF,Bus-Off Entry Detect Flag" "0: No bus-off entry detected,1: Bus-off entry detected"
|
|
bitfld.byte 0x1 2. "EPIF,Error-Passive Detect Flag" "0: No error-passive detected,1: Error-passive detected"
|
|
newline
|
|
bitfld.byte 0x1 1. "EWIF,Error-Warning Detect Flag" "0: No error-warning detected,1: Error-warning detected"
|
|
bitfld.byte 0x1 0. "BEIF,Bus Error Detect Flag" "0: No bus error detected,1: Bus error detected"
|
|
rgroup.byte 0x84E++0x1
|
|
line.byte 0x0 "RECR,Receive Error Count Register"
|
|
line.byte 0x1 "TECR,Transmit Error Count Register"
|
|
group.byte 0x850++0x1
|
|
line.byte 0x0 "ECSR,Error Code Store Register"
|
|
bitfld.byte 0x0 7. "EDPM,Error Display Mode Select" "0: Output first detected error code,1: Output accumulated error code"
|
|
bitfld.byte 0x0 6. "ADEF,ACK Delimiter Error Flag" "0: No ACK delimiter error detected,1: ACK delimiter error detected"
|
|
newline
|
|
bitfld.byte 0x0 5. "BE0F,Bit Error (dominant) Flag" "0: No bit error (dominant) detected,1: Bit error (dominant) detected"
|
|
bitfld.byte 0x0 4. "BE1F,Bit Error (recessive) Flag" "0: No bit error (recessive) detected,1: Bit error (recessive) detected"
|
|
newline
|
|
bitfld.byte 0x0 3. "CEF,CRC Error Flag" "0: No CRC error detected,1: CRC error detected"
|
|
bitfld.byte 0x0 2. "AEF,ACK Error Flag" "0: No ACK error detected,1: ACK error detected"
|
|
newline
|
|
bitfld.byte 0x0 1. "FEF,Form Error Flag" "0: No form error detected,1: Form error detected"
|
|
bitfld.byte 0x0 0. "SEF,Stuff Error Flag" "0: No stuff error detected,1: Stuff error detected"
|
|
line.byte 0x1 "CSSR,Channel Search Support Register"
|
|
rgroup.byte 0x852++0x0
|
|
line.byte 0x0 "MSSR,Mailbox Search Status Register"
|
|
bitfld.byte 0x0 7. "SEST,Search Result Status" "0: Search result found,1: No search result"
|
|
hexmask.byte 0x0 0.--4. 1. "MBNST,Search Result Mailbox Number Status"
|
|
group.byte 0x853++0x0
|
|
line.byte 0x0 "MSMR,Mailbox Search Mode Register"
|
|
bitfld.byte 0x0 0.--1. "MBSM,Mailbox Search Mode Select" "0: Receive mailbox search mode,1: Transmit mailbox search mode,?,?"
|
|
rgroup.word 0x854++0x1
|
|
line.word 0x0 "TSR,Time Stamp Register"
|
|
group.word 0x856++0x1
|
|
line.word 0x0 "AFSR,Acceptance Filter Support Register"
|
|
group.byte 0x858++0x0
|
|
line.byte 0x0 "TCR,Test Control Register"
|
|
bitfld.byte 0x0 1.--2. "TSTM,CAN Test Mode Select" "0: Not CAN test mode,1: Listen-only mode,?,?"
|
|
bitfld.byte 0x0 0. "TSTE,CAN Test Mode Enable" "0: Disable CAN test mode,1: Enable CAN test mode"
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check Calculator)"
|
|
base ad:0x40074000
|
|
group.byte 0x0++0x1
|
|
line.byte 0x0 "CRCCR0,CRC Control Register 0"
|
|
bitfld.byte 0x0 7. "DORCLR,CRCDOR/CRCDOR_HA/CRCDOR_BY Register Clear" "0: No effect,1: Clear the CRCDOR/CRCDOR_HA/CRCDOR_BY register"
|
|
bitfld.byte 0x0 6. "LMS,CRC Calculation Switching" "0: Generate CRC code for LSB-first communication,1: Generate CRC code for MSB-first communication"
|
|
newline
|
|
bitfld.byte 0x0 0.--2. "GPS,CRC Generating Polynomial Switching" "0: No calculation is executed,1: 8-bit CRC-8 (X8 + X2 + X + 1),?,?,?,?,?,?"
|
|
line.byte 0x1 "CRCCR1,CRC Control Register 1"
|
|
bitfld.byte 0x1 7. "CRCSEN,Snoop Enable" "0: Disabled,1: Enabled"
|
|
bitfld.byte 0x1 6. "CRCSWR,Snoop-On-Write/Read Switch" "0: Snoop-on-read,1: Snoop-on-write"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CRCDIR,CRC Data Input Register"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "CRCDIR_BY,CRC Data Input Register"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CRCDOR,CRC Data Output Register"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "CRCDOR_HA,CRC Data Output Register"
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "CRCDOR_BY,CRC Data Output Register"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "CRCSAR,Snoop Address Register"
|
|
hexmask.word 0x0 0.--13. 1. "CRCSA,Register Snoop Address"
|
|
tree.end
|
|
tree "CTSU2 (Capacitive Touch Sensing Unit)"
|
|
base ad:0x40082000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "CTSUCRA,CTSU Control Register A"
|
|
bitfld.long 0x0 31. "DCBACK,CTSU Current Measurement Feedback Select" "0: TSCAP pin is selected,1: Measurement pin is selected. It is recommended.."
|
|
bitfld.long 0x0 30. "DCMODE,CTSU Current Measurement Mode Select" "0: Electrostatic capacitance measurement mode,1: Current measurement mode"
|
|
newline
|
|
hexmask.long.byte 0x0 24.--29. 1. "STCLK,CTSU STCLK Select"
|
|
bitfld.long 0x0 23. "PCSEL,CTSU Boost Circuit Clock Select" "0: Sensor drive pulse divided by 2,1: STCLK"
|
|
newline
|
|
bitfld.long 0x0 22. "SDPSEL,CTSU Sensor Drive Pulse Select" "0: Random pulse,1: Normal pulse using the sensor unit clock"
|
|
bitfld.long 0x0 20.--21. "POSEL,CTSU Non-Measured Channel Output Select" "0: Output low,1: Hi-Z,?,?"
|
|
newline
|
|
bitfld.long 0x0 18.--19. "LOAD,CTSU Load Control During Measurement" "0: 2.5 microA constant current load,1: No load,?,?"
|
|
bitfld.long 0x0 17. "ATUNE2,CTSU Current Range Adjustment" "0: 80 microA when ATUNE1 = 0 40 microA when ATUNE1..,1: 20 microA when ATUNE1 = 0 160 microA when ATUNE1.."
|
|
newline
|
|
bitfld.long 0x0 16. "MD2,CTSU Measurement Mode Select 2" "0: Measure the switched capacitor current and the..,1: Measure the charge transfer by CFC circuit.."
|
|
bitfld.long 0x0 15. "MD1,CTSU Measurement Mode Select 1" "0: One-time measurement (self-capacitance method),1: Two times measurement (mutual capacitance method)"
|
|
newline
|
|
bitfld.long 0x0 14. "MD0,CTSU Measurement Mode Select 0" "0: Single scan mode,1: Multi-scan mode"
|
|
bitfld.long 0x0 12.--13. "CLK,CTSU Operating Clock Select" "0: PCLKB,1: PCLKB/2 (PCLKB divided by 2),?,?"
|
|
newline
|
|
bitfld.long 0x0 11. "ATUNE1,CTSU Current Range Adjustment" "0: 80 microA when ATUNE2 = 0 20 microA when ATUNE2..,1: 40 microA when ATUNE2 = 0 160 microA when ATUNE2.."
|
|
bitfld.long 0x0 10. "ATUNE0,CTSU Power Supply Operating Mode Setting" "0: VCC >= 2.4 V: Normal voltage operating mode VCC..,1: Low-voltage operating mode"
|
|
newline
|
|
bitfld.long 0x0 9. "CSW,TSCAP Pin Enable" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 8. "PON,CTSU Power On Control" "0: Power off the CTSU,1: Power on the CTSU"
|
|
newline
|
|
bitfld.long 0x0 6.--7. "TXVSEL,CTSU Transmission Power Supply Selection" "0: Selecting VCC as the power supply for the..,1: Selecting VCC as the power supply for the..,?,?"
|
|
bitfld.long 0x0 5. "PUMPON,CTSU Boost Circuit Control" "0: Boost circuit off,1: Boost circuit on"
|
|
newline
|
|
bitfld.long 0x0 4. "INIT,CTSU Control Block Initialization" "0,1"
|
|
bitfld.long 0x0 3. "CFCON,CTSU CFC Power On Control" "0: CFC power off,1: CFC power on"
|
|
newline
|
|
bitfld.long 0x0 2. "SNZ,CTSU Wait State Power-Saving Enable" "0: Disable power-saving function during wait state,1: Enable power-saving function during wait state"
|
|
bitfld.long 0x0 1. "CAP,CTSU Measurement Operation Start Trigger Select" "0: Software trigger,1: External trigger"
|
|
newline
|
|
bitfld.long 0x0 0. "STRT,CTSU Measurement Operation Start" "0: Stop measurement operation,1: Start measurement operation"
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "CTSUCRAL,CTSU Control Register A"
|
|
group.byte 0x0++0x3
|
|
line.byte 0x0 "CTSUCR0,CTSU Control Register A"
|
|
line.byte 0x1 "CTSUCR1,CTSU Control Register A"
|
|
line.byte 0x2 "CTSUCR2,CTSU Control Register A"
|
|
line.byte 0x3 "CTSUCR3,CTSU Control Register A"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "CTSUCRB,CTSU Control Register B"
|
|
bitfld.long 0x0 28.--29. "SSCNT,Adjusting the SUCLK frequency" "0: CTSUTRIMA.SUADJD + 0x00 (SDPSEL = 0)..,1: CTSUTRIMA.SUADJD + 0x10 (SDPSEL = 0)..,?,?"
|
|
bitfld.long 0x0 24.--26. "SSMOD,Spread Spectrum Modulation Frequency" "0: No spreading,1: 83.3 kHz,?,?,?,?,?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SST,Wait Time Sensor Stabilization"
|
|
bitfld.long 0x0 7. "PROFF,Drive Pulse Phase Control" "0: The drive pulse phase is controlled by random..,1: The drive pulse phase is not controlled by.."
|
|
newline
|
|
bitfld.long 0x0 6. "SOFF,High-Pass Noise Reduction Function Disable" "0: Turn the spread spectrum on,1: Turn the spread spectrum off"
|
|
bitfld.long 0x0 4.--5. "PRMODE,Phase Control Period" "0: 510 pulses (512 pulses when PROFF = 1),1: 126 pulses (128 pulses when PROFF = 1),?,?"
|
|
newline
|
|
hexmask.long.byte 0x0 0.--3. 1. "PRRATIO,Frequency of Drive Pulse Phase Control"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "CTSUCRBL,CTSU Control Register B"
|
|
group.byte 0x4++0x1
|
|
line.byte 0x0 "CTSUSDPRS,CTSU Control Register B"
|
|
line.byte 0x1 "CTSUSST,CTSU Control Register B"
|
|
group.word 0x6++0x1
|
|
line.word 0x0 "CTSUCRBH,CTSU Control Register B"
|
|
group.byte 0x7++0x0
|
|
line.byte 0x0 "CTSUDCLKC,CTSU Control Register B"
|
|
group.long 0x8++0x3
|
|
line.long 0x0 "CTSUMCH,CTSU Measurement Channel Register"
|
|
bitfld.long 0x0 19. "MCA3,Multiple Clocks Control" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 18. "MCA2,Multiple Clocks Control" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.long 0x0 17. "MCA1,Multiple Clocks Control" "0: Disable,1: Enable"
|
|
bitfld.long 0x0 16. "MCA0,Multiple Clocks Control" "0: Disable,1: Enable"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--13. 1. "MCH1,CTSU Measurement Channel 1"
|
|
hexmask.long.byte 0x0 0.--5. 1. "MCH0,CTSU Measurement Channel 0"
|
|
group.word 0x8++0x1
|
|
line.word 0x0 "CTSUMCHL,CTSU Measurement Channel Register"
|
|
group.byte 0x8++0x1
|
|
line.byte 0x0 "CTSUMCH0,CTSU Measurement Channel Register"
|
|
line.byte 0x1 "CTSUMCH1,CTSU Measurement Channel Register"
|
|
group.word 0xA++0x1
|
|
line.word 0x0 "CTSUMCHH,CTSU Measurement Channel Register"
|
|
group.byte 0xA++0x0
|
|
line.byte 0x0 "CTSUMFAF,CTSU Measurement Channel Register"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "CTSUCHACA,CTSU Channel Enable Control Register A"
|
|
bitfld.long 0x0 31. "CHAC31,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 30. "CHAC30,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 29. "CHAC29,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 28. "CHAC28,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 27. "CHAC27,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 26. "CHAC26,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 25. "CHAC25,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 24. "CHAC24,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 23. "CHAC23,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 22. "CHAC22,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 21. "CHAC21,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 18. "CHAC18,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 17. "CHAC17,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 16. "CHAC16,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 15. "CHAC15,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 14. "CHAC14,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 13. "CHAC13,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 12. "CHAC12,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 11. "CHAC11,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 10. "CHAC10,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 9. "CHAC09,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 8. "CHAC08,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 7. "CHAC07,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 6. "CHAC06,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 5. "CHAC05,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 4. "CHAC04,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 2. "CHAC02,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 0. "CHAC00,CTSU Channel Enable Control A" "0: Do not measure.,1: Measure."
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "CTSUCHACAL,CTSU Channel Enable Control Register A"
|
|
group.byte 0xC++0x1
|
|
line.byte 0x0 "CTSUCHAC0,CTSU Channel Enable Control Register A"
|
|
line.byte 0x1 "CTSUCHAC1,CTSU Channel Enable Control Register A"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "CTSUCHACAH,CTSU Channel Enable Control Register A"
|
|
group.byte 0xE++0x1
|
|
line.byte 0x0 "CTSUCHAC2,CTSU Channel Enable Control Register A"
|
|
line.byte 0x1 "CTSUCHAC3,CTSU Channel Enable Control Register A"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "CTSUCHACB,CTSU Channel Enable Control Register B"
|
|
bitfld.long 0x0 3. "CHAC35,CTSU Channel Enable Control B" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 2. "CHAC34,CTSU Channel Enable Control B" "0: Do not measure.,1: Measure."
|
|
newline
|
|
bitfld.long 0x0 1. "CHAC33,CTSU Channel Enable Control B" "0: Do not measure.,1: Measure."
|
|
bitfld.long 0x0 0. "CHAC32,CTSU Channel Enable Control B" "0: Do not measure.,1: Measure."
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "CTSUCHACBL,CTSU Channel Enable Control Register B"
|
|
group.byte 0x10++0x0
|
|
line.byte 0x0 "CTSUCHAC4,CTSU Channel Enable Control Register B"
|
|
group.long 0x14++0x3
|
|
line.long 0x0 "CTSUCHTRCA,CTSU Channel Transmit/Receive Control Register A"
|
|
bitfld.long 0x0 31. "CHTRC31,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 30. "CHTRC30,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 29. "CHTRC29,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 28. "CHTRC28,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 27. "CHTRC27,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 26. "CHTRC26,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 25. "CHTRC25,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 24. "CHTRC24,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 23. "CHTRC23,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 22. "CHTRC22,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 21. "CHTRC21,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 18. "CHTRC18,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 17. "CHTRC17,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 16. "CHTRC16,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 15. "CHTRC15,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 14. "CHTRC14,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 13. "CHTRC13,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 12. "CHTRC12,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 11. "CHTRC11,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 10. "CHTRC10,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 9. "CHTRC09,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 8. "CHTRC08,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 7. "CHTRC07,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 6. "CHTRC06,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 5. "CHTRC05,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 4. "CHTRC04,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 2. "CHTRC02,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 0. "CHTRC00,CTSU Channel Transmit/Receive Control A" "0: Reception,1: Transmission"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "CTSUCHTRCAL,CTSU Channel Transmit/Receive Control Register A"
|
|
group.byte 0x14++0x1
|
|
line.byte 0x0 "CTSUCHTRC0,CTSU Channel Transmit/Receive Control Register A"
|
|
line.byte 0x1 "CTSUCHTRC1,CTSU Channel Transmit/Receive Control Register A"
|
|
group.word 0x16++0x1
|
|
line.word 0x0 "CTSUCHTRCAH,CTSU Channel Transmit/Receive Control Register A"
|
|
group.byte 0x16++0x1
|
|
line.byte 0x0 "CTSUCHTRC2,CTSU Channel Transmit/Receive Control Register A"
|
|
line.byte 0x1 "CTSUCHTRC3,CTSU Channel Transmit/Receive Control Register A"
|
|
group.long 0x18++0x3
|
|
line.long 0x0 "CTSUCHTRCB,CTSU Channel Transmit/Receive Control Register B"
|
|
bitfld.long 0x0 3. "CHTRC35,CTSU Channel Transmit/Receive Control B" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 2. "CHTRC34,CTSU Channel Transmit/Receive Control B" "0: Reception,1: Transmission"
|
|
newline
|
|
bitfld.long 0x0 1. "CHTRC33,CTSU Channel Transmit/Receive Control B" "0: Reception,1: Transmission"
|
|
bitfld.long 0x0 0. "CHTRC32,CTSU Channel Transmit/Receive Control B" "0: Reception,1: Transmission"
|
|
group.word 0x18++0x1
|
|
line.word 0x0 "CTSUCHTRCBL,CTSU Channel Transmit/Receive Control Register B"
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "CTSUCHTRC4,CTSU Channel Transmit/Receive Control Register B"
|
|
group.long 0x1C++0x3
|
|
line.long 0x0 "CTSUSR,CTSU Status Register"
|
|
hexmask.long.byte 0x0 16.--21. 1. "CFCRDCH,CTSU CFC Read Channel Select"
|
|
rbitfld.long 0x0 15. "PS,CTSU Mutual Capacitance Status Flag" "0: First measurement,1: Second measurement"
|
|
newline
|
|
bitfld.long 0x0 14. "SUOVF,CTSU SUCLK Counter Overflow Flag" "0: No overflow occurred,1: Overflow occurred"
|
|
bitfld.long 0x0 13. "SENSOVF,CTSU Sensor Counter Overflow Flag" "0: No overflow occurred,1: Overflow occurred"
|
|
newline
|
|
rbitfld.long 0x0 12. "DTSR,CTSU Data Transfer Status Flag" "0: Read,1: Not read"
|
|
rbitfld.long 0x0 8.--10. "STC,CTSU Measurement Status Counter" "0: Status 0,1: Status 1,?,?,?,?,?,?"
|
|
newline
|
|
rbitfld.long 0x0 7. "ICOMP0,TSCAP Voltage Error Monitor" "0: Normal TSCAP voltage,1: Abnormal TSCAP voltage"
|
|
rbitfld.long 0x0 6. "ICOMP1,CTSU Sense Current Error Monitor" "0: Normal sensor current,1: Abnormal sensor current"
|
|
newline
|
|
bitfld.long 0x0 5. "ICOMPRST,CTSU CTSUICOMP1 Flag Reset" "0,1"
|
|
bitfld.long 0x0 0.--1. "MFC,CTSU Multi-Clock Counter" "0: Multi-clock 0,1: Multi-clock 1,?,?"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "CTSUSRL,CTSU Status Register"
|
|
group.byte 0x1C++0x1
|
|
line.byte 0x0 "CTSUSR0,CTSU Status Register"
|
|
line.byte 0x1 "CTSUST,CTSU Status Register"
|
|
group.word 0x1E++0x1
|
|
line.word 0x0 "CTSUSRH,CTSU Status Register"
|
|
group.byte 0x1E++0x0
|
|
line.byte 0x0 "CTSUSR2,CTSU Status Register"
|
|
group.long 0x20++0x3
|
|
line.long 0x0 "CTSUSO,CTSU Sensor Offset Register"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SDPA,CTSU Base Clock Setting"
|
|
hexmask.long.byte 0x0 20.--23. 1. "SSDIV,Spread Spectrum Frequency"
|
|
newline
|
|
hexmask.long.byte 0x0 10.--17. 1. "SNUM,CTSU Measurement Count Setting"
|
|
hexmask.long.word 0x0 0.--9. 1. "SO,CTSU Sensor Offset Adjustment"
|
|
group.word 0x20++0x3
|
|
line.word 0x0 "CTSUSO0,CTSU Sensor Offset Register"
|
|
line.word 0x2 "CTSUSO1,CTSU Sensor Offset Register"
|
|
rgroup.long 0x24++0x3
|
|
line.long 0x0 "CTSUSCNT,CTSU Sensor Counter Register"
|
|
hexmask.long.word 0x0 16.--31. 1. "SUCKCNT,CTSU SUCLK Counter"
|
|
hexmask.long.word 0x0 0.--15. 1. "SENSCNT,CTSU Sensor Counter"
|
|
rgroup.word 0x24++0x1
|
|
line.word 0x0 "CTSUSC,CTSU Sensor Counter Register"
|
|
group.long 0x28++0x3
|
|
line.long 0x0 "CTSUCALIB,CTSU Calibration Register"
|
|
bitfld.long 0x0 31. "TXREV,Transmit Pin Inverted Output" "0: Normal,1: Invert"
|
|
bitfld.long 0x0 30. "CCOCALIB,Calibration Selection of Current Controlled Oscillator for Measurement" "0: Capacitance measurement mode,1: Oscillator calibration mode"
|
|
newline
|
|
bitfld.long 0x0 29. "CCOCLK,Modulation Clock Select for Current Controlled Oscillator Input Current of SUCLK" "0: Operating clock selected by CTSUCRA.CLK [1:0],1: SUCLK"
|
|
bitfld.long 0x0 28. "DACCLK,Modulation Clock Select for Offset Current Circuits" "0: Operating clock selected by CTSUCRA.CLK [1:0],1: SUCLK"
|
|
newline
|
|
bitfld.long 0x0 27. "SUCARRY,Current Control Oscillator Input Current Adjustment for SUCLK" "0: Normal operation,1: All current sources can be turned on"
|
|
bitfld.long 0x0 26. "SUMSEL,Current Control Oscillator Input Current Matrix Calibration Select" "0: Capacitance measurement mode,1: Current control oscillator input current matrix.."
|
|
newline
|
|
bitfld.long 0x0 25. "DACCARRY,Offset Current Adjustment for Calibration" "0: Normal operation,1: All current sources can be turned on"
|
|
bitfld.long 0x0 24. "DACMSEL,Current Offset DAC Current Matrix Calibration Select" "0: Capacitance measurement mode,1: Current offset DAC current Calibration mode"
|
|
newline
|
|
bitfld.long 0x0 22. "CFCMODE,CFC Oscillator Calibration Mode Select" "0: CFC current measurement (Capacitance measurement..,1: External current measurement for calibration"
|
|
hexmask.long.byte 0x0 16.--21. 1. "CFCSEL,Observation CFC Clock Select"
|
|
newline
|
|
bitfld.long 0x0 11. "DCOFF,Down Converter Control" "0: Voltage down converter operation (TSCAP voltage..,1: The voltage down converter is off"
|
|
bitfld.long 0x0 10. "CFCRDMD,CFC Counter Read Mode Select" "0: Except for mutual capacitance parallel..,1: Mutual capacitance parallel measurement mode"
|
|
newline
|
|
bitfld.long 0x0 9. "IOC,TS Pin Fixed Output Value Set" "0: Low level,1: High level"
|
|
bitfld.long 0x0 8. "CNTRDSEL,Read Count Select of Sensor Counter" "0: Read once,1: Read twice"
|
|
newline
|
|
bitfld.long 0x0 7. "TSOC,Switched Capacitor Operation Calibration Select Bit" "0: Capacitance measurement mode,1: Switched capacitor operation calibration mode"
|
|
bitfld.long 0x0 6. "SUCLKEN,SUCLK Forced Oscillation Control" "0: SUCLK oscillation only during measurement,1: SUCLK always oscillates"
|
|
newline
|
|
bitfld.long 0x0 4.--5. "CLKSEL,Observation Clock Select" "0: Not selected (L fixed output),1: Measurement clock (divided by 8),?,?"
|
|
bitfld.long 0x0 3. "DRV,Power Supply Calibration Select" "0: Capacitance measurement mode,1: Power supply calibration mode"
|
|
newline
|
|
bitfld.long 0x0 2. "TSOD,TS Pin Fixed Output" "0: Capacitance measurement mode,1: Output high or low from TS terminals.."
|
|
group.word 0x28++0x3
|
|
line.word 0x0 "CTSUDBGR0,CTSU Calibration Register"
|
|
line.word 0x2 "CTSUDBGR1,CTSU Calibration Register"
|
|
group.long 0x2C++0x3
|
|
line.long 0x0 "CTSUSUCLKA,CTSU Sensor Unit Clock Control Register A"
|
|
group.word 0x2C++0x3
|
|
line.word 0x0 "CTSUSUCLK0,CTSU Sensor Unit Clock Control Register A"
|
|
line.word 0x2 "CTSUSUCLK1,CTSU Sensor Unit Clock Control Register A"
|
|
group.long 0x30++0x3
|
|
line.long 0x0 "CTSUSUCLKB,CTSU Sensor Unit Clock Control Register B"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SUMULTI3,CTSU SUCLK Multiplier Rate Setting"
|
|
hexmask.long.byte 0x0 16.--23. 1. "SUADJ3,CTSU SUCLK Frequency Adjustment"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "SUMULTI2,CTSU SUCLK Multiplier Rate Setting"
|
|
hexmask.long.byte 0x0 0.--7. 1. "SUADJ2,CTSU SUCLK Frequency Adjustment"
|
|
group.word 0x30++0x3
|
|
line.word 0x0 "CTSUSUCLK2,CTSU Sensor Unit Clock Control Register B"
|
|
line.word 0x2 "CTSUSUCLK3,CTSU Sensor Unit Clock Control Register B"
|
|
rgroup.long 0x34++0x3
|
|
line.long 0x0 "CTSUCFCCNT,CTSU CFC Counter Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "CFCCNT,CTSU CFC Counter"
|
|
rgroup.word 0x34++0x1
|
|
line.word 0x0 "CTSUCFCCNTL,CTSU CFC Counter Register"
|
|
tree.end
|
|
tree "DAC12 (12-bit D/A Converter)"
|
|
base ad:0x4005E000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "DADR0,D/A Data Register 0"
|
|
group.byte 0x4++0x3
|
|
line.byte 0x0 "DACR,D/A Control Register"
|
|
bitfld.byte 0x0 6. "DAOE0,D/A Output Enable 0" "0: Disable analog output of channel 0 (DA0),1: Enable D/A conversion of channel 0 (DA0)"
|
|
line.byte 0x1 "DADPR,DADR0 Format Select Register"
|
|
bitfld.byte 0x1 7. "DPSEL,DADR0 Format Select" "0: Right-justified format,1: Left-justified format"
|
|
line.byte 0x2 "DAADSCR,D/A A/D Synchronous Start Control Register"
|
|
bitfld.byte 0x2 7. "DAADST,D/A A/D Synchronous Conversion" "0: Do not synchronize DAC12 with ADC12 operation..,1: Synchronize DAC12 with ADC12 operation (enable.."
|
|
line.byte 0x3 "DAVREFCR,D/A VREF Control Register"
|
|
bitfld.byte 0x3 0. "REF,D/A Reference Voltage Select" "0: No reference voltage selected.,1: AVCC0/AVSS0 selected."
|
|
tree.end
|
|
tree "DBG (Debug Function)"
|
|
base ad:0x4001B000
|
|
rgroup.long 0x0++0x3
|
|
line.long 0x0 "DBGSTR,Debug Status Register"
|
|
bitfld.long 0x0 29. "CDBGPWRUPACK,Debug power-up acknowledge" "0: Debug power-up request is not acknowledged,1: Debug power-up request is acknowledged"
|
|
bitfld.long 0x0 28. "CDBGPWRUPREQ,Debug power-up request" "0: OCD is not requesting debug power up,1: OCD is requesting debug power up"
|
|
group.long 0x10++0x3
|
|
line.long 0x0 "DBGSTOPCR,Debug Stop Control Register"
|
|
bitfld.long 0x0 25. "DBGSTOP_RECCR,Mask bit for SRAM ECC error reset/interrupt" "0: Enable SRAM ECC error reset/interrupt,1: Mask SRAM ECC error reset/interrupt"
|
|
bitfld.long 0x0 24. "DBGSTOP_RPER,Mask bit for SRAM parity error reset/interrupt" "0: Enable SRAM parity error reset/interrupt,1: Mask SRAM parity error reset/interrupt"
|
|
newline
|
|
bitfld.long 0x0 18. "DBGSTOP_LVD2,Mask bit for LVD2 reset/interrupt" "0: Enable LVD2 reset/interrupt,1: Mask LVD2 reset/interrupt"
|
|
bitfld.long 0x0 17. "DBGSTOP_LVD1,Mask bit for LVD1 reset/interrupt" "0: Enable LVD1 reset/interrupt,1: Mask LVD1 reset/interrupt"
|
|
newline
|
|
bitfld.long 0x0 16. "DBGSTOP_LVD0,Mask bit for LVD0 reset" "0: Enable LVD0 reset,1: Mask LVD0 reset"
|
|
bitfld.long 0x0 1. "DBGSTOP_WDT,Mask bit for WDT reset/interrupt in the OCD run mode" "0: Enable WDT reset/interrupt,1: Mask WDT reset/interrupt and stop WDT counter"
|
|
newline
|
|
bitfld.long 0x0 0. "DBGSTOP_IWDT,Mask bit for IWDT reset/interrupt in the OCD run mode" "0: Enable IWDT reset/interrupt,1: Mask IWDT reset/interrupt and stop IWDT counter"
|
|
tree.end
|
|
tree "DOC (Data Operation Circuit)"
|
|
base ad:0x40054100
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "DOCR,DOC Control Register"
|
|
bitfld.byte 0x0 6. "DOPCFCL,DOPCF Clear" "0: Retain DOPCF flag state,1: Clear DOPCF flag"
|
|
rbitfld.byte 0x0 5. "DOPCF,DOC Flag" "0,1"
|
|
bitfld.byte 0x0 2. "DCSEL,Detection Condition Select" "0: Set DOPCF flag when data mismatch is detected,1: Set DOPCF flag when data match is detected"
|
|
bitfld.byte 0x0 0.--1. "OMS,Operating Mode Select" "0: Data comparison mode,1: Data addition mode,?,?"
|
|
group.word 0x2++0x3
|
|
line.word 0x0 "DODIR,DOC Data Input Register"
|
|
line.word 0x2 "DODSR,DOC Data Setting Register"
|
|
tree.end
|
|
tree "DTC (Data Transfer Controller)"
|
|
base ad:0x40005400
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "DTCCR,DTC Control Register"
|
|
bitfld.byte 0x0 4. "RRS,DTC Transfer Information Read Skip Enable" "0: Transfer information read is not skipped,1: Transfer information read is skipped when vector.."
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "DTCVBR,DTC Vector Base Register"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "DTCST,DTC Module Start Register"
|
|
bitfld.byte 0x0 0. "DTCST,DTC Module Start" "0: DTC module stopped.,1: DTC module started."
|
|
rgroup.word 0xE++0x1
|
|
line.word 0x0 "DTCSTS,DTC Status Register"
|
|
bitfld.word 0x0 15. "ACT,DTC Active Flag" "0: DTC transfer operation is not in progress.,1: DTC transfer operation is in progress."
|
|
hexmask.word.byte 0x0 0.--7. 1. "VECN,DTC-Activating Vector Number Monitoring"
|
|
tree.end
|
|
tree "ELC (Event Link Controller)"
|
|
base ad:0x40041000
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "ELCR,Event Link Controller Register"
|
|
bitfld.byte 0x0 7. "ELCON,All Event Link Enable" "0: ELC function is disabled.,1: ELC function is enabled."
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "ELSEGR$1,Event Link Software Event Generation Register %s"
|
|
bitfld.byte 0x0 7. "WI,ELSEGR Register Write Disable" "0: Write to ELSEGR register enabled.,1: Write to ELSEGR register disabled."
|
|
bitfld.byte 0x0 6. "WE,SEG Bit Write Enable" "0: Write to SEG bit disabled.,1: Write to SEG bit enabled."
|
|
bitfld.byte 0x0 0. "SEG,Software Event Generation" "0: Normal operation,1: Software event is generated."
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x10)++0x1
|
|
line.word 0x0 "ELSR$1,Event Link Setting Register %s"
|
|
hexmask.word.byte 0x0 0.--7. 1. "ELS,Event Link Select"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x30)++0x1
|
|
line.word 0x0 "ELSR$1,Event Link Setting Register %s"
|
|
hexmask.word.byte 0x0 0.--7. 1. "ELS,Event Link Select"
|
|
repeat.end
|
|
group.word 0x40++0x1
|
|
line.word 0x0 "ELSR12,Event Link Setting Register 12"
|
|
hexmask.word.byte 0x0 0.--7. 1. "ELS,Event Link Select"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x48)++0x1
|
|
line.word 0x0 "ELSR$1,Event Link Setting Register %s"
|
|
hexmask.word.byte 0x0 0.--7. 1. "ELS,Event Link Select"
|
|
repeat.end
|
|
group.word 0x58++0x1
|
|
line.word 0x0 "ELSR18,Event Link Setting Register 18"
|
|
hexmask.word.byte 0x0 0.--7. 1. "ELS,Event Link Select"
|
|
tree.end
|
|
tree "FLCN (Flash I/O Registers)"
|
|
base ad:0x407EC000
|
|
group.byte 0x90++0x0
|
|
line.byte 0x0 "DFLCTL,Data Flash Control Register"
|
|
bitfld.byte 0x0 0. "DFLEN,Data Flash Access Enable" "0: Access to the data flash is disabled,1: Access to the data flash is enabled"
|
|
group.byte 0x100++0x0
|
|
line.byte 0x0 "FPMCR,Flash P/E Mode Control Register"
|
|
bitfld.byte 0x0 4. "FMS1,Flash Operating Mode Select 1" "0,1"
|
|
bitfld.byte 0x0 3. "RPDIS,Code Flash P/E Disable" "0: Programming of the code flash is enabled,1: Programming of the code flash is disabled."
|
|
newline
|
|
bitfld.byte 0x0 1. "FMS0,Flash Operating Mode Select 0" "0: FMS1 = 0: Read mode FMS1 = 1: Data flash P/E..,1: FMS1 = 0: Code flash P/E mode FMS1 = 1: Setting.."
|
|
group.byte 0x104++0x0
|
|
line.byte 0x0 "FASR,Flash Area Select Register"
|
|
bitfld.byte 0x0 0. "EXS,Extra Area Select" "0: User area or data area,1: Extra area."
|
|
group.word 0x108++0x1
|
|
line.word 0x0 "FSARL,Flash Processing Start Address Register L"
|
|
hexmask.word 0x0 0.--15. 1. "FSARL,Flash Processing Start Address L"
|
|
group.word 0x110++0x1
|
|
line.word 0x0 "FSARH,Flash Processing Start Address Register H"
|
|
hexmask.word 0x0 0.--15. 1. "FSARH,Flash Processing Start Address H"
|
|
group.byte 0x114++0x0
|
|
line.byte 0x0 "FCR,Flash Control Register"
|
|
bitfld.byte 0x0 7. "OPST,Processing Start" "0: Processing stops,1: Processing starts."
|
|
bitfld.byte 0x0 6. "STOP,Forced Processing Stop" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 4. "DRC,Data Read Completion" "0: Data is not read or next data is requested,1: Data reading is complete."
|
|
hexmask.byte 0x0 0.--3. 1. "CMD,Software Command Setting"
|
|
group.word 0x118++0x1
|
|
line.word 0x0 "FEARL,Flash Processing End Address Register L"
|
|
hexmask.word 0x0 0.--15. 1. "FEARL,Flash Processing End Address L"
|
|
group.word 0x120++0x1
|
|
line.word 0x0 "FEARH,Flash Processing End Address Register H"
|
|
hexmask.word 0x0 0.--15. 1. "FEARH,Flash Processing End Address H"
|
|
group.byte 0x124++0x0
|
|
line.byte 0x0 "FRESETR,Flash Reset Register"
|
|
bitfld.byte 0x0 0. "FRESET,Software reset of the registers" "0: The registers related to the flash programming..,1: The registers related to the flash programming.."
|
|
rgroup.byte 0x12C++0x0
|
|
line.byte 0x0 "FSTATR1,Flash Status Register 1"
|
|
bitfld.byte 0x0 7. "EXRDY,Extra Area Ready Flag" "0: The software command of the FEXCR register is..,1: The software command of the FEXCR register is.."
|
|
bitfld.byte 0x0 6. "FRDY,Flash Ready Flag" "0: The software command of the FCR register is not..,1: The software command of the FCR register is.."
|
|
newline
|
|
bitfld.byte 0x0 1. "DRRDY,Data Read Ready Flag" "0: The read processing of the consecutive read..,1: The read processing of the consecutive read.."
|
|
group.word 0x130++0x1
|
|
line.word 0x0 "FWBL0,Flash Write Buffer Register L0"
|
|
hexmask.word 0x0 0.--15. 1. "WDATA,Flash Write Buffer L0"
|
|
group.word 0x138++0x1
|
|
line.word 0x0 "FWBH0,Flash Write Buffer Register H0"
|
|
hexmask.word 0x0 0.--15. 1. "WDATA,Flash Write Buffer H0"
|
|
group.byte 0x180++0x0
|
|
line.byte 0x0 "FPR,Protection Unlock Register"
|
|
hexmask.byte 0x0 0.--7. 1. "FPR,Protection Unlock"
|
|
rgroup.byte 0x184++0x0
|
|
line.byte 0x0 "FPSR,Protection Unlock Status Register"
|
|
bitfld.byte 0x0 0. "PERR,Protect Error Flag" "0: No error,1: An error occurs"
|
|
rgroup.word 0x188++0x1
|
|
line.word 0x0 "FRBL0,Flash Read Buffer Register L0"
|
|
hexmask.word 0x0 0.--15. 1. "RDATA,Flash Read Buffer L0"
|
|
rgroup.word 0x190++0x1
|
|
line.word 0x0 "FRBH0,Flash Read Buffer Register H0"
|
|
hexmask.word 0x0 0.--15. 1. "RDATA,Flash Read Buffer H0"
|
|
rgroup.word 0x1C0++0x1
|
|
line.word 0x0 "FSCMR,Flash Start-Up Setting Monitor Register"
|
|
bitfld.word 0x0 14. "FSPR,Access Window Protection Flag" "0: Access window setting disabled.,1: Access window setting enabled."
|
|
bitfld.word 0x0 8. "SASMF,Startup Area Setting Monitor Flag" "0: Setting to start up using the alternative area,1: Setting to start up using the default area"
|
|
rgroup.word 0x1C8++0x1
|
|
line.word 0x0 "FAWSMR,Flash Access Window Start Address Monitor Register"
|
|
bitfld.word 0x0 15. "FSPR,Access Window Protection Flag" "0,1"
|
|
hexmask.word 0x0 0.--10. 1. "FAWS,Access Window Start Address"
|
|
rgroup.word 0x1D0++0x1
|
|
line.word 0x0 "FAWEMR,Flash Access Window End Address Monitor Register"
|
|
bitfld.word 0x0 15. "SASMF,Startup Area Setting Monitor Flag" "0,1"
|
|
hexmask.word 0x0 0.--10. 1. "FAWE,Access Window End Address"
|
|
group.byte 0x1D8++0x0
|
|
line.byte 0x0 "FISR,Flash Initial Setting Register"
|
|
bitfld.byte 0x0 6.--7. "SAS,Startup Area Select" "0: The startup area is selected according to the..,?,?,?"
|
|
hexmask.byte 0x0 0.--5. 1. "PCKA,Flash-IF Clock Notification"
|
|
group.byte 0x1DC++0x0
|
|
line.byte 0x0 "FEXCR,Flash Extra Area Control Register"
|
|
bitfld.byte 0x0 7. "OPST,Processing Start" "0: Processing stops,1: Processing starts."
|
|
bitfld.byte 0x0 0.--2. "CMD,Software Command Setting" "0: Setting prohibited.,?,?,?,?,?,?,?"
|
|
group.word 0x1E0++0x1
|
|
line.word 0x0 "FEAML,Flash Error Address Monitor Register L"
|
|
hexmask.word 0x0 0.--15. 1. "FEAML,Flash Error Address Monitor Register L"
|
|
group.word 0x1E8++0x1
|
|
line.word 0x0 "FEAMH,Flash Error Address Monitor Register H"
|
|
hexmask.word 0x0 0.--15. 1. "FEAMH,Flash Error Address Monitor Register H"
|
|
rgroup.word 0x1F0++0x1
|
|
line.word 0x0 "FSTATR2,Flash Status Register 2"
|
|
bitfld.word 0x0 5. "EILGLERR,Extra Area Illegal Command Error Flag" "0: No illegal command or illegal access to the..,1: An illegal command or illegal access to the.."
|
|
bitfld.word 0x0 4. "ILGLERR,Illegal Command Error Flag" "0: No illegal software command or illegal access is..,1: An illegal command or illegal access is detected."
|
|
newline
|
|
bitfld.word 0x0 3. "BCERR,Blank Check Error Flag" "0: Blank checking terminates normally,1: An error occurs during blank checking."
|
|
bitfld.word 0x0 2. "PRGERR01,Program Error Flag 01" "0: Programming by the FEXCR register terminates..,1: An error occurs during programming."
|
|
newline
|
|
bitfld.word 0x0 1. "PRGERR,Program Error Flag" "0: Programming terminates normally,1: An error occurs during programming."
|
|
bitfld.word 0x0 0. "ERERR,Erase Error Flag" "0: Erasure terminates normally,1: An error occurs during erasure"
|
|
rgroup.long 0x228++0x3
|
|
line.long 0x0 "TSCDR,Temperature Sensor Calibration Data Register"
|
|
hexmask.long.word 0x0 0.--15. 1. "TSCDR,Temperature Sensor Calibration Data"
|
|
group.long 0x3A4++0x7
|
|
line.long 0x0 "CTSUTRIMA,CTSU Trimming Register A"
|
|
hexmask.long.byte 0x0 24.--31. 1. "SUADJTRIM,Coefficient of variation for the reference load resistance"
|
|
hexmask.long.byte 0x0 16.--23. 1. "SUADJD,CTSU SUCLK Frequency Adjustment"
|
|
newline
|
|
hexmask.long.byte 0x0 8.--15. 1. "DACTRIM,Linearity Adjustment of Offset Current"
|
|
hexmask.long.byte 0x0 0.--7. 1. "RTRIM,CTSU Reference Resistance Adjustment"
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|
line.long 0x4 "CTSUTRIMB,CTSU Trimming Register B"
|
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hexmask.long.byte 0x4 24.--31. 1. "TRESULT3,The coefficient of variation for the 60 kOhm reference load resistance is stored."
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hexmask.long.byte 0x4 16.--23. 1. "TRESULT2,The coefficient of variation for the 30 kOhm reference load resistance is stored."
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hexmask.long.byte 0x4 8.--15. 1. "TRESULT1,The coefficient of variation for the 15 kOhm reference load resistance is stored."
|
|
hexmask.long.byte 0x4 0.--7. 1. "TRESULT0,The coefficient of variation for the 7.5 kOhm reference load resistance is stored."
|
|
group.word 0x3FB0++0x1
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line.word 0x0 "FENTRYR,Flash P/E Mode Entry Register"
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|
hexmask.word.byte 0x0 8.--15. 1. "FEKEY,Key Code"
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bitfld.word 0x0 7. "FENTRYD,Data Flash P/E Mode Entry" "0: The data flash is the read mode,1: The data flash is the P/E mode."
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bitfld.word 0x0 0. "FENTRY0,Code Flash P/E Mode Entry 0" "0: The code flash is the read mode,1: The code flash is the P/E mode."
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group.byte 0x3FC4++0x0
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line.byte 0x0 "FLDWAITR,Memory Wait Cycle Control Register for Data Flash"
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bitfld.byte 0x0 0. "FLDWAIT1,Memory Wait Cycle Select for Data Flash" "0: 1 wait access (Default),1: 2 wait access"
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group.byte 0x3FC8++0x0
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line.byte 0x0 "PFBER,Prefetch Buffer Enable Register"
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bitfld.byte 0x0 0. "PFBE,Prefetch Buffer Enable bit" "0: Prefetch buffer is disabled,1: Prefetch buffer is enabled"
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tree.end
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tree "GPT (General Purpose Timer)"
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tree "GPT164"
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base ad:0x40078400
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group.long 0x0++0xB
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line.long 0x0 "GTWP,General PWM Timer Write-Protection Register"
|
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hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code"
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|
bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled"
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line.long 0x4 "GTSTR,General PWM Timer Software Start Register"
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bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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line.long 0x8 "GTSTP,General PWM Timer Software Stop Register"
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bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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wgroup.long 0xC++0x3
|
|
line.long 0x0 "GTCLR,General PWM Timer Software Clear Register"
|
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bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
|
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group.long 0x10++0x33
|
|
line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register"
|
|
bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input"
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newline
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bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input"
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bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input"
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bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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newline
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bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register"
|
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bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register"
|
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bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input"
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newline
|
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bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input"
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bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input"
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newline
|
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bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input"
|
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bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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newline
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bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
|
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bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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newline
|
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bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
|
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bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
|
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bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
|
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bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register"
|
|
bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input"
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newline
|
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bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input"
|
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bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input"
|
|
newline
|
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bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input"
|
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bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
|
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bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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|
newline
|
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bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
|
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bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
|
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bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
|
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bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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newline
|
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bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
|
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bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
|
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bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.."
|
|
bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
|
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bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
|
|
line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input"
|
|
bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input"
|
|
newline
|
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bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input"
|
|
bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input"
|
|
newline
|
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bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
|
|
bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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newline
|
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bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
|
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bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
|
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newline
|
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bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
|
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bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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newline
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bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
|
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bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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newline
|
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bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
|
|
bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
|
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newline
|
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bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
|
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bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
|
|
line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input"
|
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bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input"
|
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newline
|
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bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input"
|
|
bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input"
|
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newline
|
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bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
|
|
bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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newline
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bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A"
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bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input"
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bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input"
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bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input"
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bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input"
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bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
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bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input"
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bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input"
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bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input"
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bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input"
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bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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line.long 0x1C "GTCR,General PWM Timer Control Register"
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bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibited,1: PCLKD/4,?,?,?,?,?,?"
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bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?"
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bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed"
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line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
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bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.."
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bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?"
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bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.."
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bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?"
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bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up"
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line.long 0x24 "GTIOR,General PWM Timer I/O Control Register"
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bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled"
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bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.."
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bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops"
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hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select"
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bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled"
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bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.."
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bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops"
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hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select"
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line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
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bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled"
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bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.."
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bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request is selected,?,?"
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line.long 0x2C "GTST,General PWM Timer Status Register"
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rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.."
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rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.."
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rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated"
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rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward"
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bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred"
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bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred"
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bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated"
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bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated"
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bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated"
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bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated"
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bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.."
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bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.."
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line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register"
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bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1"
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bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?"
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bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?"
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bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?"
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bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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group.long 0x48++0x23
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line.long 0x0 "GTCNT,General PWM Timer Counter"
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line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A"
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line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B"
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line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C"
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line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E"
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line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D"
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line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F"
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line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register"
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line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
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group.long 0x88++0x7
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line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register"
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bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.."
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line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U"
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tree.end
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tree "GPT165"
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base ad:0x40078500
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group.long 0x0++0xB
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line.long 0x0 "GTWP,General PWM Timer Write-Protection Register"
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hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code"
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bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled"
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line.long 0x4 "GTSTR,General PWM Timer Software Start Register"
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bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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line.long 0x8 "GTSTP,General PWM Timer Software Stop Register"
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bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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wgroup.long 0xC++0x3
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line.long 0x0 "GTCLR,General PWM Timer Software Clear Register"
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bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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group.long 0x10++0x33
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line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register"
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bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register"
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bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input"
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bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input"
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bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input"
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bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input"
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bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register"
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bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register"
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bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input"
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bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input"
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bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input"
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bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input"
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bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register"
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bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register"
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bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input"
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bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input"
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bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input"
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bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input"
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bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.."
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bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register"
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bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input"
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bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input"
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bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input"
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bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input"
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bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
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bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input"
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bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input"
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bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input"
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bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input"
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bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A"
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bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input"
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bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input"
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bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input"
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bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input"
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bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
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bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input"
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bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input"
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bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input"
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bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input"
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bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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newline
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bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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line.long 0x1C "GTCR,General PWM Timer Control Register"
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bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibited,1: PCLKD/4,?,?,?,?,?,?"
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bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?"
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newline
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bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed"
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line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
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bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.."
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bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?"
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bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.."
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newline
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bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?"
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newline
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bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up"
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line.long 0x24 "GTIOR,General PWM Timer I/O Control Register"
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bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled"
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newline
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bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.."
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bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops"
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newline
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hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select"
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bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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newline
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bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled"
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bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?"
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newline
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bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.."
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newline
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bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops"
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hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select"
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line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
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bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled"
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bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.."
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newline
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bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request is selected,?,?"
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line.long 0x2C "GTST,General PWM Timer Status Register"
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rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.."
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rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.."
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newline
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rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated"
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rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward"
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newline
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bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred"
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bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred"
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newline
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bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated"
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bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated"
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newline
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bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated"
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bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated"
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newline
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bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.."
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bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.."
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line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register"
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bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1"
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bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?"
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newline
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bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?"
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bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?"
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newline
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bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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group.long 0x48++0x23
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line.long 0x0 "GTCNT,General PWM Timer Counter"
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line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A"
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line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B"
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line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C"
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line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E"
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line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D"
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line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F"
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line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register"
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line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
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group.long 0x88++0x7
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line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register"
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bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.."
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line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U"
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tree.end
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tree "GPT166"
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base ad:0x40078600
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group.long 0x0++0xB
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line.long 0x0 "GTWP,General PWM Timer Write-Protection Register"
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hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code"
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bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled"
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line.long 0x4 "GTSTR,General PWM Timer Software Start Register"
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bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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line.long 0x8 "GTSTP,General PWM Timer Software Stop Register"
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bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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wgroup.long 0xC++0x3
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line.long 0x0 "GTCLR,General PWM Timer Software Clear Register"
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bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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group.long 0x10++0x33
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line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register"
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bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register"
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bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input"
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newline
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bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input"
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bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input"
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bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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newline
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bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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newline
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bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register"
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bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register"
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bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input"
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newline
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bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input"
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bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input"
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bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register"
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bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register"
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bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input"
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bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input"
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bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input"
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bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input"
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bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.."
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bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register"
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bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input"
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bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input"
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bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input"
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bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input"
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bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
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bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input"
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bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input"
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bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input"
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bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input"
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bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A"
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bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input"
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bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input"
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bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input"
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bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input"
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bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
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bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input"
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bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input"
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bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input"
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bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input"
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bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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line.long 0x1C "GTCR,General PWM Timer Control Register"
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bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibited,1: PCLKD/4,?,?,?,?,?,?"
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bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?"
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bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed"
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line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
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bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.."
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bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?"
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bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.."
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bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?"
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bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up"
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line.long 0x24 "GTIOR,General PWM Timer I/O Control Register"
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bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled"
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bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.."
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bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops"
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hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select"
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bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled"
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bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.."
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bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops"
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hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select"
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line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
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bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled"
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bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.."
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bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request is selected,?,?"
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line.long 0x2C "GTST,General PWM Timer Status Register"
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rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.."
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rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.."
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rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated"
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rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward"
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bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred"
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bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred"
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bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated"
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bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated"
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bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated"
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bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated"
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bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.."
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bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.."
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line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register"
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bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1"
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bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?"
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bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?"
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bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?"
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bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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group.long 0x48++0x23
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line.long 0x0 "GTCNT,General PWM Timer Counter"
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line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A"
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line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B"
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line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C"
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line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E"
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line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D"
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line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F"
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line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register"
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line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
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group.long 0x88++0x7
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line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register"
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bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.."
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line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U"
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tree.end
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tree "GPT167"
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base ad:0x40078700
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group.long 0x0++0xB
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line.long 0x0 "GTWP,General PWM Timer Write-Protection Register"
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hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code"
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bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled"
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line.long 0x4 "GTSTR,General PWM Timer Software Start Register"
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bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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line.long 0x8 "GTSTP,General PWM Timer Software Stop Register"
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bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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wgroup.long 0xC++0x3
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line.long 0x0 "GTCLR,General PWM Timer Software Clear Register"
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bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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group.long 0x10++0x33
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line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register"
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bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register"
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bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input"
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bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input"
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bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input"
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bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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newline
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bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register"
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bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register"
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bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input"
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bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input"
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bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input"
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bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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newline
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bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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newline
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bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register"
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bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register"
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bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input"
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newline
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bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input"
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bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input"
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bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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newline
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bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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newline
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bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.."
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bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register"
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bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input"
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bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input"
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bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input"
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bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input"
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bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
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bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input"
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bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input"
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bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input"
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bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input"
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bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A"
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bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input"
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bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input"
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bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input"
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bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input"
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bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
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bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input"
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bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input"
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bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input"
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bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input"
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bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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line.long 0x1C "GTCR,General PWM Timer Control Register"
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bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibited,1: PCLKD/4,?,?,?,?,?,?"
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bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?"
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bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed"
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line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
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bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.."
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bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?"
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bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.."
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bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?"
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bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up"
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line.long 0x24 "GTIOR,General PWM Timer I/O Control Register"
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bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled"
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bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.."
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bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops"
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hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select"
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bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled"
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bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.."
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bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops"
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hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select"
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line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
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bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled"
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bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.."
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bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request is selected,?,?"
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line.long 0x2C "GTST,General PWM Timer Status Register"
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rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.."
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rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.."
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rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated"
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rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward"
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bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred"
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bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred"
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bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated"
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bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated"
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bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated"
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bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated"
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bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.."
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bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.."
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line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register"
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bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1"
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bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?"
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bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?"
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bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?"
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bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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group.long 0x48++0x23
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line.long 0x0 "GTCNT,General PWM Timer Counter"
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line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A"
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line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B"
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line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C"
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line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E"
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line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D"
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line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F"
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line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register"
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line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
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group.long 0x88++0x7
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line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register"
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bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.."
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line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U"
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tree.end
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tree "GPT168"
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base ad:0x40078800
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group.long 0x0++0xB
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line.long 0x0 "GTWP,General PWM Timer Write-Protection Register"
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hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code"
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bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled"
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line.long 0x4 "GTSTR,General PWM Timer Software Start Register"
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bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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line.long 0x8 "GTSTP,General PWM Timer Software Stop Register"
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bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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wgroup.long 0xC++0x3
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line.long 0x0 "GTCLR,General PWM Timer Software Clear Register"
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bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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group.long 0x10++0x33
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line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register"
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bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register"
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bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input"
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newline
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bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input"
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bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input"
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bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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newline
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bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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newline
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bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register"
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bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register"
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bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input"
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newline
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bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input"
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bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input"
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bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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newline
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bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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newline
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bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register"
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bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register"
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bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input"
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newline
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bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input"
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bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input"
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bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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newline
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bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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newline
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bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.."
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bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register"
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bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input"
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bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input"
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newline
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bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input"
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bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input"
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newline
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bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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newline
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bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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newline
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bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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newline
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bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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newline
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bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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newline
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bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
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bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input"
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bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input"
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newline
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bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input"
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bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input"
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newline
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bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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newline
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bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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newline
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bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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newline
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bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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newline
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bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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newline
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bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A"
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bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input"
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bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input"
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bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input"
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bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input"
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bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
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bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input"
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bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input"
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bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input"
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bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input"
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bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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line.long 0x1C "GTCR,General PWM Timer Control Register"
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bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibited,1: PCLKD/4,?,?,?,?,?,?"
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bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?"
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bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed"
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line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
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bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.."
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bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?"
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bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.."
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bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?"
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newline
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bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up"
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line.long 0x24 "GTIOR,General PWM Timer I/O Control Register"
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bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled"
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bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.."
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bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops"
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hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select"
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bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled"
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bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?"
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newline
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bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.."
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bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops"
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hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select"
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line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
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bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled"
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bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.."
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newline
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bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request is selected,?,?"
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line.long 0x2C "GTST,General PWM Timer Status Register"
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rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.."
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rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.."
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rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated"
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rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward"
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newline
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bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred"
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bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred"
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bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated"
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bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated"
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bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated"
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bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated"
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newline
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bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.."
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bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.."
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line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register"
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bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1"
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bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?"
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newline
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bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?"
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bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?"
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newline
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bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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group.long 0x48++0x23
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line.long 0x0 "GTCNT,General PWM Timer Counter"
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line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A"
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line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B"
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line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C"
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line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E"
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line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D"
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line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F"
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line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register"
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line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
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group.long 0x88++0x7
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line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register"
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bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.."
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line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U"
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tree.end
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tree "GPT169"
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base ad:0x40078900
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group.long 0x0++0xB
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line.long 0x0 "GTWP,General PWM Timer Write-Protection Register"
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hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code"
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bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled"
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line.long 0x4 "GTSTR,General PWM Timer Software Start Register"
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bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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line.long 0x8 "GTSTP,General PWM Timer Software Stop Register"
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bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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wgroup.long 0xC++0x3
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line.long 0x0 "GTCLR,General PWM Timer Software Clear Register"
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bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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group.long 0x10++0x33
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line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register"
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bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register"
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bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input"
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bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input"
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bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input"
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bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input"
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bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register"
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bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register"
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bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input"
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bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input"
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bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input"
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bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input"
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bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register"
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bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register"
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bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input"
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bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input"
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bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input"
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bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input"
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bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.."
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bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register"
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bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input"
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bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input"
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bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input"
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bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input"
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bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
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bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input"
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bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input"
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bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input"
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bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input"
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bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A"
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bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input"
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bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input"
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bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input"
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bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input"
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bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
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bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input"
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bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input"
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bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input"
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bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input"
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bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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line.long 0x1C "GTCR,General PWM Timer Control Register"
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bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibited,1: PCLKD/4,?,?,?,?,?,?"
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bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?"
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bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed"
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line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
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bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.."
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bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?"
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bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.."
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bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?"
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newline
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bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up"
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line.long 0x24 "GTIOR,General PWM Timer I/O Control Register"
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bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled"
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bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.."
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bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops"
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hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select"
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bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled"
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bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?"
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newline
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bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.."
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bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops"
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hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select"
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line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
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bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled"
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bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.."
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bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request is selected,?,?"
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line.long 0x2C "GTST,General PWM Timer Status Register"
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rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.."
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rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.."
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rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated"
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rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward"
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bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred"
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bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred"
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bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated"
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bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated"
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bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated"
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bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated"
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bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.."
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bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.."
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line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register"
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bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1"
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bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?"
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newline
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bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?"
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bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?"
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newline
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bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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group.long 0x48++0x23
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line.long 0x0 "GTCNT,General PWM Timer Counter"
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line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A"
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line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B"
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line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C"
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line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E"
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line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D"
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line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F"
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line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register"
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line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
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group.long 0x88++0x7
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line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register"
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bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.."
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line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U"
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tree.end
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tree "GPT320"
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base ad:0x40078000
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group.long 0x0++0xB
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line.long 0x0 "GTWP,General PWM Timer Write-Protection Register"
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hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code"
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bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled"
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line.long 0x4 "GTSTR,General PWM Timer Software Start Register"
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bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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line.long 0x8 "GTSTP,General PWM Timer Software Stop Register"
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bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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wgroup.long 0xC++0x3
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line.long 0x0 "GTCLR,General PWM Timer Software Clear Register"
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bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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group.long 0x10++0x33
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line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register"
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bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register"
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bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input"
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bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input"
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bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input"
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bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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newline
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bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register"
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bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register"
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bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input"
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bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input"
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bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input"
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bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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newline
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bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register"
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bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register"
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bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input"
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bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input"
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bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input"
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bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input"
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bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.."
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bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register"
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bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input"
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bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input"
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bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input"
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bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input"
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bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
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bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input"
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bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input"
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bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input"
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bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input"
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bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A"
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bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input"
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bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input"
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bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input"
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bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input"
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bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
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bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input"
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bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input"
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bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input"
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bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input"
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bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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line.long 0x1C "GTCR,General PWM Timer Control Register"
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bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibited,1: PCLKD/4,?,?,?,?,?,?"
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bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?"
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bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed"
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line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
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bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.."
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bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?"
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bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.."
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bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?"
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bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up"
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line.long 0x24 "GTIOR,General PWM Timer I/O Control Register"
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bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled"
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bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.."
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bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops"
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hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select"
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bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled"
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bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.."
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bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops"
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hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select"
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line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
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bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled"
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bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.."
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bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request is selected,?,?"
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line.long 0x2C "GTST,General PWM Timer Status Register"
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rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.."
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rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.."
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rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated"
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rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward"
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bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred"
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bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred"
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bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated"
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bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated"
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bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated"
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bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated"
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bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.."
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bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.."
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line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register"
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bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1"
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bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?"
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bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?"
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bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?"
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bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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group.long 0x48++0x23
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line.long 0x0 "GTCNT,General PWM Timer Counter"
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line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A"
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line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B"
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line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C"
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line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E"
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line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D"
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line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F"
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line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register"
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line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
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group.long 0x88++0x7
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line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register"
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bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.."
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line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U"
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tree.end
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tree "GPT321"
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base ad:0x40078100
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group.long 0x0++0xB
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line.long 0x0 "GTWP,General PWM Timer Write-Protection Register"
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hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code"
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bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled"
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line.long 0x4 "GTSTR,General PWM Timer Software Start Register"
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bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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line.long 0x8 "GTSTP,General PWM Timer Software Stop Register"
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bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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wgroup.long 0xC++0x3
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line.long 0x0 "GTCLR,General PWM Timer Software Clear Register"
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bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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group.long 0x10++0x33
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line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register"
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bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register"
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bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input"
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bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input"
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bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input"
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bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input"
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bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register"
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bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register"
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bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input"
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bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input"
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bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input"
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bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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newline
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bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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newline
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bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register"
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bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register"
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bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input"
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newline
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bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input"
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bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input"
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bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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newline
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bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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newline
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bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.."
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bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register"
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bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input"
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bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input"
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newline
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bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input"
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bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input"
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newline
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bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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newline
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bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
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bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input"
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bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input"
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bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input"
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bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input"
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bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A"
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bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input"
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bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input"
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bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input"
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bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input"
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bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
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bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input"
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bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input"
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bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input"
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bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input"
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bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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line.long 0x1C "GTCR,General PWM Timer Control Register"
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bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibited,1: PCLKD/4,?,?,?,?,?,?"
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bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?"
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bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed"
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line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
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bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.."
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bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?"
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bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.."
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bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?"
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bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up"
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line.long 0x24 "GTIOR,General PWM Timer I/O Control Register"
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bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled"
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bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.."
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bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops"
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hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select"
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bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled"
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bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.."
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bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops"
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hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select"
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line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
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bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled"
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bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.."
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bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request is selected,?,?"
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line.long 0x2C "GTST,General PWM Timer Status Register"
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rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.."
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rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.."
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rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated"
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rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward"
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bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred"
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bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred"
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bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated"
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bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated"
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bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated"
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bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated"
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bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.."
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bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.."
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line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register"
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bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1"
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bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?"
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bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?"
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bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?"
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bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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group.long 0x48++0x23
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line.long 0x0 "GTCNT,General PWM Timer Counter"
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line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A"
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line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B"
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line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C"
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line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E"
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line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D"
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line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F"
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line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register"
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line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
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group.long 0x88++0x7
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line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register"
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bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.."
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line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U"
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tree.end
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tree "GPT322"
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base ad:0x40078200
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group.long 0x0++0xB
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line.long 0x0 "GTWP,General PWM Timer Write-Protection Register"
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hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code"
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bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled"
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line.long 0x4 "GTSTR,General PWM Timer Software Start Register"
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bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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line.long 0x8 "GTSTP,General PWM Timer Software Stop Register"
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bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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wgroup.long 0xC++0x3
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line.long 0x0 "GTCLR,General PWM Timer Software Clear Register"
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bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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group.long 0x10++0x33
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line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register"
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bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register"
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bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input"
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bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input"
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bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input"
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bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input"
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bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register"
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bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register"
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bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input"
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bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input"
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bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input"
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bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input"
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bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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newline
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bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register"
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bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register"
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bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input"
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newline
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bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input"
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bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input"
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bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.."
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bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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newline
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bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register"
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bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input"
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bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input"
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bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input"
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bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input"
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bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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newline
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bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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newline
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bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
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bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input"
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bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input"
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newline
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bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input"
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bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input"
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newline
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bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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newline
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bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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newline
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bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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newline
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bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A"
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bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input"
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bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input"
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bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input"
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bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input"
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bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
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bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input"
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bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input"
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bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input"
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bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input"
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bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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line.long 0x1C "GTCR,General PWM Timer Control Register"
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bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibited,1: PCLKD/4,?,?,?,?,?,?"
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bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?"
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newline
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bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed"
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line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
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bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.."
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bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?"
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bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.."
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bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?"
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newline
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bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set"
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bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up"
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line.long 0x24 "GTIOR,General PWM Timer I/O Control Register"
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bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled"
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bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?"
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bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.."
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bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops"
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hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select"
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bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
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newline
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bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled"
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bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?"
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newline
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bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.."
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bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops"
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hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select"
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line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
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bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled"
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bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.."
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newline
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bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request is selected,?,?"
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line.long 0x2C "GTST,General PWM Timer Status Register"
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rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.."
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rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.."
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newline
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rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated"
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rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward"
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newline
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bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred"
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bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred"
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newline
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bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated"
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bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated"
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newline
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bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated"
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bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated"
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newline
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bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.."
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bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.."
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line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register"
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bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1"
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bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?"
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newline
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bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?"
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bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?"
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newline
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bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
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group.long 0x48++0x23
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line.long 0x0 "GTCNT,General PWM Timer Counter"
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line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A"
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line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B"
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line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C"
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line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E"
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line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D"
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line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F"
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line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register"
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line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
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group.long 0x88++0x7
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line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register"
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bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.."
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line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U"
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tree.end
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tree "GPT323"
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base ad:0x40078300
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group.long 0x0++0xB
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line.long 0x0 "GTWP,General PWM Timer Write-Protection Register"
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hexmask.long.byte 0x0 8.--15. 1. "PRKEY,GTWP Key Code"
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bitfld.long 0x0 0. "WP,Register Write Disable" "0: Write to the register enabled,1: Write to the register disabled"
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line.long 0x4 "GTSTR,General PWM Timer Software Start Register"
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bitfld.long 0x4 9. "CSTRT9,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 8. "CSTRT8,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 7. "CSTRT7,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 6. "CSTRT6,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 5. "CSTRT5,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 4. "CSTRT4,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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newline
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bitfld.long 0x4 3. "CSTRT3,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 2. "CSTRT2,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 1. "CSTRT1,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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bitfld.long 0x4 0. "CSTRT0,Channel n GTCNT Count Start (n : the same as bit position value)" "0: GTCNT counter not start,1: GTCNT counter start"
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line.long 0x8 "GTSTP,General PWM Timer Software Stop Register"
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bitfld.long 0x8 9. "CSTOP9,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 8. "CSTOP8,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 7. "CSTOP7,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 6. "CSTOP6,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 5. "CSTOP5,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 4. "CSTOP4,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 3. "CSTOP3,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 2. "CSTOP2,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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newline
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bitfld.long 0x8 1. "CSTOP1,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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bitfld.long 0x8 0. "CSTOP0,Channel n GTCNT Count Stop (n : the same as bit position value)" "0: GTCNT counter not stop,1: GTCNT counter stop"
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wgroup.long 0xC++0x3
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line.long 0x0 "GTCLR,General PWM Timer Software Clear Register"
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bitfld.long 0x0 9. "CCLR9,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 8. "CCLR8,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 7. "CCLR7,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 6. "CCLR6,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 5. "CCLR5,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 4. "CCLR4,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 3. "CCLR3,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 2. "CCLR2,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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newline
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bitfld.long 0x0 1. "CCLR1,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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bitfld.long 0x0 0. "CCLR0,Channel n GTCNT Count Clear (n : the same as bit position value)" "0: GTCNT counter is not cleared,1: GTCNT counter is cleared"
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group.long 0x10++0x33
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line.long 0x0 "GTSSR,General PWM Timer Start Source Select Register"
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bitfld.long 0x0 31. "CSTRT,Software Source Counter Start Enable" "0: Counter start disabled by the GTSTR register,1: Counter start enabled by the GTSTR register"
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bitfld.long 0x0 19. "SSELCD,ELC_GPTD Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTD input,1: Counter start enabled at the ELC_GPTD input"
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newline
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bitfld.long 0x0 18. "SSELCC,ELC_GPTC Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTC input,1: Counter start enabled at the ELC_GPTC input"
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bitfld.long 0x0 17. "SSELCB,ELC_GPTB Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTB input,1: Counter start enabled at the ELC_GPTB input"
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newline
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bitfld.long 0x0 16. "SSELCA,ELC_GPTA Event Source Counter Start Enable" "0: Counter start disabled at the ELC_GPTA input,1: Counter start enabled at the ELC_GPTA input"
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bitfld.long 0x0 15. "SSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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newline
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bitfld.long 0x0 14. "SSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 13. "SSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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newline
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bitfld.long 0x0 12. "SSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 11. "SSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 10. "SSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 9. "SSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 8. "SSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 3. "SSGTRGBF,GTETRGB Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 2. "SSGTRGBR,GTETRGB Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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bitfld.long 0x0 1. "SSGTRGAF,GTETRGA Pin Falling Input Source Counter Start Enable" "0: Counter start disabled on the falling edge of..,1: Counter start enabled on the falling edge of.."
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bitfld.long 0x0 0. "SSGTRGAR,GTETRGA Pin Rising Input Source Counter Start Enable" "0: Counter start disabled on the rising edge of..,1: Counter start enabled on the rising edge of.."
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line.long 0x4 "GTPSR,General PWM Timer Stop Source Select Register"
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bitfld.long 0x4 31. "CSTOP,Software Source Counter Stop Enable" "0: Counter stop disabled by the GTSTP register,1: Counter stop enabled by the GTSTP register"
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bitfld.long 0x4 19. "PSELCD,ELC_GPTD Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTD input,1: Counter stop enabled at the ELC_GPTD input"
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bitfld.long 0x4 18. "PSELCC,ELC_GPTC Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTC input,1: Counter stop enabled at the ELC_GPTC input"
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bitfld.long 0x4 17. "PSELCB,ELC_GPTB Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTB input,1: Counter stop enabled at the ELC_GPTB input"
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bitfld.long 0x4 16. "PSELCA,ELC_GPTA Event Source Counter Stop Enable" "0: Counter stop disabled at the ELC_GPTA input,1: Counter stop enabled at the ELC_GPTA input"
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bitfld.long 0x4 15. "PSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 14. "PSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 13. "PSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 12. "PSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 11. "PSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 10. "PSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 9. "PSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 8. "PSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 3. "PSGTRGBF,GTETRGB Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 2. "PSGTRGBR,GTETRGB Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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bitfld.long 0x4 1. "PSGTRGAF,GTETRGA Pin Falling Input Source Counter Stop Enable" "0: Counter stop disabled on the falling edge of..,1: Counter stop enabled on the falling edge of.."
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bitfld.long 0x4 0. "PSGTRGAR,GTETRGA Pin Rising Input Source Counter Stop Enable" "0: Counter stop disabled on the rising edge of..,1: Counter stop enabled on the rising edge of.."
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line.long 0x8 "GTCSR,General PWM Timer Clear Source Select Register"
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bitfld.long 0x8 31. "CCLR,Software Source Counter Clear Enable" "0: Counter clear disabled by the GTCLR register,1: Counter clear enabled by the GTCLR register"
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bitfld.long 0x8 19. "CSELCD,ELC_GPTD Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTD input,1: Counter clear enabled at the ELC_GPTD input"
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bitfld.long 0x8 18. "CSELCC,ELC_GPTC Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTC input,1: Counter clear enabled at the ELC_GPTC input"
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bitfld.long 0x8 17. "CSELCB,ELC_GPTB Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTB input,1: Counter clear enabled at the ELC_GPTB input"
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bitfld.long 0x8 16. "CSELCA,ELC_GPTA Event Source Counter Clear Enable" "0: Counter clear disabled at the ELC_GPTA input,1: Counter clear enabled at the ELC_GPTA input"
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bitfld.long 0x8 15. "CSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 14. "CSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 13. "CSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 12. "CSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 11. "CSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 10. "CSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 9. "CSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 8. "CSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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bitfld.long 0x8 3. "CSGTRGBF,GTETRGB Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 2. "CSGTRGBR,GTETRGB Pin Rising Input Source Counter Clear Enable" "0: Disable counter clear on the rising edge of..,1: Enable counter clear on the rising edge of.."
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bitfld.long 0x8 1. "CSGTRGAF,GTETRGA Pin Falling Input Source Counter Clear Enable" "0: Counter clear disabled on the falling edge of..,1: Counter clear enabled on the falling edge of.."
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bitfld.long 0x8 0. "CSGTRGAR,GTETRGA Pin Rising Input Source Counter Clear Enable" "0: Counter clear disabled on the rising edge of..,1: Counter clear enabled on the rising edge of.."
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line.long 0xC "GTUPSR,General PWM Timer Up Count Source Select Register"
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bitfld.long 0xC 19. "USELCD,ELC_GPTD Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTD input,1: Counter count up enabled at the ELC_GPTD input"
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bitfld.long 0xC 18. "USELCC,ELC_GPTC Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTC input,1: Counter count up enabled at the ELC_GPTC input"
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bitfld.long 0xC 17. "USELCB,ELC_GPTB Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTB input,1: Counter count up enabled at the ELC_GPTB input"
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bitfld.long 0xC 16. "USELCA,ELC_GPTA Event Source Counter Count Up Enable" "0: Counter count up disabled at the ELC_GPTA input,1: Counter count up enabled at the ELC_GPTA input"
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bitfld.long 0xC 15. "USCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 14. "USCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 13. "USCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 12. "USCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 11. "USCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 10. "USCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 9. "USCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 8. "USCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 3. "USGTRGBF,GTETRGB Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 2. "USGTRGBR,GTETRGB Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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bitfld.long 0xC 1. "USGTRGAF,GTETRGA Pin Falling Input Source Counter Count Up Enable" "0: Counter count up disabled on the falling edge of..,1: Counter count up enabled on the falling edge of.."
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bitfld.long 0xC 0. "USGTRGAR,GTETRGA Pin Rising Input Source Counter Count Up Enable" "0: Counter count up disabled on the rising edge of..,1: Counter count up enabled on the rising edge of.."
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line.long 0x10 "GTDNSR,General PWM Timer Down Count Source Select Register"
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bitfld.long 0x10 19. "DSELCD,ELC_GPTD Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTD input,1: Counter count down enabled at the ELC_GPTD input"
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bitfld.long 0x10 18. "DSELCC,ELC_GPTC Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTC input,1: Counter count down enabled at the ELC_GPTC input"
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bitfld.long 0x10 17. "DSELCB,ELC_GPTB Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTB input,1: Counter count down enabled at the ELC_GPTB input"
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bitfld.long 0x10 16. "DSELCA,ELC_GPTA Event Source Counter Count Down Enable" "0: Counter count down disabled at the ELC_GPTA input,1: Counter count down enabled at the ELC_GPTA input"
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bitfld.long 0x10 15. "DSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 14. "DSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 13. "DSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 12. "DSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 11. "DSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 10. "DSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 9. "DSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 8. "DSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 3. "DSGTRGBF,GTETRGB Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 2. "DSGTRGBR,GTETRGB Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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bitfld.long 0x10 1. "DSGTRGAF,GTETRGA Pin Falling Input Source Counter Count Down Enable" "0: Counter count down disabled on the falling edge..,1: Counter count down enabled on the falling edge.."
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bitfld.long 0x10 0. "DSGTRGAR,GTETRGA Pin Rising Input Source Counter Count Down Enable" "0: Counter count down disabled on the rising edge..,1: Counter count down enabled on the rising edge of.."
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line.long 0x14 "GTICASR,General PWM Timer Input Capture Source Select Register A"
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bitfld.long 0x14 19. "ASELCD,ELC_GPTD Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTD..,1: GTCCRA input capture enabled at the ELC_GPTD input"
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bitfld.long 0x14 18. "ASELCC,ELC_GPTC Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTC..,1: GTCCRA input capture enabled at the ELC_GPTC input"
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bitfld.long 0x14 17. "ASELCB,ELC_GPTB Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTB..,1: GTCCRA input capture enabled at the ELC_GPTB input"
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bitfld.long 0x14 16. "ASELCA,ELC_GPTA Event Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled at the ELC_GPTA..,1: GTCCRA input capture enabled at the ELC_GPTA input"
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bitfld.long 0x14 15. "ASCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 14. "ASCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 13. "ASCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 12. "ASCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 11. "ASCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 10. "ASCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 9. "ASCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 8. "ASCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 3. "ASGTRGBF,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 2. "ASGTRGBR,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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bitfld.long 0x14 1. "ASGTRGAF,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the falling..,1: GTCCRA input capture enabled on the falling edge.."
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bitfld.long 0x14 0. "ASGTRGAR,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "0: GTCCRA input capture disabled on the rising edge..,1: GTCCRA input capture enabled on the rising edge.."
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line.long 0x18 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
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bitfld.long 0x18 19. "BSELCD,ELC_GPTD Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTD..,1: GTCCRB input capture enabled at the ELC_GPTD input"
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bitfld.long 0x18 18. "BSELCC,ELC_GPTC Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTC..,1: GTCCRB input capture enabled at the ELC_GPTC input"
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bitfld.long 0x18 17. "BSELCB,ELC_GPTB Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTB..,1: GTCCRB input capture enabled at the ELC_GPTB input"
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bitfld.long 0x18 16. "BSELCA,ELC_GPTA Event Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled at the ELC_GPTA..,1: GTCCRB input capture enabled at the ELC_GPTA input"
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bitfld.long 0x18 15. "BSCBFAH,GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 14. "BSCBFAL,GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 13. "BSCBRAH,GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 12. "BSCBRAL,GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 11. "BSCAFBH,GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 10. "BSCAFBL,GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 9. "BSCARBH,GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 8. "BSCARBL,GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 3. "BSGTRGBF,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 2. "BSGTRGBR,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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bitfld.long 0x18 1. "BSGTRGAF,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the falling..,1: GTCCRB input capture enabled on the falling edge.."
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bitfld.long 0x18 0. "BSGTRGAR,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "0: GTCCRB input capture disabled on the rising edge..,1: GTCCRB input capture enabled on the rising edge.."
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line.long 0x1C "GTCR,General PWM Timer Control Register"
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bitfld.long 0x1C 24.--26. "TPCS,Timer Prescaler Select" "0: Setting prohibited,1: PCLKD/4,?,?,?,?,?,?"
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bitfld.long 0x1C 16.--18. "MD,Mode Select" "0: Saw-wave PWM mode (single buffer or double..,1: Saw-wave one-shot pulse mode (fixed buffer..,?,?,?,?,?,?"
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bitfld.long 0x1C 0. "CST,Count Start" "0: Count operation is stopped,1: Count operation is performed"
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line.long 0x20 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x20 27. "OBDTYR,GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOB[3:2] bits is..,1: The function selected by the GTIOB[3:2] bits is.."
|
|
bitfld.long 0x20 26. "OBDTYF,Forcible GTIOCnB Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
|
|
newline
|
|
bitfld.long 0x20 24.--25. "OBDTY,GTIOCnB Output Duty Setting" "0: GTIOCnB pin duty depends on the compare match,1: GTIOCnB pin duty depends on the compare match,?,?"
|
|
bitfld.long 0x20 19. "OADTYR,GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting" "0: The function selected by the GTIOA[3:2] bits is..,1: The function selected by the GTIOA[3:2] bits is.."
|
|
newline
|
|
bitfld.long 0x20 18. "OADTYF,Forcible GTIOCnA Output Duty Setting" "0: Not forcibly set,1: Forcibly set"
|
|
bitfld.long 0x20 16.--17. "OADTY,GTIOCnA Output Duty Setting" "0: GTIOCnA pin duty depends on the compare match,1: GTIOCnA pin duty depends on the compare match,?,?"
|
|
newline
|
|
bitfld.long 0x20 1. "UDF,Forcible Count Direction Setting" "0: Not forcibly set,1: Forcibly set"
|
|
bitfld.long 0x20 0. "UD,Count Direction Setting" "0: GTCNT counts down,1: GTCNT counts up"
|
|
line.long 0x24 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x24 30.--31. "NFCSB,Noise Filter B Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
|
|
bitfld.long 0x24 29. "NFBEN,Noise Filter B Enable" "0: The noise filter for the GTIOCnB pin is disabled,1: The noise filter for the GTIOCnB pin is enabled"
|
|
newline
|
|
bitfld.long 0x24 25.--26. "OBDF,GTIOCnB Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnB pin is set to Hi-Z in response to..,?,?"
|
|
bitfld.long 0x24 24. "OBE,GTIOCnB Pin Output Enable" "0: Output is disabled,1: Output is enabled"
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|
newline
|
|
bitfld.long 0x24 23. "OBHLD,GTIOCnB Pin Output Setting at the Start/Stop Count" "0: The GTIOCnB pin output level at the start/stop..,1: The GTIOCnB pin output level is retained at the.."
|
|
bitfld.long 0x24 22. "OBDFLT,GTIOCnB Pin Output Value Setting at the Count Stop" "0: The GTIOCnB pin outputs low when counting stops,1: The GTIOCnB pin outputs high when counting stops"
|
|
newline
|
|
hexmask.long.byte 0x24 16.--20. 1. "GTIOB,GTIOCnB Pin Function Select"
|
|
bitfld.long 0x24 14.--15. "NFCSA,Noise Filter A Sampling Clock Select" "0: PCLKD/1,1: PCLKD/4,?,?"
|
|
newline
|
|
bitfld.long 0x24 13. "NFAEN,Noise Filter A Enable" "0: The noise filter for the GTIOCnA pin is disabled,1: The noise filter for the GTIOCnA pin is enabled"
|
|
bitfld.long 0x24 9.--10. "OADF,GTIOCnA Pin Disable Value Setting" "0: None of the below options are specified,1: GTIOCnA pin is set to Hi-Z in response to..,?,?"
|
|
newline
|
|
bitfld.long 0x24 8. "OAE,GTIOCnA Pin Output Enable" "0: Output is disabled,1: Output is enabled"
|
|
bitfld.long 0x24 7. "OAHLD,GTIOCnA Pin Output Setting at the Start/Stop Count" "0: The GTIOCnA pin output level at the start or..,1: The GTIOCnA pin output level is retained at the.."
|
|
newline
|
|
bitfld.long 0x24 6. "OADFLT,GTIOCnA Pin Output Value Setting at the Count Stop" "0: The GTIOCnA pin outputs low when counting stops,1: The GTIOCnA pin outputs high when counting stops"
|
|
hexmask.long.byte 0x24 0.--4. 1. "GTIOA,GTIOCnA Pin Function Select"
|
|
line.long 0x28 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x28 30. "GRPABL,Same Time Output Level Low Disable Request Enable" "0: Same time output level low disable request..,1: Same time output level low disable request enabled"
|
|
bitfld.long 0x28 29. "GRPABH,Same Time Output Level High Disable Request Enable" "0: Same time output level high disable request..,1: Same time output level high disable request.."
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|
newline
|
|
bitfld.long 0x28 24.--25. "GRP,Output Disable Source Select" "0: Setting prohibited,1: Group B output disable request is selected,?,?"
|
|
line.long 0x2C "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x2C 30. "OABLF,Same Time Output Level Low Flag" "0: No simultaneous generation of 0 both for the..,1: A simultaneous generation of 0 both for the.."
|
|
rbitfld.long 0x2C 29. "OABHF,Same Time Output Level High Flag" "0: No simultaneous generation of 1 both for the..,1: A simultaneous generation of 1 both for the.."
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|
newline
|
|
rbitfld.long 0x2C 24. "ODF,Output Disable Flag" "0: No output disable request is generated,1: An output disable request is generated"
|
|
rbitfld.long 0x2C 15. "TUCF,Count Direction Flag" "0: GTCNT counter counts downward,1: GTCNT counter counts upward"
|
|
newline
|
|
bitfld.long 0x2C 7. "TCFPU,Underflow Flag" "0: No underflow (trough) occurred,1: An underflow (trough) occurred"
|
|
bitfld.long 0x2C 6. "TCFPO,Overflow Flag" "0: No overflow (crest) occurred,1: An overflow (crest) occurred"
|
|
newline
|
|
bitfld.long 0x2C 5. "TCFF,Input Compare Match Flag F" "0: No compare match of GTCCRF is generated,1: A compare match of GTCCRF is generated"
|
|
bitfld.long 0x2C 4. "TCFE,Input Compare Match Flag E" "0: No compare match of GTCCRE is generated,1: A compare match of GTCCRE is generated"
|
|
newline
|
|
bitfld.long 0x2C 3. "TCFD,Input Compare Match Flag D" "0: No compare match of GTCCRD is generated,1: A compare match of GTCCRD is generated"
|
|
bitfld.long 0x2C 2. "TCFC,Input Compare Match Flag C" "0: No compare match of GTCCRC is generated,1: A compare match of GTCCRC is generated"
|
|
newline
|
|
bitfld.long 0x2C 1. "TCFB,Input Capture/Compare Match Flag B" "0: No input capture/compare match of GTCCRB is..,1: An input capture/compare match of GTCCRB is.."
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|
bitfld.long 0x2C 0. "TCFA,Input Capture/Compare Match Flag A" "0: No input capture/compare match of GTCCRA is..,1: An input capture/compare match of GTCCRA is.."
|
|
line.long 0x30 "GTBER,General PWM Timer Buffer Enable Register"
|
|
bitfld.long 0x30 22. "CCRSWT,GTCCRA and GTCCRB Forcible Buffer Operation" "0,1"
|
|
bitfld.long 0x30 20.--21. "PR,GTPR Buffer Operation" "0: Setting prohibited,1: Single buffer operation (GTPBR --> GTPR),?,?"
|
|
newline
|
|
bitfld.long 0x30 18.--19. "CCRB,GTCCRB Buffer Operation" "0: Double buffer operation (GTCCRB <----> GTCCRE..,1: Single buffer operation (GTCCRB <----> GTCCRE),?,?"
|
|
bitfld.long 0x30 16.--17. "CCRA,GTCCRA Buffer Operation" "0: Double buffer operation (GTCCRA <----> GTCCRC..,1: Single buffer operation (GTCCRA <---->GTCCRC),?,?"
|
|
newline
|
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bitfld.long 0x30 1. "BD1,GTPR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
|
|
bitfld.long 0x30 0. "BD0,GTCCR Buffer Operation Disable" "0: Buffer operation is enabled,1: Buffer operation is disabled"
|
|
group.long 0x48++0x23
|
|
line.long 0x0 "GTCNT,General PWM Timer Counter"
|
|
line.long 0x4 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
line.long 0x8 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
line.long 0xC "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
line.long 0x10 "GTCCRE,General PWM Timer Compare Capture Register E"
|
|
line.long 0x14 "GTCCRD,General PWM Timer Compare Capture Register D"
|
|
line.long 0x18 "GTCCRF,General PWM Timer Compare Capture Register F"
|
|
line.long 0x1C "GTPR,General PWM Timer Cycle Setting Register"
|
|
line.long 0x20 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long 0x88++0x7
|
|
line.long 0x0 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x0 0. "TDE,Negative-Phase Waveform Setting" "0: GTCCRB is set without using GTDVU,1: GTDVU is used to set the compare match value for.."
|
|
line.long 0x4 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
tree.end
|
|
tree.end
|
|
tree "GPT_OPS (Output Phase Switching Controller)"
|
|
base ad:0x40078FF0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x0 30.--31. "NFCS,External Input Noise Filter Clock Selection" "0: PCLKD/1,1: PCLKD/4,?,?"
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|
bitfld.long 0x0 29. "NFEN,External Input Noise Filter Enable" "0: Do not use a noise filter on the external input,1: Use a noise filter on the external input"
|
|
newline
|
|
bitfld.long 0x0 26. "GODF,Group Output Disable Function" "0: This bit function is ignored,1: Group disable clears the OPSCR.EN bit"
|
|
bitfld.long 0x0 24.--25. "GRP,Output Disabled Source Selection" "0,1,2,3"
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|
newline
|
|
bitfld.long 0x0 21. "ALIGN,Input Phase Alignment" "0: Input phase aligned to PCLKD,1: Input phase aligned to the falling edge of PWM"
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|
bitfld.long 0x0 20. "RV,Output Phase Rotation Direction Reversal Control" "0: Positive rotation,1: Reverse rotation"
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|
newline
|
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bitfld.long 0x0 19. "INV,Output Phase Invert Control" "0: Positive logic (active-high) output,1: Negative logic (active-low) output"
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|
bitfld.long 0x0 18. "N,Negative-Phase Output (N) Control" "0: Level signal output,1: PWM signal output"
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|
newline
|
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bitfld.long 0x0 17. "P,Positive-Phase Output (P) Control" "0: Level signal output,1: PWM signal output"
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|
bitfld.long 0x0 16. "FB,External Feedback Signal Enable" "0: Select the external input,1: Select the soft setting (OPSCR.UF VF WF)"
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|
newline
|
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bitfld.long 0x0 8. "EN,Output Phase Enable" "0: Do not output (Hi-Z external pin),1: Output"
|
|
rbitfld.long 0x0 6. "W,Input W-Phase Monitor" "0,1"
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newline
|
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rbitfld.long 0x0 5. "V,Input V-Phase Monitor" "0,1"
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|
rbitfld.long 0x0 4. "U,Input U-Phase Monitor" "0,1"
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|
newline
|
|
bitfld.long 0x0 2. "WF," "0,1"
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|
bitfld.long 0x0 1. "VF," "0,1"
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|
newline
|
|
bitfld.long 0x0 0. "UF," "0,1"
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|
tree.end
|
|
tree "ICU (ICU for CPU)"
|
|
base ad:0x40006000
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x1)
|
|
group.byte ($2)++0x0
|
|
line.byte 0x0 "IRQCR$1,IRQ Control Register %s"
|
|
bitfld.byte 0x0 7. "FLTEN,IRQi Digital Filter Enable" "0: Digital filter is disabled,1: Digital filter is enabled."
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bitfld.byte 0x0 4.--5. "FCLKSEL,IRQi Digital Filter Sampling Clock Select" "0: PCLKB,1: PCLKB/8,?,?"
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|
newline
|
|
bitfld.byte 0x0 0.--1. "IRQMD,IRQi Detection Sense Select" "0: Falling edge,1: Rising edge,?,?"
|
|
repeat.end
|
|
group.byte 0x100++0x0
|
|
line.byte 0x0 "NMICR,NMI Pin Interrupt Control Register"
|
|
bitfld.byte 0x0 7. "NFLTEN,NMI Digital Filter Enable" "0: Disabled.,1: Enabled."
|
|
bitfld.byte 0x0 4.--5. "NFCLKSEL,NMI Digital Filter Sampling Clock Select" "0: PCLKB,1: PCLKB/8,?,?"
|
|
newline
|
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bitfld.byte 0x0 0. "NMIMD,NMI Detection Set" "0: Falling edge,1: Rising edge"
|
|
group.word 0x120++0x1
|
|
line.word 0x0 "NMIER,Non-Maskable Interrupt Enable Register"
|
|
bitfld.word 0x0 12. "SPEEN,CPU Stack Pointer Monitor Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.word 0x0 11. "BUSMEN,Bus Master MPU Error Interrupt Enable" "0: Disabled,1: Enabled"
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|
newline
|
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bitfld.word 0x0 10. "BUSSEN,Bus Slave MPU Error Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.word 0x0 9. "RECCEN,SRAM ECC Error Interrupt Enable" "0: Disabled,1: Enabled"
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|
newline
|
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bitfld.word 0x0 8. "RPEEN,SRAM Parity Error Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.word 0x0 7. "NMIEN,NMI Pin Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 6. "OSTEN,Main Clock Oscillation Stop Detection Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.word 0x0 3. "LVD2EN,Voltage monitor 2 Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 2. "LVD1EN,Voltage monitor 1 Interrupt Enable" "0: Disabled,1: Enabled"
|
|
bitfld.word 0x0 1. "WDTEN,WDT Underflow/Refresh Error Interrupt Enable" "0: Disabled,1: Enabled"
|
|
newline
|
|
bitfld.word 0x0 0. "IWDTEN,IWDT Underflow/Refresh Error Interrupt Enable" "0: Disabled,1: Enabled."
|
|
group.word 0x130++0x1
|
|
line.word 0x0 "NMICLR,Non-Maskable Interrupt Status Clear Register"
|
|
bitfld.word 0x0 12. "SPECLR,CPU Stack Pointer Monitor Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.SPEST flag"
|
|
bitfld.word 0x0 11. "BUSMCLR,Bus Master MPU Error Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.BUSMST flag"
|
|
newline
|
|
bitfld.word 0x0 10. "BUSSCLR,Bus Slave MPU Error Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.BUSSST flag"
|
|
bitfld.word 0x0 9. "RECCCLR,SRAM ECC Error Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.RECCST flag"
|
|
newline
|
|
bitfld.word 0x0 8. "RPECLR,SRAM Parity Error Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.RPEST flag"
|
|
bitfld.word 0x0 7. "NMICLR,NMI Pin Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.NMIST flag"
|
|
newline
|
|
bitfld.word 0x0 6. "OSTCLR,Oscillation Stop Detection Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.OSTST flag"
|
|
bitfld.word 0x0 3. "LVD2CLR,Voltage Monitor 2 Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.LVD2ST flag."
|
|
newline
|
|
bitfld.word 0x0 2. "LVD1CLR,Voltage Monitor 1 Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.LVD1ST flag"
|
|
bitfld.word 0x0 1. "WDTCLR,WDT Underflow/Refresh Error Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.WDTST flag"
|
|
newline
|
|
bitfld.word 0x0 0. "IWDTCLR,IWDT Underflow/Refresh Error Interrupt Status Flag Clear" "0: No effect,1: Clear the NMISR.IWDTST flag"
|
|
rgroup.word 0x140++0x1
|
|
line.word 0x0 "NMISR,Non-Maskable Interrupt Status Register"
|
|
bitfld.word 0x0 12. "SPEST,CPU Stack Pointer Monitor Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
|
bitfld.word 0x0 11. "BUSMST,Bus Master MPU Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
|
newline
|
|
bitfld.word 0x0 10. "BUSSST,Bus Slave MPU Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested."
|
|
bitfld.word 0x0 9. "RECCST,SRAM ECC Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
|
newline
|
|
bitfld.word 0x0 8. "RPEST,SRAM Parity Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
|
bitfld.word 0x0 7. "NMIST,NMI Pin Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
|
newline
|
|
bitfld.word 0x0 6. "OSTST,Main Clock Oscillation Stop Detection Interrupt Status Flag" "0: Interrupt not requested for main clock..,1: Interrupt requested for main clock oscillation.."
|
|
bitfld.word 0x0 3. "LVD2ST,Voltage Monitor 2 Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
|
newline
|
|
bitfld.word 0x0 2. "LVD1ST,Voltage Monitor 1 Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
|
bitfld.word 0x0 1. "WDTST,WDT Underflow/Refresh Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
|
newline
|
|
bitfld.word 0x0 0. "IWDTST,IWDT Underflow/Refresh Error Interrupt Status Flag" "0: Interrupt not requested,1: Interrupt requested"
|
|
group.long 0x1A0++0x3
|
|
line.long 0x0 "WUPEN,Wake Up Interrupt Enable Register"
|
|
bitfld.long 0x0 31. "IIC0WUPEN,IIC0 Address Match Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by IIC0..,1: Software Standby/Snooze Mode returns by IIC0.."
|
|
bitfld.long 0x0 30. "AGT1CBWUPEN,AGT1 Compare Match B Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by AGT1..,1: Software Standby/Snooze Mode returns by AGT1.."
|
|
newline
|
|
bitfld.long 0x0 29. "AGT1CAWUPEN,AGT1 Compare Match A Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by AGT1..,1: Software Standby/Snooze Mode returns by AGT1.."
|
|
bitfld.long 0x0 28. "AGT1UDWUPEN,AGT1 Underflow Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by AGT1..,1: Software Standby/Snooze Mode returns by AGT1.."
|
|
newline
|
|
bitfld.long 0x0 25. "RTCPRDWUPEN,RTC Period Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by RTC..,1: Software Standby/Snooze Mode returns by RTC.."
|
|
bitfld.long 0x0 24. "RTCALMWUPEN,RTC Alarm Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by RTC..,1: Software Standby/Snooze Mode returns by RTC.."
|
|
newline
|
|
bitfld.long 0x0 23. "ACMPLP0WUPEN,ACMPLP0 Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by ACMPLP0..,1: Software Standby/Snooze Mode returns by ACMPLP0.."
|
|
bitfld.long 0x0 19. "LVD2WUPEN,LVD2 Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by LVD2..,1: Software Standby/Snooze Mode returns by LVD2.."
|
|
newline
|
|
bitfld.long 0x0 18. "LVD1WUPEN,LVD1 Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by LVD1..,1: Software Standby/Snooze Mode returns by LVD1.."
|
|
bitfld.long 0x0 17. "KEYWUPEN,Key Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by KEY..,1: Software Standby/Snooze Mode returns by KEY.."
|
|
newline
|
|
bitfld.long 0x0 16. "IWDTWUPEN,IWDT Interrupt Software Standby/Snooze Mode Returns Enable" "0: Software Standby/Snooze Mode returns by IWDT..,1: Software Standby/Snooze Mode returns by IWDT.."
|
|
hexmask.long.byte 0x0 0.--7. 1. "IRQWUPEN,IRQ Interrupt Software Standby/Snooze Mode Returns Enable"
|
|
group.byte 0x1C0++0x0
|
|
line.byte 0x0 "IELEN,ICU event Enable Register"
|
|
bitfld.byte 0x0 1. "IELEN,Parts Asynchronous Interrupts Enable except RTC (when LPOPTEN bit = 1)" "0: Disabled,1: Enabled"
|
|
bitfld.byte 0x0 0. "RTCINTEN,RTCALM and RTCPRD Interrupts Enable (when LPOPTEN bit = 1)" "0: Disabled,1: Enabled"
|
|
group.word 0x200++0x1
|
|
line.word 0x0 "SELSR0,SYS Event Link Setting Register"
|
|
repeat 32. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x300)++0x3
|
|
line.long 0x0 "IELSR$1,ICU Event Link Setting Register %s"
|
|
repeat.end
|
|
tree.end
|
|
tree "IIC (Inter-Integrated Circuit)"
|
|
tree "IIC0"
|
|
base ad:0x40053000
|
|
group.byte 0x0++0x9
|
|
line.byte 0x0 "ICCR1,I2C Bus Control Register 1"
|
|
bitfld.byte 0x0 7. "ICE,I2C Bus Interface Enable" "0: Disable (SCLn and SDAn pins in inactive state),1: Enable (SCLn and SDAn pins in active state)"
|
|
bitfld.byte 0x0 6. "IICRST,I2C Bus Interface Internal Reset" "0: Release IIC reset or internal reset,1: Initiate IIC reset or internal reset"
|
|
newline
|
|
bitfld.byte 0x0 5. "CLO,Extra SCL Clock Cycle Output" "0: Do not output extra SCL clock cycle (default),1: Output extra SCL clock cycle"
|
|
bitfld.byte 0x0 4. "SOWP,SCLO/SDAO Write Protect" "0: Write enable SCLO and SDAO bits,1: Write protect SCLO and SDAO bits"
|
|
newline
|
|
bitfld.byte 0x0 3. "SCLO,SCL Output Control/Monitor" "0: Read: IIC drives SCLn pin low Write: IIC drives..,1: Read: IIC releases SCLn pin Write: IIC releases.."
|
|
bitfld.byte 0x0 2. "SDAO,SDA Output Control/Monitor" "0: Read: IIC drives SDAn pin low Write: IIC drives..,1: Read: IIC releases SDAn pin Write: IIC releases.."
|
|
newline
|
|
rbitfld.byte 0x0 1. "SCLI,SCL Line Monitor" "0: SCLn line is low,1: SCLn line is high"
|
|
rbitfld.byte 0x0 0. "SDAI,SDA Line Monitor" "0: SDAn line is low,1: SDAn line is high"
|
|
line.byte 0x1 "ICCR2,I2C Bus Control Register 2"
|
|
rbitfld.byte 0x1 7. "BBSY,Bus Busy Detection Flag" "0: I2C bus released (bus free state),1: I2C bus occupied (bus busy state)"
|
|
bitfld.byte 0x1 6. "MST,Master/Slave Mode" "0: Slave mode,1: Master mode"
|
|
newline
|
|
bitfld.byte 0x1 5. "TRS,Transmit/Receive Mode" "0: Receive mode,1: Transmit mode"
|
|
bitfld.byte 0x1 3. "SP,Stop Condition Issuance Request" "0: Do not issue a stop condition request,1: Issue a stop condition request"
|
|
newline
|
|
bitfld.byte 0x1 2. "RS,Restart Condition Issuance Request" "0: Do not issue a restart condition request,1: Issue a restart condition request"
|
|
bitfld.byte 0x1 1. "ST,Start Condition Issuance Request" "0: Do not issue a start condition request,1: Issue a start condition request"
|
|
line.byte 0x2 "ICMR1,I2C Bus Mode Register 1"
|
|
bitfld.byte 0x2 7. "MTWP,MST/TRS Write Protect" "0: Write protect MST and TRS bits in ICCR2,1: Write enable MST and TRS bits in ICCR2"
|
|
bitfld.byte 0x2 4.--6. "CKS,Internal Reference Clock Select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x2 3. "BCWP,BC Write Protect" "0: Write enable BC[2:0] bits,1: Write protect BC[2:0] bits"
|
|
bitfld.byte 0x2 0.--2. "BC,Bit Counter" "0: 9 bits,1: 2 bits,?,?,?,?,?,?"
|
|
line.byte 0x3 "ICMR2,I2C Bus Mode Register 2"
|
|
bitfld.byte 0x3 7. "DLCS,SDA Output Delay Clock Source Select" "0: Select internal reference clock (IIC-phi) as the..,1: Select internal reference clock divided by 2.."
|
|
bitfld.byte 0x3 4.--6. "SDDL,SDA Output Delay Counter" "0: No output delay,1: 1 IIC-phi cycle (When ICMR2.DLCS = 0 (IIC-phi))..,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.byte 0x3 2. "TMOH,Timeout H Count Control" "0: Disable count while SCLn line is high,1: Enable count while SCLn line is high"
|
|
bitfld.byte 0x3 1. "TMOL,Timeout L Count Control" "0: Disable count while SCLn line is low,1: Enable count while SCLn line is low"
|
|
newline
|
|
bitfld.byte 0x3 0. "TMOS,Timeout Detection Time Select" "0: Select long mode,1: Select short mode"
|
|
line.byte 0x4 "ICMR3,I2C Bus Mode Register 3"
|
|
bitfld.byte 0x4 7. "SMBS,SMBus/I2C Bus Select" "0: Select I2C Bus,1: Select SMBus"
|
|
bitfld.byte 0x4 6. "WAIT,Low-hold is released by reading ICDRR." "0: No wait (The SCLn line is not held low during..,1: Wait (The SCLn line is held low during the.."
|
|
newline
|
|
bitfld.byte 0x4 5. "RDRFS,RDRF Flag Set Timing Select" "0: Set the RDRF flag on the rising edge of the 9th..,1: Set the RDRF flag on the rising edge of the 8th.."
|
|
bitfld.byte 0x4 4. "ACKWP,ACKBT Write Protect" "0: Write protect ACKBT bit,1: Write enable ACKBT bit"
|
|
newline
|
|
bitfld.byte 0x4 3. "ACKBT,Transmit Acknowledge" "0: Send 0 as the acknowledge bit (ACK transmission),1: Send 1 as the acknowledge bit (NACK transmission)"
|
|
rbitfld.byte 0x4 2. "ACKBR,Receive Acknowledge" "0: 0 received as the acknowledge bit (ACK reception),1: 1 received as the acknowledge bit (NACK reception)"
|
|
newline
|
|
bitfld.byte 0x4 0.--1. "NF,Noise Filter Stage Select" "0: Filter out noise of up to 1 IIC-phi cycle..,1: Filter out noise of up to 2 IIC-phi cycles..,?,?"
|
|
line.byte 0x5 "ICFER,I2C Bus Function Enable Register"
|
|
bitfld.byte 0x5 6. "SCLE,SCL Synchronous Circuit Enable" "0: Do not use the SCL synchronous circuit,1: Use the SCL synchronous circuit"
|
|
bitfld.byte 0x5 5. "NFE,Digital Noise Filter Circuit Enable" "0: Do not use the digital noise filter circuit,1: Use the digital noise filter circuit"
|
|
newline
|
|
bitfld.byte 0x5 4. "NACKE,NACK Reception Transfer Suspension Enable" "0: Do not suspend transfer operation during NACK..,1: Suspend transfer operation during NACK reception.."
|
|
bitfld.byte 0x5 3. "SALE,Slave Arbitration-Lost Detection Enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.byte 0x5 2. "NALE,NACK Transmission Arbitration-Lost Detection Enable" "0: Disable,1: Enable"
|
|
bitfld.byte 0x5 1. "MALE,Master Arbitration-Lost Detection Enable" "0: Disable the arbitration-lost detection function..,1: Enable the arbitration-lost detection function.."
|
|
newline
|
|
bitfld.byte 0x5 0. "TMOE,Timeout Function Enable" "0: Disable,1: Enable"
|
|
line.byte 0x6 "ICSER,I2C Bus Status Enable Register"
|
|
bitfld.byte 0x6 7. "HOAE,Host Address Enable" "0: Disable host address detection,1: Enable host address detection"
|
|
bitfld.byte 0x6 5. "DIDE,Device-ID Address Detection Enable" "0: Disable device-ID address detection,1: Enable device-ID address detection"
|
|
newline
|
|
bitfld.byte 0x6 3. "GCAE,General Call Address Enable" "0: Disable general call address detection,1: Enable general call address detection"
|
|
bitfld.byte 0x6 2. "SAR2E,Slave Address Register 2 Enable" "0: Disable slave address in SARL2 and SARU2,1: Enable slave address in SARL2 and SARU2"
|
|
newline
|
|
bitfld.byte 0x6 1. "SAR1E,Slave Address Register 1 Enable" "0: Disable slave address in SARL1 and SARU1,1: Enable slave address in SARL1 and SARU1"
|
|
bitfld.byte 0x6 0. "SAR0E,Slave Address Register 0 Enable" "0: Disable slave address in SARL0 and SARU0,1: Enable slave address in SARL0 and SARU0"
|
|
line.byte 0x7 "ICIER,I2C Bus Interrupt Enable Register"
|
|
bitfld.byte 0x7 7. "TIE,Transmit Data Empty Interrupt Request Enable" "0: Disable transmit data empty interrupt (IICn_TXI)..,1: Enable transmit data empty interrupt (IICn_TXI).."
|
|
bitfld.byte 0x7 6. "TEIE,Transmit End Interrupt Request Enable" "0: Disable transmit end interrupt (IICn_TEI) request,1: Enable transmit end interrupt (IICn_TEI) request"
|
|
newline
|
|
bitfld.byte 0x7 5. "RIE,Receive Data Full Interrupt Request Enable" "0: Disable receive data full interrupt (IICn_RXI)..,1: Enable receive data full interrupt (IICn_RXI).."
|
|
bitfld.byte 0x7 4. "NAKIE,NACK Reception Interrupt Request Enable" "0: Disable NACK reception interrupt (NAKI) request,1: Enable NACK reception interrupt (NAKI) request"
|
|
newline
|
|
bitfld.byte 0x7 3. "SPIE,Stop Condition Detection Interrupt Request Enable" "0: Disable stop condition detection interrupt (SPI)..,1: Enable stop condition detection interrupt (SPI).."
|
|
bitfld.byte 0x7 2. "STIE,Start Condition Detection Interrupt Request Enable" "0: Disable start condition detection interrupt..,1: Enable start condition detection interrupt (STI).."
|
|
newline
|
|
bitfld.byte 0x7 1. "ALIE,Arbitration-Lost Interrupt Request Enable" "0: Disable arbitration-lost interrupt (ALI) request,1: Enable arbitration-lost interrupt (ALI) request"
|
|
bitfld.byte 0x7 0. "TMOIE,Timeout Interrupt Request Enable" "0: Disable timeout interrupt (TMOI) request,1: Enable timeout interrupt (TMOI) request"
|
|
line.byte 0x8 "ICSR1,I2C Bus Status Register 1"
|
|
bitfld.byte 0x8 7. "HOA,Host Address Detection Flag" "0: Host address not detected,1: Host address detected"
|
|
bitfld.byte 0x8 5. "DID,Device-ID Address Detection Flag" "0: Device-ID command not detected,1: Device-ID command detected"
|
|
newline
|
|
bitfld.byte 0x8 3. "GCA,General Call Address Detection Flag" "0: General call address not detected,1: General call address detected"
|
|
bitfld.byte 0x8 2. "AAS2,Slave Address 2 Detection Flag" "0: Slave address 2 not detected,1: Slave address 2 detected"
|
|
newline
|
|
bitfld.byte 0x8 1. "AAS1,Slave Address 1 Detection Flag" "0: Slave address 1 not detected,1: Slave address 1 detected"
|
|
bitfld.byte 0x8 0. "AAS0,Slave Address 0 Detection Flag" "0: Slave address 0 not detected,1: Slave address 0 detected"
|
|
line.byte 0x9 "ICSR2,I2C Bus Status Register 2"
|
|
rbitfld.byte 0x9 7. "TDRE,Transmit Data Empty Flag" "0: ICDRT contains transmit data,1: ICDRT contains no transmit data"
|
|
bitfld.byte 0x9 6. "TEND,Transmit End Flag" "0: Data being transmitted,1: Data transmit complete"
|
|
newline
|
|
bitfld.byte 0x9 5. "RDRF,Receive Data Full Flag" "0: ICDRR contains no receive data,1: ICDRR contains receive data"
|
|
bitfld.byte 0x9 4. "NACKF,NACK Detection Flag" "0: NACK not detected,1: NACK detected"
|
|
newline
|
|
bitfld.byte 0x9 3. "STOP,Stop Condition Detection Flag" "0: Stop condition not detected,1: Stop condition detected"
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|
bitfld.byte 0x9 2. "START,Start Condition Detection Flag" "0: Start condition not detected,1: Start condition detected"
|
|
newline
|
|
bitfld.byte 0x9 1. "AL,Arbitration-Lost Flag" "0: Arbitration not lost,1: Arbitration lost"
|
|
bitfld.byte 0x9 0. "TMOF,Timeout Detection Flag" "0: Timeout not detected,1: Timeout detected"
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.byte ($2+0xA)++0x0
|
|
line.byte 0x0 "SARL$1,Slave Address Register Ly"
|
|
hexmask.byte 0x0 1.--7. 1. "SVA,7-bit Address/10-bit Address Lower Bits"
|
|
bitfld.byte 0x0 0. "SVA0,10-bit Address LSB" "0,1"
|
|
repeat.end
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.byte ($2+0xB)++0x0
|
|
line.byte 0x0 "SARU$1,Slave Address Register Uy"
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|
bitfld.byte 0x0 1.--2. "SVA,10-bit Address Upper Bits" "0,1,2,3"
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|
bitfld.byte 0x0 0. "FS,7-bit/10-bit Address Format Select" "0: Select 7-bit address format,1: Select 10-bit address format"
|
|
repeat.end
|
|
group.byte 0x10++0x2
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line.byte 0x0 "ICBRL,I2C Bus Bit Rate Low-Level Register"
|
|
hexmask.byte 0x0 0.--4. 1. "BRL,Bit Rate Low-Level Period"
|
|
line.byte 0x1 "ICBRH,I2C Bus Bit Rate High-Level Register"
|
|
hexmask.byte 0x1 0.--4. 1. "BRH,Bit Rate High-Level Period"
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|
line.byte 0x2 "ICDRT,I2C Bus Transmit Data Register"
|
|
rgroup.byte 0x13++0x0
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line.byte 0x0 "ICDRR,I2C Bus Receive Data Register"
|
|
tree.end
|
|
tree "IIC1"
|
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base ad:0x40053100
|
|
group.byte 0x0++0x9
|
|
line.byte 0x0 "ICCR1,I2C Bus Control Register 1"
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bitfld.byte 0x0 7. "ICE,I2C Bus Interface Enable" "0: Disable (SCLn and SDAn pins in inactive state),1: Enable (SCLn and SDAn pins in active state)"
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|
bitfld.byte 0x0 6. "IICRST,I2C Bus Interface Internal Reset" "0: Release IIC reset or internal reset,1: Initiate IIC reset or internal reset"
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newline
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bitfld.byte 0x0 5. "CLO,Extra SCL Clock Cycle Output" "0: Do not output extra SCL clock cycle (default),1: Output extra SCL clock cycle"
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bitfld.byte 0x0 4. "SOWP,SCLO/SDAO Write Protect" "0: Write enable SCLO and SDAO bits,1: Write protect SCLO and SDAO bits"
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|
newline
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bitfld.byte 0x0 3. "SCLO,SCL Output Control/Monitor" "0: Read: IIC drives SCLn pin low Write: IIC drives..,1: Read: IIC releases SCLn pin Write: IIC releases.."
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bitfld.byte 0x0 2. "SDAO,SDA Output Control/Monitor" "0: Read: IIC drives SDAn pin low Write: IIC drives..,1: Read: IIC releases SDAn pin Write: IIC releases.."
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|
newline
|
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rbitfld.byte 0x0 1. "SCLI,SCL Line Monitor" "0: SCLn line is low,1: SCLn line is high"
|
|
rbitfld.byte 0x0 0. "SDAI,SDA Line Monitor" "0: SDAn line is low,1: SDAn line is high"
|
|
line.byte 0x1 "ICCR2,I2C Bus Control Register 2"
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rbitfld.byte 0x1 7. "BBSY,Bus Busy Detection Flag" "0: I2C bus released (bus free state),1: I2C bus occupied (bus busy state)"
|
|
bitfld.byte 0x1 6. "MST,Master/Slave Mode" "0: Slave mode,1: Master mode"
|
|
newline
|
|
bitfld.byte 0x1 5. "TRS,Transmit/Receive Mode" "0: Receive mode,1: Transmit mode"
|
|
bitfld.byte 0x1 3. "SP,Stop Condition Issuance Request" "0: Do not issue a stop condition request,1: Issue a stop condition request"
|
|
newline
|
|
bitfld.byte 0x1 2. "RS,Restart Condition Issuance Request" "0: Do not issue a restart condition request,1: Issue a restart condition request"
|
|
bitfld.byte 0x1 1. "ST,Start Condition Issuance Request" "0: Do not issue a start condition request,1: Issue a start condition request"
|
|
line.byte 0x2 "ICMR1,I2C Bus Mode Register 1"
|
|
bitfld.byte 0x2 7. "MTWP,MST/TRS Write Protect" "0: Write protect MST and TRS bits in ICCR2,1: Write enable MST and TRS bits in ICCR2"
|
|
bitfld.byte 0x2 4.--6. "CKS,Internal Reference Clock Select" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
bitfld.byte 0x2 3. "BCWP,BC Write Protect" "0: Write enable BC[2:0] bits,1: Write protect BC[2:0] bits"
|
|
bitfld.byte 0x2 0.--2. "BC,Bit Counter" "0: 9 bits,1: 2 bits,?,?,?,?,?,?"
|
|
line.byte 0x3 "ICMR2,I2C Bus Mode Register 2"
|
|
bitfld.byte 0x3 7. "DLCS,SDA Output Delay Clock Source Select" "0: Select internal reference clock (IIC-phi) as the..,1: Select internal reference clock divided by 2.."
|
|
bitfld.byte 0x3 4.--6. "SDDL,SDA Output Delay Counter" "0: No output delay,1: 1 IIC-phi cycle (When ICMR2.DLCS = 0 (IIC-phi))..,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.byte 0x3 2. "TMOH,Timeout H Count Control" "0: Disable count while SCLn line is high,1: Enable count while SCLn line is high"
|
|
bitfld.byte 0x3 1. "TMOL,Timeout L Count Control" "0: Disable count while SCLn line is low,1: Enable count while SCLn line is low"
|
|
newline
|
|
bitfld.byte 0x3 0. "TMOS,Timeout Detection Time Select" "0: Select long mode,1: Select short mode"
|
|
line.byte 0x4 "ICMR3,I2C Bus Mode Register 3"
|
|
bitfld.byte 0x4 7. "SMBS,SMBus/I2C Bus Select" "0: Select I2C Bus,1: Select SMBus"
|
|
bitfld.byte 0x4 6. "WAIT,Low-hold is released by reading ICDRR." "0: No wait (The SCLn line is not held low during..,1: Wait (The SCLn line is held low during the.."
|
|
newline
|
|
bitfld.byte 0x4 5. "RDRFS,RDRF Flag Set Timing Select" "0: Set the RDRF flag on the rising edge of the 9th..,1: Set the RDRF flag on the rising edge of the 8th.."
|
|
bitfld.byte 0x4 4. "ACKWP,ACKBT Write Protect" "0: Write protect ACKBT bit,1: Write enable ACKBT bit"
|
|
newline
|
|
bitfld.byte 0x4 3. "ACKBT,Transmit Acknowledge" "0: Send 0 as the acknowledge bit (ACK transmission),1: Send 1 as the acknowledge bit (NACK transmission)"
|
|
rbitfld.byte 0x4 2. "ACKBR,Receive Acknowledge" "0: 0 received as the acknowledge bit (ACK reception),1: 1 received as the acknowledge bit (NACK reception)"
|
|
newline
|
|
bitfld.byte 0x4 0.--1. "NF,Noise Filter Stage Select" "0: Filter out noise of up to 1 IIC-phi cycle..,1: Filter out noise of up to 2 IIC-phi cycles..,?,?"
|
|
line.byte 0x5 "ICFER,I2C Bus Function Enable Register"
|
|
bitfld.byte 0x5 6. "SCLE,SCL Synchronous Circuit Enable" "0: Do not use the SCL synchronous circuit,1: Use the SCL synchronous circuit"
|
|
bitfld.byte 0x5 5. "NFE,Digital Noise Filter Circuit Enable" "0: Do not use the digital noise filter circuit,1: Use the digital noise filter circuit"
|
|
newline
|
|
bitfld.byte 0x5 4. "NACKE,NACK Reception Transfer Suspension Enable" "0: Do not suspend transfer operation during NACK..,1: Suspend transfer operation during NACK reception.."
|
|
bitfld.byte 0x5 3. "SALE,Slave Arbitration-Lost Detection Enable" "0: Disable,1: Enable"
|
|
newline
|
|
bitfld.byte 0x5 2. "NALE,NACK Transmission Arbitration-Lost Detection Enable" "0: Disable,1: Enable"
|
|
bitfld.byte 0x5 1. "MALE,Master Arbitration-Lost Detection Enable" "0: Disable the arbitration-lost detection function..,1: Enable the arbitration-lost detection function.."
|
|
newline
|
|
bitfld.byte 0x5 0. "TMOE,Timeout Function Enable" "0: Disable,1: Enable"
|
|
line.byte 0x6 "ICSER,I2C Bus Status Enable Register"
|
|
bitfld.byte 0x6 7. "HOAE,Host Address Enable" "0: Disable host address detection,1: Enable host address detection"
|
|
bitfld.byte 0x6 5. "DIDE,Device-ID Address Detection Enable" "0: Disable device-ID address detection,1: Enable device-ID address detection"
|
|
newline
|
|
bitfld.byte 0x6 3. "GCAE,General Call Address Enable" "0: Disable general call address detection,1: Enable general call address detection"
|
|
bitfld.byte 0x6 2. "SAR2E,Slave Address Register 2 Enable" "0: Disable slave address in SARL2 and SARU2,1: Enable slave address in SARL2 and SARU2"
|
|
newline
|
|
bitfld.byte 0x6 1. "SAR1E,Slave Address Register 1 Enable" "0: Disable slave address in SARL1 and SARU1,1: Enable slave address in SARL1 and SARU1"
|
|
bitfld.byte 0x6 0. "SAR0E,Slave Address Register 0 Enable" "0: Disable slave address in SARL0 and SARU0,1: Enable slave address in SARL0 and SARU0"
|
|
line.byte 0x7 "ICIER,I2C Bus Interrupt Enable Register"
|
|
bitfld.byte 0x7 7. "TIE,Transmit Data Empty Interrupt Request Enable" "0: Disable transmit data empty interrupt (IICn_TXI)..,1: Enable transmit data empty interrupt (IICn_TXI).."
|
|
bitfld.byte 0x7 6. "TEIE,Transmit End Interrupt Request Enable" "0: Disable transmit end interrupt (IICn_TEI) request,1: Enable transmit end interrupt (IICn_TEI) request"
|
|
newline
|
|
bitfld.byte 0x7 5. "RIE,Receive Data Full Interrupt Request Enable" "0: Disable receive data full interrupt (IICn_RXI)..,1: Enable receive data full interrupt (IICn_RXI).."
|
|
bitfld.byte 0x7 4. "NAKIE,NACK Reception Interrupt Request Enable" "0: Disable NACK reception interrupt (NAKI) request,1: Enable NACK reception interrupt (NAKI) request"
|
|
newline
|
|
bitfld.byte 0x7 3. "SPIE,Stop Condition Detection Interrupt Request Enable" "0: Disable stop condition detection interrupt (SPI)..,1: Enable stop condition detection interrupt (SPI).."
|
|
bitfld.byte 0x7 2. "STIE,Start Condition Detection Interrupt Request Enable" "0: Disable start condition detection interrupt..,1: Enable start condition detection interrupt (STI).."
|
|
newline
|
|
bitfld.byte 0x7 1. "ALIE,Arbitration-Lost Interrupt Request Enable" "0: Disable arbitration-lost interrupt (ALI) request,1: Enable arbitration-lost interrupt (ALI) request"
|
|
bitfld.byte 0x7 0. "TMOIE,Timeout Interrupt Request Enable" "0: Disable timeout interrupt (TMOI) request,1: Enable timeout interrupt (TMOI) request"
|
|
line.byte 0x8 "ICSR1,I2C Bus Status Register 1"
|
|
bitfld.byte 0x8 7. "HOA,Host Address Detection Flag" "0: Host address not detected,1: Host address detected"
|
|
bitfld.byte 0x8 5. "DID,Device-ID Address Detection Flag" "0: Device-ID command not detected,1: Device-ID command detected"
|
|
newline
|
|
bitfld.byte 0x8 3. "GCA,General Call Address Detection Flag" "0: General call address not detected,1: General call address detected"
|
|
bitfld.byte 0x8 2. "AAS2,Slave Address 2 Detection Flag" "0: Slave address 2 not detected,1: Slave address 2 detected"
|
|
newline
|
|
bitfld.byte 0x8 1. "AAS1,Slave Address 1 Detection Flag" "0: Slave address 1 not detected,1: Slave address 1 detected"
|
|
bitfld.byte 0x8 0. "AAS0,Slave Address 0 Detection Flag" "0: Slave address 0 not detected,1: Slave address 0 detected"
|
|
line.byte 0x9 "ICSR2,I2C Bus Status Register 2"
|
|
rbitfld.byte 0x9 7. "TDRE,Transmit Data Empty Flag" "0: ICDRT contains transmit data,1: ICDRT contains no transmit data"
|
|
bitfld.byte 0x9 6. "TEND,Transmit End Flag" "0: Data being transmitted,1: Data transmit complete"
|
|
newline
|
|
bitfld.byte 0x9 5. "RDRF,Receive Data Full Flag" "0: ICDRR contains no receive data,1: ICDRR contains receive data"
|
|
bitfld.byte 0x9 4. "NACKF,NACK Detection Flag" "0: NACK not detected,1: NACK detected"
|
|
newline
|
|
bitfld.byte 0x9 3. "STOP,Stop Condition Detection Flag" "0: Stop condition not detected,1: Stop condition detected"
|
|
bitfld.byte 0x9 2. "START,Start Condition Detection Flag" "0: Start condition not detected,1: Start condition detected"
|
|
newline
|
|
bitfld.byte 0x9 1. "AL,Arbitration-Lost Flag" "0: Arbitration not lost,1: Arbitration lost"
|
|
bitfld.byte 0x9 0. "TMOF,Timeout Detection Flag" "0: Timeout not detected,1: Timeout detected"
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.byte ($2+0xA)++0x0
|
|
line.byte 0x0 "SARL$1,Slave Address Register Ly"
|
|
hexmask.byte 0x0 1.--7. 1. "SVA,7-bit Address/10-bit Address Lower Bits"
|
|
bitfld.byte 0x0 0. "SVA0,10-bit Address LSB" "0,1"
|
|
repeat.end
|
|
repeat 3. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.byte ($2+0xB)++0x0
|
|
line.byte 0x0 "SARU$1,Slave Address Register Uy"
|
|
bitfld.byte 0x0 1.--2. "SVA,10-bit Address Upper Bits" "0,1,2,3"
|
|
bitfld.byte 0x0 0. "FS,7-bit/10-bit Address Format Select" "0: Select 7-bit address format,1: Select 10-bit address format"
|
|
repeat.end
|
|
group.byte 0x10++0x2
|
|
line.byte 0x0 "ICBRL,I2C Bus Bit Rate Low-Level Register"
|
|
hexmask.byte 0x0 0.--4. 1. "BRL,Bit Rate Low-Level Period"
|
|
line.byte 0x1 "ICBRH,I2C Bus Bit Rate High-Level Register"
|
|
hexmask.byte 0x1 0.--4. 1. "BRH,Bit Rate High-Level Period"
|
|
line.byte 0x2 "ICDRT,I2C Bus Transmit Data Register"
|
|
rgroup.byte 0x13++0x0
|
|
line.byte 0x0 "ICDRR,I2C Bus Receive Data Register"
|
|
tree.end
|
|
tree.end
|
|
tree "IIC0WU (Inter-Integrated Circuit 0 Wake-up Unit)"
|
|
base ad:0x40053014
|
|
group.byte 0x2++0x1
|
|
line.byte 0x0 "ICWUR,I2C Bus Wakeup Unit Register"
|
|
bitfld.byte 0x0 7. "WUE,Wakeup Function Enable" "0: Disable wakeup function,1: Enable wakeup function"
|
|
bitfld.byte 0x0 6. "WUIE,Wakeup Interrupt Request Enable" "0: Disable wakeup interrupt request (IIC0_WUI),1: Enable wakeup interrupt request (IIC0_WUI)"
|
|
newline
|
|
bitfld.byte 0x0 5. "WUF,Wakeup Event Occurrence Flag" "0: Slave address not matching during wakeup,1: Slave address matching during wakeup"
|
|
bitfld.byte 0x0 4. "WUACK,ACK Bit for Wakeup Mode" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0. "WUAFA,Wakeup Analog Filter Additional Selection" "0: Do not add the wakeup analog filter,1: Add the wakeup analog filter"
|
|
line.byte 0x1 "ICWUR2,I2C Bus Wakeup Unit Register 2"
|
|
rbitfld.byte 0x1 2. "WUSYF,Wakeup Function Synchronous Operation Status Flag" "0: IIC asynchronous circuit enable condition,1: IIC synchronous circuit enable condition"
|
|
rbitfld.byte 0x1 1. "WUASYF,Wakeup Function Asynchronous Operation Status Flag" "0: IIC synchronous circuit enable condition,1: IIC asynchronous circuit enable condition"
|
|
newline
|
|
bitfld.byte 0x1 0. "WUSEN,Wakeup Function Synchronous Enable" "0: IIC asynchronous circuit enable,1: IIC synchronous circuit enable"
|
|
tree.end
|
|
tree "IWDT (Independent Watchdog Timer)"
|
|
base ad:0x40044400
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "IWDTRR,IWDT Refresh Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "IWDTSR,IWDT Status Register"
|
|
bitfld.word 0x0 15. "REFEF,Refresh Error Flag" "0: No refresh error occurred,1: Refresh error occurred"
|
|
bitfld.word 0x0 14. "UNDFF,Underflow Flag" "0: No underflow occurred,1: Underflow occurred"
|
|
hexmask.word 0x0 0.--13. 1. "CNTVAL,Down-counter Value"
|
|
tree.end
|
|
tree "KINT (Key Interrupt Function)"
|
|
base ad:0x40080000
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "KRCTL,Key Return Control Register"
|
|
bitfld.byte 0x0 7. "KRMD,Usage of Key Interrupt Flags (KRF.KIF0 to KRF.KIF7)" "0: Do not use key interrupt flags,1: Use key interrupt flags"
|
|
bitfld.byte 0x0 0. "KREG,Detection Edge Selection (KR00 to KR07 pins)" "0: Falling edge,1: Rising edge"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "KRF,Key Return Flag Register"
|
|
bitfld.byte 0x0 7. "KIF7,Key Interrupt Flag n" "0: No interrupt detected,1: Interrupt detected"
|
|
bitfld.byte 0x0 6. "KIF6,Key Interrupt Flag n" "0: No interrupt detected,1: Interrupt detected"
|
|
bitfld.byte 0x0 5. "KIF5,Key Interrupt Flag n" "0: No interrupt detected,1: Interrupt detected"
|
|
newline
|
|
bitfld.byte 0x0 4. "KIF4,Key Interrupt Flag n" "0: No interrupt detected,1: Interrupt detected"
|
|
bitfld.byte 0x0 3. "KIF3,Key Interrupt Flag n" "0: No interrupt detected,1: Interrupt detected"
|
|
bitfld.byte 0x0 2. "KIF2,Key Interrupt Flag n" "0: No interrupt detected,1: Interrupt detected"
|
|
newline
|
|
bitfld.byte 0x0 1. "KIF1,Key Interrupt Flag n" "0: No interrupt detected,1: Interrupt detected"
|
|
bitfld.byte 0x0 0. "KIF0,Key Interrupt Flag n" "0: No interrupt detected,1: Interrupt detected"
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "KRM,Key Return Mode Register"
|
|
bitfld.byte 0x0 7. "KIMC7,Key Interrupt Mode Control n" "0: Do not detect key interrupt signals,1: Detect key interrupt signals"
|
|
bitfld.byte 0x0 6. "KIMC6,Key Interrupt Mode Control n" "0: Do not detect key interrupt signals,1: Detect key interrupt signals"
|
|
bitfld.byte 0x0 5. "KIMC5,Key Interrupt Mode Control n" "0: Do not detect key interrupt signals,1: Detect key interrupt signals"
|
|
newline
|
|
bitfld.byte 0x0 4. "KIMC4,Key Interrupt Mode Control n" "0: Do not detect key interrupt signals,1: Detect key interrupt signals"
|
|
bitfld.byte 0x0 3. "KIMC3,Key Interrupt Mode Control n" "0: Do not detect key interrupt signals,1: Detect key interrupt signals"
|
|
bitfld.byte 0x0 2. "KIMC2,Key Interrupt Mode Control n" "0: Do not detect key interrupt signals,1: Detect key interrupt signals"
|
|
newline
|
|
bitfld.byte 0x0 1. "KIMC1,Key Interrupt Mode Control n" "0: Do not detect key interrupt signals,1: Detect key interrupt signals"
|
|
bitfld.byte 0x0 0. "KIMC0,Key Interrupt Mode Control n" "0: Do not detect key interrupt signals,1: Detect key interrupt signals"
|
|
tree.end
|
|
tree "MSTP (Module Stop Control B C D)"
|
|
base ad:0x40047000
|
|
group.long 0x0++0xB
|
|
line.long 0x0 "MSTPCRB,Module Stop Control Register B"
|
|
bitfld.long 0x0 31. "MSTPB31,Serial Communication Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x0 30. "MSTPB30,Serial Communication Interface 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x0 29. "MSTPB29,Serial Communication Interface 2 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
newline
|
|
bitfld.long 0x0 28. "MSTPB28,Serial Communication Interface 3 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x0 22. "MSTPB22,Serial Communication Interface 9 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x0 19. "MSTPB19,Serial Peripheral Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
newline
|
|
bitfld.long 0x0 18. "MSTPB18,Serial Peripheral Interface 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x0 9. "MSTPB9,I2C Bus Interface 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x0 8. "MSTPB8,I2C Bus Interface 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
newline
|
|
bitfld.long 0x0 2. "MSTPB2,Controller Area Network 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
line.long 0x4 "MSTPCRC,Module Stop Control Register C"
|
|
bitfld.long 0x4 31. "MSTPC31,AES Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x4 28. "MSTPC28,True Random Number Generator Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x4 14. "MSTPC14,Event Link Controller Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
newline
|
|
bitfld.long 0x4 13. "MSTPC13,Data Operation Circuit Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x4 3. "MSTPC3,Capacitive Sensing Unit Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x4 1. "MSTPC1,Cyclic Redundancy Check Calculator Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
newline
|
|
bitfld.long 0x4 0. "MSTPC0,Clock Frequency Accuracy Measurement Circuit Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
line.long 0x8 "MSTPCRD,Module Stop Control Register D"
|
|
bitfld.long 0x8 29. "MSTPD29,Low-Power Analog Comparator Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x8 20. "MSTPD20,12-bit D/A Converter Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x8 16. "MSTPD16,12-bit A/D Converter Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
newline
|
|
bitfld.long 0x8 14. "MSTPD14,Port Output Enable for GPT Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x8 6. "MSTPD6,General PWM Timer 164 to 169 and PWM Delay Generation Circuit Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x8 5. "MSTPD5,General PWM Timer 32n Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
newline
|
|
bitfld.long 0x8 3. "MSTPD3,Low Power Asynchronous General Purpose Timer 0 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
bitfld.long 0x8 2. "MSTPD2,Low Power Asynchronous General Purpose Timer 1 Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "LSMRWDIS,Low Speed Module R/W Disable Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "PRKEY,LSMRWDIS Key Code"
|
|
bitfld.word 0x0 7. "WREN,Write Enable for bits [2:0]" "0: Write protect for bits [2:0],1: Write enable for bits [2:0]"
|
|
bitfld.word 0x0 2. "IWDTIDS,IWDT Register Clock Control" "0: IWDT operates as normal,1: Stop the IWDT register R/W clock"
|
|
newline
|
|
bitfld.word 0x0 1. "WDTDIS,WDT Operate Clock Control" "0: WDT operates as normal,1: Stop the WDT clock and register R/W clock"
|
|
bitfld.word 0x0 0. "RTCRWDIS,RTC Register R/W Enable Control" "0: RTC register R/W clock always on,1: RTC register R/W clock stops"
|
|
tree.end
|
|
tree "PFS (Pmn Pin Function Control Register)"
|
|
base ad:0x40040800
|
|
repeat 9. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2)++0x3
|
|
line.long 0x0 "P00$1PFS,Port 00%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 9. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x2)++0x1
|
|
line.word 0x0 "P00$1PFS_HA,Port 00%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 9. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0x3)++0x0
|
|
line.byte 0x0 "P00$1PFS_BY,Port 00%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x28)++0x3
|
|
line.long 0x0 "P0$1PFS,Port 0%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x2A)++0x1
|
|
line.word 0x0 "P0$1PFS_HA,Port 0%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0x2B)++0x0
|
|
line.byte 0x0 "P0$1PFS_BY,Port 0%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x40)++0x3
|
|
line.long 0x0 "P10$1PFS,Port 10%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x42)++0x1
|
|
line.word 0x0 "P10$1PFS_HA,Port 10%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 8. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0x43)++0x0
|
|
line.byte 0x0 "P10$1PFS_BY,Port 10%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
group.long 0x60++0x3
|
|
line.long 0x0 "P108PFS,Port 108 Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.word 0x62++0x1
|
|
line.word 0x0 "P108PFS_HA,Port 108 Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.byte 0x63++0x0
|
|
line.byte 0x0 "P108PFS_BY,Port 108 Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.long 0x64++0x3
|
|
line.long 0x0 "P109PFS,Port 109 Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.word 0x66++0x1
|
|
line.word 0x0 "P109PFS_HA,Port 109 Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.byte 0x67++0x0
|
|
line.byte 0x0 "P109PFS_BY,Port 109 Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x68)++0x3
|
|
line.long 0x0 "P1$1PFS,Port 1%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x6A)++0x1
|
|
line.word 0x0 "P1$1PFS_HA,Port 1%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0x6B)++0x0
|
|
line.byte 0x0 "P1$1PFS_BY,Port 1%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
group.long 0x80++0x3
|
|
line.long 0x0 "P200PFS,Port 200 Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.word 0x82++0x1
|
|
line.word 0x0 "P200PFS_HA,Port 200 Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.byte 0x83++0x0
|
|
line.byte 0x0 "P200PFS_BY,Port 200 Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.long 0x84++0x3
|
|
line.long 0x0 "P201PFS,Port 201 Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.word 0x86++0x1
|
|
line.word 0x0 "P201PFS_HA,Port 201 Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.byte 0x87++0x0
|
|
line.byte 0x0 "P201PFS_BY,Port 201 Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x88)++0x3
|
|
line.long 0x0 "P20$1PFS,Port 20%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x8A)++0x1
|
|
line.word 0x0 "P20$1PFS_HA,Port 20%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0x8B)++0x0
|
|
line.byte 0x0 "P20$1PFS_BY,Port 20%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xB0)++0x3
|
|
line.long 0x0 "P2$1PFS,Port 2%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0xB2)++0x1
|
|
line.word 0x0 "P2$1PFS_HA,Port 2%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 12.--13. "EOFR,Event on Falling/Event on Rising" "0: Don't care,1: Detect rising edge,?,?"
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
newline
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0xB3)++0x0
|
|
line.byte 0x0 "P2$1PFS_BY,Port 2%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
group.long 0xC0++0x3
|
|
line.long 0x0 "P300PFS,Port 300 Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.word 0xC2++0x1
|
|
line.word 0x0 "P300PFS_HA,Port 300 Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.byte 0xC3++0x0
|
|
line.byte 0x0 "P300PFS_BY,Port 300 Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0xC4)++0x3
|
|
line.long 0x0 "P30$1PFS,Port 30%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0xC6)++0x1
|
|
line.word 0x0 "P30$1PFS_HA,Port 30%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 7. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0xC7)++0x0
|
|
line.byte 0x0 "P30$1PFS_BY,Port 30%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 10. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x100)++0x3
|
|
line.long 0x0 "P40$1PFS,Port 40%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 10. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x102)++0x1
|
|
line.word 0x0 "P40$1PFS_HA,Port 40%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 10. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0x103)++0x0
|
|
line.byte 0x0 "P40$1PFS_BY,Port 40%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x128)++0x3
|
|
line.long 0x0 "P4$1PFS,Port 4%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x12A)++0x1
|
|
line.word 0x0 "P4$1PFS_HA,Port 4%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0x12B)++0x0
|
|
line.byte 0x0 "P4$1PFS_BY,Port 4%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x140)++0x3
|
|
line.long 0x0 "P50$1PFS,Port 50%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x142)++0x1
|
|
line.word 0x0 "P50$1PFS_HA,Port 50%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 6. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0x143)++0x0
|
|
line.byte 0x0 "P50$1PFS_BY,Port 50%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x180)++0x3
|
|
line.long 0x0 "P60$1PFS,Port 60%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x182)++0x1
|
|
line.word 0x0 "P60$1PFS_HA,Port 60%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0x183)++0x0
|
|
line.byte 0x0 "P60$1PFS_BY,Port 60%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x1A0)++0x3
|
|
line.long 0x0 "P60$1PFS,Port 60%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x1A2)++0x1
|
|
line.word 0x0 "P60$1PFS_HA,Port 60%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0x1A3)++0x0
|
|
line.byte 0x0 "P60$1PFS_BY,Port 60%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
group.long 0x1A8++0x3
|
|
line.long 0x0 "P610PFS,Port 610 Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.word 0x1AA++0x1
|
|
line.word 0x0 "P610PFS_HA,Port 610 Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.byte 0x1AB++0x0
|
|
line.byte 0x0 "P610PFS_BY,Port 610 Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.long 0x1E0++0x3
|
|
line.long 0x0 "P708PFS,Port 708 Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.word 0x1E2++0x1
|
|
line.word 0x0 "P708PFS_HA,Port 708 Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.byte 0x1E3++0x0
|
|
line.byte 0x0 "P708PFS_BY,Port 708 Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.long 0x1F8++0x3
|
|
line.long 0x0 "P714PFS,Port 714 Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.word 0x1FA++0x1
|
|
line.word 0x0 "P714PFS_HA,Port 714 Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
group.byte 0x1FB++0x0
|
|
line.byte 0x0 "P714PFS_BY,Port 714 Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.long ($2+0x220)++0x3
|
|
line.long 0x0 "P80$1PFS,Port 80%s Pin Function Select Register"
|
|
hexmask.long.byte 0x0 24.--28. 1. "PSEL,Peripheral Select"
|
|
bitfld.long 0x0 16. "PMR,Port Mode Control" "0: Use as general I/O pin,1: Use as I/O port for peripheral functions"
|
|
newline
|
|
bitfld.long 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.long 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.long 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.long 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.long 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.long 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.word ($2+0x222)++0x1
|
|
line.word 0x0 "P80$1PFS_HA,Port 80%s Pin Function Select Register"
|
|
bitfld.word 0x0 15. "ASEL,Analog Input Enable" "0: Do not use as analog pin,1: Use as analog pin"
|
|
bitfld.word 0x0 14. "ISEL,IRQ Input Enable" "0: Do not use as IRQn input pin,1: Use as IRQn input pin"
|
|
newline
|
|
bitfld.word 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.word 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.word 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.word 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x4)
|
|
group.byte ($2+0x223)++0x0
|
|
line.byte 0x0 "P80$1PFS_BY,Port 80%s Pin Function Select Register"
|
|
bitfld.byte 0x0 6. "NCODR,N-Channel Open-Drain Control" "0: Output CMOS,1: Output NMOS open-drain"
|
|
bitfld.byte 0x0 4. "PCR,Pull-up Control" "0: Disable input pull-up,1: Enable input pull-up"
|
|
newline
|
|
bitfld.byte 0x0 2. "PDR,Port Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rbitfld.byte 0x0 1. "PIDR,Port State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.byte 0x0 0. "PODR,Port Output Data" "0: Output low,1: Output high"
|
|
repeat.end
|
|
group.byte 0x503++0x0
|
|
line.byte 0x0 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x0 7. "B0WI,PFSWE Bit Write Disable" "0: Writing to the PFSWE bit is enabled,1: Writing to the PFSWE bit is disabled"
|
|
bitfld.byte 0x0 6. "PFSWE,PmnPFS Register Write Enable" "0: Writing to the PmnPFS register is disabled,1: Writing to the PmnPFS register is enabled"
|
|
group.byte 0x50F++0x0
|
|
line.byte 0x0 "PRWCNTR,Port Read Wait Control Register"
|
|
bitfld.byte 0x0 0.--1. "WAIT,Wait Cycle Control" "0: Setting prohibited,1: Insert a 1-cycle wait,?,?"
|
|
tree.end
|
|
tree "POEG (Port Output Enable Module for GPT)"
|
|
base ad:0x40042000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "POEGGA,POEG Group A Setting Register"
|
|
bitfld.long 0x0 30.--31. "NFCS,Noise Filter Clock Select" "0: Sample GTETRGn pin input level three times every..,1: Sample GTETRGn pin input level three times every..,?,?"
|
|
bitfld.long 0x0 29. "NFEN,Noise Filter Enable" "0: Disable noise filtering,1: Enable noise filtering"
|
|
newline
|
|
bitfld.long 0x0 28. "INV,GTETRGn Input Reverse" "0: Input GTETRGn as-is,1: Input GTETRGn in reverse"
|
|
rbitfld.long 0x0 16. "ST,GTETRGn Input Status Flag" "0: GTETRGn input after filtering was 0,1: GTETRGn input after filtering was 1"
|
|
newline
|
|
bitfld.long 0x0 6. "OSTPE,Oscillation Stop Detection Enable" "0: Disable output-disable requests from oscillation..,1: Enable output-disable requests from oscillation.."
|
|
bitfld.long 0x0 5. "IOCE,Enable for GPT Output-Disable Request" "0: Disable output-disable requests from GPT,1: Enable output-disable requests from GPT"
|
|
newline
|
|
bitfld.long 0x0 4. "PIDE,Port Input Detection Enable" "0: Disable output-disable requests from the GTETRGn..,1: Enable output-disable requests from the GTETRGn.."
|
|
bitfld.long 0x0 3. "SSF,Software Stop Flag" "0: No output-disable request from software occurred,1: Output-disable request from software occurred"
|
|
newline
|
|
bitfld.long 0x0 2. "OSTPF,Oscillation Stop Detection Flag" "0: No output-disable request from oscillation stop..,1: Output-disable request from oscillation stop.."
|
|
bitfld.long 0x0 1. "IOCF,Detection Flag for GPT Output-Disable Request" "0: No output-disable request from GPT occurred.,1: Output-disable request from GPT occurred."
|
|
newline
|
|
bitfld.long 0x0 0. "PIDF,Port Input Detection Flag" "0: No output-disable request from the GTETRGn pin..,1: Output-disable request from the GTETRGn pin.."
|
|
group.long 0x100++0x3
|
|
line.long 0x0 "POEGGB,POEG Group B Setting Register"
|
|
bitfld.long 0x0 30.--31. "NFCS,Noise Filter Clock Select" "0: Sample GTETRGn pin input level three times every..,1: Sample GTETRGn pin input level three times every..,?,?"
|
|
bitfld.long 0x0 29. "NFEN,Noise Filter Enable" "0: Disable noise filtering,1: Enable noise filtering"
|
|
newline
|
|
bitfld.long 0x0 28. "INV,GTETRGn Input Reverse" "0: Input GTETRGn as-is,1: Input GTETRGn in reverse"
|
|
rbitfld.long 0x0 16. "ST,GTETRGn Input Status Flag" "0: GTETRGn input after filtering was 0,1: GTETRGn input after filtering was 1"
|
|
newline
|
|
bitfld.long 0x0 6. "OSTPE,Oscillation Stop Detection Enable" "0: Disable output-disable requests from oscillation..,1: Enable output-disable requests from oscillation.."
|
|
bitfld.long 0x0 5. "IOCE,Enable for GPT Output-Disable Request" "0: Disable output-disable requests from GPT,1: Enable output-disable requests from GPT"
|
|
newline
|
|
bitfld.long 0x0 4. "PIDE,Port Input Detection Enable" "0: Disable output-disable requests from the GTETRGn..,1: Enable output-disable requests from the GTETRGn.."
|
|
bitfld.long 0x0 3. "SSF,Software Stop Flag" "0: No output-disable request from software occurred,1: Output-disable request from software occurred"
|
|
newline
|
|
bitfld.long 0x0 2. "OSTPF,Oscillation Stop Detection Flag" "0: No output-disable request from oscillation stop..,1: Output-disable request from oscillation stop.."
|
|
bitfld.long 0x0 1. "IOCF,Detection Flag for GPT Output-Disable Request" "0: No output-disable request from GPT occurred.,1: Output-disable request from GPT occurred."
|
|
newline
|
|
bitfld.long 0x0 0. "PIDF,Port Input Detection Flag" "0: No output-disable request from the GTETRGn pin..,1: Output-disable request from the GTETRGn pin.."
|
|
tree.end
|
|
tree "PORT (Port Control Registers)"
|
|
tree "PORT0"
|
|
base ad:0x40040000
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "PODR,Port Control Register 1"
|
|
bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
line.word 0x2 "PDR,Port Control Register 1"
|
|
bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
rgroup.word 0x6++0x1
|
|
line.word 0x0 "PIDR,Port Control Register 2"
|
|
bitfld.word 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
wgroup.word 0x8++0x3
|
|
line.word 0x0 "PORR,Port Control Register 3"
|
|
bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
line.word 0x2 "POSR,Port Control Register 3"
|
|
bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
tree.end
|
|
tree "PORT1"
|
|
base ad:0x40040020
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "PODR,Port Control Register 1"
|
|
bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
line.word 0x2 "PDR,Port Control Register 1"
|
|
bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x0 31. "EIDR15,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 30. "EIDR14,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 29. "EIDR13,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.long 0x0 28. "EIDR12,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 27. "EIDR11,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 26. "EIDR10,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.long 0x0 25. "EIDR09,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 24. "EIDR08,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 23. "EIDR07,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.long 0x0 22. "EIDR06,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 21. "EIDR05,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 20. "EIDR04,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.long 0x0 19. "EIDR03,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 18. "EIDR02,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 17. "EIDR01,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.long 0x0 16. "EIDR00,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
rgroup.word 0x4++0x3
|
|
line.word 0x0 "EIDR,Port Control Register 2"
|
|
bitfld.word 0x0 15. "EIDR15,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 14. "EIDR14,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 13. "EIDR13,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.word 0x0 12. "EIDR12,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 11. "EIDR11,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 10. "EIDR10,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.word 0x0 9. "EIDR09,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 8. "EIDR08,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 7. "EIDR07,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.word 0x0 6. "EIDR06,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 5. "EIDR05,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 4. "EIDR04,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.word 0x0 3. "EIDR03,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 2. "EIDR02,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 1. "EIDR01,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.word 0x0 0. "EIDR00,Port Event Input Data" "0: Low input,1: High input"
|
|
line.word 0x2 "PIDR,Port Control Register 2"
|
|
bitfld.word 0x2 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x2 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x2 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x2 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x2 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x2 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
wgroup.word 0x8++0x3
|
|
line.word 0x0 "PORR,Port Control Register 3"
|
|
bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
line.word 0x2 "POSR,Port Control Register 3"
|
|
bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "PCNTR4,Port Control Register 4"
|
|
bitfld.long 0x0 31. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 30. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 29. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 28. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 27. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 26. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 25. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 24. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 23. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 22. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 21. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 20. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 19. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 18. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 17. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 16. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "EORR,Port Control Register 4"
|
|
bitfld.word 0x0 15. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 14. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 13. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 12. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 11. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 10. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 9. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 8. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 7. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 6. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 5. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 4. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 3. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 2. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 1. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 0. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
line.word 0x2 "EOSR,Port Control Register 4"
|
|
bitfld.word 0x2 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
tree.end
|
|
tree "PORT2"
|
|
base ad:0x40040040
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "PODR,Port Control Register 1"
|
|
bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
line.word 0x2 "PDR,Port Control Register 1"
|
|
bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x0 31. "EIDR15,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 30. "EIDR14,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 29. "EIDR13,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.long 0x0 28. "EIDR12,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 27. "EIDR11,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 26. "EIDR10,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.long 0x0 25. "EIDR09,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 24. "EIDR08,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 23. "EIDR07,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.long 0x0 22. "EIDR06,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 21. "EIDR05,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 20. "EIDR04,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.long 0x0 19. "EIDR03,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 18. "EIDR02,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 17. "EIDR01,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.long 0x0 16. "EIDR00,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
rgroup.word 0x4++0x3
|
|
line.word 0x0 "EIDR,Port Control Register 2"
|
|
bitfld.word 0x0 15. "EIDR15,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 14. "EIDR14,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 13. "EIDR13,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.word 0x0 12. "EIDR12,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 11. "EIDR11,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 10. "EIDR10,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.word 0x0 9. "EIDR09,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 8. "EIDR08,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 7. "EIDR07,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.word 0x0 6. "EIDR06,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 5. "EIDR05,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 4. "EIDR04,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.word 0x0 3. "EIDR03,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 2. "EIDR02,Port Event Input Data" "0: Low input,1: High input"
|
|
bitfld.word 0x0 1. "EIDR01,Port Event Input Data" "0: Low input,1: High input"
|
|
newline
|
|
bitfld.word 0x0 0. "EIDR00,Port Event Input Data" "0: Low input,1: High input"
|
|
line.word 0x2 "PIDR,Port Control Register 2"
|
|
bitfld.word 0x2 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x2 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x2 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x2 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x2 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x2 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x2 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
wgroup.word 0x8++0x3
|
|
line.word 0x0 "PORR,Port Control Register 3"
|
|
bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
line.word 0x2 "POSR,Port Control Register 3"
|
|
bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
group.long 0xC++0x3
|
|
line.long 0x0 "PCNTR4,Port Control Register 4"
|
|
bitfld.long 0x0 31. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 30. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 29. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 28. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 27. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 26. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 25. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 24. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 23. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 22. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 21. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 20. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 19. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 18. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 17. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 16. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
group.word 0xC++0x3
|
|
line.word 0x0 "EORR,Port Control Register 4"
|
|
bitfld.word 0x0 15. "EORR15,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 14. "EORR14,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 13. "EORR13,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 12. "EORR12,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 11. "EORR11,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 10. "EORR10,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 9. "EORR09,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 8. "EORR08,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 7. "EORR07,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 6. "EORR06,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 5. "EORR05,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 4. "EORR04,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 3. "EORR03,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 2. "EORR02,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 1. "EORR01,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 0. "EORR00,Pmn Event Output Reset" "0: No effect on output,1: Low output"
|
|
line.word 0x2 "EOSR,Port Control Register 4"
|
|
bitfld.word 0x2 15. "EOSR15,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 14. "EOSR14,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 13. "EOSR13,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 12. "EOSR12,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 11. "EOSR11,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 10. "EOSR10,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 9. "EOSR09,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 8. "EOSR08,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 7. "EOSR07,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 6. "EOSR06,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 5. "EOSR05,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 4. "EOSR04,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 3. "EOSR03,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 2. "EOSR02,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 1. "EOSR01,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 0. "EOSR00,Pmn Event Output Set" "0: No effect on output,1: High output"
|
|
tree.end
|
|
tree "PORT3"
|
|
base ad:0x40040060
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "PODR,Port Control Register 1"
|
|
bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
line.word 0x2 "PDR,Port Control Register 1"
|
|
bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
rgroup.word 0x6++0x1
|
|
line.word 0x0 "PIDR,Port Control Register 2"
|
|
bitfld.word 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
wgroup.word 0x8++0x3
|
|
line.word 0x0 "PORR,Port Control Register 3"
|
|
bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
line.word 0x2 "POSR,Port Control Register 3"
|
|
bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
tree.end
|
|
tree "PORT4"
|
|
base ad:0x40040080
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "PODR,Port Control Register 1"
|
|
bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
line.word 0x2 "PDR,Port Control Register 1"
|
|
bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
rgroup.word 0x6++0x1
|
|
line.word 0x0 "PIDR,Port Control Register 2"
|
|
bitfld.word 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
wgroup.word 0x8++0x3
|
|
line.word 0x0 "PORR,Port Control Register 3"
|
|
bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
line.word 0x2 "POSR,Port Control Register 3"
|
|
bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
tree.end
|
|
tree "PORT5"
|
|
base ad:0x400400A0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "PODR,Port Control Register 1"
|
|
bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
line.word 0x2 "PDR,Port Control Register 1"
|
|
bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
rgroup.word 0x6++0x1
|
|
line.word 0x0 "PIDR,Port Control Register 2"
|
|
bitfld.word 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
wgroup.word 0x8++0x3
|
|
line.word 0x0 "PORR,Port Control Register 3"
|
|
bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
line.word 0x2 "POSR,Port Control Register 3"
|
|
bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
tree.end
|
|
tree "PORT6"
|
|
base ad:0x400400C0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "PODR,Port Control Register 1"
|
|
bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
line.word 0x2 "PDR,Port Control Register 1"
|
|
bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
rgroup.word 0x6++0x1
|
|
line.word 0x0 "PIDR,Port Control Register 2"
|
|
bitfld.word 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
wgroup.word 0x8++0x3
|
|
line.word 0x0 "PORR,Port Control Register 3"
|
|
bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
line.word 0x2 "POSR,Port Control Register 3"
|
|
bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
tree.end
|
|
tree "PORT7"
|
|
base ad:0x400400E0
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "PODR,Port Control Register 1"
|
|
bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
line.word 0x2 "PDR,Port Control Register 1"
|
|
bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
rgroup.word 0x6++0x1
|
|
line.word 0x0 "PIDR,Port Control Register 2"
|
|
bitfld.word 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
wgroup.word 0x8++0x3
|
|
line.word 0x0 "PORR,Port Control Register 3"
|
|
bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
line.word 0x2 "POSR,Port Control Register 3"
|
|
bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
tree.end
|
|
tree "PORT8"
|
|
base ad:0x40040100
|
|
group.long 0x0++0x3
|
|
line.long 0x0 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x0 31. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 30. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 29. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 28. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 27. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 26. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 25. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 24. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 23. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 22. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 21. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 20. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 19. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 18. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 17. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 16. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.long 0x0 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.long 0x0 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.long 0x0 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
group.word 0x0++0x3
|
|
line.word 0x0 "PODR,Port Control Register 1"
|
|
bitfld.word 0x0 15. "PODR15,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 14. "PODR14,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 13. "PODR13,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 12. "PODR12,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 11. "PODR11,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 10. "PODR10,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 9. "PODR09,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 8. "PODR08,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 7. "PODR07,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 6. "PODR06,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 5. "PODR05,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 4. "PODR04,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 3. "PODR03,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 2. "PODR02,Pmn Output Data" "0: Low output,1: High output"
|
|
bitfld.word 0x0 1. "PODR01,Pmn Output Data" "0: Low output,1: High output"
|
|
newline
|
|
bitfld.word 0x0 0. "PODR00,Pmn Output Data" "0: Low output,1: High output"
|
|
line.word 0x2 "PDR,Port Control Register 1"
|
|
bitfld.word 0x2 15. "PDR15,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 14. "PDR14,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 13. "PDR13,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 12. "PDR12,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 11. "PDR11,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 10. "PDR10,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 9. "PDR09,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 8. "PDR08,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 7. "PDR07,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 6. "PDR06,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 5. "PDR05,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 4. "PDR04,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 3. "PDR03,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 2. "PDR02,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
bitfld.word 0x2 1. "PDR01,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
newline
|
|
bitfld.word 0x2 0. "PDR00,Pmn Direction" "0: Input (functions as an input pin),1: Output (functions as an output pin)"
|
|
rgroup.long 0x4++0x3
|
|
line.long 0x0 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.long 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.long 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
rgroup.word 0x6++0x1
|
|
line.word 0x0 "PIDR,Port Control Register 2"
|
|
bitfld.word 0x0 15. "PIDR15,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 14. "PIDR14,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 13. "PIDR13,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 12. "PIDR12,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 11. "PIDR11,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 10. "PIDR10,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 9. "PIDR09,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 8. "PIDR08,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 7. "PIDR07,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 6. "PIDR06,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 5. "PIDR05,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 4. "PIDR04,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 3. "PIDR03,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 2. "PIDR02,Pmn State" "0: Low level,1: High level"
|
|
bitfld.word 0x0 1. "PIDR01,Pmn State" "0: Low level,1: High level"
|
|
newline
|
|
bitfld.word 0x0 0. "PIDR00,Pmn State" "0: Low level,1: High level"
|
|
wgroup.long 0x8++0x3
|
|
line.long 0x0 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x0 31. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 30. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 29. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 28. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 27. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 26. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 25. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 24. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 23. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 22. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 21. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 20. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 19. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 18. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 17. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.long 0x0 16. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.long 0x0 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.long 0x0 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.long 0x0 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
wgroup.word 0x8++0x3
|
|
line.word 0x0 "PORR,Port Control Register 3"
|
|
bitfld.word 0x0 15. "PORR15,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 14. "PORR14,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 13. "PORR13,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 12. "PORR12,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 11. "PORR11,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 10. "PORR10,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 9. "PORR09,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 8. "PORR08,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 7. "PORR07,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 6. "PORR06,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 5. "PORR05,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 4. "PORR04,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 3. "PORR03,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 2. "PORR02,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
bitfld.word 0x0 1. "PORR01,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
newline
|
|
bitfld.word 0x0 0. "PORR00,Pmn Output Reset" "0: No effect on output,1: Low output"
|
|
line.word 0x2 "POSR,Port Control Register 3"
|
|
bitfld.word 0x2 15. "POSR15,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 14. "POSR14,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 13. "POSR13,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 12. "POSR12,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 11. "POSR11,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 10. "POSR10,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 9. "POSR09,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 8. "POSR08,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 7. "POSR07,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 6. "POSR06,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 5. "POSR05,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 4. "POSR04,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 3. "POSR03,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 2. "POSR02,Pmn Output Set" "0: No effect on output,1: High output"
|
|
bitfld.word 0x2 1. "POSR01,Pmn Output Set" "0: No effect on output,1: High output"
|
|
newline
|
|
bitfld.word 0x2 0. "POSR00,Pmn Output Set" "0: No effect on output,1: High output"
|
|
tree.end
|
|
tree.end
|
|
tree "RMPU (Renesas Memory Protection Unit)"
|
|
base ad:0x40000000
|
|
group.word 0x0++0x1
|
|
line.word 0x0 "MMPUCTLA,Bus Master MPU Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code"
|
|
bitfld.word 0x0 1. "OAD,Operation After Detection" "0: Non-maskable interrupt,1: Reset"
|
|
newline
|
|
bitfld.word 0x0 0. "ENABLE,Master Group Enable" "0: Master group A disabled,1: Master group A enabled"
|
|
group.word 0x102++0x1
|
|
line.word 0x0 "MMPUPTA,Group A Protection of Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code"
|
|
bitfld.word 0x0 0. "PROTECT,Protection of Register" "0: All bus master MPU group A register writes are..,1: All bus master MPU group A register writes are.."
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.word ($2+0x200)++0x1
|
|
line.word 0x0 "MMPUACA$1,Group A Region %s access control register"
|
|
bitfld.word 0x0 2. "WP,Write Protection" "0: Write permission,1: Write protection"
|
|
bitfld.word 0x0 1. "RP,Read Protection" "0: Read permission,1: Read protection"
|
|
newline
|
|
bitfld.word 0x0 0. "ENABLE,Region Enable" "0: Group A region n disabled,1: Group A region n enabled"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.long ($2+0x204)++0x3
|
|
line.long 0x0 "MMPUSA$1,Group A Region %s Start Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "MMPUSA,Region Start Address"
|
|
repeat.end
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x10)
|
|
group.long ($2+0x208)++0x3
|
|
line.long 0x0 "MMPUEA$1,Group A Region %s End Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "MMPUEA,Region End Address"
|
|
repeat.end
|
|
group.word 0xC00++0x1
|
|
line.word 0x0 "SMPUCTL,Slave MPU Control Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code"
|
|
bitfld.word 0x0 1. "PROTECT,Protection of Register" "0: All bus slave register writes are permitted,1: All bus slave register writes are protected."
|
|
newline
|
|
bitfld.word 0x0 0. "OAD,Operation After Detection" "0: Non-maskable interrupt,1: Reset"
|
|
group.word 0xC10++0x1
|
|
line.word 0x0 "SMPUMBIU,Access Control Register for Memory Bus 1"
|
|
bitfld.word 0x0 3. "WPGRPA,Master MPU Group A Write Protection" "0: Memory protection write for master MPU group A..,1: Memory protection write for master MPU group A.."
|
|
bitfld.word 0x0 2. "RPGRPA,Master MPU Group A Read Protection" "0: Memory protection read for master MPU group A..,1: Memory protection read for master MPU group A.."
|
|
group.word 0xC14++0x1
|
|
line.word 0x0 "SMPUFBIU,Access Control Register for Internal Peripheral Bus 9"
|
|
bitfld.word 0x0 3. "WPGRPA,Master MPU Group A Write Protection" "0: Memory protection for master MPU group A write..,1: Memory protection for master MPU group A write.."
|
|
bitfld.word 0x0 2. "RPGRPA,Master MPU Group A Read Protection" "0: Memory protection for master MPU group A read..,1: Memory protection for master MPU group A read.."
|
|
newline
|
|
bitfld.word 0x0 1. "WPCPU,CPU Write Protection" "0: Memory protection for CPU write disabled,1: Memory protection for CPU write enabled"
|
|
bitfld.word 0x0 0. "RPCPU,CPU Read Protection" "0: Memory protection for CPU read disabled,1: Memory protection for CPU read enabled"
|
|
group.word 0xC18++0x1
|
|
line.word 0x0 "SMPUSRAM0,Access Control Register for Memory Bus 4"
|
|
bitfld.word 0x0 3. "WPGRPA,Master MPU Group A Write Protection" "0: Memory protection for master MPU group A write..,1: Memory protection for master MPU group A write.."
|
|
bitfld.word 0x0 2. "RPGRPA,Master MPU Group A Read Protection" "0: Memory protection for master MPU group A read..,1: Memory protection for master MPU group A read.."
|
|
newline
|
|
bitfld.word 0x0 1. "WPCPU,CPU Write Protection" "0: Memory protection for CPU write disabled,1: Memory protection for CPU write enabled"
|
|
bitfld.word 0x0 0. "RPCPU,CPU Read Protection" "0: Memory protection for CPU read disabled,1: Memory protection for CPU read enabled"
|
|
group.word 0xC20++0x1
|
|
line.word 0x0 "SMPUP0BIU,Access Control Register for Internal Peripheral Bus 1"
|
|
bitfld.word 0x0 3. "WPGRPA,Master MPU Group A Write Protection" "0: Memory protection for master MPU group A write..,1: Memory protection for master MPU group A write.."
|
|
bitfld.word 0x0 2. "RPGRPA,Master MPU Group A Read Protection" "0: Memory protection for master MPU group A read..,1: Memory protection for master MPU group A read.."
|
|
newline
|
|
bitfld.word 0x0 1. "WPCPU,CPU Write Protection" "0: Memory protection for CPU write disabled,1: Memory protection for CPU write enabled"
|
|
bitfld.word 0x0 0. "RPCPU,CPU Read Protection" "0: Memory protection for CPU read disabled,1: Memory protection for CPU read enabled"
|
|
group.word 0xC24++0x1
|
|
line.word 0x0 "SMPUP2BIU,Access Control Register for Internal Peripheral Bus 3"
|
|
bitfld.word 0x0 3. "WPGRPA,Master MPU Group A Write Protection" "0: Memory protection for master MPU group A write..,1: Memory protection for master MPU group A write.."
|
|
bitfld.word 0x0 2. "RPGRPA,Master MPU Group A Read Protection" "0: Memory protection for master MPU group A read..,1: Memory protection for master MPU group A read.."
|
|
newline
|
|
bitfld.word 0x0 1. "WPCPU,CPU Write Protection" "0: Memory protection for CPU write disabled,1: Memory protection for CPU write enabled"
|
|
bitfld.word 0x0 0. "RPCPU,CPU Read Protection" "0: Memory protection for CPU read disabled,1: Memory protection for CPU read enabled"
|
|
group.word 0xC28++0x1
|
|
line.word 0x0 "SMPUP6BIU,Access Control Register for Internal Peripheral Bus 7"
|
|
bitfld.word 0x0 3. "WPGRPA,Master MPU Group A Write Protection" "0: Master MPU group A write of memory protection..,1: Master MPU group A write of memory protection.."
|
|
bitfld.word 0x0 2. "RPGRPA,Master MPU Group A Read Protection" "0: Master MPU group A read of memory protection..,1: Master MPU group A read of memory protection.."
|
|
newline
|
|
bitfld.word 0x0 1. "WPCPU,CPU Write Protection" "0: CPU write of memory protection disabled,1: CPU write of memory protection enabled"
|
|
bitfld.word 0x0 0. "RPCPU,CPU Read Protection" "0: CPU read of memory protection disabled,1: CPU read of memory protection enabled"
|
|
group.word 0xD00++0x1
|
|
line.word 0x0 "MSPMPUOAD,Stack Pointer Monitor Operation After Detection Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code"
|
|
bitfld.word 0x0 0. "OAD,Operation after Detection" "0: Non-maskable interrupt,1: Reset"
|
|
group.word 0xD04++0x3
|
|
line.word 0x0 "MSPMPUCTL,Stack Pointer Monitor Access Control Register"
|
|
bitfld.word 0x0 8. "ERROR,Stack Pointer Monitor Error Flag" "0: Stack pointer has not overflowed or underflowed,1: Stack pointer has overflowed or underflowed"
|
|
bitfld.word 0x0 0. "ENABLE,Stack Pointer Monitor Enable" "0: Stack pointer monitor is disabled,1: Stack pointer monitor is enabled"
|
|
line.word 0x2 "MSPMPUPT,Stack Pointer Monitor Protection Register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "KEY,Key Code"
|
|
bitfld.word 0x2 0. "PROTECT,Protection of Register" "0: Stack pointer monitor register writes are..,1: Stack pointer monitor register writes are.."
|
|
group.long 0xD08++0x7
|
|
line.long 0x0 "MSPMPUSA,Main Stack Pointer (MSP) Monitor Start Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "MSPMPUSA,Region Start Address"
|
|
line.long 0x4 "MSPMPUEA,Main Stack Pointer (MSP) Monitor End Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "MSPMPUEA,Region End Address"
|
|
group.word 0xD10++0x1
|
|
line.word 0x0 "PSPMPUOAD,Stack Pointer Monitor Operation After Detection Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "KEY,Key Code"
|
|
bitfld.word 0x0 0. "OAD,Operation after Detection" "0: Non-maskable interrupt,1: Reset"
|
|
group.word 0xD14++0x3
|
|
line.word 0x0 "PSPMPUCTL,Stack Pointer Monitor Access Control Register"
|
|
bitfld.word 0x0 8. "ERROR,Stack Pointer Monitor Error Flag" "0: Stack pointer has not overflowed or underflowed,1: Stack pointer has overflowed or underflowed"
|
|
bitfld.word 0x0 0. "ENABLE,Stack Pointer Monitor Enable" "0: Stack pointer monitor is disabled,1: Stack pointer monitor is enabled"
|
|
line.word 0x2 "PSPMPUPT,Stack Pointer Monitor Protection Register"
|
|
hexmask.word.byte 0x2 8.--15. 1. "KEY,Key Code"
|
|
bitfld.word 0x2 0. "PROTECT,Protection of Register" "0: Stack pointer monitor register writes are..,1: Stack pointer monitor register writes are.."
|
|
group.long 0xD18++0x7
|
|
line.long 0x0 "PSPMPUSA,Process Stack Pointer (PSP) Monitor Start Address Register"
|
|
hexmask.long 0x0 0.--31. 1. "PSPMPUSA,Region Start Address"
|
|
line.long 0x4 "PSPMPUEA,Process Stack Pointer (PSP) Monitor End Address Register"
|
|
hexmask.long 0x4 0.--31. 1. "PSPMPUEA,Region End Address"
|
|
tree.end
|
|
tree "RTC (Realtime Clock)"
|
|
base ad:0x40044000
|
|
rgroup.byte 0x0++0x0
|
|
line.byte 0x0 "R64CNT,64-Hz Counter"
|
|
bitfld.byte 0x0 7. "R64OVF," "0,1"
|
|
bitfld.byte 0x0 6. "F1HZ,1-Hz Flag" "?,1: Hz Flag"
|
|
newline
|
|
bitfld.byte 0x0 5. "F2HZ,2-Hz Flag" "0,1"
|
|
bitfld.byte 0x0 4. "F4HZ,4-Hz Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 3. "F8HZ,8-Hz Flag" "0,1"
|
|
bitfld.byte 0x0 2. "F16HZ,16-Hz Flag" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 1. "F32HZ,32-Hz Flag" "0,1"
|
|
bitfld.byte 0x0 0. "F64HZ,64-Hz Flag" "0,1"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.byte ($2+0x2)++0x0
|
|
line.byte 0x0 "BCNT$1,Binary Counter %s"
|
|
hexmask.byte 0x0 0.--7. 1. "BCNT,Binary Counter"
|
|
repeat.end
|
|
group.byte 0x2++0x0
|
|
line.byte 0x0 "RSECCNT,Second Counter (in Calendar Count Mode)"
|
|
bitfld.byte 0x0 4.--6. "SEC10,10-Second Count" "0,1,2,3,4,5,6,7"
|
|
hexmask.byte 0x0 0.--3. 1. "SEC1,1-Second Count"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "RMINCNT,Minute Counter (in Calendar Count Mode)"
|
|
bitfld.byte 0x0 4.--6. "MIN10,10-Minute Count" "0,1,2,3,4,5,6,7"
|
|
hexmask.byte 0x0 0.--3. 1. "MIN1,1-Minute Count"
|
|
group.byte 0x6++0x0
|
|
line.byte 0x0 "RHRCNT,Hour Counter (in Calendar Count Mode)"
|
|
bitfld.byte 0x0 6. "PM,AM/PM select for time counter setting." "0: AM,1: PM"
|
|
bitfld.byte 0x0 4.--5. "HR10,10-Hour Count" "0,1,2,3"
|
|
newline
|
|
hexmask.byte 0x0 0.--3. 1. "HR1,1-Hour Count"
|
|
group.byte 0x8++0x0
|
|
line.byte 0x0 "RWKCNT,Day-of-Week Counter (in Calendar Count Mode)"
|
|
bitfld.byte 0x0 0.--2. "DAYW,Day-of-Week Counting" "0: Sunday,1: Monday,?,?,?,?,?,?"
|
|
group.byte 0xA++0x0
|
|
line.byte 0x0 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x0 4.--5. "DATE10,10-Day Count" "0,1,2,3"
|
|
hexmask.byte 0x0 0.--3. 1. "DATE1,1-Day Count"
|
|
group.byte 0xC++0x0
|
|
line.byte 0x0 "RMONCNT,Month Counter"
|
|
bitfld.byte 0x0 4. "MON10,10-Month Count" "0,1"
|
|
hexmask.byte 0x0 0.--3. 1. "MON1,1-Month Count"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "RYRCNT,Year Counter"
|
|
hexmask.word.byte 0x0 4.--7. 1. "YR10,10-Year Count"
|
|
hexmask.word.byte 0x0 0.--3. 1. "YR1,1-Year Count"
|
|
repeat 4. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.byte ($2+0x10)++0x0
|
|
line.byte 0x0 "BCNT$1AR,Binary Counter %s Alarm Register"
|
|
hexmask.byte 0x0 0.--7. 1. "BCNTAR,Alarm register associated with the 32-bit binary counter"
|
|
repeat.end
|
|
group.byte 0x10++0x0
|
|
line.byte 0x0 "RSECAR,Second Alarm Register (in Calendar Count Mode)"
|
|
bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RSECCNT..,1: Compare register value with RSECCNT counter value"
|
|
bitfld.byte 0x0 4.--6. "SEC10,10 Seconds" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.byte 0x0 0.--3. 1. "SEC1,1 Second"
|
|
group.byte 0x12++0x0
|
|
line.byte 0x0 "RMINAR,Minute Alarm Register (in Calendar Count Mode)"
|
|
bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RMINCNT..,1: Compare register value with RMINCNT counter value"
|
|
bitfld.byte 0x0 4.--6. "MIN10,10 Minutes" "0,1,2,3,4,5,6,7"
|
|
newline
|
|
hexmask.byte 0x0 0.--3. 1. "MIN1,1 Minute"
|
|
group.byte 0x14++0x0
|
|
line.byte 0x0 "RHRAR,Hour Alarm Register (in Calendar Count Mode)"
|
|
bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RHRCNT..,1: Compare register value with RHRCNT counter value"
|
|
bitfld.byte 0x0 6. "PM,AM/PM select for alarm setting." "0: AM,1: PM"
|
|
newline
|
|
bitfld.byte 0x0 4.--5. "HR10,10 Hours" "0,1,2,3"
|
|
hexmask.byte 0x0 0.--3. 1. "HR1,1 Hour"
|
|
group.byte 0x16++0x0
|
|
line.byte 0x0 "RWKAR,Day-of-Week Alarm Register (in Calendar Count Mode)"
|
|
bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RWKCNT..,1: Compare register value with RWKCNT counter value"
|
|
bitfld.byte 0x0 0.--2. "DAYW,Day-of-Week Setting" "0: Sunday,1: Monday,?,?,?,?,?,?"
|
|
repeat 2. (increment 0x0 0x1)(increment 0x0 0x2)
|
|
group.byte ($2+0x18)++0x0
|
|
line.byte 0x0 "BCNT$1AER,Binary Counter %s Alarm Enable Register"
|
|
hexmask.byte 0x0 0.--7. 1. "ENB,Setting the alarm enable associated with the 32-bit binary counter"
|
|
repeat.end
|
|
group.byte 0x18++0x0
|
|
line.byte 0x0 "RDAYAR,Date Alarm Register (in Calendar Count Mode)"
|
|
bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RDAYCNT..,1: Compare register value with RDAYCNT counter value"
|
|
bitfld.byte 0x0 4.--5. "DATE10,10 Days" "0,1,2,3"
|
|
newline
|
|
hexmask.byte 0x0 0.--3. 1. "DATE1,1 Day"
|
|
group.byte 0x1A++0x0
|
|
line.byte 0x0 "RMONAR,Month Alarm Register (in Calendar Count Mode)"
|
|
bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with RMONCNT..,1: Compare register value with RMONCNT counter value"
|
|
bitfld.byte 0x0 4. "MON10,10 Months" "0,1"
|
|
newline
|
|
hexmask.byte 0x0 0.--3. 1. "MON1,1 Month"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "BCNT2AER,Binary Counter 2 Alarm Enable Register"
|
|
hexmask.word.byte 0x0 0.--7. 1. "ENB,Setting the alarm enable associated with the 32-bit binary counter"
|
|
group.word 0x1C++0x1
|
|
line.word 0x0 "RYRAR,Year Alarm Register (in Calendar Count Mode)"
|
|
hexmask.word.byte 0x0 4.--7. 1. "YR10,10 Years"
|
|
hexmask.word.byte 0x0 0.--3. 1. "YR1,1 Year"
|
|
group.byte 0x1E++0x0
|
|
line.byte 0x0 "BCNT3AER,Binary Counter 3 Alarm Enable Register"
|
|
hexmask.byte 0x0 0.--7. 1. "ENB,Setting the alarm enable associated with the 32-bit binary counter"
|
|
group.byte 0x1E++0x0
|
|
line.byte 0x0 "RYRAREN,Year Alarm Enable Register (in Calendar Count Mode)"
|
|
bitfld.byte 0x0 7. "ENB,ENB" "0: Do not compare register value with the RYRCNT..,1: Compare register value with the RYRCNT counter.."
|
|
group.byte 0x22++0x0
|
|
line.byte 0x0 "RCR1,RTC Control Register 1"
|
|
hexmask.byte 0x0 4.--7. 1. "PES,Periodic Interrupt Select"
|
|
bitfld.byte 0x0 3. "RTCOS,RTCOUT Output Select" "0: Outputs 1 Hz on RTCOUT,1: Outputs 64 Hz RTCOUT"
|
|
newline
|
|
bitfld.byte 0x0 2. "PIE,Periodic Interrupt Enable" "0: Disable periodic interrupt requests,1: Enable periodic interrupt requests"
|
|
bitfld.byte 0x0 1. "CIE,Carry Interrupt Enable" "0: Disable carry interrupt requests,1: Enable carry interrupt requests"
|
|
newline
|
|
bitfld.byte 0x0 0. "AIE,Alarm Interrupt Enable" "0: Disable alarm interrupt requests,1: Enable alarm interrupt requests"
|
|
group.byte 0x24++0x0
|
|
line.byte 0x0 "RCR2,RTC Control Register 2 (in Calendar Count Mode)"
|
|
bitfld.byte 0x0 7. "CNTMD,Count Mode Select" "0: Calendar count mode,1: Binary count mode"
|
|
bitfld.byte 0x0 6. "HR24,Hours Mode" "0: Operate RTC in 12-hour mode,1: Operate RTC in 24-hour mode"
|
|
newline
|
|
bitfld.byte 0x0 5. "AADJP,Automatic Adjustment Period Select" "0: In normal operation mode adjust RADJ.ADJ[5:0]..,1: In normal operation mode adjust RADJ.ADJ[5:0].."
|
|
bitfld.byte 0x0 4. "AADJE,Automatic Adjustment Enable" "0: Disable automatic adjustment,1: Enable automatic adjustment"
|
|
newline
|
|
bitfld.byte 0x0 3. "RTCOE,RTCOUT Output Enable" "0: Disable RTCOUT output,1: Enable RTCOUT output"
|
|
bitfld.byte 0x0 2. "ADJ30,30-Second Adjustment" "0: In writing: Invalid (writing 0 has no effect).,1: In writing: Execute 30-second adjustment. In.."
|
|
newline
|
|
bitfld.byte 0x0 1. "RESET,RTC Software Reset" "0: In writing: Invalid (writing 0 has no effect).,1: In writing: Initialize the prescaler and target.."
|
|
bitfld.byte 0x0 0. "START,Start" "0: Stop prescaler and time counter,1: Operate prescaler and time counter normally"
|
|
group.byte 0x24++0x0
|
|
line.byte 0x0 "RCR2_BCNT,RTC Control Register 2 (in Binary Count Mode)"
|
|
bitfld.byte 0x0 7. "CNTMD,Count Mode Select" "0: Calendar count mode,1: Binary count mode"
|
|
bitfld.byte 0x0 5. "AADJP,Automatic Adjustment Period Select" "0: In normal operation mode add or subtract the..,1: In normal operation mode add or subtract the.."
|
|
newline
|
|
bitfld.byte 0x0 4. "AADJE,Automatic Adjustment Enable" "0: Disable automatic adjustment,1: Enable automatic adjustment"
|
|
bitfld.byte 0x0 3. "RTCOE,RTCOUT Output Enable" "0: Disable RTCOUT output,1: Enable RTCOUT output"
|
|
newline
|
|
bitfld.byte 0x0 1. "RESET,RTC Software Reset" "0: In writing: Invalid (writing 0 has no effect).,1: In writing: Initialize the prescaler and target.."
|
|
bitfld.byte 0x0 0. "START,Start" "0: Stop the 32-bit binary counter 64-Hz counter and..,1: Operate the 32-bit binary counter 64-Hz counter.."
|
|
group.byte 0x28++0x0
|
|
line.byte 0x0 "RCR4,RTC Control Register 4"
|
|
bitfld.byte 0x0 7. "ROPSEL,RTC Operation Mode Select" "0: Normal operation mode is selected.,1: Low-consumption clock mode is selected."
|
|
bitfld.byte 0x0 0. "RCKSEL,Count Source Select in normal operation mode" "0: Sub-clock oscillator is selected,1: LOCO is selected"
|
|
group.word 0x2A++0x3
|
|
line.word 0x0 "RFRH,Frequency Register H"
|
|
bitfld.word 0x0 0. "RFC16,Write 0 before writing to the RFRL register after a cold start." "0,1"
|
|
line.word 0x2 "RFRL,Frequency Register L"
|
|
hexmask.word 0x2 0.--15. 1. "RFC,Frequency Comparison Value"
|
|
group.byte 0x2E++0x0
|
|
line.byte 0x0 "RADJ,Time Error Adjustment Register"
|
|
bitfld.byte 0x0 6.--7. "PMADJ,Plus-Minus" "0: Do not perform adjustment.,1: In normal operation mode adjustment is performed..,?,?"
|
|
hexmask.byte 0x0 0.--5. 1. "ADJ,Adjustment Value"
|
|
tree.end
|
|
tree "SCI (Serial Communication Interface)"
|
|
tree "SCI0"
|
|
base ad:0x40070000
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "SMR,Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"
|
|
bitfld.byte 0x0 7. "CM,Communication Mode" "0: Asynchronous mode or simple IIC mode,1: Clock synchronous mode or simple SPI mode"
|
|
bitfld.byte 0x0 6. "CHR,Character Length" "0: SCMR.CHR1 = 0: Transmit/receive in 9-bit data..,1: SCMR.CHR1 = 0: Transmit/receive in 9-bit data.."
|
|
newline
|
|
bitfld.byte 0x0 5. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.."
|
|
bitfld.byte 0x0 4. "PM,Parity Mode" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.byte 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit,1: 2 stop bits"
|
|
bitfld.byte 0x0 2. "MP,Multi-Processor Mode" "0: Disable multi-processor communications function,1: Enable multi-processor communications function"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock (n = 0),1: PCLK/4 clock (n = 1),?,?"
|
|
group.byte 0x0++0x2
|
|
line.byte 0x0 "SMR_SMCI,Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "GM,GSM Mode" "0: Normal mode operation,1: GSM mode operation"
|
|
bitfld.byte 0x0 6. "BLK,Block Transfer Mode" "0: Normal mode operation,1: Block transfer mode operation"
|
|
newline
|
|
bitfld.byte 0x0 5. "PE,Parity Enable" "0,1"
|
|
bitfld.byte 0x0 4. "PM,Parity Mode" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.byte 0x0 2.--3. "BCP,Base Clock Pulse" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock (n = 0),1: PCLK/4 clock (n = 1),?,?"
|
|
line.byte 0x1 "BRR,Bit Rate Register"
|
|
line.byte 0x2 "SCR,Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"
|
|
bitfld.byte 0x2 7. "TIE,Transmit Interrupt Enable" "0: Disable SCIn_TXI interrupt requests,1: Enable SCIn_TXI interrupt requests"
|
|
bitfld.byte 0x2 6. "RIE,Receive Interrupt Enable" "0: Disable SCIn_RXI and SCIn_ERI interrupt requests,1: Enable SCIn_RXI and SCIn_ERI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x2 5. "TE,Transmit Enable" "0: Disable serial transmission,1: Enable serial transmission"
|
|
bitfld.byte 0x2 4. "RE,Receive Enable" "0: Disable serial reception,1: Enable serial reception"
|
|
newline
|
|
bitfld.byte 0x2 3. "MPIE,Multi-Processor Interrupt Enable" "0: Normal reception,1: When data with the multi-processor bit set to 0.."
|
|
bitfld.byte 0x2 2. "TEIE,Transmit End Interrupt Enable" "0: Disable SCIn_TEI interrupt requests,1: Enable SCIn_TEI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x2 0.--1. "CKE,Clock Enable" "0: In asynchronous mode input a clock with a..,1: In asynchronous mode a clock with the same..,?,?"
|
|
group.byte 0x2++0x2
|
|
line.byte 0x0 "SCR_SMCI,Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "TIE,Transmit Interrupt Enable" "0: Disable SCIn_TXI interrupt requests,1: Enable SCIn_TXI interrupt requests"
|
|
bitfld.byte 0x0 6. "RIE,Receive Interrupt Enable" "0: Disable SCIn_RXI and SCIn_ERI interrupt requests,1: Enable SCIn_RXI and SCIn_ERI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x0 5. "TE,Transmit Enable" "0: Disable serial transmission,1: Enable serial transmission"
|
|
bitfld.byte 0x0 4. "RE,Receive Enable" "0: Disable serial reception,1: Enable serial reception"
|
|
newline
|
|
bitfld.byte 0x0 3. "MPIE,Multi-Processor Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "TEIE,Transmit End Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "CKE,Clock Enable" "0: When SMR_SMCI.GM = 0: Disable output The SCKn..,1: When SMR_SMCI.GM = 0: Output clock When..,?,?"
|
|
line.byte 0x1 "TDR,Transmit Data Register"
|
|
line.byte 0x2 "SSR,Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0. FCR.FM = 0)"
|
|
bitfld.byte 0x2 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data in TDR register,1: No transmit data in TDR register"
|
|
bitfld.byte 0x2 6. "RDRF,Receive Data Full Flag" "0: No received data in RDR register,1: Received data in RDR register"
|
|
newline
|
|
bitfld.byte 0x2 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
bitfld.byte 0x2 4. "FER,Framing Error Flag" "0: No framing error occurred,1: Framing error occurred"
|
|
newline
|
|
bitfld.byte 0x2 3. "PER,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
rbitfld.byte 0x2 2. "TEND,Transmit End Flag" "0: A character is being transmitted,1: Character transfer is complete"
|
|
newline
|
|
rbitfld.byte 0x2 1. "MPB,Multi-Processor" "0: Data transmission cycle,1: ID transmission cycle"
|
|
bitfld.byte 0x2 0. "MPBT,Multi-Processor Bit Transfer" "0: Data transmission cycle,1: ID transmission cycle"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "SSR_FIFO,Serial Status Register for Non-Smart Card Interface and FIFO Mode (SCMR.SMIF = 0. FCR.FM = 1)"
|
|
bitfld.byte 0x0 7. "TDFE,Transmit FIFO Data Empty Flag" "0: The amount of transmit data written in FTDRHL..,1: The amount of transmit data written in FTDRHL is.."
|
|
bitfld.byte 0x0 6. "RDF,Receive FIFO Data Full Flag" "0: The amount of receive data written in FRDRHL is..,1: The amount of receive data written in FRDRHL is.."
|
|
newline
|
|
bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
bitfld.byte 0x0 4. "FER,Framing Error Flag" "0: No framing error occurred,1: Framing error occurred"
|
|
newline
|
|
bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
bitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted,1: Character transfer is complete"
|
|
newline
|
|
bitfld.byte 0x0 0. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: Next receive data is not received for a period.."
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "SSR_SMCI,Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data in TDR register,1: No transmit data in TDR register"
|
|
bitfld.byte 0x0 6. "RDRF,Receive Data Full Flag" "0: No received data in RDR register,1: Received data in RDR register"
|
|
newline
|
|
bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
bitfld.byte 0x0 4. "ERS,Error Signal Status Flag" "0: No low error signal response,1: Low error signal response occurred"
|
|
newline
|
|
bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
rbitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted,1: Character transfer is complete"
|
|
newline
|
|
rbitfld.byte 0x0 1. "MPB,Multi-Processor" "0,1"
|
|
bitfld.byte 0x0 0. "MPBT,Multi-Processor Bit Transfer" "0,1"
|
|
rgroup.byte 0x5++0x0
|
|
line.byte 0x0 "RDR,Receive Data Register"
|
|
group.byte 0x6++0x5
|
|
line.byte 0x0 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x0 7. "BCP2,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x0 4. "CHR1,Character Length 1" "0: SMR.CHR = 0: Transmit/receive in 9-bit data..,1: SMR.CHR = 0: Transmit/receive in 8-bit data.."
|
|
newline
|
|
bitfld.byte 0x0 3. "SDIR,Transmitted/Received Data Transfer Direction" "0: Transfer LSB-first,1: Transfer MSB-first"
|
|
bitfld.byte 0x0 2. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted as they are.,1: TDR register contents are inverted before.."
|
|
newline
|
|
bitfld.byte 0x0 0. "SMIF,Smart Card Interface Mode Select" "0: Non-smart card interface mode (asynchronous mode..,1: Smart card interface mode"
|
|
line.byte 0x1 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x1 7. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: Detect low level on RXDn pin as start bit,1: Detect falling edge of RXDn pin as start bit"
|
|
bitfld.byte 0x1 6. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Output clock from baud rate generator with..,1: Output clock from baud rate generator with.."
|
|
newline
|
|
bitfld.byte 0x1 5. "NFEN,Digital Noise Filter Function Enable" "0: In asynchronous mode: Disable noise cancellation..,1: In asynchronous mode: Enable noise cancellation.."
|
|
bitfld.byte 0x1 4. "ABCS,Asynchronous Mode Base Clock Select" "0: Select 16 base clock cycles for 1-bit period,1: Select 8 base clock cycles for 1-bit period"
|
|
newline
|
|
bitfld.byte 0x1 3. "ABCSE,Asynchronous Mode Extended Base Clock Select 1" "0: Clock cycles for 1-bit period determined by..,1: Baud rate is 6 base clock cycles for 1-bit period"
|
|
bitfld.byte 0x1 2. "BRME,Bit Rate Modulation Enable" "0: Disable bit rate modulation function,1: Enable bit rate modulation function"
|
|
line.byte 0x2 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x2 0.--2. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: In asynchronous mode: Setting prohibited In..,?,?,?,?,?,?"
|
|
line.byte 0x3 "SIMR1,IIC Mode Register 1"
|
|
hexmask.byte 0x3 3.--7. 1. "IICDL,SDAn Delay Output Select"
|
|
bitfld.byte 0x3 0. "IICM,Simple IIC Mode Select" "0: SCMR.SMIF = 0: Asynchronous mode (including..,1: SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1:.."
|
|
line.byte 0x4 "SIMR2,IIC Mode Register 2"
|
|
bitfld.byte 0x4 5. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and ACK/NACK reception"
|
|
bitfld.byte 0x4 1. "IICCSC,Clock Synchronization" "0: Do not synchronize with clock signal,1: Synchronize with clock signal"
|
|
newline
|
|
bitfld.byte 0x4 0. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts"
|
|
line.byte 0x5 "SIMR3,IIC Mode Register 3"
|
|
bitfld.byte 0x5 6.--7. "IICSCLS,SCLn Output Select" "0: Output serial clock,1: Generate start restart or stop condition,?,?"
|
|
bitfld.byte 0x5 4.--5. "IICSDAS,SDAn Output Select" "0: Output serial data,1: Generate start restart or stop condition,?,?"
|
|
newline
|
|
bitfld.byte 0x5 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: No requests are being made for generating..,1: Generation of start restart or stop condition is.."
|
|
bitfld.byte 0x5 2. "IICSTPREQ,Stop Condition Generation" "0: Do not generate stop condition,1: Generate stop condition"
|
|
newline
|
|
bitfld.byte 0x5 1. "IICRSTAREQ,Restart Condition Generation" "0: Do not generate restart condition,1: Generate restart condition"
|
|
bitfld.byte 0x5 0. "IICSTAREQ,Start Condition Generation" "0: Do not generate start condition,1: Generate start condition"
|
|
rgroup.byte 0xC++0x0
|
|
line.byte 0x0 "SISR,IIC Status Register"
|
|
bitfld.byte 0x0 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received"
|
|
group.byte 0xD++0x0
|
|
line.byte 0x0 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x0 7. "CKPH,Clock Phase Select" "0: Do not delay clock,1: Delay clock"
|
|
bitfld.byte 0x0 6. "CKPOL,Clock Polarity Select" "0: Do not invert clock polarity,1: Invert clock polarity"
|
|
newline
|
|
bitfld.byte 0x0 4. "MFF,Mode Fault Flag" "0: No mode fault error,1: Mode fault error"
|
|
bitfld.byte 0x0 2. "MSS,Master Slave Select" "0: Transmit through TXDn pin and receive through..,1: Receive through TXDn pin and transmit through.."
|
|
newline
|
|
bitfld.byte 0x0 1. "CTSE,CTS Enable" "0: Disable CTS function (enable RTS output function),1: Enable CTS function"
|
|
bitfld.byte 0x0 0. "SSE,SSn Pin Function Enable" "0: Disable SSn pin function,1: Enable SSn pin function"
|
|
wgroup.word 0xE++0x1
|
|
line.word 0x0 "FTDRHL,Transmit FIFO Data Register"
|
|
bitfld.word 0x0 9. "MPBT,Multi-Processor Transfer Bit Flag" "0: Data transmission cycle,1: ID transmission cycle"
|
|
hexmask.word 0x0 0.--8. 1. "TDAT,Serial transmit data"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "TDRHL,Transmit Data Register"
|
|
hexmask.word 0x0 0.--8. 1. "TDAT,Serial Transmit Data"
|
|
wgroup.byte 0xE++0x1
|
|
line.byte 0x0 "FTDRH,Transmit FIFO Data Register"
|
|
bitfld.byte 0x0 1. "MPBT,Multi-Processor Transfer Bit Flag" "0: Data transmission cycle,1: ID transmission cycle"
|
|
line.byte 0x1 "FTDRL,Transmit FIFO Data Register"
|
|
hexmask.byte 0x1 0.--7. 1. "TDAT,Serial transmit data"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "FRDRHL,Receive FIFO Data Register"
|
|
bitfld.word 0x0 14. "RDF,Receive FIFO Data Full Flag" "0: The amount of receive data written in FRDRH and..,1: The amount of receive data written in FRDRH and.."
|
|
bitfld.word 0x0 13. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
newline
|
|
bitfld.word 0x0 12. "FER,Framing Error Flag" "0: No framing error occurred in the first data of..,1: Framing error occurred in the first data of.."
|
|
bitfld.word 0x0 11. "PER,Parity Error Flag" "0: No parity error occurred in the first data of..,1: Parity error occurred in the first data of FRDRH.."
|
|
newline
|
|
bitfld.word 0x0 10. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: Next receive data is not received for a period.."
|
|
bitfld.word 0x0 9. "MPB,Multi-Processor Bit Flag" "0: Data transmission cycle,1: ID transmission cycle"
|
|
newline
|
|
hexmask.word 0x0 0.--8. 1. "RDAT,Serial receive data"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RDRHL,Receive Data Register"
|
|
hexmask.word 0x0 0.--8. 1. "RDAT,Serial Receive Data"
|
|
rgroup.byte 0x10++0x1
|
|
line.byte 0x0 "FRDRH,Receive FIFO Data Register"
|
|
bitfld.byte 0x0 6. "RDF,Receive FIFO Data Full Flag" "0: The amount of receive data written in FRDRH and..,1: The amount of receive data written in FRDRH and.."
|
|
bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
newline
|
|
bitfld.byte 0x0 4. "FER,Framing Error Flag" "0: No framing error occurred in the first data of..,1: Framing error occurred in the first data of.."
|
|
bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred in the first data of..,1: Parity error occurred in the first data of FRDRH.."
|
|
newline
|
|
bitfld.byte 0x0 2. "DR,Receive Data Ready Flag" "0: Receiving is in progress or no received data..,1: Next receive data is not received for a period.."
|
|
bitfld.byte 0x0 1. "MPB,Multi-Processor Bit Flag" "0: Data transmission cycle,1: ID transmission cycle"
|
|
line.byte 0x1 "FRDRL,Receive FIFO Data Register"
|
|
hexmask.byte 0x1 0.--7. 1. "RDAT,Serial receive data"
|
|
group.byte 0x12++0x1
|
|
line.byte 0x0 "MDDR,Modulation Duty Register"
|
|
line.byte 0x1 "DCCR,Data Compare Match Control Register"
|
|
bitfld.byte 0x1 7. "DCME,Data Compare Match Enable" "0: Disable address match function,1: Enable address match function"
|
|
bitfld.byte 0x1 6. "IDSEL,ID Frame Select" "0: Always compare data regardless of the MPB bit..,1: Only compare data when MPB bit = 1 (ID frame)"
|
|
newline
|
|
bitfld.byte 0x1 4. "DFER,Data Compare Match Framing Error Flag" "0: No framing error occurred,1: Framing error occurred"
|
|
bitfld.byte 0x1 3. "DPER,Data Compare Match Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
newline
|
|
bitfld.byte 0x1 0. "DCMF,Data Compare Match Flag" "0: Not matched,1: Matched"
|
|
group.word 0x14++0x1
|
|
line.word 0x0 "FCR,FIFO Control Register"
|
|
hexmask.word.byte 0x0 12.--15. 1. "RSTRG,RTS Output Active Trigger Number Select"
|
|
hexmask.word.byte 0x0 8.--11. 1. "RTRG,Receive FIFO Data Trigger Number"
|
|
newline
|
|
hexmask.word.byte 0x0 4.--7. 1. "TTRG,Transmit FIFO Data Trigger Number"
|
|
bitfld.word 0x0 3. "DRES,Receive Data Ready Error Select" "0: Receive data full interrupt (SCIn_RXI),1: Receive error interrupt (SCIn_ERI)"
|
|
newline
|
|
bitfld.word 0x0 2. "TFRST,Transmit FIFO Data Register Reset" "0: Do not reset FTDRHL,1: Reset FTDRHL"
|
|
bitfld.word 0x0 1. "RFRST,Receive FIFO Data Register Reset" "0: Do not reset FRDRHL,1: Reset FRDRHL"
|
|
newline
|
|
bitfld.word 0x0 0. "FM,FIFO Mode Select" "0: Non-FIFO mode. Selects TDR/RDR or TDRHL/RDRHL..,1: FIFO mode. Selects FTDRHL/FRDRHL for.."
|
|
rgroup.word 0x16++0x3
|
|
line.word 0x0 "FDR,FIFO Data Count Register"
|
|
hexmask.word.byte 0x0 8.--12. 1. "T,Transmit FIFO Data Count"
|
|
hexmask.word.byte 0x0 0.--4. 1. "R,Receive FIFO Data Count"
|
|
line.word 0x2 "LSR,Line Status Register"
|
|
hexmask.word.byte 0x2 8.--12. 1. "PNUM,Parity Error Count"
|
|
hexmask.word.byte 0x2 2.--6. 1. "FNUM,Framing Error Count"
|
|
newline
|
|
bitfld.word 0x2 0. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
group.word 0x1A++0x1
|
|
line.word 0x0 "CDR,Compare Match Data Register"
|
|
hexmask.word 0x0 0.--8. 1. "CMPD,Compare Match Data"
|
|
group.byte 0x1C++0x0
|
|
line.byte 0x0 "SPTR,Serial Port Register"
|
|
bitfld.byte 0x0 2. "SPB2IO,Serial Port Break I/O" "0: Do not output value of SPB2DT bit on TXDn pin,1: Output value of SPB2DT bit on TXDn pin"
|
|
bitfld.byte 0x0 1. "SPB2DT,Serial Port Break Data Select" "0,1"
|
|
newline
|
|
rbitfld.byte 0x0 0. "RXDMON,Serial Input Data Monitor" "0,1"
|
|
tree.end
|
|
tree "SCI1"
|
|
base ad:0x40070020
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "SMR,Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"
|
|
bitfld.byte 0x0 7. "CM,Communication Mode" "0: Asynchronous mode or simple IIC mode,1: Clock synchronous mode or simple SPI mode"
|
|
bitfld.byte 0x0 6. "CHR,Character Length" "0: SCMR.CHR1 = 0: Transmit/receive in 9-bit data..,1: SCMR.CHR1 = 0: Transmit/receive in 9-bit data.."
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|
newline
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bitfld.byte 0x0 5. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.."
|
|
bitfld.byte 0x0 4. "PM,Parity Mode" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.byte 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit,1: 2 stop bits"
|
|
bitfld.byte 0x0 2. "MP,Multi-Processor Mode" "0: Disable multi-processor communications function,1: Enable multi-processor communications function"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock (n = 0),1: PCLK/4 clock (n = 1),?,?"
|
|
group.byte 0x0++0x2
|
|
line.byte 0x0 "SMR_SMCI,Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "GM,GSM Mode" "0: Normal mode operation,1: GSM mode operation"
|
|
bitfld.byte 0x0 6. "BLK,Block Transfer Mode" "0: Normal mode operation,1: Block transfer mode operation"
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|
newline
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|
bitfld.byte 0x0 5. "PE,Parity Enable" "0,1"
|
|
bitfld.byte 0x0 4. "PM,Parity Mode" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.byte 0x0 2.--3. "BCP,Base Clock Pulse" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock (n = 0),1: PCLK/4 clock (n = 1),?,?"
|
|
line.byte 0x1 "BRR,Bit Rate Register"
|
|
line.byte 0x2 "SCR,Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"
|
|
bitfld.byte 0x2 7. "TIE,Transmit Interrupt Enable" "0: Disable SCIn_TXI interrupt requests,1: Enable SCIn_TXI interrupt requests"
|
|
bitfld.byte 0x2 6. "RIE,Receive Interrupt Enable" "0: Disable SCIn_RXI and SCIn_ERI interrupt requests,1: Enable SCIn_RXI and SCIn_ERI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x2 5. "TE,Transmit Enable" "0: Disable serial transmission,1: Enable serial transmission"
|
|
bitfld.byte 0x2 4. "RE,Receive Enable" "0: Disable serial reception,1: Enable serial reception"
|
|
newline
|
|
bitfld.byte 0x2 3. "MPIE,Multi-Processor Interrupt Enable" "0: Normal reception,1: When data with the multi-processor bit set to 0.."
|
|
bitfld.byte 0x2 2. "TEIE,Transmit End Interrupt Enable" "0: Disable SCIn_TEI interrupt requests,1: Enable SCIn_TEI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x2 0.--1. "CKE,Clock Enable" "0: In asynchronous mode input a clock with a..,1: In asynchronous mode a clock with the same..,?,?"
|
|
group.byte 0x2++0x2
|
|
line.byte 0x0 "SCR_SMCI,Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "TIE,Transmit Interrupt Enable" "0: Disable SCIn_TXI interrupt requests,1: Enable SCIn_TXI interrupt requests"
|
|
bitfld.byte 0x0 6. "RIE,Receive Interrupt Enable" "0: Disable SCIn_RXI and SCIn_ERI interrupt requests,1: Enable SCIn_RXI and SCIn_ERI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x0 5. "TE,Transmit Enable" "0: Disable serial transmission,1: Enable serial transmission"
|
|
bitfld.byte 0x0 4. "RE,Receive Enable" "0: Disable serial reception,1: Enable serial reception"
|
|
newline
|
|
bitfld.byte 0x0 3. "MPIE,Multi-Processor Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "TEIE,Transmit End Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "CKE,Clock Enable" "0: When SMR_SMCI.GM = 0: Disable output The SCKn..,1: When SMR_SMCI.GM = 0: Output clock When..,?,?"
|
|
line.byte 0x1 "TDR,Transmit Data Register"
|
|
line.byte 0x2 "SSR,Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0. FCR.FM = 0)"
|
|
bitfld.byte 0x2 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data in TDR register,1: No transmit data in TDR register"
|
|
bitfld.byte 0x2 6. "RDRF,Receive Data Full Flag" "0: No received data in RDR register,1: Received data in RDR register"
|
|
newline
|
|
bitfld.byte 0x2 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
bitfld.byte 0x2 4. "FER,Framing Error Flag" "0: No framing error occurred,1: Framing error occurred"
|
|
newline
|
|
bitfld.byte 0x2 3. "PER,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
rbitfld.byte 0x2 2. "TEND,Transmit End Flag" "0: A character is being transmitted,1: Character transfer is complete"
|
|
newline
|
|
rbitfld.byte 0x2 1. "MPB,Multi-Processor" "0: Data transmission cycle,1: ID transmission cycle"
|
|
bitfld.byte 0x2 0. "MPBT,Multi-Processor Bit Transfer" "0: Data transmission cycle,1: ID transmission cycle"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "SSR_SMCI,Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data in TDR register,1: No transmit data in TDR register"
|
|
bitfld.byte 0x0 6. "RDRF,Receive Data Full Flag" "0: No received data in RDR register,1: Received data in RDR register"
|
|
newline
|
|
bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
bitfld.byte 0x0 4. "ERS,Error Signal Status Flag" "0: No low error signal response,1: Low error signal response occurred"
|
|
newline
|
|
bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
rbitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted,1: Character transfer is complete"
|
|
newline
|
|
rbitfld.byte 0x0 1. "MPB,Multi-Processor" "0,1"
|
|
bitfld.byte 0x0 0. "MPBT,Multi-Processor Bit Transfer" "0,1"
|
|
rgroup.byte 0x5++0x0
|
|
line.byte 0x0 "RDR,Receive Data Register"
|
|
group.byte 0x6++0x5
|
|
line.byte 0x0 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x0 7. "BCP2,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x0 4. "CHR1,Character Length 1" "0: SMR.CHR = 0: Transmit/receive in 9-bit data..,1: SMR.CHR = 0: Transmit/receive in 8-bit data.."
|
|
newline
|
|
bitfld.byte 0x0 3. "SDIR,Transmitted/Received Data Transfer Direction" "0: Transfer LSB-first,1: Transfer MSB-first"
|
|
bitfld.byte 0x0 2. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted as they are.,1: TDR register contents are inverted before.."
|
|
newline
|
|
bitfld.byte 0x0 0. "SMIF,Smart Card Interface Mode Select" "0: Non-smart card interface mode (asynchronous mode..,1: Smart card interface mode"
|
|
line.byte 0x1 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x1 7. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: Detect low level on RXDn pin as start bit,1: Detect falling edge of RXDn pin as start bit"
|
|
bitfld.byte 0x1 6. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Output clock from baud rate generator with..,1: Output clock from baud rate generator with.."
|
|
newline
|
|
bitfld.byte 0x1 5. "NFEN,Digital Noise Filter Function Enable" "0: In asynchronous mode: Disable noise cancellation..,1: In asynchronous mode: Enable noise cancellation.."
|
|
bitfld.byte 0x1 4. "ABCS,Asynchronous Mode Base Clock Select" "0: Select 16 base clock cycles for 1-bit period,1: Select 8 base clock cycles for 1-bit period"
|
|
newline
|
|
bitfld.byte 0x1 3. "ABCSE,Asynchronous Mode Extended Base Clock Select 1" "0: Clock cycles for 1-bit period determined by..,1: Baud rate is 6 base clock cycles for 1-bit period"
|
|
bitfld.byte 0x1 2. "BRME,Bit Rate Modulation Enable" "0: Disable bit rate modulation function,1: Enable bit rate modulation function"
|
|
line.byte 0x2 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x2 0.--2. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: In asynchronous mode: Setting prohibited In..,?,?,?,?,?,?"
|
|
line.byte 0x3 "SIMR1,IIC Mode Register 1"
|
|
hexmask.byte 0x3 3.--7. 1. "IICDL,SDAn Delay Output Select"
|
|
bitfld.byte 0x3 0. "IICM,Simple IIC Mode Select" "0: SCMR.SMIF = 0: Asynchronous mode (including..,1: SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1:.."
|
|
line.byte 0x4 "SIMR2,IIC Mode Register 2"
|
|
bitfld.byte 0x4 5. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and ACK/NACK reception"
|
|
bitfld.byte 0x4 1. "IICCSC,Clock Synchronization" "0: Do not synchronize with clock signal,1: Synchronize with clock signal"
|
|
newline
|
|
bitfld.byte 0x4 0. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts"
|
|
line.byte 0x5 "SIMR3,IIC Mode Register 3"
|
|
bitfld.byte 0x5 6.--7. "IICSCLS,SCLn Output Select" "0: Output serial clock,1: Generate start restart or stop condition,?,?"
|
|
bitfld.byte 0x5 4.--5. "IICSDAS,SDAn Output Select" "0: Output serial data,1: Generate start restart or stop condition,?,?"
|
|
newline
|
|
bitfld.byte 0x5 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: No requests are being made for generating..,1: Generation of start restart or stop condition is.."
|
|
bitfld.byte 0x5 2. "IICSTPREQ,Stop Condition Generation" "0: Do not generate stop condition,1: Generate stop condition"
|
|
newline
|
|
bitfld.byte 0x5 1. "IICRSTAREQ,Restart Condition Generation" "0: Do not generate restart condition,1: Generate restart condition"
|
|
bitfld.byte 0x5 0. "IICSTAREQ,Start Condition Generation" "0: Do not generate start condition,1: Generate start condition"
|
|
rgroup.byte 0xC++0x0
|
|
line.byte 0x0 "SISR,IIC Status Register"
|
|
bitfld.byte 0x0 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received"
|
|
group.byte 0xD++0x0
|
|
line.byte 0x0 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x0 7. "CKPH,Clock Phase Select" "0: Do not delay clock,1: Delay clock"
|
|
bitfld.byte 0x0 6. "CKPOL,Clock Polarity Select" "0: Do not invert clock polarity,1: Invert clock polarity"
|
|
newline
|
|
bitfld.byte 0x0 4. "MFF,Mode Fault Flag" "0: No mode fault error,1: Mode fault error"
|
|
bitfld.byte 0x0 2. "MSS,Master Slave Select" "0: Transmit through TXDn pin and receive through..,1: Receive through TXDn pin and transmit through.."
|
|
newline
|
|
bitfld.byte 0x0 1. "CTSE,CTS Enable" "0: Disable CTS function (enable RTS output function),1: Enable CTS function"
|
|
bitfld.byte 0x0 0. "SSE,SSn Pin Function Enable" "0: Disable SSn pin function,1: Enable SSn pin function"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "TDRHL,Transmit Data Register"
|
|
hexmask.word 0x0 0.--8. 1. "TDAT,Serial Transmit Data"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RDRHL,Receive Data Register"
|
|
hexmask.word 0x0 0.--8. 1. "RDAT,Serial Receive Data"
|
|
group.byte 0x12++0x0
|
|
line.byte 0x0 "MDDR,Modulation Duty Register"
|
|
tree.end
|
|
tree "SCI2"
|
|
base ad:0x40070040
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "SMR,Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"
|
|
bitfld.byte 0x0 7. "CM,Communication Mode" "0: Asynchronous mode or simple IIC mode,1: Clock synchronous mode or simple SPI mode"
|
|
bitfld.byte 0x0 6. "CHR,Character Length" "0: SCMR.CHR1 = 0: Transmit/receive in 9-bit data..,1: SCMR.CHR1 = 0: Transmit/receive in 9-bit data.."
|
|
newline
|
|
bitfld.byte 0x0 5. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.."
|
|
bitfld.byte 0x0 4. "PM,Parity Mode" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.byte 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit,1: 2 stop bits"
|
|
bitfld.byte 0x0 2. "MP,Multi-Processor Mode" "0: Disable multi-processor communications function,1: Enable multi-processor communications function"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock (n = 0),1: PCLK/4 clock (n = 1),?,?"
|
|
group.byte 0x0++0x2
|
|
line.byte 0x0 "SMR_SMCI,Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "GM,GSM Mode" "0: Normal mode operation,1: GSM mode operation"
|
|
bitfld.byte 0x0 6. "BLK,Block Transfer Mode" "0: Normal mode operation,1: Block transfer mode operation"
|
|
newline
|
|
bitfld.byte 0x0 5. "PE,Parity Enable" "0,1"
|
|
bitfld.byte 0x0 4. "PM,Parity Mode" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.byte 0x0 2.--3. "BCP,Base Clock Pulse" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock (n = 0),1: PCLK/4 clock (n = 1),?,?"
|
|
line.byte 0x1 "BRR,Bit Rate Register"
|
|
line.byte 0x2 "SCR,Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"
|
|
bitfld.byte 0x2 7. "TIE,Transmit Interrupt Enable" "0: Disable SCIn_TXI interrupt requests,1: Enable SCIn_TXI interrupt requests"
|
|
bitfld.byte 0x2 6. "RIE,Receive Interrupt Enable" "0: Disable SCIn_RXI and SCIn_ERI interrupt requests,1: Enable SCIn_RXI and SCIn_ERI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x2 5. "TE,Transmit Enable" "0: Disable serial transmission,1: Enable serial transmission"
|
|
bitfld.byte 0x2 4. "RE,Receive Enable" "0: Disable serial reception,1: Enable serial reception"
|
|
newline
|
|
bitfld.byte 0x2 3. "MPIE,Multi-Processor Interrupt Enable" "0: Normal reception,1: When data with the multi-processor bit set to 0.."
|
|
bitfld.byte 0x2 2. "TEIE,Transmit End Interrupt Enable" "0: Disable SCIn_TEI interrupt requests,1: Enable SCIn_TEI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x2 0.--1. "CKE,Clock Enable" "0: In asynchronous mode input a clock with a..,1: In asynchronous mode a clock with the same..,?,?"
|
|
group.byte 0x2++0x2
|
|
line.byte 0x0 "SCR_SMCI,Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "TIE,Transmit Interrupt Enable" "0: Disable SCIn_TXI interrupt requests,1: Enable SCIn_TXI interrupt requests"
|
|
bitfld.byte 0x0 6. "RIE,Receive Interrupt Enable" "0: Disable SCIn_RXI and SCIn_ERI interrupt requests,1: Enable SCIn_RXI and SCIn_ERI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x0 5. "TE,Transmit Enable" "0: Disable serial transmission,1: Enable serial transmission"
|
|
bitfld.byte 0x0 4. "RE,Receive Enable" "0: Disable serial reception,1: Enable serial reception"
|
|
newline
|
|
bitfld.byte 0x0 3. "MPIE,Multi-Processor Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "TEIE,Transmit End Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "CKE,Clock Enable" "0: When SMR_SMCI.GM = 0: Disable output The SCKn..,1: When SMR_SMCI.GM = 0: Output clock When..,?,?"
|
|
line.byte 0x1 "TDR,Transmit Data Register"
|
|
line.byte 0x2 "SSR,Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0. FCR.FM = 0)"
|
|
bitfld.byte 0x2 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data in TDR register,1: No transmit data in TDR register"
|
|
bitfld.byte 0x2 6. "RDRF,Receive Data Full Flag" "0: No received data in RDR register,1: Received data in RDR register"
|
|
newline
|
|
bitfld.byte 0x2 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
bitfld.byte 0x2 4. "FER,Framing Error Flag" "0: No framing error occurred,1: Framing error occurred"
|
|
newline
|
|
bitfld.byte 0x2 3. "PER,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
rbitfld.byte 0x2 2. "TEND,Transmit End Flag" "0: A character is being transmitted,1: Character transfer is complete"
|
|
newline
|
|
rbitfld.byte 0x2 1. "MPB,Multi-Processor" "0: Data transmission cycle,1: ID transmission cycle"
|
|
bitfld.byte 0x2 0. "MPBT,Multi-Processor Bit Transfer" "0: Data transmission cycle,1: ID transmission cycle"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "SSR_SMCI,Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data in TDR register,1: No transmit data in TDR register"
|
|
bitfld.byte 0x0 6. "RDRF,Receive Data Full Flag" "0: No received data in RDR register,1: Received data in RDR register"
|
|
newline
|
|
bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
bitfld.byte 0x0 4. "ERS,Error Signal Status Flag" "0: No low error signal response,1: Low error signal response occurred"
|
|
newline
|
|
bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
rbitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted,1: Character transfer is complete"
|
|
newline
|
|
rbitfld.byte 0x0 1. "MPB,Multi-Processor" "0,1"
|
|
bitfld.byte 0x0 0. "MPBT,Multi-Processor Bit Transfer" "0,1"
|
|
rgroup.byte 0x5++0x0
|
|
line.byte 0x0 "RDR,Receive Data Register"
|
|
group.byte 0x6++0x5
|
|
line.byte 0x0 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x0 7. "BCP2,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x0 4. "CHR1,Character Length 1" "0: SMR.CHR = 0: Transmit/receive in 9-bit data..,1: SMR.CHR = 0: Transmit/receive in 8-bit data.."
|
|
newline
|
|
bitfld.byte 0x0 3. "SDIR,Transmitted/Received Data Transfer Direction" "0: Transfer LSB-first,1: Transfer MSB-first"
|
|
bitfld.byte 0x0 2. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted as they are.,1: TDR register contents are inverted before.."
|
|
newline
|
|
bitfld.byte 0x0 0. "SMIF,Smart Card Interface Mode Select" "0: Non-smart card interface mode (asynchronous mode..,1: Smart card interface mode"
|
|
line.byte 0x1 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x1 7. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: Detect low level on RXDn pin as start bit,1: Detect falling edge of RXDn pin as start bit"
|
|
bitfld.byte 0x1 6. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Output clock from baud rate generator with..,1: Output clock from baud rate generator with.."
|
|
newline
|
|
bitfld.byte 0x1 5. "NFEN,Digital Noise Filter Function Enable" "0: In asynchronous mode: Disable noise cancellation..,1: In asynchronous mode: Enable noise cancellation.."
|
|
bitfld.byte 0x1 4. "ABCS,Asynchronous Mode Base Clock Select" "0: Select 16 base clock cycles for 1-bit period,1: Select 8 base clock cycles for 1-bit period"
|
|
newline
|
|
bitfld.byte 0x1 3. "ABCSE,Asynchronous Mode Extended Base Clock Select 1" "0: Clock cycles for 1-bit period determined by..,1: Baud rate is 6 base clock cycles for 1-bit period"
|
|
bitfld.byte 0x1 2. "BRME,Bit Rate Modulation Enable" "0: Disable bit rate modulation function,1: Enable bit rate modulation function"
|
|
line.byte 0x2 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x2 0.--2. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: In asynchronous mode: Setting prohibited In..,?,?,?,?,?,?"
|
|
line.byte 0x3 "SIMR1,IIC Mode Register 1"
|
|
hexmask.byte 0x3 3.--7. 1. "IICDL,SDAn Delay Output Select"
|
|
bitfld.byte 0x3 0. "IICM,Simple IIC Mode Select" "0: SCMR.SMIF = 0: Asynchronous mode (including..,1: SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1:.."
|
|
line.byte 0x4 "SIMR2,IIC Mode Register 2"
|
|
bitfld.byte 0x4 5. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and ACK/NACK reception"
|
|
bitfld.byte 0x4 1. "IICCSC,Clock Synchronization" "0: Do not synchronize with clock signal,1: Synchronize with clock signal"
|
|
newline
|
|
bitfld.byte 0x4 0. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts"
|
|
line.byte 0x5 "SIMR3,IIC Mode Register 3"
|
|
bitfld.byte 0x5 6.--7. "IICSCLS,SCLn Output Select" "0: Output serial clock,1: Generate start restart or stop condition,?,?"
|
|
bitfld.byte 0x5 4.--5. "IICSDAS,SDAn Output Select" "0: Output serial data,1: Generate start restart or stop condition,?,?"
|
|
newline
|
|
bitfld.byte 0x5 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: No requests are being made for generating..,1: Generation of start restart or stop condition is.."
|
|
bitfld.byte 0x5 2. "IICSTPREQ,Stop Condition Generation" "0: Do not generate stop condition,1: Generate stop condition"
|
|
newline
|
|
bitfld.byte 0x5 1. "IICRSTAREQ,Restart Condition Generation" "0: Do not generate restart condition,1: Generate restart condition"
|
|
bitfld.byte 0x5 0. "IICSTAREQ,Start Condition Generation" "0: Do not generate start condition,1: Generate start condition"
|
|
rgroup.byte 0xC++0x0
|
|
line.byte 0x0 "SISR,IIC Status Register"
|
|
bitfld.byte 0x0 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received"
|
|
group.byte 0xD++0x0
|
|
line.byte 0x0 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x0 7. "CKPH,Clock Phase Select" "0: Do not delay clock,1: Delay clock"
|
|
bitfld.byte 0x0 6. "CKPOL,Clock Polarity Select" "0: Do not invert clock polarity,1: Invert clock polarity"
|
|
newline
|
|
bitfld.byte 0x0 4. "MFF,Mode Fault Flag" "0: No mode fault error,1: Mode fault error"
|
|
bitfld.byte 0x0 2. "MSS,Master Slave Select" "0: Transmit through TXDn pin and receive through..,1: Receive through TXDn pin and transmit through.."
|
|
newline
|
|
bitfld.byte 0x0 1. "CTSE,CTS Enable" "0: Disable CTS function (enable RTS output function),1: Enable CTS function"
|
|
bitfld.byte 0x0 0. "SSE,SSn Pin Function Enable" "0: Disable SSn pin function,1: Enable SSn pin function"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "TDRHL,Transmit Data Register"
|
|
hexmask.word 0x0 0.--8. 1. "TDAT,Serial Transmit Data"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RDRHL,Receive Data Register"
|
|
hexmask.word 0x0 0.--8. 1. "RDAT,Serial Receive Data"
|
|
group.byte 0x12++0x0
|
|
line.byte 0x0 "MDDR,Modulation Duty Register"
|
|
tree.end
|
|
tree "SCI3"
|
|
base ad:0x40070060
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "SMR,Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"
|
|
bitfld.byte 0x0 7. "CM,Communication Mode" "0: Asynchronous mode or simple IIC mode,1: Clock synchronous mode or simple SPI mode"
|
|
bitfld.byte 0x0 6. "CHR,Character Length" "0: SCMR.CHR1 = 0: Transmit/receive in 9-bit data..,1: SCMR.CHR1 = 0: Transmit/receive in 9-bit data.."
|
|
newline
|
|
bitfld.byte 0x0 5. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.."
|
|
bitfld.byte 0x0 4. "PM,Parity Mode" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.byte 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit,1: 2 stop bits"
|
|
bitfld.byte 0x0 2. "MP,Multi-Processor Mode" "0: Disable multi-processor communications function,1: Enable multi-processor communications function"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock (n = 0),1: PCLK/4 clock (n = 1),?,?"
|
|
group.byte 0x0++0x2
|
|
line.byte 0x0 "SMR_SMCI,Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "GM,GSM Mode" "0: Normal mode operation,1: GSM mode operation"
|
|
bitfld.byte 0x0 6. "BLK,Block Transfer Mode" "0: Normal mode operation,1: Block transfer mode operation"
|
|
newline
|
|
bitfld.byte 0x0 5. "PE,Parity Enable" "0,1"
|
|
bitfld.byte 0x0 4. "PM,Parity Mode" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.byte 0x0 2.--3. "BCP,Base Clock Pulse" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock (n = 0),1: PCLK/4 clock (n = 1),?,?"
|
|
line.byte 0x1 "BRR,Bit Rate Register"
|
|
line.byte 0x2 "SCR,Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"
|
|
bitfld.byte 0x2 7. "TIE,Transmit Interrupt Enable" "0: Disable SCIn_TXI interrupt requests,1: Enable SCIn_TXI interrupt requests"
|
|
bitfld.byte 0x2 6. "RIE,Receive Interrupt Enable" "0: Disable SCIn_RXI and SCIn_ERI interrupt requests,1: Enable SCIn_RXI and SCIn_ERI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x2 5. "TE,Transmit Enable" "0: Disable serial transmission,1: Enable serial transmission"
|
|
bitfld.byte 0x2 4. "RE,Receive Enable" "0: Disable serial reception,1: Enable serial reception"
|
|
newline
|
|
bitfld.byte 0x2 3. "MPIE,Multi-Processor Interrupt Enable" "0: Normal reception,1: When data with the multi-processor bit set to 0.."
|
|
bitfld.byte 0x2 2. "TEIE,Transmit End Interrupt Enable" "0: Disable SCIn_TEI interrupt requests,1: Enable SCIn_TEI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x2 0.--1. "CKE,Clock Enable" "0: In asynchronous mode input a clock with a..,1: In asynchronous mode a clock with the same..,?,?"
|
|
group.byte 0x2++0x2
|
|
line.byte 0x0 "SCR_SMCI,Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "TIE,Transmit Interrupt Enable" "0: Disable SCIn_TXI interrupt requests,1: Enable SCIn_TXI interrupt requests"
|
|
bitfld.byte 0x0 6. "RIE,Receive Interrupt Enable" "0: Disable SCIn_RXI and SCIn_ERI interrupt requests,1: Enable SCIn_RXI and SCIn_ERI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x0 5. "TE,Transmit Enable" "0: Disable serial transmission,1: Enable serial transmission"
|
|
bitfld.byte 0x0 4. "RE,Receive Enable" "0: Disable serial reception,1: Enable serial reception"
|
|
newline
|
|
bitfld.byte 0x0 3. "MPIE,Multi-Processor Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "TEIE,Transmit End Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "CKE,Clock Enable" "0: When SMR_SMCI.GM = 0: Disable output The SCKn..,1: When SMR_SMCI.GM = 0: Output clock When..,?,?"
|
|
line.byte 0x1 "TDR,Transmit Data Register"
|
|
line.byte 0x2 "SSR,Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0. FCR.FM = 0)"
|
|
bitfld.byte 0x2 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data in TDR register,1: No transmit data in TDR register"
|
|
bitfld.byte 0x2 6. "RDRF,Receive Data Full Flag" "0: No received data in RDR register,1: Received data in RDR register"
|
|
newline
|
|
bitfld.byte 0x2 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
bitfld.byte 0x2 4. "FER,Framing Error Flag" "0: No framing error occurred,1: Framing error occurred"
|
|
newline
|
|
bitfld.byte 0x2 3. "PER,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
rbitfld.byte 0x2 2. "TEND,Transmit End Flag" "0: A character is being transmitted,1: Character transfer is complete"
|
|
newline
|
|
rbitfld.byte 0x2 1. "MPB,Multi-Processor" "0: Data transmission cycle,1: ID transmission cycle"
|
|
bitfld.byte 0x2 0. "MPBT,Multi-Processor Bit Transfer" "0: Data transmission cycle,1: ID transmission cycle"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "SSR_SMCI,Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data in TDR register,1: No transmit data in TDR register"
|
|
bitfld.byte 0x0 6. "RDRF,Receive Data Full Flag" "0: No received data in RDR register,1: Received data in RDR register"
|
|
newline
|
|
bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
bitfld.byte 0x0 4. "ERS,Error Signal Status Flag" "0: No low error signal response,1: Low error signal response occurred"
|
|
newline
|
|
bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
rbitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted,1: Character transfer is complete"
|
|
newline
|
|
rbitfld.byte 0x0 1. "MPB,Multi-Processor" "0,1"
|
|
bitfld.byte 0x0 0. "MPBT,Multi-Processor Bit Transfer" "0,1"
|
|
rgroup.byte 0x5++0x0
|
|
line.byte 0x0 "RDR,Receive Data Register"
|
|
group.byte 0x6++0x5
|
|
line.byte 0x0 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x0 7. "BCP2,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x0 4. "CHR1,Character Length 1" "0: SMR.CHR = 0: Transmit/receive in 9-bit data..,1: SMR.CHR = 0: Transmit/receive in 8-bit data.."
|
|
newline
|
|
bitfld.byte 0x0 3. "SDIR,Transmitted/Received Data Transfer Direction" "0: Transfer LSB-first,1: Transfer MSB-first"
|
|
bitfld.byte 0x0 2. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted as they are.,1: TDR register contents are inverted before.."
|
|
newline
|
|
bitfld.byte 0x0 0. "SMIF,Smart Card Interface Mode Select" "0: Non-smart card interface mode (asynchronous mode..,1: Smart card interface mode"
|
|
line.byte 0x1 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x1 7. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: Detect low level on RXDn pin as start bit,1: Detect falling edge of RXDn pin as start bit"
|
|
bitfld.byte 0x1 6. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Output clock from baud rate generator with..,1: Output clock from baud rate generator with.."
|
|
newline
|
|
bitfld.byte 0x1 5. "NFEN,Digital Noise Filter Function Enable" "0: In asynchronous mode: Disable noise cancellation..,1: In asynchronous mode: Enable noise cancellation.."
|
|
bitfld.byte 0x1 4. "ABCS,Asynchronous Mode Base Clock Select" "0: Select 16 base clock cycles for 1-bit period,1: Select 8 base clock cycles for 1-bit period"
|
|
newline
|
|
bitfld.byte 0x1 3. "ABCSE,Asynchronous Mode Extended Base Clock Select 1" "0: Clock cycles for 1-bit period determined by..,1: Baud rate is 6 base clock cycles for 1-bit period"
|
|
bitfld.byte 0x1 2. "BRME,Bit Rate Modulation Enable" "0: Disable bit rate modulation function,1: Enable bit rate modulation function"
|
|
line.byte 0x2 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x2 0.--2. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: In asynchronous mode: Setting prohibited In..,?,?,?,?,?,?"
|
|
line.byte 0x3 "SIMR1,IIC Mode Register 1"
|
|
hexmask.byte 0x3 3.--7. 1. "IICDL,SDAn Delay Output Select"
|
|
bitfld.byte 0x3 0. "IICM,Simple IIC Mode Select" "0: SCMR.SMIF = 0: Asynchronous mode (including..,1: SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1:.."
|
|
line.byte 0x4 "SIMR2,IIC Mode Register 2"
|
|
bitfld.byte 0x4 5. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and ACK/NACK reception"
|
|
bitfld.byte 0x4 1. "IICCSC,Clock Synchronization" "0: Do not synchronize with clock signal,1: Synchronize with clock signal"
|
|
newline
|
|
bitfld.byte 0x4 0. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts"
|
|
line.byte 0x5 "SIMR3,IIC Mode Register 3"
|
|
bitfld.byte 0x5 6.--7. "IICSCLS,SCLn Output Select" "0: Output serial clock,1: Generate start restart or stop condition,?,?"
|
|
bitfld.byte 0x5 4.--5. "IICSDAS,SDAn Output Select" "0: Output serial data,1: Generate start restart or stop condition,?,?"
|
|
newline
|
|
bitfld.byte 0x5 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: No requests are being made for generating..,1: Generation of start restart or stop condition is.."
|
|
bitfld.byte 0x5 2. "IICSTPREQ,Stop Condition Generation" "0: Do not generate stop condition,1: Generate stop condition"
|
|
newline
|
|
bitfld.byte 0x5 1. "IICRSTAREQ,Restart Condition Generation" "0: Do not generate restart condition,1: Generate restart condition"
|
|
bitfld.byte 0x5 0. "IICSTAREQ,Start Condition Generation" "0: Do not generate start condition,1: Generate start condition"
|
|
rgroup.byte 0xC++0x0
|
|
line.byte 0x0 "SISR,IIC Status Register"
|
|
bitfld.byte 0x0 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received"
|
|
group.byte 0xD++0x0
|
|
line.byte 0x0 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x0 7. "CKPH,Clock Phase Select" "0: Do not delay clock,1: Delay clock"
|
|
bitfld.byte 0x0 6. "CKPOL,Clock Polarity Select" "0: Do not invert clock polarity,1: Invert clock polarity"
|
|
newline
|
|
bitfld.byte 0x0 4. "MFF,Mode Fault Flag" "0: No mode fault error,1: Mode fault error"
|
|
bitfld.byte 0x0 2. "MSS,Master Slave Select" "0: Transmit through TXDn pin and receive through..,1: Receive through TXDn pin and transmit through.."
|
|
newline
|
|
bitfld.byte 0x0 1. "CTSE,CTS Enable" "0: Disable CTS function (enable RTS output function),1: Enable CTS function"
|
|
bitfld.byte 0x0 0. "SSE,SSn Pin Function Enable" "0: Disable SSn pin function,1: Enable SSn pin function"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "TDRHL,Transmit Data Register"
|
|
hexmask.word 0x0 0.--8. 1. "TDAT,Serial Transmit Data"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RDRHL,Receive Data Register"
|
|
hexmask.word 0x0 0.--8. 1. "RDAT,Serial Receive Data"
|
|
group.byte 0x12++0x0
|
|
line.byte 0x0 "MDDR,Modulation Duty Register"
|
|
tree.end
|
|
tree "SCI9"
|
|
base ad:0x40070120
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "SMR,Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"
|
|
bitfld.byte 0x0 7. "CM,Communication Mode" "0: Asynchronous mode or simple IIC mode,1: Clock synchronous mode or simple SPI mode"
|
|
bitfld.byte 0x0 6. "CHR,Character Length" "0: SCMR.CHR1 = 0: Transmit/receive in 9-bit data..,1: SCMR.CHR1 = 0: Transmit/receive in 9-bit data.."
|
|
newline
|
|
bitfld.byte 0x0 5. "PE,Parity Enable" "0: When transmitting: Do not add parity bit When..,1: When transmitting: Add parity bit When.."
|
|
bitfld.byte 0x0 4. "PM,Parity Mode" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.byte 0x0 3. "STOP,Stop Bit Length" "0: 1 stop bit,1: 2 stop bits"
|
|
bitfld.byte 0x0 2. "MP,Multi-Processor Mode" "0: Disable multi-processor communications function,1: Enable multi-processor communications function"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock (n = 0),1: PCLK/4 clock (n = 1),?,?"
|
|
group.byte 0x0++0x2
|
|
line.byte 0x0 "SMR_SMCI,Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "GM,GSM Mode" "0: Normal mode operation,1: GSM mode operation"
|
|
bitfld.byte 0x0 6. "BLK,Block Transfer Mode" "0: Normal mode operation,1: Block transfer mode operation"
|
|
newline
|
|
bitfld.byte 0x0 5. "PE,Parity Enable" "0,1"
|
|
bitfld.byte 0x0 4. "PM,Parity Mode" "0: Even parity,1: Odd parity"
|
|
newline
|
|
bitfld.byte 0x0 2.--3. "BCP,Base Clock Pulse" "0,1,2,3"
|
|
bitfld.byte 0x0 0.--1. "CKS,Clock Select" "0: PCLK clock (n = 0),1: PCLK/4 clock (n = 1),?,?"
|
|
line.byte 0x1 "BRR,Bit Rate Register"
|
|
line.byte 0x2 "SCR,Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"
|
|
bitfld.byte 0x2 7. "TIE,Transmit Interrupt Enable" "0: Disable SCIn_TXI interrupt requests,1: Enable SCIn_TXI interrupt requests"
|
|
bitfld.byte 0x2 6. "RIE,Receive Interrupt Enable" "0: Disable SCIn_RXI and SCIn_ERI interrupt requests,1: Enable SCIn_RXI and SCIn_ERI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x2 5. "TE,Transmit Enable" "0: Disable serial transmission,1: Enable serial transmission"
|
|
bitfld.byte 0x2 4. "RE,Receive Enable" "0: Disable serial reception,1: Enable serial reception"
|
|
newline
|
|
bitfld.byte 0x2 3. "MPIE,Multi-Processor Interrupt Enable" "0: Normal reception,1: When data with the multi-processor bit set to 0.."
|
|
bitfld.byte 0x2 2. "TEIE,Transmit End Interrupt Enable" "0: Disable SCIn_TEI interrupt requests,1: Enable SCIn_TEI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x2 0.--1. "CKE,Clock Enable" "0: In asynchronous mode input a clock with a..,1: In asynchronous mode a clock with the same..,?,?"
|
|
group.byte 0x2++0x2
|
|
line.byte 0x0 "SCR_SMCI,Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "TIE,Transmit Interrupt Enable" "0: Disable SCIn_TXI interrupt requests,1: Enable SCIn_TXI interrupt requests"
|
|
bitfld.byte 0x0 6. "RIE,Receive Interrupt Enable" "0: Disable SCIn_RXI and SCIn_ERI interrupt requests,1: Enable SCIn_RXI and SCIn_ERI interrupt requests"
|
|
newline
|
|
bitfld.byte 0x0 5. "TE,Transmit Enable" "0: Disable serial transmission,1: Enable serial transmission"
|
|
bitfld.byte 0x0 4. "RE,Receive Enable" "0: Disable serial reception,1: Enable serial reception"
|
|
newline
|
|
bitfld.byte 0x0 3. "MPIE,Multi-Processor Interrupt Enable" "0,1"
|
|
bitfld.byte 0x0 2. "TEIE,Transmit End Interrupt Enable" "0,1"
|
|
newline
|
|
bitfld.byte 0x0 0.--1. "CKE,Clock Enable" "0: When SMR_SMCI.GM = 0: Disable output The SCKn..,1: When SMR_SMCI.GM = 0: Output clock When..,?,?"
|
|
line.byte 0x1 "TDR,Transmit Data Register"
|
|
line.byte 0x2 "SSR,Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0. FCR.FM = 0)"
|
|
bitfld.byte 0x2 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data in TDR register,1: No transmit data in TDR register"
|
|
bitfld.byte 0x2 6. "RDRF,Receive Data Full Flag" "0: No received data in RDR register,1: Received data in RDR register"
|
|
newline
|
|
bitfld.byte 0x2 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
bitfld.byte 0x2 4. "FER,Framing Error Flag" "0: No framing error occurred,1: Framing error occurred"
|
|
newline
|
|
bitfld.byte 0x2 3. "PER,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
rbitfld.byte 0x2 2. "TEND,Transmit End Flag" "0: A character is being transmitted,1: Character transfer is complete"
|
|
newline
|
|
rbitfld.byte 0x2 1. "MPB,Multi-Processor" "0: Data transmission cycle,1: ID transmission cycle"
|
|
bitfld.byte 0x2 0. "MPBT,Multi-Processor Bit Transfer" "0: Data transmission cycle,1: ID transmission cycle"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "SSR_SMCI,Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1)"
|
|
bitfld.byte 0x0 7. "TDRE,Transmit Data Empty Flag" "0: Transmit data in TDR register,1: No transmit data in TDR register"
|
|
bitfld.byte 0x0 6. "RDRF,Receive Data Full Flag" "0: No received data in RDR register,1: Received data in RDR register"
|
|
newline
|
|
bitfld.byte 0x0 5. "ORER,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
bitfld.byte 0x0 4. "ERS,Error Signal Status Flag" "0: No low error signal response,1: Low error signal response occurred"
|
|
newline
|
|
bitfld.byte 0x0 3. "PER,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
rbitfld.byte 0x0 2. "TEND,Transmit End Flag" "0: A character is being transmitted,1: Character transfer is complete"
|
|
newline
|
|
rbitfld.byte 0x0 1. "MPB,Multi-Processor" "0,1"
|
|
bitfld.byte 0x0 0. "MPBT,Multi-Processor Bit Transfer" "0,1"
|
|
rgroup.byte 0x5++0x0
|
|
line.byte 0x0 "RDR,Receive Data Register"
|
|
group.byte 0x6++0x5
|
|
line.byte 0x0 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x0 7. "BCP2,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x0 4. "CHR1,Character Length 1" "0: SMR.CHR = 0: Transmit/receive in 9-bit data..,1: SMR.CHR = 0: Transmit/receive in 8-bit data.."
|
|
newline
|
|
bitfld.byte 0x0 3. "SDIR,Transmitted/Received Data Transfer Direction" "0: Transfer LSB-first,1: Transfer MSB-first"
|
|
bitfld.byte 0x0 2. "SINV,Transmitted/Received Data Invert" "0: TDR contents are transmitted as they are.,1: TDR register contents are inverted before.."
|
|
newline
|
|
bitfld.byte 0x0 0. "SMIF,Smart Card Interface Mode Select" "0: Non-smart card interface mode (asynchronous mode..,1: Smart card interface mode"
|
|
line.byte 0x1 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x1 7. "RXDESEL,Asynchronous Start Bit Edge Detection Select" "0: Detect low level on RXDn pin as start bit,1: Detect falling edge of RXDn pin as start bit"
|
|
bitfld.byte 0x1 6. "BGDM,Baud Rate Generator Double-Speed Mode Select" "0: Output clock from baud rate generator with..,1: Output clock from baud rate generator with.."
|
|
newline
|
|
bitfld.byte 0x1 5. "NFEN,Digital Noise Filter Function Enable" "0: In asynchronous mode: Disable noise cancellation..,1: In asynchronous mode: Enable noise cancellation.."
|
|
bitfld.byte 0x1 4. "ABCS,Asynchronous Mode Base Clock Select" "0: Select 16 base clock cycles for 1-bit period,1: Select 8 base clock cycles for 1-bit period"
|
|
newline
|
|
bitfld.byte 0x1 3. "ABCSE,Asynchronous Mode Extended Base Clock Select 1" "0: Clock cycles for 1-bit period determined by..,1: Baud rate is 6 base clock cycles for 1-bit period"
|
|
bitfld.byte 0x1 2. "BRME,Bit Rate Modulation Enable" "0: Disable bit rate modulation function,1: Enable bit rate modulation function"
|
|
line.byte 0x2 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x2 0.--2. "NFCS,Noise Filter Clock Select" "0: Setting prohibited,1: In asynchronous mode: Setting prohibited In..,?,?,?,?,?,?"
|
|
line.byte 0x3 "SIMR1,IIC Mode Register 1"
|
|
hexmask.byte 0x3 3.--7. 1. "IICDL,SDAn Delay Output Select"
|
|
bitfld.byte 0x3 0. "IICM,Simple IIC Mode Select" "0: SCMR.SMIF = 0: Asynchronous mode (including..,1: SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1:.."
|
|
line.byte 0x4 "SIMR2,IIC Mode Register 2"
|
|
bitfld.byte 0x4 5. "IICACKT,ACK Transmission Data" "0: ACK transmission,1: NACK transmission and ACK/NACK reception"
|
|
bitfld.byte 0x4 1. "IICCSC,Clock Synchronization" "0: Do not synchronize with clock signal,1: Synchronize with clock signal"
|
|
newline
|
|
bitfld.byte 0x4 0. "IICINTM,IIC Interrupt Mode Select" "0: Use ACK/NACK interrupts,1: Use reception and transmission interrupts"
|
|
line.byte 0x5 "SIMR3,IIC Mode Register 3"
|
|
bitfld.byte 0x5 6.--7. "IICSCLS,SCLn Output Select" "0: Output serial clock,1: Generate start restart or stop condition,?,?"
|
|
bitfld.byte 0x5 4.--5. "IICSDAS,SDAn Output Select" "0: Output serial data,1: Generate start restart or stop condition,?,?"
|
|
newline
|
|
bitfld.byte 0x5 3. "IICSTIF,Issuing of Start Restart or Stop Condition Completed Flag" "0: No requests are being made for generating..,1: Generation of start restart or stop condition is.."
|
|
bitfld.byte 0x5 2. "IICSTPREQ,Stop Condition Generation" "0: Do not generate stop condition,1: Generate stop condition"
|
|
newline
|
|
bitfld.byte 0x5 1. "IICRSTAREQ,Restart Condition Generation" "0: Do not generate restart condition,1: Generate restart condition"
|
|
bitfld.byte 0x5 0. "IICSTAREQ,Start Condition Generation" "0: Do not generate start condition,1: Generate start condition"
|
|
rgroup.byte 0xC++0x0
|
|
line.byte 0x0 "SISR,IIC Status Register"
|
|
bitfld.byte 0x0 0. "IICACKR,ACK Reception Data Flag" "0: ACK received,1: NACK received"
|
|
group.byte 0xD++0x0
|
|
line.byte 0x0 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x0 7. "CKPH,Clock Phase Select" "0: Do not delay clock,1: Delay clock"
|
|
bitfld.byte 0x0 6. "CKPOL,Clock Polarity Select" "0: Do not invert clock polarity,1: Invert clock polarity"
|
|
newline
|
|
bitfld.byte 0x0 4. "MFF,Mode Fault Flag" "0: No mode fault error,1: Mode fault error"
|
|
bitfld.byte 0x0 2. "MSS,Master Slave Select" "0: Transmit through TXDn pin and receive through..,1: Receive through TXDn pin and transmit through.."
|
|
newline
|
|
bitfld.byte 0x0 1. "CTSE,CTS Enable" "0: Disable CTS function (enable RTS output function),1: Enable CTS function"
|
|
bitfld.byte 0x0 0. "SSE,SSn Pin Function Enable" "0: Disable SSn pin function,1: Enable SSn pin function"
|
|
group.word 0xE++0x1
|
|
line.word 0x0 "TDRHL,Transmit Data Register"
|
|
hexmask.word 0x0 0.--8. 1. "TDAT,Serial Transmit Data"
|
|
rgroup.word 0x10++0x1
|
|
line.word 0x0 "RDRHL,Receive Data Register"
|
|
hexmask.word 0x0 0.--8. 1. "RDAT,Serial Receive Data"
|
|
group.byte 0x12++0x0
|
|
line.byte 0x0 "MDDR,Modulation Duty Register"
|
|
tree.end
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
tree "SPI0"
|
|
base ad:0x40072000
|
|
group.byte 0x0++0x3
|
|
line.byte 0x0 "SPCR,SPI Control Register"
|
|
bitfld.byte 0x0 7. "SPRIE,SPI Receive Buffer Full Interrupt Enable" "0: Disable SPI receive buffer full interrupt requests,1: Enable SPI receive buffer full interrupt requests"
|
|
bitfld.byte 0x0 6. "SPE,SPI Function Enable" "0: Disable SPI function,1: Enable SPI function"
|
|
newline
|
|
bitfld.byte 0x0 5. "SPTIE,Transmit Buffer Empty Interrupt Enable" "0: Disable transmit buffer empty interrupt requests,1: Enable transmit buffer empty interrupt requests"
|
|
bitfld.byte 0x0 4. "SPEIE,SPI Error Interrupt Enable" "0: Disable SPI error interrupt requests,1: Enable SPI error interrupt requests"
|
|
newline
|
|
bitfld.byte 0x0 3. "MSTR,SPI Master/Slave Mode Select" "0: Select slave mode,1: Select master mode"
|
|
bitfld.byte 0x0 2. "MODFEN,Mode Fault Error Detection Enable" "0: Disable detection of mode fault errors,1: Enable detection of mode fault errors"
|
|
newline
|
|
bitfld.byte 0x0 1. "TXMD,Communications Operating Mode Select" "0: Select full-duplex synchronous serial..,1: Select serial communications with transmit-only"
|
|
bitfld.byte 0x0 0. "SPMS,SPI Mode Select" "0: Select SPI operation (4-wire method),1: Select clock synchronous operation (3-wire method)"
|
|
line.byte 0x1 "SSLP,SPI Slave Select Polarity Register"
|
|
bitfld.byte 0x1 3. "SSL3P,SSLn3 Signal Polarity Setting" "0: Set SSLn3 signal to active-low,1: Set SSLn3 signal to active-high"
|
|
bitfld.byte 0x1 2. "SSL2P,SSLn2 Signal Polarity Setting" "0: Set SSLn2 signal to active-low,1: Set SSLn2 signal to active-high"
|
|
newline
|
|
bitfld.byte 0x1 1. "SSL1P,SSLn1 Signal Polarity Setting" "0: Set SSLn1 signal to active-low,1: Set SSLn1 signal to active-high"
|
|
bitfld.byte 0x1 0. "SSL0P,SSLn0 Signal Polarity Setting" "0: Set SSLn0 signal to active-low,1: Set SSLn0 signal to active-high"
|
|
line.byte 0x2 "SPPCR,SPI Pin Control Register"
|
|
bitfld.byte 0x2 5. "MOIFE,MOSI Idle Value Fixing Enable" "0: Set MOSI output value to equal final data from..,1: Set MOSI output value to equal value set in the.."
|
|
bitfld.byte 0x2 4. "MOIFV,MOSI Idle Fixed Value" "0: Set level output on MOSIn pin during MOSI idling..,1: Set level output on MOSIn pin during MOSI idling.."
|
|
newline
|
|
bitfld.byte 0x2 1. "SPLP2,SPI Loopback 2" "0: Normal mode,1: Loopback mode (receive data = transmit data)"
|
|
bitfld.byte 0x2 0. "SPLP,SPI Loopback" "0: Normal mode,1: Loopback mode (receive data = inverted transmit.."
|
|
line.byte 0x3 "SPSR,SPI Status Register"
|
|
bitfld.byte 0x3 7. "SPRF,SPI Receive Buffer Full Flag" "0: No valid data is in SPDR/SPDR_HA,1: Valid data is in SPDR/SPDR_HA"
|
|
bitfld.byte 0x3 5. "SPTEF,SPI Transmit Buffer Empty Flag" "0: Data is in the transmit buffer,1: No data is in the transmit buffer"
|
|
newline
|
|
bitfld.byte 0x3 4. "UDRF,Underrun Error Flag" "0: Mode fault error occurred (MODF = 1),1: Underrun error occurred (MODF = 1)"
|
|
bitfld.byte 0x3 3. "PERF,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
newline
|
|
bitfld.byte 0x3 2. "MODF,Mode Fault Error Flag" "0: No mode fault or underrun error occurred,1: Mode fault error or underrun error occurred"
|
|
rbitfld.byte 0x3 1. "IDLNF,SPI Idle Flag" "0: SPI is in the idle state,1: SPI is in the transfer state"
|
|
newline
|
|
bitfld.byte 0x3 0. "OVRF,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "SPDR,SPI Data Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPDR_HA,SPI Data Register"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "SPDR_BY,SPI Data Register"
|
|
group.byte 0xA++0x5
|
|
line.byte 0x0 "SPBR,SPI Bit Rate Register"
|
|
line.byte 0x1 "SPDCR,SPI Data Control Register"
|
|
bitfld.byte 0x1 6. "SPBYT,SPI Byte Access Specification" "0: SPDR/SPDR_HA is accessed in halfword or word..,1: SPDR_BY is accessed in byte (SPLW is invalid)"
|
|
bitfld.byte 0x1 5. "SPLW,SPI Word Access/Halfword Access Specification" "0: Set SPDR_HA to valid for halfword access,1: Set SPDR to valid for word access"
|
|
newline
|
|
bitfld.byte 0x1 4. "SPRDTD,SPI Receive/Transmit Data Select" "0: Read SPDR/SPDR_HA values from receive buffer,1: Read SPDR/SPDR_HA values from transmit buffer.."
|
|
line.byte 0x2 "SPCKD,SPI Clock Delay Register"
|
|
bitfld.byte 0x2 0.--2. "SCKDL,RSPCK Delay Setting" "0: 1 RSPCK,1: 2 RSPCK,?,?,?,?,?,?"
|
|
line.byte 0x3 "SSLND,SPI Slave Select Negation Delay Register"
|
|
bitfld.byte 0x3 0.--2. "SLNDL,SSL Negation Delay Setting" "0: 1 RSPCK,1: 2 RSPCK,?,?,?,?,?,?"
|
|
line.byte 0x4 "SPND,SPI Next-Access Delay Register"
|
|
bitfld.byte 0x4 0.--2. "SPNDL,SPI Next-Access Delay Setting" "0: 1 RSPCK + 2 PCLKB,1: 2 RSPCK + 2 PCLKB,?,?,?,?,?,?"
|
|
line.byte 0x5 "SPCR2,SPI Control Register 2"
|
|
bitfld.byte 0x5 4. "SCKASE,RSPCK Auto-Stop Function Enable" "0: Disable RSPCK auto-stop function,1: Enable RSPCK auto-stop function"
|
|
bitfld.byte 0x5 3. "PTE,Parity Self-Testing" "0: Disable self-diagnosis function of the parity..,1: Enable self-diagnosis function of the parity.."
|
|
newline
|
|
bitfld.byte 0x5 2. "SPIIE,SPI Idle Interrupt Enable" "0: Disable idle interrupt requests,1: Enable idle interrupt requests"
|
|
bitfld.byte 0x5 1. "SPOE,Parity Mode" "0: Select even parity for transmission and reception,1: Select odd parity for transmission and reception"
|
|
newline
|
|
bitfld.byte 0x5 0. "SPPE,Parity Enable" "0: Do not add parity bit to transmit data and do..,1: When SPCR.TXMD = 0: Add parity bit to transmit.."
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPCMD0,SPI Command Register 0"
|
|
bitfld.word 0x0 15. "SCKDEN,RSPCK Delay Setting Enable" "0: Select RSPCK delay of 1 RSPCK,1: Select RSPCK delay equal to the setting in the.."
|
|
bitfld.word 0x0 14. "SLNDEN,SSL Negation Delay Setting Enable" "0: Select SSL negation delay of 1 RSPCK,1: Select SSL negation delay equal to the setting.."
|
|
newline
|
|
bitfld.word 0x0 13. "SPNDEN,SPI Next-Access Delay Enable" "0: Select next-access delay of 1 RSPCK + 2 PCLKB,1: Select next-access delay equal to the setting in.."
|
|
bitfld.word 0x0 12. "LSBF,SPI LSB First" "0: MSB-first,1: LSB-first"
|
|
newline
|
|
hexmask.word.byte 0x0 8.--11. 1. "SPB,SPI Data Length Setting"
|
|
bitfld.word 0x0 4.--6. "SSLA,SSL Signal Assertion Setting" "0: Setting prohibited,1: SSL1,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "BRDV,Bit Rate Division Setting" "0: Base bit rate,1: Base bit rate divided by 2,?,?"
|
|
bitfld.word 0x0 1. "CPOL,RSPCK Polarity Setting" "0: Set RSPCK low during idle,1: Set RSPCK high during idle"
|
|
newline
|
|
bitfld.word 0x0 0. "CPHA,RSPCK Phase Setting" "0: Select data sampling on leading edge data change..,1: Select data change on leading edge data sampling.."
|
|
tree.end
|
|
tree "SPI1"
|
|
base ad:0x40072100
|
|
group.byte 0x0++0x3
|
|
line.byte 0x0 "SPCR,SPI Control Register"
|
|
bitfld.byte 0x0 7. "SPRIE,SPI Receive Buffer Full Interrupt Enable" "0: Disable SPI receive buffer full interrupt requests,1: Enable SPI receive buffer full interrupt requests"
|
|
bitfld.byte 0x0 6. "SPE,SPI Function Enable" "0: Disable SPI function,1: Enable SPI function"
|
|
newline
|
|
bitfld.byte 0x0 5. "SPTIE,Transmit Buffer Empty Interrupt Enable" "0: Disable transmit buffer empty interrupt requests,1: Enable transmit buffer empty interrupt requests"
|
|
bitfld.byte 0x0 4. "SPEIE,SPI Error Interrupt Enable" "0: Disable SPI error interrupt requests,1: Enable SPI error interrupt requests"
|
|
newline
|
|
bitfld.byte 0x0 3. "MSTR,SPI Master/Slave Mode Select" "0: Select slave mode,1: Select master mode"
|
|
bitfld.byte 0x0 2. "MODFEN,Mode Fault Error Detection Enable" "0: Disable detection of mode fault errors,1: Enable detection of mode fault errors"
|
|
newline
|
|
bitfld.byte 0x0 1. "TXMD,Communications Operating Mode Select" "0: Select full-duplex synchronous serial..,1: Select serial communications with transmit-only"
|
|
bitfld.byte 0x0 0. "SPMS,SPI Mode Select" "0: Select SPI operation (4-wire method),1: Select clock synchronous operation (3-wire method)"
|
|
line.byte 0x1 "SSLP,SPI Slave Select Polarity Register"
|
|
bitfld.byte 0x1 3. "SSL3P,SSLn3 Signal Polarity Setting" "0: Set SSLn3 signal to active-low,1: Set SSLn3 signal to active-high"
|
|
bitfld.byte 0x1 2. "SSL2P,SSLn2 Signal Polarity Setting" "0: Set SSLn2 signal to active-low,1: Set SSLn2 signal to active-high"
|
|
newline
|
|
bitfld.byte 0x1 1. "SSL1P,SSLn1 Signal Polarity Setting" "0: Set SSLn1 signal to active-low,1: Set SSLn1 signal to active-high"
|
|
bitfld.byte 0x1 0. "SSL0P,SSLn0 Signal Polarity Setting" "0: Set SSLn0 signal to active-low,1: Set SSLn0 signal to active-high"
|
|
line.byte 0x2 "SPPCR,SPI Pin Control Register"
|
|
bitfld.byte 0x2 5. "MOIFE,MOSI Idle Value Fixing Enable" "0: Set MOSI output value to equal final data from..,1: Set MOSI output value to equal value set in the.."
|
|
bitfld.byte 0x2 4. "MOIFV,MOSI Idle Fixed Value" "0: Set level output on MOSIn pin during MOSI idling..,1: Set level output on MOSIn pin during MOSI idling.."
|
|
newline
|
|
bitfld.byte 0x2 1. "SPLP2,SPI Loopback 2" "0: Normal mode,1: Loopback mode (receive data = transmit data)"
|
|
bitfld.byte 0x2 0. "SPLP,SPI Loopback" "0: Normal mode,1: Loopback mode (receive data = inverted transmit.."
|
|
line.byte 0x3 "SPSR,SPI Status Register"
|
|
bitfld.byte 0x3 7. "SPRF,SPI Receive Buffer Full Flag" "0: No valid data is in SPDR/SPDR_HA,1: Valid data is in SPDR/SPDR_HA"
|
|
bitfld.byte 0x3 5. "SPTEF,SPI Transmit Buffer Empty Flag" "0: Data is in the transmit buffer,1: No data is in the transmit buffer"
|
|
newline
|
|
bitfld.byte 0x3 4. "UDRF,Underrun Error Flag" "0: Mode fault error occurred (MODF = 1),1: Underrun error occurred (MODF = 1)"
|
|
bitfld.byte 0x3 3. "PERF,Parity Error Flag" "0: No parity error occurred,1: Parity error occurred"
|
|
newline
|
|
bitfld.byte 0x3 2. "MODF,Mode Fault Error Flag" "0: No mode fault or underrun error occurred,1: Mode fault error or underrun error occurred"
|
|
rbitfld.byte 0x3 1. "IDLNF,SPI Idle Flag" "0: SPI is in the idle state,1: SPI is in the transfer state"
|
|
newline
|
|
bitfld.byte 0x3 0. "OVRF,Overrun Error Flag" "0: No overrun error occurred,1: Overrun error occurred"
|
|
group.long 0x4++0x3
|
|
line.long 0x0 "SPDR,SPI Data Register"
|
|
group.word 0x4++0x1
|
|
line.word 0x0 "SPDR_HA,SPI Data Register"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "SPDR_BY,SPI Data Register"
|
|
group.byte 0xA++0x5
|
|
line.byte 0x0 "SPBR,SPI Bit Rate Register"
|
|
line.byte 0x1 "SPDCR,SPI Data Control Register"
|
|
bitfld.byte 0x1 6. "SPBYT,SPI Byte Access Specification" "0: SPDR/SPDR_HA is accessed in halfword or word..,1: SPDR_BY is accessed in byte (SPLW is invalid)"
|
|
bitfld.byte 0x1 5. "SPLW,SPI Word Access/Halfword Access Specification" "0: Set SPDR_HA to valid for halfword access,1: Set SPDR to valid for word access"
|
|
newline
|
|
bitfld.byte 0x1 4. "SPRDTD,SPI Receive/Transmit Data Select" "0: Read SPDR/SPDR_HA values from receive buffer,1: Read SPDR/SPDR_HA values from transmit buffer.."
|
|
line.byte 0x2 "SPCKD,SPI Clock Delay Register"
|
|
bitfld.byte 0x2 0.--2. "SCKDL,RSPCK Delay Setting" "0: 1 RSPCK,1: 2 RSPCK,?,?,?,?,?,?"
|
|
line.byte 0x3 "SSLND,SPI Slave Select Negation Delay Register"
|
|
bitfld.byte 0x3 0.--2. "SLNDL,SSL Negation Delay Setting" "0: 1 RSPCK,1: 2 RSPCK,?,?,?,?,?,?"
|
|
line.byte 0x4 "SPND,SPI Next-Access Delay Register"
|
|
bitfld.byte 0x4 0.--2. "SPNDL,SPI Next-Access Delay Setting" "0: 1 RSPCK + 2 PCLKB,1: 2 RSPCK + 2 PCLKB,?,?,?,?,?,?"
|
|
line.byte 0x5 "SPCR2,SPI Control Register 2"
|
|
bitfld.byte 0x5 4. "SCKASE,RSPCK Auto-Stop Function Enable" "0: Disable RSPCK auto-stop function,1: Enable RSPCK auto-stop function"
|
|
bitfld.byte 0x5 3. "PTE,Parity Self-Testing" "0: Disable self-diagnosis function of the parity..,1: Enable self-diagnosis function of the parity.."
|
|
newline
|
|
bitfld.byte 0x5 2. "SPIIE,SPI Idle Interrupt Enable" "0: Disable idle interrupt requests,1: Enable idle interrupt requests"
|
|
bitfld.byte 0x5 1. "SPOE,Parity Mode" "0: Select even parity for transmission and reception,1: Select odd parity for transmission and reception"
|
|
newline
|
|
bitfld.byte 0x5 0. "SPPE,Parity Enable" "0: Do not add parity bit to transmit data and do..,1: When SPCR.TXMD = 0: Add parity bit to transmit.."
|
|
group.word 0x10++0x1
|
|
line.word 0x0 "SPCMD0,SPI Command Register 0"
|
|
bitfld.word 0x0 15. "SCKDEN,RSPCK Delay Setting Enable" "0: Select RSPCK delay of 1 RSPCK,1: Select RSPCK delay equal to the setting in the.."
|
|
bitfld.word 0x0 14. "SLNDEN,SSL Negation Delay Setting Enable" "0: Select SSL negation delay of 1 RSPCK,1: Select SSL negation delay equal to the setting.."
|
|
newline
|
|
bitfld.word 0x0 13. "SPNDEN,SPI Next-Access Delay Enable" "0: Select next-access delay of 1 RSPCK + 2 PCLKB,1: Select next-access delay equal to the setting in.."
|
|
bitfld.word 0x0 12. "LSBF,SPI LSB First" "0: MSB-first,1: LSB-first"
|
|
newline
|
|
hexmask.word.byte 0x0 8.--11. 1. "SPB,SPI Data Length Setting"
|
|
bitfld.word 0x0 4.--6. "SSLA,SSL Signal Assertion Setting" "0: Setting prohibited,1: SSL1,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.word 0x0 2.--3. "BRDV,Bit Rate Division Setting" "0: Base bit rate,1: Base bit rate divided by 2,?,?"
|
|
bitfld.word 0x0 1. "CPOL,RSPCK Polarity Setting" "0: Set RSPCK low during idle,1: Set RSPCK high during idle"
|
|
newline
|
|
bitfld.word 0x0 0. "CPHA,RSPCK Phase Setting" "0: Select data sampling on leading edge data change..,1: Select data change on leading edge data sampling.."
|
|
tree.end
|
|
tree.end
|
|
tree "SRAM (SRAM Control)"
|
|
base ad:0x40002000
|
|
group.byte 0x0++0x0
|
|
line.byte 0x0 "PARIOAD,SRAM Parity Error Operation After Detection Register"
|
|
bitfld.byte 0x0 0. "OAD,Operation After Detection" "0: Non-maskable interrupt,1: Reset"
|
|
group.byte 0x4++0x0
|
|
line.byte 0x0 "SRAMPRCR,SRAM Protection Register"
|
|
hexmask.byte 0x0 1.--7. 1. "KW,Write Key Code"
|
|
bitfld.byte 0x0 0. "SRAMPRCR,Register Write Control" "0: Disable writes to protected registers,1: Enable writes to protected registers"
|
|
group.byte 0xC0++0x4
|
|
line.byte 0x0 "ECCMODE,ECC Operating Mode Control Register"
|
|
bitfld.byte 0x0 0.--1. "ECCMOD,ECC Operating Mode Select" "0: Disable ECC function,1: Setting prohibited,?,?"
|
|
line.byte 0x1 "ECC2STS,ECC 2-Bit Error Status Register"
|
|
bitfld.byte 0x1 0. "ECC2ERR,ECC 2-Bit Error Status" "0: No 2-bit ECC error occurred,1: 2-bit ECC error occurred"
|
|
line.byte 0x2 "ECC1STSEN,ECC 1-Bit Error Information Update Enable Register"
|
|
bitfld.byte 0x2 0. "E1STSEN,ECC 1-Bit Error Information Update Enable" "0: Disable updating of 1-bit ECC error information,1: Bit Error Information Update Enable"
|
|
line.byte 0x3 "ECC1STS,ECC 1-Bit Error Status Register"
|
|
bitfld.byte 0x3 0. "ECC1ERR,ECC 1-Bit Error Status" "0: No 1-bit ECC error occurred,1: Bit Error Status"
|
|
line.byte 0x4 "ECCPRCR,ECC Protection Register"
|
|
hexmask.byte 0x4 1.--7. 1. "KW,Write Key Code"
|
|
bitfld.byte 0x4 0. "ECCPRCR,Register Write Control" "0: Disable writes to the protected registers,1: Enable writes to the protected registers"
|
|
group.byte 0xD0++0x0
|
|
line.byte 0x0 "ECCPRCR2,ECC Protection Register 2"
|
|
hexmask.byte 0x0 1.--7. 1. "KW2,Write Key Code"
|
|
bitfld.byte 0x0 0. "ECCPRCR2,Register Write Control" "0: Disable writes to the protected registers,1: Enable writes to the protected registers"
|
|
group.byte 0xD4++0x0
|
|
line.byte 0x0 "ECCETST,ECC Test Control Register"
|
|
bitfld.byte 0x0 0. "TSTBYP,ECC Bypass Select" "0: Disable ECC bypass,1: Enable ECC bypass"
|
|
group.byte 0xD8++0x0
|
|
line.byte 0x0 "ECCOAD,SRAM ECC Error Operation After Detection Register"
|
|
bitfld.byte 0x0 0. "OAD,Operation After Detection" "0: Non-maskable interrupt,1: Reset"
|
|
tree.end
|
|
tree "SYSC (System Control)"
|
|
base ad:0x4001E000
|
|
group.word 0xC++0x1
|
|
line.word 0x0 "SBYCR,Standby Control Register"
|
|
bitfld.word 0x0 15. "SSBY,Software Standby Mode Select" "0: Sleep mode,1: Software Standby mode."
|
|
group.long 0x1C++0x7
|
|
line.long 0x0 "MSTPCRA,Module Stop Control Register A"
|
|
bitfld.long 0x0 22. "MSTPA22,DTC Module Stop" "0: Cancel the module-stop state,1: Enter the module-stop state"
|
|
line.long 0x4 "SCKDIVCR,System Clock Division Control Register"
|
|
bitfld.long 0x4 24.--26. "ICK,System Clock (ICLK) Select" "0: Settings prohibited,1: x 1/2,?,?,?,?,?,?"
|
|
bitfld.long 0x4 8.--10. "PCKB,Peripheral Module Clock B (PCLKB) Select" "0: Settings prohibited,1: x 1/2,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.long 0x4 0.--2. "PCKD,Peripheral Module Clock D (PCLKD) Select" "0: Settings prohibited,1: x 1/2,?,?,?,?,?,?"
|
|
group.byte 0x26++0x0
|
|
line.byte 0x0 "SCKSCR,System Clock Source Control Register"
|
|
bitfld.byte 0x0 0.--2. "CKSEL,Clock Source Select" "0: HOCO,1: MOCO,?,?,?,?,?,?"
|
|
group.byte 0x31++0x1
|
|
line.byte 0x0 "MEMWAIT,Memory Wait Cycle Control Register for Code Flash"
|
|
bitfld.byte 0x0 0. "MEMWAIT,Memory Wait Cycle Select for Code Flash" "0: No wait,1: Wait"
|
|
line.byte 0x1 "MOSCCR,Main Clock Oscillator Control Register"
|
|
bitfld.byte 0x1 0. "MOSTP,Main Clock Oscillator Stop" "0: Operate the main clock oscillator,1: Stop the main clock oscillator"
|
|
group.byte 0x36++0x0
|
|
line.byte 0x0 "HOCOCR,High-Speed On-Chip Oscillator Control Register"
|
|
bitfld.byte 0x0 0. "HCSTP,HOCO Stop" "0: Operate the HOCO clock,1: Stop the HOCO clock"
|
|
group.byte 0x38++0x0
|
|
line.byte 0x0 "MOCOCR,Middle-Speed On-Chip Oscillator Control Register"
|
|
bitfld.byte 0x0 0. "MCSTP,MOCO Stop" "0: MOCO clock is operating,1: MOCO clock is stopped"
|
|
rgroup.byte 0x3C++0x0
|
|
line.byte 0x0 "OSCSF,Oscillation Stabilization Flag Register"
|
|
bitfld.byte 0x0 3. "MOSCSF,Main Clock Oscillation Stabilization Flag" "0: The main clock oscillator is stopped (MOSTP = 1)..,1: The main clock oscillator is stable so is.."
|
|
bitfld.byte 0x0 0. "HOCOSF,HOCO Clock Oscillation Stabilization Flag" "0: The HOCO clock is stopped or is not yet stable,1: The HOCO clock is stable so is available for use.."
|
|
group.byte 0x3E++0x0
|
|
line.byte 0x0 "CKOCR,Clock Out Control Register"
|
|
bitfld.byte 0x0 7. "CKOEN,Clock Out Enable" "0: Disable clock out,1: Enable clock out"
|
|
bitfld.byte 0x0 4.--6. "CKODIV,Clock Output Frequency Division Ratio" "0: x 1/1,1: x 1/2,?,?,?,?,?,?"
|
|
newline
|
|
bitfld.byte 0x0 0.--2. "CKOSEL,Clock Out Source Select" "0: Setting prohibited,1: MOCO,?,?,?,?,?,?"
|
|
group.byte 0x40++0x1
|
|
line.byte 0x0 "OSTDCR,Oscillation Stop Detection Control Register"
|
|
bitfld.byte 0x0 7. "OSTDE,Oscillation Stop Detection Function Enable" "0: Disable oscillation stop detection function,1: Enable oscillation stop detection function"
|
|
bitfld.byte 0x0 0. "OSTDIE,Oscillation Stop Detection Interrupt Enable" "0: Disable oscillation stop detection interrupt (do..,1: Enable oscillation stop detection interrupt.."
|
|
line.byte 0x1 "OSTDSR,Oscillation Stop Detection Status Register"
|
|
bitfld.byte 0x1 0. "OSTDF,Oscillation Stop Detection Flag" "0: Main clock oscillation stop not detected,1: Main clock oscillation stop detected"
|
|
group.byte 0x4C++0x0
|
|
line.byte 0x0 "LPOPT,Lower Power Operation Control Register"
|
|
bitfld.byte 0x0 7. "LPOPTEN,Lower Power Operation Enable" "0: All lower power counter measure disable,1: All lower power counter measure enable"
|
|
bitfld.byte 0x0 3. "BPFCLKDIS,BPF Clock Disable Control" "0: Flash register R/W clock operates as normal,1: Flash register R/W clock stops."
|
|
newline
|
|
bitfld.byte 0x0 1.--2. "DCLKDIS,Debug Clock Disable Control" "0: Debug clock stops (valid only when LPOPT.LPOPTEN..,?,?,?"
|
|
bitfld.byte 0x0 0. "MPUDIS,MPU Clock Disable Control" "0: MPU operates as normal,1: MPU operate clock stops (MPU function disable)."
|
|
group.byte 0x61++0x1
|
|
line.byte 0x0 "MOCOUTCR,MOCO User Trimming Control Register"
|
|
hexmask.byte 0x0 0.--7. 1. "MOCOUTRM,MOCO User Trimming"
|
|
line.byte 0x1 "HOCOUTCR,HOCO User Trimming Control Register"
|
|
hexmask.byte 0x1 0.--7. 1. "HOCOUTRM,HOCO User Trimming"
|
|
group.byte 0x92++0x0
|
|
line.byte 0x0 "SNZCR,Snooze Control Register"
|
|
bitfld.byte 0x0 7. "SNZE,Snooze mode Enable" "0: Disable Snooze mode,1: Enable Snooze mode"
|
|
bitfld.byte 0x0 1. "SNZDTCEN,DTC Enable in Snooze mode" "0: Disable DTC operation,1: Enable DTC operation"
|
|
newline
|
|
bitfld.byte 0x0 0. "RXDREQEN,RXD0 Snooze Request Enable" "0: Ignore RXD0 falling edge in Software Standby mode,1: Detect RXD0 falling edge in Software Standby mode"
|
|
group.byte 0x94++0x0
|
|
line.byte 0x0 "SNZEDCR0,Snooze End Control Register 0"
|
|
bitfld.byte 0x0 7. "SCI0UMTED,SCI0 Address Mismatch Snooze End Enable" "0: Disable the snooze end request,1: Enable the snooze end request"
|
|
bitfld.byte 0x0 4. "AD0UMTED,ADC12 Compare Mismatch Snooze End Enable" "0: Disable the snooze end request,1: Enable the snooze end request"
|
|
newline
|
|
bitfld.byte 0x0 3. "AD0MATED,ADC12 Compare Match Snooze End Enable" "0: Disable the snooze end request,1: Enable the snooze end request"
|
|
bitfld.byte 0x0 2. "DTCNZRED,Not Last DTC Transmission Completion Snooze End Enable" "0: Disable the snooze end request,1: Enable the snooze end request"
|
|
newline
|
|
bitfld.byte 0x0 1. "DTCZRED,Last DTC Transmission Completion Snooze End Enable" "0: Disable the snooze end request,1: Enable the snooze end request"
|
|
bitfld.byte 0x0 0. "AGTUNFED,AGT1 Underflow Snooze End Enable" "0: Disable the snooze end request,1: Enable the snooze end request"
|
|
group.long 0x98++0x3
|
|
line.long 0x0 "SNZREQCR0,Snooze Request Control Register 0"
|
|
bitfld.long 0x0 30. "SNZREQEN30,Enable AGT1 compare match B snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
bitfld.long 0x0 29. "SNZREQEN29,Enable AGT1 compare match A snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
newline
|
|
bitfld.long 0x0 28. "SNZREQEN28,Enable AGT1 underflow snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
bitfld.long 0x0 25. "SNZREQEN25,Enable RTC period snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
newline
|
|
bitfld.long 0x0 24. "SNZREQEN24,Enable RTC alarm snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
bitfld.long 0x0 23. "SNZREQEN23,Enable ACMPLP snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
newline
|
|
bitfld.long 0x0 17. "SNZREQEN17,Enable KEY_INTKR snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
bitfld.long 0x0 7. "SNZREQEN7,Enable IRQ7 pin snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
newline
|
|
bitfld.long 0x0 6. "SNZREQEN6,Enable IRQ6 pin snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
bitfld.long 0x0 5. "SNZREQEN5,Enable IRQ5 pin snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
newline
|
|
bitfld.long 0x0 4. "SNZREQEN4,Enable IRQ4 pin snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
bitfld.long 0x0 3. "SNZREQEN3,Enable IRQ3 pin snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
newline
|
|
bitfld.long 0x0 2. "SNZREQEN2,Enable IRQ2 pin snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
bitfld.long 0x0 1. "SNZREQEN1,Enable IRQ1 pin snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
newline
|
|
bitfld.long 0x0 0. "SNZREQEN0,Enable IRQ0 pin snooze request" "0: Disable the snooze request,1: Enable the snooze request"
|
|
group.byte 0x9F++0x1
|
|
line.byte 0x0 "PSMCR,Power Save Memory Control Register"
|
|
bitfld.byte 0x0 0.--1. "PSMC,Power Save Memory Control" "0: All SRAMs are on in Software Standby mode,1: 8 KB SRAM (0x2000_4000 to 0x2000_5FFF) is on in..,?,?"
|
|
line.byte 0x1 "OPCCR,Operating Power Control Register"
|
|
rbitfld.byte 0x1 4. "OPCMTSF,Operating Power Control Mode Transition Status Flag" "0: Transition completed,1: During transition"
|
|
bitfld.byte 0x1 0.--1. "OPCM,Operating Power Control Mode Select" "0: High-speed mode,1: Middle-speed mode,?,?"
|
|
group.byte 0xA2++0x0
|
|
line.byte 0x0 "MOSCWTCR,Main Clock Oscillator Wait Control Register"
|
|
hexmask.byte 0x0 0.--3. 1. "MSTS,Main Clock Oscillator Wait Time Setting"
|
|
group.byte 0xAA++0x0
|
|
line.byte 0x0 "SOPCCR,Sub Operating Power Control Register"
|
|
rbitfld.byte 0x0 4. "SOPCMTSF,Operating Power Control Mode Transition Status Flag" "0: Transition completed,1: During transition"
|
|
bitfld.byte 0x0 0. "SOPCM,Sub Operating Power Control Mode Select" "0: Other than Subosc-speed mode,1: Subosc-speed mode"
|
|
group.word 0xC0++0x1
|
|
line.word 0x0 "RSTSR1,Reset Status Register 1"
|
|
bitfld.word 0x0 12. "SPERF,CPU Stack Pointer Error Reset Detect Flag" "0: CPU stack pointer error reset not detected,1: CPU stack pointer error reset detected"
|
|
bitfld.word 0x0 11. "BUSMRF,Bus Master MPU Error Reset Detect Flag" "0: Bus master MPU error reset not detected,1: Bus master MPU error reset detected"
|
|
newline
|
|
bitfld.word 0x0 10. "BUSSRF,Bus Slave MPU Error Reset Detect Flag" "0: Bus slave MPU error reset not detected,1: Bus slave MPU error reset detected"
|
|
bitfld.word 0x0 9. "REERF,SRAM ECC Error Reset Detect Flag" "0: SRAM ECC error reset not detected,1: SRAM ECC error reset detected"
|
|
newline
|
|
bitfld.word 0x0 8. "RPERF,SRAM Parity Error Reset Detect Flag" "0: SRAM parity error reset not detected,1: SRAM parity error reset detected"
|
|
bitfld.word 0x0 2. "SWRF,Software Reset Detect Flag" "0: Software reset not detected,1: Software reset detected"
|
|
newline
|
|
bitfld.word 0x0 1. "WDTRF,Watchdog Timer Reset Detect Flag" "0: Watchdog timer reset not detected,1: Watchdog timer reset detected"
|
|
bitfld.word 0x0 0. "IWDTRF,Independent Watchdog Timer Reset Detect Flag" "0: Independent watchdog timer reset not detected,1: Independent watchdog timer reset detected"
|
|
group.byte 0xE0++0x3
|
|
line.byte 0x0 "LVD1CR1,Voltage Monitor 1 Circuit Control Register"
|
|
bitfld.byte 0x0 2. "IRQSEL,Voltage Monitor 1 Interrupt Type Select" "0: Non-maskable interrupt,1: Maskable interrupt"
|
|
bitfld.byte 0x0 0.--1. "IDTSEL,Voltage Monitor 1 Interrupt Generation Condition Select" "0: When VCC >= Vdet1 (rise) is detected,1: When VCC < Vdet1 (fall) is detected,?,?"
|
|
line.byte 0x1 "LVD1SR,Voltage Monitor 1 Circuit Status Register"
|
|
rbitfld.byte 0x1 1. "MON,Voltage Monitor 1 Signal Monitor Flag" "0: VCC < Vdet1,1: VCC >= Vdet1 or MON is disabled"
|
|
bitfld.byte 0x1 0. "DET,Voltage Monitor 1 Voltage Variation Detection Flag" "0: Not detected,1: Vdet1 crossing is detected"
|
|
line.byte 0x2 "LVD2CR1,Voltage Monitor 2 Circuit Control Register 1"
|
|
bitfld.byte 0x2 2. "IRQSEL,Voltage Monitor 2 Interrupt Type Select" "0: Non-maskable interrupt,1: Maskable interrupt"
|
|
bitfld.byte 0x2 0.--1. "IDTSEL,Voltage Monitor 2 Interrupt Generation Condition Select" "0: When VCC>= Vdet2 (rise) is detected,1: When VCC < Vdet2 (fall) is detected,?,?"
|
|
line.byte 0x3 "LVD2SR,Voltage Monitor 2 Circuit Status Register"
|
|
rbitfld.byte 0x3 1. "MON,Voltage Monitor 2 Signal Monitor Flag" "0: VCC < Vdet2,1: VCC>= Vdet2 or MON is disabled"
|
|
bitfld.byte 0x3 0. "DET,Voltage Monitor 2 Voltage Variation Detection Flag" "0: Not detected,1: Vdet2 crossing is detected"
|
|
group.word 0x3FE++0x1
|
|
line.word 0x0 "PRCR,Protect Register"
|
|
hexmask.word.byte 0x0 8.--15. 1. "PRKEY,PRC Key Code"
|
|
bitfld.word 0x0 3. "PRC3,Enable writing to the registers related to the LVD" "0: Disable writes,1: Enable writes"
|
|
newline
|
|
bitfld.word 0x0 1. "PRC1,Enable writing to the registers related to the low power modes" "0: Disable writes,1: Enable writes"
|
|
bitfld.word 0x0 0. "PRC0,Enable writing to the registers related to the clock generation circuit" "0: Disable writes,1: Enable writes"
|
|
group.byte 0x40E++0x0
|
|
line.byte 0x0 "SYOCDCR,System Control OCD Control Register"
|
|
bitfld.byte 0x0 7. "DBGEN,Debugger Enable bit" "0: On-chip debugger is disabled,1: On-chip debugger is enabled"
|
|
group.byte 0x410++0x1
|
|
line.byte 0x0 "RSTSR0,Reset Status Register 0"
|
|
bitfld.byte 0x0 3. "LVD2RF,Voltage Monitor 2 Reset Detect Flag" "0: Voltage monitor 2 reset not detected,1: Voltage monitor 2 reset detected"
|
|
bitfld.byte 0x0 2. "LVD1RF,Voltage Monitor 1 Reset Detect Flag" "0: Voltage monitor 1 reset not detected,1: Voltage monitor 1 reset detected"
|
|
newline
|
|
bitfld.byte 0x0 1. "LVD0RF,Voltage Monitor 0 Reset Detect Flag" "0: Voltage monitor 0 reset not detected,1: Voltage monitor 0 reset detected"
|
|
bitfld.byte 0x0 0. "PORF,Power-On Reset Detect Flag" "0: Power-on reset not detected,1: Power-on reset detected"
|
|
line.byte 0x1 "RSTSR2,Reset Status Register 2"
|
|
bitfld.byte 0x1 0. "CWSF,Cold/Warm Start Determination Flag" "0: Cold start,1: Warm start"
|
|
group.byte 0x413++0x0
|
|
line.byte 0x0 "MOMCR,Main Clock Oscillator Mode Oscillation Control Register"
|
|
bitfld.byte 0x0 6. "MOSEL,Main Clock Oscillator Switching" "0: Resonator,1: External clock input"
|
|
bitfld.byte 0x0 3. "MODRV1,Main Clock Oscillator Drive Capability 1 Switching" "0: 10 MHz to 20 MHz,1: 1 MHz to 10 MHz"
|
|
group.byte 0x417++0x1
|
|
line.byte 0x0 "LVCMPCR,Voltage Monitor Circuit Control Register"
|
|
bitfld.byte 0x0 6. "LVD2E,Voltage Detection 2 Enable" "0: Voltage detection 2 circuit disabled,1: Voltage detection 2 circuit enabled"
|
|
bitfld.byte 0x0 5. "LVD1E,Voltage Detection 1 Enable" "0: Voltage detection 1 circuit disabled,1: Voltage detection 1 circuit enabled"
|
|
line.byte 0x1 "LVDLVLR,Voltage Detection Level Select Register"
|
|
bitfld.byte 0x1 5.--7. "LVD2LVL,Voltage Detection 2 Level Select (Standard voltage during fall in voltage)" "0: Setting prohibited,1: Vdet2_1,?,?,?,?,?,?"
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hexmask.byte 0x1 0.--4. 1. "LVD1LVL,Voltage Detection 1 Level Select (Standard voltage during fall in voltage)"
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group.byte 0x41A++0x1
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line.byte 0x0 "LVD1CR0,Voltage Monitor 1 Circuit Control Register 0"
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bitfld.byte 0x0 7. "RN,Voltage Monitor 1 Reset Negate Select" "0: Negate after a stabilization time (tLVD1) when..,1: Negate after a stabilization time (tLVD1) on.."
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bitfld.byte 0x0 6. "RI,Voltage Monitor 1 Circuit Mode Select" "0: Generate voltage monitor 1 interrupt on Vdet1..,1: Enable voltage monitor 1 reset when the voltage.."
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newline
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bitfld.byte 0x0 2. "CMPE,Voltage Monitor 1 Circuit Comparison Result Output Enable" "0: Disable voltage monitor 1 circuit comparison..,1: Enable voltage monitor 1 circuit comparison.."
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bitfld.byte 0x0 0. "RIE,Voltage Monitor 1 Interrupt/Reset Enable" "0: Disable,1: Enable"
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line.byte 0x1 "LVD2CR0,Voltage Monitor 2 Circuit Control Register 0"
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bitfld.byte 0x1 7. "RN,Voltage Monitor 2 Reset Negate Select" "0: Negate after a stabilization time (tLVD2) when..,1: Negate after a stabilization time (tLVD2) on.."
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bitfld.byte 0x1 6. "RI,Voltage Monitor 2 Circuit Mode Select" "0: Generate voltage monitor 2 interrupt on Vdet2..,1: Enable voltage monitor 2 reset when the voltage.."
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newline
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bitfld.byte 0x1 2. "CMPE,Voltage Monitor 2 Circuit Comparison Result Output Enable" "0: Disable voltage monitor 2 circuit comparison..,1: Enable voltage monitor 2 circuit comparison.."
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bitfld.byte 0x1 0. "RIE,Voltage Monitor 2 Interrupt/Reset Enable" "0: Disable,1: Enable"
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group.byte 0x440++0x1
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line.byte 0x0 "DCDCCTL,DCDC/LDO Control Register"
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bitfld.byte 0x0 7. "PD,DCDC VREF Generate Disable bit" "0: DCDC VREF BIAS output enable,1: DCDC VREF BIAS output disable"
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bitfld.byte 0x0 6. "FST,DCDC Fast Startup" "0: Fast startupBecause it is a circuit-oriented..,1: Not fast startupBecause it is a circuit-oriented.."
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newline
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bitfld.byte 0x0 5. "LCBOOST,LDO LCBOOST Mode Control bit" "0: LDO power mode is other than LCBOOST,1: LDO power mode is in LCBOOST"
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bitfld.byte 0x0 4. "STOPZA,DCDC IO Buffer Power Control bit" "0: DCDC IO buffer power down,1: DCDC IO buffer power up"
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newline
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bitfld.byte 0x0 1. "OCPEN,DCDC OCP Function Enable bit" "0: DCDC OCP (Over Current Protection) Function..,1: DCDC OCP (Over Current Protection) Function enable"
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bitfld.byte 0x0 0. "DCDCON,LDO/DCDC on/off Control bit" "0: LDO is on and DCDC is off,1: LDO is off and DCDC is on"
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line.byte 0x1 "VCCSEL,Voltage Level Selection Control Register"
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bitfld.byte 0x1 0.--1. "VCCSEL,DCDC Working Voltage Level Selection" "0: 2.7 V =< VCC < 3.6 V,1: 3.6 V =< VCC < 4.5 V,?,?"
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group.byte 0x480++0x2
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line.byte 0x0 "SOSCCR,Sub-Clock Oscillator Control Register"
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bitfld.byte 0x0 0. "SOSTP,Sub Clock Oscillator Stop" "0: Operate the sub-clock oscillator,1: Stop the sub-clock oscillator"
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line.byte 0x1 "SOMCR,Sub-Clock Oscillator Mode Control Register"
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bitfld.byte 0x1 0.--1. "SODRV,Sub-Clock Oscillator Drive Capability Switching" "0: Normal Mode,1: Low Power Mode 1,?,?"
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line.byte 0x2 "SOMRG,Sub-Clock Oscillator Margin Check Register"
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bitfld.byte 0x2 0.--1. "SOSCMRG,Sub Clock Oscillator Margin check Switching" "0: Normal Current,1: Lower Margin check,?,?"
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group.byte 0x490++0x0
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line.byte 0x0 "LOCOCR,Low-Speed On-Chip Oscillator Control Register"
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bitfld.byte 0x0 0. "LCSTP,LOCO Stop" "0: Operate the LOCO clock,1: Stop the LOCO clock"
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group.byte 0x492++0x0
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line.byte 0x0 "LOCOUTCR,LOCO User Trimming Control Register"
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hexmask.byte 0x0 0.--7. 1. "LOCOUTRM,LOCO User Trimming"
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tree.end
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tree "WDT (Watchdog Timer)"
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base ad:0x40044200
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group.byte 0x0++0x0
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line.byte 0x0 "WDTRR,WDT Refresh Register"
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group.word 0x2++0x3
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line.word 0x0 "WDTCR,WDT Control Register"
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bitfld.word 0x0 12.--13. "RPSS,Window Start Position Select" "0: 25%,1: 50%,?,?"
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bitfld.word 0x0 8.--9. "RPES,Window End Position Select" "0: 75%,1: 50%,?,?"
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hexmask.word.byte 0x0 4.--7. 1. "CKS,Clock Division Ratio Select"
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bitfld.word 0x0 0.--1. "TOPS,Timeout Period Select" "0: 1024 cycles (0x03FF),1: 4096 cycles (0x0FFF),?,?"
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line.word 0x2 "WDTSR,WDT Status Register"
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bitfld.word 0x2 15. "REFEF,Refresh Error Flag" "0: No refresh error occurred,1: Refresh error occurred"
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bitfld.word 0x2 14. "UNDFF,Underflow Flag" "0: No underflow occurred,1: Underflow occurred"
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hexmask.word 0x2 0.--13. 1. "CNTVAL,Down-Counter Value"
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group.byte 0x6++0x0
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line.byte 0x0 "WDTRCR,WDT Reset Control Register"
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bitfld.byte 0x0 7. "RSTIRQS,WDT Behavior Selection" "0: Interrupt,1: Reset"
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group.byte 0x8++0x0
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line.byte 0x0 "WDTCSTPR,WDT Count Stop Control Register"
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bitfld.byte 0x0 7. "SLCSTP,Sleep-Mode Count Stop Control Register" "0: Disable count stop,1: Stop count on transition to Sleep mode"
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tree.end
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AUTOINDENT.OFF
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