13834 lines
948 KiB
Plaintext
13834 lines
948 KiB
Plaintext
; --------------------------------------------------------------------------------
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; @Title: RF7FS1 On-Chip Peripherals
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; @Props: Released
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; @Author: AST, WIL
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; @Changelog: 2016-10-12 WIL
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; @Manufacturer: RENESAS - Renesas Technology, Corp.
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; @Doc: r01um0003eu0100_synergy_s124.pdf (Rev.1 2016-02)
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; @Chip: R7FS124762A01CLM, R7FS124763A01CFL, R7FS124763A01CFM, R7FS124763A01CNB,
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; R7FS124763A01CNE, R7FS124763A01CNF, R7FS124772A01CLM, R7FS124773A01CFL,
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; R7FS124773A01CFM, R7FS124773A01CNB, R7FS124773A01CNE, R7FS124773A01CNF,
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; @Core: Cortex-M0P
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; @Copyright: (C) 1989-2016 Lauterbach GmbH, licensed for use with TRACE32(R) only
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; --------------------------------------------------------------------------------
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; $Id: perr7fs1.per 7408 2016-10-29 12:43:37Z askoncej $
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;
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; Known problems:
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; Low power modes(SNZREQCR) probably wrong description of bits ex. [SNZREQEN28 - Snooze Request Enable 26]
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config 16. 8.
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base ad:0x0
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tree.close "Core Registers (Cortex-M0+)"
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AUTOINDENT.PUSH
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AUTOINDENT.OFF
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tree "System Control"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 0x8
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if (CORENAME()=="CORTEXM1")
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "No effect,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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else
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group.long 0x10++0x0b
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line.long 0x00 "STCSR,SysTick Control and Status Register"
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bitfld.long 0x00 16. " COUNTFLAG ,Returns 1 if timer counted to 0" "0,1"
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bitfld.long 0x00 2. " CLKSOURCE ,Always reads as one" "External clock,Processor clock"
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textline " "
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bitfld.long 0x00 1. " TICKINT ,Counting down to 0 " "No SysTick,SysTick"
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bitfld.long 0x00 0. " ENABLE ,Counter enable" "Disabled,Enabled"
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line.long 0x04 "STRVR,SysTick Reload Value Register"
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hexmask.long.tbyte 0x04 0.--23. 1. " RELOAD ,Value to load into the STCVR when the counter reaches 0"
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line.long 0x08 "STCVR,SysTick Current Value Register"
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hexmask.long.tbyte 0x08 0.--23. 1. " CURRENT ,Reads return the current value of the SysTick counter"
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endif
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if (CORENAME()=="CORTEXM1")
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Reads as one" "0,1"
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bitfld.long 0x00 30. " SKEW ,Reads as zero" "0,1"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Indicates calibration value is not known"
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else
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rgroup.long 0x1c++0x03
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line.long 0x00 "STCR,SysTick Calibration Value Register"
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bitfld.long 0x00 31. " NOREF ,Indicates whether the IMPL_DEF reference clock is provided" "Implemented,Not implemented"
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bitfld.long 0x00 30. " SKEW ,Indicates whether the 10ms calibration value is exact" "Exact,Inexact"
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textline " "
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hexmask.long.tbyte 0x00 0.--23. 1. " TENMS ,Holds a reload value to be used for 10ms (100Hz) timing subject to system clock skew errors"
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endif
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rgroup.long 0xd00++0x03
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line.long 0x00 "CPUID,CPU ID Base Register"
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hexmask.long.byte 0x00 24.--31. 1. " IMPLEMENTER ,Implementer code"
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hexmask.long.byte 0x00 20.--23. 1. " VARIANT ,Implementation defined variant number"
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textline " "
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hexmask.long.byte 0x00 4.--15. 1. " PARTNO ,Number of processor within family"
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hexmask.long.byte 0x00 0.--3. 1. " REVISION ,Implementation defined revision number"
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group.long 0xd04++0x03
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line.long 0x00 "ICSR,Interrupt Control State Register"
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bitfld.long 0x00 31. " NMIPENDSET ,Setting this bit will activate an NMI" "No effect,Set pending"
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bitfld.long 0x00 28. " PENDSVSET ,Set a pending PendSV interrupt" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 27. " PENDSVCLR ,Clear a pending PendSV interrupt" "No effect,Clear pending"
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bitfld.long 0x00 26. " PENDSTSET ,Set a pending SysTick" "No effect,Set pending"
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textline " "
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bitfld.long 0x00 25. " PENDSVCLR ,Clear a pending SysTick" "No effect,Clear pending"
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bitfld.long 0x00 23. " ISRPREEMPT ,Pending exception service" "No service,Service"
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textline " "
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bitfld.long 0x00 22. " ISRPENDING ,External interrupt pending flag" "No interrupt,Interrupt"
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hexmask.long.byte 0x00 12.--17. 1. " VECTPENDING ,Active exception number field"
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textline " "
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hexmask.long.byte 0x00 0.--5. 1. " VECTACTIVET ,Active exception number field"
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if (CORENAME()=="CORTEXM0+")
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group.long 0xd08++0x03
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line.long 0x00 "VTOR,Vector Table Offset Register"
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hexmask.long 0x00 7.--31. 0x80 " TBLOFF ,Vector table address"
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else
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textline " "
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endif
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group.long 0xd0c++0x03
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line.long 0x00 "AIRCR,Application Interrupt and Reset Control Register"
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hexmask.long.word 0x00 16.--31. 1. " VECTKEY ,Vector Key"
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bitfld.long 0x00 15. " ENDIANNESS ,Data endianness bit" "Little-endian,Big-endian"
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textline " "
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bitfld.long 0x00 2. " SYSRESETREQ ,System reset setup request" "No effect,Reset"
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bitfld.long 0x00 1. " VECTCLRACTIVE ,Clears all active state information" "No clear,Clear"
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group.long 0xd10++0x03
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line.long 0x00 "SCR,System Control Register"
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bitfld.long 0x00 4. " SEVONPEND ,Determines whether an interrupt transition from inactive state to pending state is a wakeup event" "Not wakeup,Wakeup"
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bitfld.long 0x00 2. " SLEEPDEEP ,Provides a qualifying hint indicating that waking from sleep might take longer" "Not deep sleep,Deep sleep"
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textline " "
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bitfld.long 0x00 1. " SLEEPONEXIT ,Determines whether, on an exit from an ISR that returns to the base level of execution priority, the processor enters a sleep state" "Disabled,Enabled"
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rgroup.long 0xd14++0x03
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line.long 0x00 "CCR,Configuration and Control Register"
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bitfld.long 0x00 9. " STKALIGN ,Indicates whether on exception entry all exceptions are entered with 8-byte stack alignment and the context to restore it is saved" "Reserved,Aligned"
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bitfld.long 0x00 3. " UNALIGN_TRP ,Indicates that all unaligned accesses results in a Hard Fault" "Reserved,Trapped"
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group.long 0xd1c++0x0b
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line.long 0x00 "SHPR2,System Handler Priority Register 2"
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bitfld.long 0x00 30.--31. " PRI_11 ,Priority of system handler 11-SVCall" "00,01,10,11"
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line.long 0x04 "SHPR3,System Handler Priority Register 3"
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bitfld.long 0x04 30.--31. " PRI_15 ,Priority of system handler 15-SysTick" "00,01,10,11"
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bitfld.long 0x04 22.--23. " PRI_14 ,Priority of system handler 14- PendSV" "00,01,10,11"
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line.long 0x08 "SHCSR,System Handler Control and State Register"
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bitfld.long 0x08 15. " SVCALLPENDED ,Reads as 1 if SVCall is pending" "Not pending,Pending"
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if (CORENAME()=="CORTEXM0+")
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hgroup.long 0x08++0x03
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hide.long 0x00 "ACTLR,Auxiliary Control Register"
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else
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textline " "
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endif
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else
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newline
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textline "COREDEBUG component base address not specified"
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newline
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endif
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tree.end
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tree "Memory Protection Unit (MPU)"
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sif COMPonent.AVAILABLE("COREDEBUG")
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base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
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width 15.
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rgroup.long 0xD90++0x03
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line.long 0x00 "MPU_TYPE,MPU Type Register"
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bitfld.long 0x00 8.--15. 1. " DREGION ,Number of regions supported by the MPU" "0,1,2,3,4,5,6,7,8,?..."
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group.long 0xD94++0x03
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line.long 0x00 "MPU_CTRL,MPU Control Register"
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bitfld.long 0x00 2. " PRIVDEFENA ,Enables the default memory map as a background region for privileged access" "Disabled,Enabled"
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bitfld.long 0x00 1. " HFNMIENA ,Handlers executing with priority less than 0 access memory with the MPU enabled or with the MPU disabled" "MPU disabled,MPU enabled"
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bitfld.long 0x00 0. " ENABLE ,Enables the MPU" "Disabled,Enabled"
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group.long 0xD98++0x03
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line.long 0x00 "MPU_RNR,MPU Region Number Register"
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hexmask.long.byte 0x00 0.--7. 1. " REGION ,Indicates the memory region accessed by MPU_RBAR and MPU_RASR"
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tree.close "MPU regions"
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x0
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group.long 0xD9C++0x03 "Region 0"
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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line.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 0 (not implemented)"
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RBAR0,MPU Region Base Address Register 0"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x0
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hide.long 0x00 "MPU_RASR0,MPU Region Attribute and Size Register 0"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x1
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group.long 0xD9C++0x03 "Region 1"
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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line.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 1 (not implemented)"
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RBAR1,MPU Region Base Address Register 1"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x1
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hide.long 0x00 "MPU_RASR1,MPU Region Attribute and Size Register 1"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x2
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group.long 0xD9C++0x03 "Region 2"
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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line.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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hgroup.long 0xD9C++0x03 "Region 2 (not implemented)"
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saveout 0xD98 %l 0x2
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hide.long 0x00 "MPU_RBAR2,MPU Region Base Address Register 2"
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hgroup.long 0xDA0++0x03
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saveout 0xD98 %l 0x2
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hide.long 0x00 "MPU_RASR2,MPU Region Attribute and Size Register 2"
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textline " "
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textline " "
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endif
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if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x3
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group.long 0xD9C++0x03 "Region 3"
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saveout 0xD98 %l 0x3
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line.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
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hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
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group.long 0xDA0++0x03
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saveout 0xD98 %l 0x3
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line.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
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bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
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bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
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bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
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textline " "
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bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
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bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
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bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
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textline " "
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bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
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bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
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bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
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bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
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bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
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bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
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bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
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bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
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bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
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bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
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else
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|
hgroup.long 0xD9C++0x03 "Region 3 (not implemented)"
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saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RBAR3,MPU Region Base Address Register 3"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x3
|
|
hide.long 0x00 "MPU_RASR3,MPU Region Attribute and Size Register 3"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x4
|
|
group.long 0xD9C++0x03 "Region 4"
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
line.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 4 (not implemented)"
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RBAR4,MPU Region Base Address Register 4"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x4
|
|
hide.long 0x00 "MPU_RASR4,MPU Region Attribute and Size Register 4"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x5
|
|
group.long 0xD9C++0x03 "Region 5"
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
line.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 5 (not implemented)"
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RBAR5,MPU Region Base Address Register 5"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x5
|
|
hide.long 0x00 "MPU_RASR5,MPU Region Attribute and Size Register 5"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x6
|
|
group.long 0xD9C++0x03 "Region 6"
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
line.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 6 (not implemented)"
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RBAR6,MPU Region Base Address Register 6"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x6
|
|
hide.long 0x00 "MPU_RASR6,MPU Region Attribute and Size Register 6"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
if ((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xD90)&0xff00)>>8)>0x7
|
|
group.long 0xD9C++0x03 "Region 7"
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hexmask.long 0x00 8.--31. 0x20 " ADDR ,Base address of the region"
|
|
group.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
line.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
bitfld.long 0x00 28. " XN ,eXecute Never" "Execute,Not execute"
|
|
bitfld.long 0x00 24.--26. " AP ,Data Access Permission" "No access,S:RW U:--,S:RW U:R-,S:RW U:RR,reserved,S:R- U:--,S:R- U:R-,S:R- U:R-"
|
|
bitfld.long 0x00 19.--21. " TEX ,Type Extension Field" "0,1,2,3,4,5,6,7"
|
|
textline " "
|
|
bitfld.long 0x00 18. " S ,Shareable Bit" "Not shareable,Shareable"
|
|
bitfld.long 0x00 17. " C ,Cacheable Bit" "Not cacheable,Cacheable"
|
|
bitfld.long 0x00 16. " B ,Bufferable Bit" "Not bufferable,Bufferable"
|
|
textline " "
|
|
bitfld.long 0x00 15. " SRD[7..0] ,Subregion 7 Disable" "0,1"
|
|
bitfld.long 0x00 14. ",Subregion 6 Disable" "0,1"
|
|
bitfld.long 0x00 13. ",Subregion 5 Disable" "0,1"
|
|
bitfld.long 0x00 12. ",Subregion 4 Disable" "0,1"
|
|
bitfld.long 0x00 11. ",Subregion 3 Disable" "0,1"
|
|
bitfld.long 0x00 10. ",Subregion 2 Disable" "0,1"
|
|
bitfld.long 0x00 9. ",Subregion 1 Disabled" "0,1"
|
|
bitfld.long 0x00 8. ",Subregion 0 Disable" "0,1"
|
|
bitfld.long 0x00 1.--5. " SIZE ,Indicates the region size" "-,-,-,-,-,-,-,256 B,512 B,1 kB,2 kB,4 kB,8 kB,16 kB,32 kB,64 kB,128 kB,256 kB,512 kB,1 MB,2 MB,4 MB,8 MB,16 MB,32 MB,64 MB,128 MB,256 MB,512 MB,1 GB,2 GB,4 GB"
|
|
bitfld.long 0x00 0. " ENABLE ,Enables this region" "Disabled,Enabled"
|
|
else
|
|
hgroup.long 0xD9C++0x03 "Region 7 (not implemented)"
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RBAR7,MPU Region Base Address Register 7"
|
|
hgroup.long 0xDA0++0x03
|
|
saveout 0xD98 %l 0x7
|
|
hide.long 0x00 "MPU_RASR7,MPU Region Attribute and Size Register 7"
|
|
textline " "
|
|
textline " "
|
|
endif
|
|
tree.end
|
|
width 0x0b
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Nested Vectored Interrupt Controller (NVIC)"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 12.
|
|
tree "Interrupt Enable Registers"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "SET/CLREN,Interrupt Set/Clear Enable Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENA31 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENA30 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENA29 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENA28 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENA27 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENA26 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENA25 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENA24 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENA23 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENA22 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENA21 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENA20 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENA19 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENA18 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENA17 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENA16 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENA15 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENA14 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENA13 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENA12 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENA11 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENA10 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENA9 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENA8 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENA7 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENA6 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENA5 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENA4 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENA3 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENA2 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENA1 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENA0 ,Interrupt Set/Clear Enable Bit" "Disabled,Enabled"
|
|
tree.end
|
|
tree "Interrupt Pending Registers"
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "SET/CLRPEN,Interrupt Set/Clear Pending Register"
|
|
setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEN31 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEN30 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEN29 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEN28 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEN27 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEN26 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEN25 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEN24 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEN23 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEN22 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEN21 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEN20 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEN19 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEN18 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEN17 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEN16 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEN15 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEN14 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEN13 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEN12 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEN11 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEN10 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEN9 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEN8 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEN7 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEN6 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEN5 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEN4 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEN3 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEN2 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
textline " "
|
|
setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEN1 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEN0 ,Interrupt Set/Clear Pending" "Not pending,Pending"
|
|
tree.end
|
|
width 6.
|
|
tree "Interrupt Priority Registers"
|
|
group.long 0x400++0x1F
|
|
line.long 0x00 "INT0,Interrupt Priority Register"
|
|
bitfld.long 0x00 30.--31. " IP_3 ,Priority of interrupt 3" "0,1,2,3"
|
|
bitfld.long 0x00 22.--23. " IP_2 ,Priority of interrupt 2" "0,1,2,3"
|
|
bitfld.long 0x00 14.--15. " IP_1 ,Priority of interrupt 1" "0,1,2,3"
|
|
bitfld.long 0x00 6.--7. " IP_0 ,Priority of interrupt 0" "0,1,2,3"
|
|
line.long 0x04 "INT1,Interrupt Priority Register"
|
|
bitfld.long 0x04 30.--31. " IP_7 ,Priority of interrupt 7" "0,1,2,3"
|
|
bitfld.long 0x04 22.--23. " IP_6 ,Priority of interrupt 6" "0,1,2,3"
|
|
bitfld.long 0x04 14.--15. " IP_5 ,Priority of interrupt 5" "0,1,2,3"
|
|
bitfld.long 0x04 6.--7. " IP_4 ,Priority of interrupt 4" "0,1,2,3"
|
|
line.long 0x08 "INT2,Interrupt Priority Register"
|
|
bitfld.long 0x08 30.--31. " IP_11 ,Priority of interrupt 11" "0,1,2,3"
|
|
bitfld.long 0x08 22.--23. " IP_10 ,Priority of interrupt 10" "0,1,2,3"
|
|
bitfld.long 0x08 14.--15. " IP_9 ,Priority of interrupt 9" "0,1,2,3"
|
|
bitfld.long 0x08 6.--7. " IP_8 ,Priority of interrupt 8" "0,1,2,3"
|
|
line.long 0x0C "INT3,Interrupt Priority Register"
|
|
bitfld.long 0x0C 30.--31. " IP_15 ,Priority of interrupt 15" "0,1,2,3"
|
|
bitfld.long 0x0C 22.--23. " IP_14 ,Priority of interrupt 14" "0,1,2,3"
|
|
bitfld.long 0x0C 14.--15. " IP_13 ,Priority of interrupt 13" "0,1,2,3"
|
|
bitfld.long 0x0C 6.--7. " IP_12 ,Priority of interrupt 12" "0,1,2,3"
|
|
line.long 0x10 "INT4,Interrupt Priority Register"
|
|
bitfld.long 0x10 30.--31. " IP_19 ,Priority of interrupt 19" "0,1,2,3"
|
|
bitfld.long 0x10 22.--23. " IP_18 ,Priority of interrupt 18" "0,1,2,3"
|
|
bitfld.long 0x10 14.--15. " IP_17 ,Priority of interrupt 17" "0,1,2,3"
|
|
bitfld.long 0x10 6.--7. " IP_16 ,Priority of interrupt 16" "0,1,2,3"
|
|
line.long 0x14 "INT5,Interrupt Priority Register"
|
|
bitfld.long 0x14 30.--31. " IP_23 ,Priority of interrupt 23" "0,1,2,3"
|
|
bitfld.long 0x14 22.--23. " IP_22 ,Priority of interrupt 22" "0,1,2,3"
|
|
bitfld.long 0x14 14.--15. " IP_21 ,Priority of interrupt 21" "0,1,2,3"
|
|
bitfld.long 0x14 6.--7. " IP_20 ,Priority of interrupt 20" "0,1,2,3"
|
|
line.long 0x18 "INT6,Interrupt Priority Register"
|
|
bitfld.long 0x18 30.--31. " IP_27 ,Priority of interrupt 27" "0,1,2,3"
|
|
bitfld.long 0x18 22.--23. " IP_26 ,Priority of interrupt 26" "0,1,2,3"
|
|
bitfld.long 0x18 14.--15. " IP_25 ,Priority of interrupt 25" "0,1,2,3"
|
|
bitfld.long 0x18 6.--7. " IP_24 ,Priority of interrupt 24" "0,1,2,3"
|
|
line.long 0x1C "INT7,Interrupt Priority Register"
|
|
bitfld.long 0x1C 30.--31. " IP_31 ,Priority of interrupt 31" "0,1,2,3"
|
|
bitfld.long 0x1C 22.--23. " IP_30 ,Priority of interrupt 30" "0,1,2,3"
|
|
bitfld.long 0x1C 14.--15. " IP_29 ,Priority of interrupt 29" "0,1,2,3"
|
|
bitfld.long 0x1C 6.--7. " IP_28 ,Priority of interrupt 28" "0,1,2,3"
|
|
tree.end
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Debug"
|
|
tree "Core Debug"
|
|
sif COMPonent.AVAILABLE("COREDEBUG")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))
|
|
width 0xA
|
|
group.long 0xD30++0x03
|
|
line.long 0x00 "DFSR,Data Fault Status Register"
|
|
eventfld.long 0x00 4. " EXTERNAL ,External debug request flag" "No occurred,Occurred"
|
|
eventfld.long 0x00 3. " VCATCH ,Vector catch flag" "No occurred,Occurred"
|
|
textline " "
|
|
eventfld.long 0x00 2. " DWTRAP ,Data Watchpoint flag" "No match,Match"
|
|
textline " "
|
|
eventfld.long 0x00 1. " BKPT ,BKPT flag" "No match,Match"
|
|
eventfld.long 0x00 0. " HALTED ,Halt request flag" "No request,Request"
|
|
if (CORENAME()=="CORTEXM1")
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 18. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
else
|
|
if (((per.l(CONvert.ADDRESSTODUALPORT(COMPonent.BASE("COREDEBUG",-1))+0xDF0))&0x01)==0x00)
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not completed,Completed"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
textline " "
|
|
textfld " "
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
else
|
|
group.long 0xDF0++0x03
|
|
line.long 0x00 "DHCSR,Debug Halting Control and Status Register"
|
|
bitfld.long 0x00 31. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 30. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 29. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 28. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 27. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 26. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 25. " S_RESET_ST/DBGKEY ,Core Reset/Debug Key" "No reset,Reset"
|
|
bitfld.long 0x00 24. " S_RETIRE_ST/DBGKEY ,Instruction completed since last read/Debug Key" "Not read,Read"
|
|
textline " "
|
|
bitfld.long 0x00 23. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 22. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 21. " DBGKEY ,Debug Key" "0,1"
|
|
bitfld.long 0x00 20. " DBGKEY ,Debug Key" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 19. " S_LOCKUP/DBGKEY ,Core Lockup Status/Debug Key" "Not locked up,Locked up"
|
|
bitfld.long 0x00 18. " S_SLEEP/DBGKEY ,Core Sleep Status/Debug Key" "Not sleeping,Sleeping"
|
|
textline " "
|
|
bitfld.long 0x00 17. " S_HALT/DBGKEY ,Core Halted Status/Debug Key" "Not halted,Halted"
|
|
bitfld.long 0x00 16. " S_REGRDY/DBGKEY ,Register R/W on the Debug Core Register Selector/Debug Key" "Not available,Available"
|
|
textline " "
|
|
bitfld.long 0x00 3. " C_MASKINTS ,Interrupts Mask" "Not masked,Masked"
|
|
bitfld.long 0x00 2. " C_STEP ,Steps the core in halted debug" "Not halted,Halted"
|
|
textline " "
|
|
bitfld.long 0x00 1. " C_HALT ,Core Halted" "Not halted,Halted"
|
|
bitfld.long 0x00 0. " C_DEBUGEN ,Debug Enable" "Disabled,Enabled"
|
|
endif
|
|
endif
|
|
wgroup.long 0xDF4++0x03
|
|
line.long 0x00 "DCRSR,Debug Core Selector Register"
|
|
bitfld.long 0x00 16. " REGWnR ,Register Read/Write" "Read,Write"
|
|
bitfld.long 0x00 0.--4. " REGSEL ,Register Selection" "R0,R1,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,Current SP,LR,DebugReturnAddress,xPSR Flags,MSP,PSP,Reserved,CONTROL[1]/PRIMASK[0],?..."
|
|
group.long 0xDF8++0x07
|
|
line.long 0x00 "DCRDR,Debug Core Register Data Register"
|
|
hexmask.long 0x00 0.--31. 1. " DATA ,Data for reading and writing registers to and from the processor"
|
|
line.long 0x04 "DEMCR,Debug Exception and Monitor Control Register"
|
|
bitfld.long 0x04 24. " DWTENA ,Global enable or disable for the DW unit" "Disabled,Enabled"
|
|
bitfld.long 0x04 10. " VC_HARDERR ,Debug trap on a Hard Fault" "No error,Error"
|
|
textline " "
|
|
bitfld.long 0x04 0. " VC_CORERESET ,Reset Vector Catch" "No reset,Reset"
|
|
width 0x0B
|
|
else
|
|
newline
|
|
textline "COREDEBUG component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Breakpoint Unit (BPU)"
|
|
sif COMPonent.AVAILABLE("BPU")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("BPU",-1))
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "BP_CTRL,Breakpoint Control Register"
|
|
bitfld.long 0x00 4.--7. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.long 0x00 1. " KEY ,Key field" "No write,Write"
|
|
bitfld.long 0x00 0. " ENABLE ,Breakpoint unit enable bit" "Disabled,Enabled"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "B_COMP0,Breakpoint Comparator Registers 0"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 0" "Disabled,Enabled"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "B_COMP1,Breakpoint Comparator Registers 1"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 1" "Disabled,Enabled"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "B_COMP2,Breakpoint Comparator Registers 2"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 2" "Disabled,Enabled"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "B_COMP3,Breakpoint Comparator Registers 3"
|
|
bitfld.long 0x00 30.--31. " BP_MATCH ,Happens when the COMP address is matched" "No matching,Lower halfword,Upper halfword,Both halfwords"
|
|
hexmask.long 0x00 2.--28. 2. " COMP ,Comparison address"
|
|
bitfld.long 0x00 0. " ENABLE ,Compare enable for Breakpoint Comparator Register 3" "Disabled,Enabled"
|
|
else
|
|
newline
|
|
textline "BPU component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree "Data Watchpoint and Trace Unit (DWT)"
|
|
sif COMPonent.AVAILABLE("DWT")
|
|
base CONvert.ADDRESSTODUALPORT(COMPonent.BASE("DWT",-1))
|
|
width 14.
|
|
rgroup.long 0x00++0x03
|
|
line.long 0x00 "DW_CTRL,DW Control Register "
|
|
bitfld.long 0x00 28.--31. " NUM_CODE1 ,Number of comparators" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
rgroup.long 0x1c++0x03
|
|
line.long 0x00 "DW_PCSR,DW Program Counter Sample Register"
|
|
hexmask.long 0x00 0.--31. 1. " EIASAMPLE ,Execution instruction address sample or 0xFFFFFFFF"
|
|
group.long 0x20++0x0b
|
|
line.long 0x00 "DW_COMP0,DW Comparator Register 0"
|
|
hexmask.long 0x00 0.--31. 1. " COMP1 ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK0,DW Mask Register 0"
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION0,DW Function Register 0"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
group.long 0x30++0x0b
|
|
line.long 0x00 "DW_COMP1,DW Comparator Register 1"
|
|
hexmask.long 0x00 0.--31. 1. " COMP ,Compare against PC or the data address"
|
|
line.long 0x04 "DW_MASK1,DW Mask Register 1 "
|
|
hexmask.long.byte 0x04 0.--4. 1. " MASK ,Mask on data address when matching against COMP"
|
|
line.long 0x08 "DW_FUNCTION1,DW Function Register 1"
|
|
bitfld.long 0x08 24. " MATCHED ,Comparator match" "No match,Match"
|
|
bitfld.long 0x08 0.--3. " FUNCTION , Settings for DW Function Registers" "Disabled,Reserved,Reserved,Reserved,On PC match,Read address,Write address,R/W address,?..."
|
|
else
|
|
newline
|
|
textline "DWT component base address not specified"
|
|
newline
|
|
endif
|
|
tree.end
|
|
tree.end
|
|
AUTOINDENT.POP
|
|
tree.end
|
|
tree "Resets"
|
|
base ad:0x4001E000
|
|
width 8.
|
|
group.byte 0x410++0x00
|
|
line.byte 0x00 "RSTSR0,Reset Status Register 0"
|
|
bitfld.byte 0x00 3. " LVD2RF ,Voltage Monitor 2 Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " LVD1RF ,Voltage Monitor 1 Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 1. " LVD0RF ,Voltage Monitor 0 Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " PORF ,Power-On Reset Detect Flag" "Not detected,Detected"
|
|
group.word 0x0C0++0x01
|
|
line.word 0x00 "RSTSR1,Reset Status Register 1"
|
|
bitfld.word 0x00 8. " RPERF ,SRAM Parity Error Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.word 0x00 2. " SWRF ,Software Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.word 0x00 1. " WDTRF ,Watchdog Timer Reset Detect Flag" "Not detected,Detected"
|
|
bitfld.word 0x00 0. " IWDTRF ,Independent Watchdog Timer Reset Detect Flag" "Not detected,Detected"
|
|
group.byte 0x411++0x00
|
|
line.byte 0x00 "RSTSR2,Reset Status Register 0"
|
|
bitfld.byte 0x00 0. " CWSF ,Cold/Warm Start Determination Flag" "Cold start,Warm start"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Option-Setting Memory and Information Memory"
|
|
base ad:0x00000000
|
|
width 12.
|
|
rgroup.long 0x400++0x07
|
|
line.long 0x00 "OFS0,Option Function Select Register 0"
|
|
bitfld.long 0x00 30. " WDTSTPCTL ,WDT Stop Control" "Counting continues,Counting stops"
|
|
bitfld.long 0x00 28. " WDTRSTIRQS ,WDT Reset Interrupt Request Select" "NMI,Reset"
|
|
bitfld.long 0x00 26.--27. " WDTRPSS ,WDT Window Start Position Select" "25%,50%,75%,100%"
|
|
bitfld.long 0x00 24.--25. " WDTRPES ,WDT Window End Position Select" "75%,50%,25%,0%"
|
|
textline " "
|
|
bitfld.long 0x00 20.--23. " WDTCKS ,WDT Clock Frequency Division Ratio Select" ",PCLKB/4,,,PCLKB/64,,PCLKB/512,PCLKB/2048,PCLKB/8192,,,,,,,PCLKB/128"
|
|
bitfld.long 0x00 18.--19. " WDTTOPS ,WDT Timeout Period Select" "1024,4096,8192,16384"
|
|
bitfld.long 0x00 17. " WDTSTRT ,WDT Start Mode Select" "Auto-start,Register-start"
|
|
bitfld.long 0x00 14. " IWDTSTPCTL ,IWDT Stop Control" "Counting continues,Counting stops"
|
|
textline " "
|
|
bitfld.long 0x00 12. " IWDTRSTIRQS ,IWDT Reset Interrupt Request Select" "Interrupt enabled,Reset enabled"
|
|
bitfld.long 0x00 10.--11. " IWDTRPSS ,IWDT Window Start Position Select" "25%,50%,75%,100%"
|
|
bitfld.long 0x00 8.--9. " IWDTRPES ,IWDT Window End Position Select" "75%,50%,25%,0%"
|
|
bitfld.long 0x00 4.--7. " IWDTCKS ,IWDT-Dedicated Clock Frequency Division Ratio Select" "1,,1/16,1/32,1/64,1/256,,,,,,,,,,1/128"
|
|
textline " "
|
|
bitfld.long 0x00 2.--3. " IWDTTOPS ,IWDT Timeout Period Select" "128,512,1024,2048"
|
|
bitfld.long 0x00 1. " IWDTSTRT ,IWDT Start Mode Select" "Auto-start,Disabled"
|
|
line.long 0x04 "OFS1,Option Function Select Register 1"
|
|
bitfld.long 0x04 12.--14. " HOCOFRQ1 ,HOCO Frequency Setting 1" "24MHz,,32MHz,,48MHz,64MHz,?..."
|
|
bitfld.long 0x04 8. " HOCOEN ,HOCO Oscillation Enable" "Enabled,Disabled"
|
|
bitfld.long 0x04 3.--5. " VDSEL1 ,Voltage Detection 0 Level Select" "3.84V,2.82V,2.51V,1.90V,1.70V,?..."
|
|
bitfld.long 0x04 2. " LVDAS ,Voltage Detection 0 Circuit Start" "Enabled,Disabled"
|
|
rgroup.long 0x1010008++0x03
|
|
line.long 0x00 "AWSC,Access Window Setting Control Register"
|
|
bitfld.long 0x00 14. " FSPR ,Write/Erase Protection of Access Window and Start-Up Area Select Function" "Invalid,Valid"
|
|
bitfld.long 0x00 8. " BTFLG ,Start-Up Area Select Flag For Boot Swap" "Exchanged,Not exchanged"
|
|
rgroup.long 0x1010010++0x03
|
|
line.long 0x00 "AWS,Access Window Setting Register"
|
|
hexmask.long.word 0x00 16.--27. 1. " FAWE ,Access Window End Block Address"
|
|
hexmask.long.word 0x00 0.--11. 1. " FAWS ,Access Window Start Block Address"
|
|
group.long 0x1010018++0x03
|
|
line.long 0x00 "OSIS[0:31],OCD/Serial Programmer ID Setting Register"
|
|
group.long 0x1010020++0x03
|
|
line.long 0x00 "OSIS[32:63],OCD/Serial Programmer ID Setting Register"
|
|
group.long 0x1010028++0x03
|
|
line.long 0x00 "OSIS[64:95],OCD/Serial Programmer ID Setting Register"
|
|
group.long 0x1010030++0x03
|
|
line.long 0x00 "OSIS[96:12],OCD/Serial Programmer ID Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "LVD (Low Voltage Detection)"
|
|
base ad:0x4001E000
|
|
width 9.
|
|
if (((per.w(ad:0x4001E3FE))&0x08)==0x08)
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "LVD1CR1,Voltage Monitor 1 Circuit Control Register 1"
|
|
bitfld.byte 0x00 2. " IRQSEL ,Voltage Monitor 1 Interrupt Type Select" "Non-maskable,Maskable"
|
|
bitfld.byte 0x00 0.--1. " IDTSEL ,Voltage Monitor 1 Interrupt Generation Condition Select" "Rise,Drop,Rise/Drop,?..."
|
|
group.byte 0xE1++0x00
|
|
line.byte 0x00 "LVD1SR,Voltage Monitor 1 Circuit Status Register"
|
|
rbitfld.byte 0x00 1. " MON ,Voltage Monitor 1 Signal Monitor Flag" "VCC<Vdet1,VCC>=Vdet1/Disabled"
|
|
bitfld.byte 0x00 0. " DET ,Voltage Monitor 1 Voltage Change Detection Flag" "Not detected,Crossing detection"
|
|
group.byte 0xE2++0x00
|
|
line.byte 0x00 "LVD2CR1,Voltage Monitor 2 Circuit Control Register 1"
|
|
bitfld.byte 0x00 2. " IRQSEL ,Voltage Monitor 2 Interrupt Type Select" "Non-maskable,Maskable"
|
|
bitfld.byte 0x00 0.--1. " IDTSEL ,Voltage Monitor 2 Interrupt Generation Condition Select" "Rise,Drop,Drop/Rise,?..."
|
|
group.byte 0xE3++0x00
|
|
line.byte 0x00 "LVD2SR,Voltage Monitor 2 Circuit Status Register"
|
|
rbitfld.byte 0x00 1. " MON ,Voltage Monitor 1 Signal Monitor Flag" "VCC<Vdet1,VCC>=Vdet1/Disabled"
|
|
bitfld.byte 0x00 0. " DET ,Voltage Monitor 2 Voltage Change Detection Flag" "Not detected,Crossing detection"
|
|
group.byte 0x417++0x01
|
|
line.byte 0x00 "LVCMPCR,Voltage Monitor Circuit Control Register"
|
|
bitfld.byte 0x00 6. " LVD2E ,Voltage Detection 2 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LVD1E ,Voltage Detection 1 Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "LVDLVLR,Voltage Detection Level Select Register"
|
|
bitfld.byte 0x01 5.--7. " LVD2LVL ,Voltage Detection 2 Level Select" "4.29V,4.14V,4.02V,3.84,?..."
|
|
bitfld.byte 0x01 0.--4. " LVD1LVL ,Voltage Detection 1 Level Select" "4.29V,4.14V,4.02V,3.84V,3.10V,3.00V,2.90V,2.79V,2.68V,2.58V,2.48V,2.20V,1.96V,1.86V,1.75V,1.65V,?..."
|
|
group.byte 0x41A++0x01
|
|
line.byte 0x00 "LVD1CR0,Voltage Monitor 1 Circuit Control Register 0"
|
|
bitfld.byte 0x00 6. " RN ,Voltage Monitor 1 Reset Negate Select" "VCC>Vdet1,LVD1 reset"
|
|
bitfld.byte 0x00 5. " RI ,Voltage Monitor 1 Circuit Mode Select" "Interrupt,Reset"
|
|
bitfld.byte 0x00 6. " CMPE ,Voltage Monitor 1 Circuit Comparison Result Output Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " RIE ,Voltage Monitor 1 Interrupt/Reset Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "LVD2CR0,Voltage Monitor 2 Circuit Control Register 0"
|
|
bitfld.byte 0x01 6. " RN ,Voltage Monitor 2 Reset Negate Select" "VCC>Vdet2,LVD2 reset"
|
|
bitfld.byte 0x01 5. " RI ,Voltage Monitor 2 Circuit Mode Select" "Interrupt,Reset"
|
|
bitfld.byte 0x01 6. " CMPE ,Voltage Monitor 2 Circuit Comparison Result Output Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " RIE ,Voltage Monitor 2 Interrupt/Reset Enable" "Disabled,Enabled"
|
|
else
|
|
rgroup.byte 0xE0++0x00
|
|
line.byte 0x00 "LVD1CR1,Voltage Monitor 1 Circuit Control Register 1"
|
|
bitfld.byte 0x00 2. " IRQSEL ,Voltage Monitor 1 Interrupt Type Select" "Non-maskable,Maskable"
|
|
bitfld.byte 0x00 0.--1. " IDTSEL ,Voltage Monitor 1 Interrupt Generation Condition Select" "Rise,Drop,Rise/Drop,?..."
|
|
rgroup.byte 0xE1++0x00
|
|
line.byte 0x00 "LVD1SR,Voltage Monitor 1 Circuit Status Register"
|
|
bitfld.byte 0x00 1. " MON ,Voltage Monitor 1 Signal Monitor Flag" "VCC<Vdet1,VCC>=Vdet1/Disabled"
|
|
bitfld.byte 0x00 0. " DET ,Voltage Monitor 1 Voltage Change Detection Flag" "Not detected,Crossing detection"
|
|
rgroup.byte 0xE2++0x00
|
|
line.byte 0x00 "LVD2CR1,Voltage Monitor 2 Circuit Control Register 1"
|
|
bitfld.byte 0x00 2. " IRQSEL ,Voltage Monitor 2 Interrupt Type Select" "Non-maskable,Maskable"
|
|
bitfld.byte 0x00 0.--1. " IDTSEL ,Voltage Monitor 2 Interrupt Generation Condition Select" "Rise,Drop,Drop/Rise,?..."
|
|
rgroup.byte 0xE3++0x00
|
|
line.byte 0x00 "LVD2SR,Voltage Monitor 2 Circuit Status Register"
|
|
bitfld.byte 0x00 1. " MON ,Voltage Monitor 1 Signal Monitor Flag" "VCC<Vdet1,VCC>=Vdet1/Disabled"
|
|
bitfld.byte 0x00 0. " DET ,Voltage Monitor 2 Voltage Change Detection Flag" "Not detected,Crossing detection"
|
|
rgroup.byte 0x417++0x01
|
|
line.byte 0x00 "LVCMPCR,Voltage Monitor Circuit Control Register"
|
|
bitfld.byte 0x00 6. " LVD2E ,Voltage Detection 2 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " LVD1E ,Voltage Detection 1 Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "LVDLVLR,Voltage Detection Level Select Register"
|
|
bitfld.byte 0x01 5.--7. " LVD2LVL ,Voltage Detection 2 Level Select" "4.29V,4.14V,4.02V,3.84,?..."
|
|
bitfld.byte 0x01 0.--4. " LVD1LVL ,Voltage Detection 1 Level Select" "4.29V,4.14V,4.02V,3.84V,3.10V,3.00V,2.90V,2.79V,2.68V,2.58V,2.48V,2.20V,1.96V,1.86V,1.75V,1.65V,?..."
|
|
rgroup.byte 0x41A++0x01
|
|
line.byte 0x00 "LVD1CR0,Voltage Monitor 1 Circuit Control Register 0"
|
|
bitfld.byte 0x00 6. " RN ,Voltage Monitor 1 Reset Negate Select" "VCC>Vdet1,LVD1 reset"
|
|
bitfld.byte 0x00 5. " RI ,Voltage Monitor 1 Circuit Mode Select" "Interrupt,Reset"
|
|
bitfld.byte 0x00 6. " CMPE ,Voltage Monitor 1 Circuit Comparison Result Output Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " RIE ,Voltage Monitor 1 Interrupt/Reset Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "LVD2CR0,Voltage Monitor 2 Circuit Control Register 0"
|
|
bitfld.byte 0x01 6. " RN ,Voltage Monitor 2 Reset Negate Select" "VCC>Vdet2,LVD2 reset"
|
|
bitfld.byte 0x01 5. " RI ,Voltage Monitor 2 Circuit Mode Select" "Interrupt,Reset"
|
|
bitfld.byte 0x01 6. " CMPE ,Voltage Monitor 2 Circuit Comparison Result Output Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " RIE ,Voltage Monitor 2 Interrupt/Reset Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Clock Generation Circuit"
|
|
base ad:0x4001E000
|
|
width 10.
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "SCKDIVCR,System Clock Division Control Register"
|
|
bitfld.long 0x00 24.--26. " ICK ,System Clock (ICLK) Select" "1,1/2,1/4,1/8,1/16,1/32,1/64,?..."
|
|
bitfld.long 0x00 8.--10. " PCKB ,Peripheral Module Clock B (PCLKB) Select" "1,1/2,1/4,1/8,1/16,1/32,1/64,?..."
|
|
bitfld.long 0x00 0.--2. " PCKD ,Peripheral Module Clock D" "1,1/2,1/4,1/8,1/16,1/32,1/64,?..."
|
|
group.byte 0x26++0x00
|
|
line.byte 0x00 "SCKSCR,System Clock Source Control Register"
|
|
bitfld.byte 0x00 0.--2. " CKSEL ,Clock Source Select" "HOCO,MOCO,LOCO,MOSC,SOSC,?..."
|
|
group.byte 0x32++0x00
|
|
line.byte 0x00 "MOSSCCR,Main Clock Oscillator Control Register"
|
|
bitfld.byte 0x00 0. " MOSTP ,Main Clock Oscillator Stop" "Operating,Stopped"
|
|
group.byte 0x480++0x00
|
|
line.byte 0x00 "SOSCCR,Sub-clock Oscillator Control Register"
|
|
bitfld.byte 0x00 0. " SOSTP ,Sub-Clock Oscillator Stop" "Operating,Stopped"
|
|
group.byte 0x490++0x00
|
|
line.byte 0x00 "LOCOCR,Low-Speed On-Chip Oscillator Control Register"
|
|
bitfld.byte 0x00 0. " LCSTP ,LOCO Stop" "Operating,Stopped"
|
|
group.byte 0x36++0x00
|
|
line.byte 0x00 "HOCOCR,High-Speed On-Chip Oscillator Control Register"
|
|
bitfld.byte 0x00 0. " HCSTP ,HOCO Stop" "Operating,Stopped"
|
|
group.byte 0x38++0x00
|
|
line.byte 0x00 "MOCOCR,Middle-Speed On-Chip Oscillator Control Register"
|
|
bitfld.byte 0x00 0. " MCSTP ,MOCO Stop" "Operating,Stopped"
|
|
rgroup.byte 0x3C++0x00
|
|
line.byte 0x00 "OSCSF,Oscillation Stabilization Flag Register"
|
|
bitfld.byte 0x00 3. " MOCOSF ,Main Clock Oscillation Stabilization Flag" "Not stabilized,Stabilized"
|
|
bitfld.byte 0x00 0. " HOCOSF ,HOCO Clock Oscillation Stabilization Flag" "Not stabilized,Stabilized"
|
|
group.byte 0x40++0x00
|
|
line.byte 0x00 "OSTDCR,Oscillation Stop Detection Control Register"
|
|
bitfld.byte 0x00 7. " OSTDE ,Oscillation Stop Detection Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " OSTDIE ,Oscillation Stop Detection Interrupt Enable" "Disabled,Enabled"
|
|
group.byte 0x41++0x00
|
|
line.byte 0x00 "OSTDSR,Oscillation Stop Detection Status Register"
|
|
bitfld.byte 0x00 0. " OSTDF ,Oscillation Stop Detection Flag" "Not detected,Detected"
|
|
group.byte 0xA2++0x00
|
|
line.byte 0x00 "MOSCWTCR,Main Clock Oscillator Wait Control Register"
|
|
bitfld.byte 0x00 0.--3. " MSTS ,Main Clock Oscillator Wait Time Setting" "2 cycles,1024 cycles,2048 cycles,4096 cycles,8192 cycles,16384 cycles,32768 cycles,65536 cycles,131072 cycles,262144 cycles,?..."
|
|
group.byte 0xA5++0x00
|
|
line.byte 0x00 "HOCOWTCR,High-Speed On-Chip Oscillator Wait Control Register"
|
|
bitfld.byte 0x00 0.--2. " HSTS ,HOCO wait time setting" ",,,,,245/679 cycles,541 cycles,?..."
|
|
group.byte 0x413++0x00
|
|
line.byte 0x00 "MOMCR,Main Clock Oscillator Mode Oscillation Control Register"
|
|
bitfld.byte 0x00 6. " MOSEL ,Main Clock Oscillator Switching" "Resonator,External clock"
|
|
bitfld.byte 0x00 3. " MODRV1 ,Main Clock Oscillator Drive Capability 1 Switching" "10-20Mhz,1-10Mhz"
|
|
group.byte 0x481++0x00
|
|
line.byte 0x00 "SOMCR,Sub-clock Oscillator Mode Control Register"
|
|
bitfld.byte 0x00 0.--1. " SODRV ,Sub-Clock Oscillator Drive Capability Switching" "Normal,Low 1,Low 2,Low 3"
|
|
group.byte 0x03E++0x00
|
|
line.byte 0x00 "CKOCR,Clock Out Control Register"
|
|
bitfld.byte 0x00 7. " CKOEN ,Clock Out Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--6. " CKODIV ,Clock Out input frequency Division Select" "1,/2,/4,/8,/16,/32,/64,/128"
|
|
bitfld.byte 0x00 0.--2. " CKOSEL ,Clock Out Source Select" "HOCO,MOCO,LOCO,MOSC,SOSC,?..."
|
|
group.byte 0x492++0x00
|
|
line.byte 0x00 "LOCOUTRM,LOCO User Trimming"
|
|
group.byte 0x61++0x00
|
|
line.byte 0x00 "MOCOUTCR,MOCO User Trimming Control Register"
|
|
group.byte 0x62++0x00
|
|
line.byte 0x00 "HOCOUTCR,HOCO User Trimming Control Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CAC (Clock Frequency Accuracy Measurement Circuit)"
|
|
base ad:0x40044600
|
|
width 9.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "CACR0,CAC Control Register 0"
|
|
bitfld.byte 0x00 0. " CFME ,Clock Frequency Measurement Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "CACR1,CAC Control Register 1"
|
|
bitfld.byte 0x01 6.--7. " EDGES ,Valid Edge Select" "Rising,Falling,Both,?..."
|
|
bitfld.byte 0x01 4.--5. " TCSS ,Measurement Target Clock Frequency Division Ratio Select" "1,1/4,1/8,1/32"
|
|
bitfld.byte 0x01 1.--3. " FMCS ,Measurement Target Clock Select" "Main,Sub,HOCO,MOCO,LOCO,PCLKB,IWDTCLK,?..."
|
|
textline " "
|
|
bitfld.byte 0x01 0. " CACREFE ,CACREF Pin Input Enable" "Disabled,Enabled"
|
|
line.byte 0x02 "CACR2,CAC Control Register 2"
|
|
bitfld.byte 0x02 6.--7. " DFS ,Digital Filter Select" "Disabled,1,1/4,1/16"
|
|
bitfld.byte 0x02 4.--5. " RCDS ,Measurement Reference Clock Frequency Division Ratio Select" "1/32,1/128,1/1024,1/8192"
|
|
bitfld.byte 0x02 1.--3. " RSCS ,Measurement Reference Clock Select" "Main,Sub,HOCO,MOCO,LOCO,PCLKB,IWDTCLK,?..."
|
|
textline " "
|
|
bitfld.byte 0x02 0. " RPS ,Reference Signal Select" "CACREF,Internal"
|
|
line.byte 0x03 "CAICR,CAC Interrupt Control Register"
|
|
bitfld.byte 0x03 6. " OVFFCL ,OVFF Clear" "No effect,Clear"
|
|
bitfld.byte 0x03 5. " MENDFCL ,MENDF Clear" "No effect,Clear"
|
|
bitfld.byte 0x03 4. " FERRFCL ,FERRF Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.byte 0x03 2. " OVFIE ,Overflow Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 1. " MENDIE ,Measurement End Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " FERRIE ,Frequency Error Interrupt Request Enable" "Disabled,Enabled"
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "CASTR,CAC Status Register"
|
|
bitfld.byte 0x00 2. " OVFF ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.byte 0x00 1. " MENDF ,Measurement End Flag" "In progress,Ended"
|
|
bitfld.byte 0x00 0. " FERRF ,Frequency Error Flag" "No error,Error"
|
|
group.word 0x06++0x05
|
|
line.word 0x00 "CAULVR,CAC Upper-Limit Value Setting Register"
|
|
line.word 0x02 "CALLVR,CAC Lower-Limit Value Setting Register"
|
|
line.word 0x04 "CACNTBR,CAC Counter Buffer Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Low Power Modes"
|
|
base ad:0x4001E000
|
|
width 10.
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "SBYCR,Standby Control Register"
|
|
bitfld.word 0x00 15. " SSBY ,Software Standby" "Sleep mode,Standby mode"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "MSTPCRA,Module Stop Control Register A"
|
|
bitfld.long 0x00 22. " MSTPA22 ,Data Transfer Controller Module Stop" "Canceled,Entered"
|
|
group.long 0x29000++0x0B
|
|
line.long 0x00 "MSTPCRB,Module Stop Control Register B"
|
|
bitfld.long 0x00 31. " MSTPB31 ,Serial Communication Interface 0 Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x00 30. " MSTPB30 ,Serial Communication Interface 1 Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x00 22. " MSTPB22 ,Serial Communication Interface 9 Module Stop" "Canceled,Entered"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MSTPB19 ,Serial Peripheral Interface 0 Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x00 18. " MSTPB18 ,Serial Peripheral Interface 1 Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x00 11. " MSTPB11 ,Universal Serial Bus 2.0 Full Speed Interface Module" "Canceled,Entered"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MSTPB9 ,I2C Bus Interface 0 Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x00 8. " MSTPB8 ,I2C Bus Interface 1 Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x00 2. " MSTPB2 ,Controller Area Network 0 Module Stop" "Canceled,Entered"
|
|
line.long 0x04 "MSTPCRC,Module Stop Control Register C"
|
|
bitfld.long 0x04 31. " MSTPC31 ,AES Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x04 28. " MSTPC28 ,Random Number Generator Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x04 14. " MSTPC14 ,Event Link Controller Module Stop" "Canceled,Entered"
|
|
textline " "
|
|
bitfld.long 0x04 13. " MSTPC13 ,Data Operation Circuit Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x04 3. " MSTPC3 ,Capacitive Touch Sensing Unit Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x04 1. " MSTPC1 ,Cyclic Redundancy Check Calculator Module Stop" "Canceled,Entered"
|
|
textline " "
|
|
bitfld.long 0x04 0. " MSTPC0 ,Clock Frequency Accuracy Measurement Circuit Module Stop" "Canceled,Entered"
|
|
line.long 0x08 "MSTPCRD,Module Stop Control Register D"
|
|
bitfld.long 0x08 29. " MSTPD29 ,Low-Power Analog Comparator Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x08 20. " MSTPD20 ,12-Bit D/A Converter Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x08 16. " MSTPD16 ,14-Bit A/D Converter Module Stop" "Canceled,Entered"
|
|
textline " "
|
|
bitfld.long 0x08 14. " MSTPD14 ,Port Output Enable for GPT Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x08 6. " MSTPD6 ,General PWM Timer 166 to 161 Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x08 5. " MSTPD5 ,General PWM Timer 320 Module Stop" "Canceled,Entered"
|
|
textline " "
|
|
bitfld.long 0x08 3. " MSTPD3 ,Asynchronous General Purpose Timer 0 Module Stop" "Canceled,Entered"
|
|
bitfld.long 0x08 2. " MSTPD2 ,Asynchronous General Purpose Timer 1 Module Stop" "Canceled,Entered"
|
|
group.byte 0xA0++0x00
|
|
line.byte 0x00 "OPCCR,Operating Power Control Register"
|
|
rbitfld.byte 0x00 4. " OPCMTSF ,Operating Power Control Mode Transition Status Flag" "Completed,Ongoing"
|
|
bitfld.byte 0x00 0.--1. " OPCM ,Operating Power Control Mode Select" "High-speed,Middle-speed,Low-voltage,Low-speed"
|
|
group.byte 0xAA++0x00
|
|
line.byte 0x00 "SOPCCR,Sub Operating Power Control Register"
|
|
rbitfld.byte 0x00 4. " SOPCMTSF ,Sub Operating Power Control Mode Transition Status Flag" "Completed,Ongoing"
|
|
bitfld.byte 0x00 0. " SOPCM ,Sub Operating Power Control Mode Select" "No Subosc-speed,Subosc-speed"
|
|
group.byte 0x92++0x00
|
|
line.byte 0x00 "SNZCR,Snooze Control Register"
|
|
bitfld.byte 0x00 7. " SNZE ,Snooze mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " SNZDTCEN ,DTC Enable in Snooze mode" "Disabled, Enabled"
|
|
bitfld.byte 0x00 0. " RXDREQEN ,RXD0 Snooze Request Enable" "Disabled,Enabled"
|
|
group.byte 0x94++0x00
|
|
line.byte 0x00 "SNZEDCR,Snooze End Control Register"
|
|
bitfld.byte 0x00 7. " SCI0UMTED ,SCI0 Address Mismatch Snooze End Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " AD0UMTED ,ADC140 Compare Mismatch Snooze End Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " AD0MATED ,ADC140 Compare Match Snooze End Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " DTCNZRED ,Not Last DTC Transmission Completion Snooze End Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " DTCZRED ,Last DTC Transmission Completion Snooze End Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AGTUNFED ,AGT1 Underflow Snooze End Enable" "Disabled,Enabled"
|
|
group.long 0x98++0x03
|
|
line.long 0x00 "SNZREQCR,Snooze Request Control Register"
|
|
bitfld.long 0x00 30. " SNZREQEN30 ,Snooze Request Enable 30" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " SNZREQEN29 ,Snooze Request Enable 29" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " SNZREQEN28 ,Snooze Request Enable 28" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " SNZREQEN25 ,Snooze Request Enable 25" "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " SNZREQEN24 ,Snooze Request Enable 24" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " SNZREQEN23 ,Snooze Request Enable 23" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 17. " SNZREQEN17 ,Snooze Request Enable 17" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " SNZREQEN7 ,Snooze Request Enable 7" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " SNZREQEN6 ,Snooze Request Enable 6" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 5. " SNZREQEN5 ,Snooze Request Enable 5" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " SNZREQEN4 ,Snooze Request Enable 4" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SNZREQEN3 ,Snooze Request Enable 3" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " SNZREQEN2 ,Snooze Request Enable 2" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SNZREQEN1 ,Snooze Request Enable 1" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " SNZREQEN0 ,Snooze Request Enable 0" "Disabled,Enabled"
|
|
group.byte 0x9E++0x00
|
|
line.byte 0x00 "FLSTOP,Flash Operation Control Register"
|
|
bitfld.byte 0x00 4. " FLSTPF ,Flash Memory Operation Status Flag" "Completed,Ongoing"
|
|
bitfld.byte 0x00 0. " FLSTOP ,Selecting ON/OFF of the Flash Memory Operation" "On,Off"
|
|
group.byte 0x40E++0x00
|
|
line.byte 0x00 "SYOCDCR,System Control OCD Control Register"
|
|
bitfld.byte 0x00 7. " DBGEN ,Debugger Enable bit" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Register Write Protection"
|
|
base ad:0x4001E3FE
|
|
width 6.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "PRCR,Protect Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " PRKEY ,PRC Key Code"
|
|
bitfld.word 0x00 3. " PRC3 ,Protect Bit 3" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " PRC1 ,Protect Bit 1" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " PRC0 ,Protect Bit 0" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ICU (Interrupt Controller Unit)"
|
|
base ad:0x40006000
|
|
width 9.
|
|
group.byte (0x00+0x0)++0x00
|
|
line.byte 0x00 "IRQCR0,IRQ Control Register 0"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ0 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ0 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ0 Detection Sense Select" "Falling edge,Rising edge,Both edges,Low level"
|
|
group.byte (0x00+0x1)++0x00
|
|
line.byte 0x00 "IRQCR1,IRQ Control Register 1"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ1 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ1 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ1 Detection Sense Select" "Falling edge,Rising edge,Both edges,Low level"
|
|
group.byte (0x00+0x2)++0x00
|
|
line.byte 0x00 "IRQCR2,IRQ Control Register 2"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ2 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ2 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ2 Detection Sense Select" "Falling edge,Rising edge,Both edges,Low level"
|
|
group.byte (0x00+0x3)++0x00
|
|
line.byte 0x00 "IRQCR3,IRQ Control Register 3"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ3 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ3 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ3 Detection Sense Select" "Falling edge,Rising edge,Both edges,Low level"
|
|
group.byte (0x00+0x4)++0x00
|
|
line.byte 0x00 "IRQCR4,IRQ Control Register 4"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ4 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ4 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ4 Detection Sense Select" "Falling edge,Rising edge,Both edges,Low level"
|
|
group.byte (0x00+0x5)++0x00
|
|
line.byte 0x00 "IRQCR5,IRQ Control Register 5"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ5 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ5 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ5 Detection Sense Select" "Falling edge,Rising edge,Both edges,Low level"
|
|
group.byte (0x00+0x6)++0x00
|
|
line.byte 0x00 "IRQCR6,IRQ Control Register 6"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ6 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ6 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ6 Detection Sense Select" "Falling edge,Rising edge,Both edges,Low level"
|
|
group.byte (0x00+0x7)++0x00
|
|
line.byte 0x00 "IRQCR7,IRQ Control Register 7"
|
|
bitfld.byte 0x00 7. " FLTEN ,IRQ7 Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " FCLKSEL ,IRQ7 Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0.--1. " IRQMD ,IRQ7 Detection Sense Select" "Falling edge,Rising edge,Both edges,Low level"
|
|
rgroup.word 0x140++0x01
|
|
line.word 0x00 "NMISR,Non-Maskable Interrupt Status Register"
|
|
bitfld.word 0x00 8. " RPEST ,SRAM Parity Error Interrupt Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 7. " NMIST ,NMI Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " OSTST ,Oscillation Stop Detection Interrupt Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 3. " LVD2ST ,Voltage Monitor 2 Interrupt Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 2. " LVD1ST ,Voltage Monitor 1 Interrupt Status Flag" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 1. " WDTST ,WDT Underflow/Refresh Error Status Flag" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 0. " IWDTST ,IWDT Underflow/Refresh Error Status Flag" "No interrupt,Interrupt"
|
|
group.word 0x120++0x01
|
|
line.word 0x00 "NMIER,Non-Maskable Interrupt Enable Register"
|
|
bitfld.word 0x00 8. " RPEEN ,SRAM Parity Error Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " NMIEN ,NMI Pin Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " OSTEN ,Oscillation Stop Detection Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " LVD2EN ,Voltage Monitor 2 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 2. " LVD1EN ,Voltage monitor 1 Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " WDTEN ,WDT Underflow/Refresh Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 0. " IWDTEN ,IWDT Underflow/Refresh Error Interrupt Enable" "Disabled,Enabled"
|
|
group.word 0x130++0x01
|
|
line.word 0x00 "NMICLR,Non-Maskable Interrupt Status Clear Register"
|
|
bitfld.word 0x00 8. " RPECLR ,SRAM Parity Error Clear" "No effect,Clear"
|
|
bitfld.word 0x00 7. " NMICLR ,NMI Clear" "No effect,Clear"
|
|
bitfld.word 0x00 6. " OSTCLR ,OST Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 3. " LVD2CLR ,LVD2 Clear" "No effect,Clear"
|
|
bitfld.word 0x00 2. " LVD1CLR ,LVD1 Clear" "No effect,Clear"
|
|
bitfld.word 0x00 1. " WDTCLR ,WDT Clear" "No effect,Clear"
|
|
textline " "
|
|
bitfld.word 0x00 0. " IWDTCLR ,IWDT Clear" "No effect,Clear"
|
|
group.byte 0x100++0x00
|
|
line.byte 0x00 "NMICR,NMI Pin Interrupt Control Register"
|
|
bitfld.byte 0x00 7. " NFLTEN ,NMI Digital Filter Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4.--5. " NFCLKSEL ,NMI Digital Filter Sampling Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/64"
|
|
bitfld.byte 0x00 0. " NMIMD ,NMI Detection Set" "Falling edge,Rising edge"
|
|
group.long 0x0++0x03
|
|
line.long 0x00 "IELSR0,ICU Event Link Setting Register 0"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x4++0x03
|
|
line.long 0x00 "IELSR1,ICU Event Link Setting Register 1"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x8++0x03
|
|
line.long 0x00 "IELSR2,ICU Event Link Setting Register 2"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0xC++0x03
|
|
line.long 0x00 "IELSR3,ICU Event Link Setting Register 3"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "IELSR4,ICU Event Link Setting Register 4"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "IELSR5,ICU Event Link Setting Register 5"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "IELSR6,ICU Event Link Setting Register 6"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "IELSR7,ICU Event Link Setting Register 7"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "IELSR8,ICU Event Link Setting Register 8"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "IELSR9,ICU Event Link Setting Register 9"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "IELSR10,ICU Event Link Setting Register 10"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "IELSR11,ICU Event Link Setting Register 11"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "IELSR12,ICU Event Link Setting Register 12"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "IELSR13,ICU Event Link Setting Register 13"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "IELSR14,ICU Event Link Setting Register 14"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "IELSR15,ICU Event Link Setting Register 15"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x40++0x03
|
|
line.long 0x00 "IELSR16,ICU Event Link Setting Register 16"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x44++0x03
|
|
line.long 0x00 "IELSR17,ICU Event Link Setting Register 17"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x48++0x03
|
|
line.long 0x00 "IELSR18,ICU Event Link Setting Register 18"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "IELSR19,ICU Event Link Setting Register 19"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x50++0x03
|
|
line.long 0x00 "IELSR20,ICU Event Link Setting Register 20"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x54++0x03
|
|
line.long 0x00 "IELSR21,ICU Event Link Setting Register 21"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x58++0x03
|
|
line.long 0x00 "IELSR22,ICU Event Link Setting Register 22"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x5C++0x03
|
|
line.long 0x00 "IELSR23,ICU Event Link Setting Register 23"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x60++0x03
|
|
line.long 0x00 "IELSR24,ICU Event Link Setting Register 24"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x64++0x03
|
|
line.long 0x00 "IELSR25,ICU Event Link Setting Register 25"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x68++0x03
|
|
line.long 0x00 "IELSR26,ICU Event Link Setting Register 26"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x6C++0x03
|
|
line.long 0x00 "IELSR27,ICU Event Link Setting Register 27"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x70++0x03
|
|
line.long 0x00 "IELSR28,ICU Event Link Setting Register 28"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x74++0x03
|
|
line.long 0x00 "IELSR29,ICU Event Link Setting Register 29"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x78++0x03
|
|
line.long 0x00 "IELSR30,ICU Event Link Setting Register 30"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.long 0x7C++0x03
|
|
line.long 0x00 "IELSR31,ICU Event Link Setting Register 31"
|
|
bitfld.long 0x00 24. " DTCE ,DTC Activation Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IR ,Interrupt Status Flag" "No interrupt,Interrupt"
|
|
hexmask.long.byte 0x00 0.--7. 1. " IELS ,ICU Event Link Select"
|
|
group.word 0x200++0x01
|
|
line.word 0x00 "SELSR0,SYS Event Link Setting Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " SELS ,SYS Event Link Select"
|
|
group.long 0x1A0++0x03
|
|
line.long 0x00 "WUPEN,Wake Up Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " IIC0WUPEN ,IIC0 Address Match Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " AGT1CBWUPEN ,AGT1 Compare Match B Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " AGT1CAWUPEN ,AGT1 Compare Match A Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " AGT1UDWUPEN ,AGT1 Underflow Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " USBFSWUPEN ,USBFS Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " RTCPRDWUPEN ,RTC Period Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 24. " RTCALMWUPEN ,RTC Alarm Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " ACMPLP0WUPEN ,ACMPLP0 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " LVD2WUPEN ,LVD2 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " LVD1WUPEN ,LVD1 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " KEYWUPEN ,Key Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " IWDTWUPEN ,IWDT Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " IRQWUPEN7 ,IRQ7 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " IRQWUPEN6 ,IRQ6 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IRQWUPEN5 ,IRQ5 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " IRQWUPEN4 ,IRQ4 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " IRQWUPEN3 ,IRQ3 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " IRQWUPEN2 ,IRQ2 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " IRQWUPEN1 ,IRQ1 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " IRQWUPEN0 ,IRQ0 Interrupt Software Standby Returns Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Buses"
|
|
base ad:0x40004000
|
|
width 13.
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "BUSMCNTSYS,Master Bus Control Register"
|
|
bitfld.word 0x00 15. " IERES ,Ignore Error Responses" "Reported,Not reported"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "BUSMCNTDMA,Master Bus Control Register"
|
|
bitfld.word 0x00 15. " IERES ,Ignore Error Responses" "Reported,Not reported"
|
|
group.word 0x100++0x01
|
|
line.word 0x00 "BUSSCNTFLI,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,?..."
|
|
group.word 0x10C++0x01
|
|
line.word 0x00 "BUSSCNTRAM0,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,?..."
|
|
group.word 0x114++0x01
|
|
line.word 0x00 "BUSSCNTP0B,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,?..."
|
|
group.word 0x118++0x01
|
|
line.word 0x00 "BUSSCNTP2B,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,?..."
|
|
group.word 0x120++0x01
|
|
line.word 0x00 "BUSSCNTP4B,Slave Bus Control Register"
|
|
bitfld.word 0x00 4.--5. " ARBMET ,Arbitration Method" "Fixed priority,Round-robin,?..."
|
|
width 0x0B
|
|
tree.end
|
|
tree "DTC (Data Transfer Controller)"
|
|
width 8.
|
|
base ad:(per.l(ad:0x40005400+0x04))
|
|
group.byte (0x0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x0+0x03)))&0xC0)==0x00)
|
|
group.word (0x0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x10+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x10+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x10+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x10+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x10+0x03)))&0xC0)==0x00)
|
|
group.word (0x10+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x10+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x10+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x20+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x20+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x20+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x20+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x20+0x03)))&0xC0)==0x00)
|
|
group.word (0x20+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x20+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x20+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x30+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x30+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x30+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x30+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x30+0x03)))&0xC0)==0x00)
|
|
group.word (0x30+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x30+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x30+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x40+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x40+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x40+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x40+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x40+0x03)))&0xC0)==0x00)
|
|
group.word (0x40+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x40+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x40+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x50+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x50+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x50+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x50+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x50+0x03)))&0xC0)==0x00)
|
|
group.word (0x50+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x50+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x50+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x60+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x60+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x60+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x60+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x60+0x03)))&0xC0)==0x00)
|
|
group.word (0x60+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x60+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x60+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x70+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x70+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x70+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x70+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x70+0x03)))&0xC0)==0x00)
|
|
group.word (0x70+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x70+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x70+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x80+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x80+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x80+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x80+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x80+0x03)))&0xC0)==0x00)
|
|
group.word (0x80+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x80+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x80+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x90+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x90+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x90+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x90+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x90+0x03)))&0xC0)==0x00)
|
|
group.word (0x90+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x90+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x90+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0xA0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0xA0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0xA0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0xA0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0xA0+0x03)))&0xC0)==0x00)
|
|
group.word (0xA0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0xA0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0xA0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0xB0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0xB0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0xB0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0xB0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0xB0+0x03)))&0xC0)==0x00)
|
|
group.word (0xB0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0xB0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0xB0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0xC0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0xC0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0xC0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0xC0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0xC0+0x03)))&0xC0)==0x00)
|
|
group.word (0xC0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0xC0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0xC0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0xD0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0xD0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0xD0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0xD0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0xD0+0x03)))&0xC0)==0x00)
|
|
group.word (0xD0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0xD0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0xD0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0xE0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0xE0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0xE0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0xE0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0xE0+0x03)))&0xC0)==0x00)
|
|
group.word (0xE0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0xE0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0xE0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0xF0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0xF0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0xF0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0xF0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0xF0+0x03)))&0xC0)==0x00)
|
|
group.word (0xF0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0xF0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0xF0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x100+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x100+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x100+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x100+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x100+0x03)))&0xC0)==0x00)
|
|
group.word (0x100+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x100+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x100+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x110+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x110+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x110+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x110+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x110+0x03)))&0xC0)==0x00)
|
|
group.word (0x110+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x110+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x110+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x120+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x120+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x120+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x120+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x120+0x03)))&0xC0)==0x00)
|
|
group.word (0x120+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x120+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x120+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x130+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x130+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x130+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x130+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x130+0x03)))&0xC0)==0x00)
|
|
group.word (0x130+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x130+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x130+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x140+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x140+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x140+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x140+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x140+0x03)))&0xC0)==0x00)
|
|
group.word (0x140+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x140+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x140+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x150+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x150+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x150+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x150+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x150+0x03)))&0xC0)==0x00)
|
|
group.word (0x150+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x150+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x150+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x160+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x160+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x160+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x160+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x160+0x03)))&0xC0)==0x00)
|
|
group.word (0x160+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x160+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x160+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x170+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x170+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x170+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x170+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x170+0x03)))&0xC0)==0x00)
|
|
group.word (0x170+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x170+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x170+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x180+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x180+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x180+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x180+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x180+0x03)))&0xC0)==0x00)
|
|
group.word (0x180+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x180+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x180+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x190+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x190+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x190+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x190+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x190+0x03)))&0xC0)==0x00)
|
|
group.word (0x190+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x190+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x190+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x1A0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x1A0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x1A0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x1A0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x1A0+0x03)))&0xC0)==0x00)
|
|
group.word (0x1A0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x1A0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x1A0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x1B0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x1B0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x1B0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x1B0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x1B0+0x03)))&0xC0)==0x00)
|
|
group.word (0x1B0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x1B0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x1B0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x1C0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x1C0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x1C0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x1C0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x1C0+0x03)))&0xC0)==0x00)
|
|
group.word (0x1C0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x1C0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x1C0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x1D0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x1D0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x1D0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x1D0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x1D0+0x03)))&0xC0)==0x00)
|
|
group.word (0x1D0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x1D0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x1D0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x1E0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x1E0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x1E0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x1E0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x1E0+0x03)))&0xC0)==0x00)
|
|
group.word (0x1E0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x1E0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x1E0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x1F0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x1F0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x1F0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x1F0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x1F0+0x03)))&0xC0)==0x00)
|
|
group.word (0x1F0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x1F0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x1F0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x200+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x200+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x200+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x200+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x200+0x03)))&0xC0)==0x00)
|
|
group.word (0x200+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x200+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x200+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x210+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x210+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x210+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x210+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x210+0x03)))&0xC0)==0x00)
|
|
group.word (0x210+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x210+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x210+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x220+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x220+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x220+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x220+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x220+0x03)))&0xC0)==0x00)
|
|
group.word (0x220+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x220+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x220+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x230+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x230+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x230+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x230+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x230+0x03)))&0xC0)==0x00)
|
|
group.word (0x230+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x230+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x230+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x240+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x240+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x240+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x240+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x240+0x03)))&0xC0)==0x00)
|
|
group.word (0x240+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x240+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x240+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x250+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x250+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x250+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x250+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x250+0x03)))&0xC0)==0x00)
|
|
group.word (0x250+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x250+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x250+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x260+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x260+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x260+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x260+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x260+0x03)))&0xC0)==0x00)
|
|
group.word (0x260+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x260+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x260+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x270+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x270+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x270+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x270+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x270+0x03)))&0xC0)==0x00)
|
|
group.word (0x270+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x270+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x270+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x280+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x280+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x280+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x280+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x280+0x03)))&0xC0)==0x00)
|
|
group.word (0x280+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x280+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x280+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x290+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x290+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x290+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x290+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x290+0x03)))&0xC0)==0x00)
|
|
group.word (0x290+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x290+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x290+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x2A0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x2A0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x2A0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x2A0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x2A0+0x03)))&0xC0)==0x00)
|
|
group.word (0x2A0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x2A0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x2A0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x2B0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x2B0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x2B0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x2B0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x2B0+0x03)))&0xC0)==0x00)
|
|
group.word (0x2B0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x2B0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x2B0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x2C0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x2C0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x2C0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x2C0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x2C0+0x03)))&0xC0)==0x00)
|
|
group.word (0x2C0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x2C0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x2C0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x2D0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x2D0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x2D0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x2D0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x2D0+0x03)))&0xC0)==0x00)
|
|
group.word (0x2D0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x2D0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x2D0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x2E0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x2E0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x2E0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x2E0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x2E0+0x03)))&0xC0)==0x00)
|
|
group.word (0x2E0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x2E0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x2E0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x2F0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x2F0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x2F0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x2F0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x2F0+0x03)))&0xC0)==0x00)
|
|
group.word (0x2F0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x2F0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x2F0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x300+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x300+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x300+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x300+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x300+0x03)))&0xC0)==0x00)
|
|
group.word (0x300+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x300+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x300+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x310+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x310+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x310+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x310+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x310+0x03)))&0xC0)==0x00)
|
|
group.word (0x310+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x310+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x310+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x320+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x320+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x320+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x320+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x320+0x03)))&0xC0)==0x00)
|
|
group.word (0x320+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x320+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x320+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x330+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x330+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x330+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x330+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x330+0x03)))&0xC0)==0x00)
|
|
group.word (0x330+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x330+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x330+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x340+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x340+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x340+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x340+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x340+0x03)))&0xC0)==0x00)
|
|
group.word (0x340+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x340+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x340+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x350+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x350+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x350+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x350+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x350+0x03)))&0xC0)==0x00)
|
|
group.word (0x350+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x350+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x350+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x360+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x360+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x360+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x360+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x360+0x03)))&0xC0)==0x00)
|
|
group.word (0x360+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x360+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x360+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x370+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x370+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x370+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x370+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x370+0x03)))&0xC0)==0x00)
|
|
group.word (0x370+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x370+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x370+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x380+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x380+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x380+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x380+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x380+0x03)))&0xC0)==0x00)
|
|
group.word (0x380+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x380+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x380+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x390+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x390+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x390+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x390+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x390+0x03)))&0xC0)==0x00)
|
|
group.word (0x390+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x390+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x390+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x3A0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x3A0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x3A0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x3A0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x3A0+0x03)))&0xC0)==0x00)
|
|
group.word (0x3A0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x3A0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x3A0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x3B0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x3B0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x3B0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x3B0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x3B0+0x03)))&0xC0)==0x00)
|
|
group.word (0x3B0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x3B0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x3B0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x3C0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x3C0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x3C0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x3C0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x3C0+0x03)))&0xC0)==0x00)
|
|
group.word (0x3C0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x3C0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x3C0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x3D0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x3D0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x3D0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x3D0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x3D0+0x03)))&0xC0)==0x00)
|
|
group.word (0x3D0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x3D0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x3D0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x3E0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x3E0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x3E0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x3E0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x3E0+0x03)))&0xC0)==0x00)
|
|
group.word (0x3E0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x3E0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x3E0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
group.byte (0x3F0+0x03)++0x00
|
|
line.byte 0x00 "MRA,DTC Mode Register A"
|
|
bitfld.byte 0x00 6.--7. " MD ,DTC Transfer Mode Select" "Normal,Repeat,Block,?..."
|
|
bitfld.byte 0x00 4.--5. " SZ ,DTC Data Transfer Size" "8-bit,16-bit,32-bit,?..."
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.byte (0x3F0+0x02)++0x00
|
|
line.byte 0x00 "MRB,DTC Mode Register B"
|
|
bitfld.byte 0x00 7. " CHNE ,DTC Chain Transfer Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " CHNS ,DTC Chain Transfer Select" "Continuous,1->0 or 1->CRAH"
|
|
bitfld.byte 0x00 5. " DISEL ,DTC Interrupt Select" "On specified data,Always"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " DTS ,DTC Transfer Mode Select" "Destination,Source"
|
|
bitfld.byte 0x00 2.--3. " SM ,Transfer Source Address Addressing Mode" "Fixed,Fixed,Inc. after data tranfer,Dec. after data tranfer"
|
|
group.long (0x3F0+0x04)++0x03
|
|
line.long 0x00 "SAR,DTC Transfer Source Register"
|
|
group.long (0x3F0+0x08)++0x03
|
|
line.long 0x00 "DAR,DTC Transfer Destination Register"
|
|
if (((per.l(ad:(per.l(ad:0x40005400+0x04))+(0x3F0+0x03)))&0xC0)==0x00)
|
|
group.word (0x3F0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
else
|
|
group.word (0x3F0+0x0E)++0x01
|
|
line.word 0x00 "CRA,DTC Transfer Count Register A"
|
|
hexmask.word.byte 0x00 8.--15. 1. " CRAH ,Transfer Counter A Upper Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CRAL ,Transfer Counter A Lower Register"
|
|
endif
|
|
group.word (0x3F0+0x0C)++0x01
|
|
line.word 0x00 "CRB,DTC Transfer Count Register B"
|
|
base ad:0x40005400
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "DTCCR,DTC Control Register"
|
|
bitfld.byte 0x00 4. " RSS ,DTC Transfer Information Read Skip Enable" "Disabled,Enabled"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "DTCVBR,DTC Vector Base Register"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "DTCST,DTC Module Start Register"
|
|
bitfld.byte 0x00 0. " DTCST ,DTC Module Start" "Stopped,Started"
|
|
rgroup.word 0x0E++0x01
|
|
line.word 0x00 "DTCSTS,DTC Status Register"
|
|
bitfld.word 0x00 15. " ACT ,DTC Active Flag" "Not in progress,In progress"
|
|
hexmask.word.byte 0x00 0.--7. 1. " VECN ,DTC-Activating Vector Number Monitoring"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ELC (Event Link Controller)"
|
|
base ad:0x40041000
|
|
width 9.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "ELCR,Event Link Controller Register"
|
|
bitfld.byte 0x00 7. " ELCON ,All Event Link Enable" "Disabled,Enabled"
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "ELSEGR0,Event Link Software Event Generation Register 0"
|
|
bitfld.byte 0x00 7. " WI ,ELSEGR Register Write Disable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 6. " WE ,SEG Bit Write Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SEG ,Software Event Generation" "Normal operation,Event generated"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "ELSEGR1,Event Link Software Event Generation Register 1"
|
|
bitfld.byte 0x00 7. " WI ,ELSEGR Register Write Disable" "Enabled,Disabled"
|
|
bitfld.byte 0x00 6. " WE ,SEG Bit Write Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " SEG ,Software Event Generation" "Normal operation,Event generated"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "ELSR0,Event Link Setting Register 0"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ELS ,Event Link Select"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "ELSR1,Event Link Setting Register 1"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ELS ,Event Link Select"
|
|
group.word 0x18++0x01
|
|
line.word 0x00 "ELSR2,Event Link Setting Register 2"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ELS ,Event Link Select"
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "ELSR3,Event Link Setting Register 3"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ELS ,Event Link Select"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "ELSR8,Event Link Setting Register 8"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ELS ,Event Link Select"
|
|
group.word 0x34++0x01
|
|
line.word 0x00 "ELSR9,Event Link Setting Register 9"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ELS ,Event Link Select"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "ELSR12,Event Link Setting Register 12"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ELS ,Event Link Select"
|
|
group.word 0x48++0x01
|
|
line.word 0x00 "ELSR14,Event Link Setting Register 14"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ELS ,Event Link Select"
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "ELSR15,Event Link Setting Register 15"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ELS ,Event Link Select"
|
|
group.word 0x58++0x01
|
|
line.word 0x00 "ELSR18,Event Link Setting Register 18"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ELS ,Event Link Select"
|
|
width 0x0B
|
|
tree.end
|
|
tree "IO"
|
|
tree "Port 0"
|
|
base ad:0x40040000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x00 31. " PODR15 ,P015 Output Data" "Low,High"
|
|
bitfld.long 0x00 30. " PODR14 ,P014 Output Data" "Low,High"
|
|
bitfld.long 0x00 29. " PODR13 ,P013 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PODR12 ,P012 Output Data" "Low,High"
|
|
bitfld.long 0x00 27. " PODR11 ,P011 Output Data" "Low,High"
|
|
bitfld.long 0x00 26. " PODR10 ,P010 Output Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 20. " PODR04 ,P004 Output Data" "Low,High"
|
|
bitfld.long 0x00 19. " PODR03 ,P003 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 18. " PODR02 ,P002 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 17. " PODR01 ,P001 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PODR00 ,P000 Output Data" "Low,High"
|
|
bitfld.long 0x00 15. " PDR15 ,P015 Direction" "Input,Output"
|
|
bitfld.long 0x00 14. " PDR14 ,P014 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " PDR13 ,P013 Direction" "Input,Output"
|
|
bitfld.long 0x00 12. " PDR12 ,P012 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDR11 ,P011 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 10. " PDR10 ,P010 Direction" "Input,Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 4. " PDR04 ,P004 Direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDR03 ,P003 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 2. " PDR02 ,P002 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 1. " PDR01 ,P001 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " PDR00 ,P000 Direction" "Input,Output"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x00 15. " PIDR15 ,P015 Input Data" "Low,High"
|
|
bitfld.long 0x00 14. " PIDR14 ,P014 Input Data" "Low,High"
|
|
bitfld.long 0x00 13. " PIDR13 ,P013 Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PIDR12 ,P012 Input Data" "Low,High"
|
|
bitfld.long 0x00 11. " PIDR11 ,P011 Input Data" "Low,High"
|
|
bitfld.long 0x00 10. " PIDR10 ,P010 Input Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 4. " PIDR04 ,P004 Input Data" "Low,High"
|
|
bitfld.long 0x00 3. " PIDR03 ,P003 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 2. " PIDR02 ,P002 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 1. " PIDR01 ,P001 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " PIDR00 ,P000 Input Data" "Low,High"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x00 31. " PORR15 ,P015 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 30. " PORR14 ,P014 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 29. " PORR13 ,P013 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PORR12 ,P012 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 27. " PORR11 ,P011 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 26. " PORR10 ,P010 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 20. " PORR04 ,P004 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 19. " PORR03 ,P003 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 18. " PORR02 ,P002 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 17. " PORR01 ,P001 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PORR00 ,P000 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 15. " POSR15 ,P015 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 14. " POSR14 ,P014 Output Set" "Not affected,High output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " POSR13 ,P013 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 12. " POSR12 ,P012 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 11. " POSR11 ,P011 Output Set" "Not affected,High output"
|
|
textline " "
|
|
bitfld.long 0x00 10. " POSR10 ,P010 Output Set" "Not affected,High output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 4. " POSR04 ,P004 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 3. " POSR03 ,P003 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 2. " POSR02 ,P002 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 1. " POSR01 ,P001 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " POSR00 ,P000 Output Set" "Not affected,High output"
|
|
width 0x0B
|
|
textline ""
|
|
base ad:0x40040800
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P000PFS,Port 000 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,TS21,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P001PFS,Port 001 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,TS22,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P002PFS,Port 002 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,TS23,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "P003PFS,Port 003 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,TS24,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "P004PFS,Port 004 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,TS25,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "P010PFS,Port 010 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,TS30,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "P011PFS,Port 011 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,TS31,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "P012PFS,Port 012 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "P013PFS,Port 013 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "P014PFS,Port 014 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "P015PFS,Port 015 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,TS28,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port 1"
|
|
base ad:0x40040020
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 29. " PODR13 ,P113 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " PODR12 ,P112 Output Data" "Low,High"
|
|
bitfld.long 0x00 27. " PODR11 ,P111 Output Data" "Low,High"
|
|
bitfld.long 0x00 26. " PODR10 ,P110 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PODR09 ,P109 Output Data" "Low,High"
|
|
bitfld.long 0x00 24. " PODR08 ,P108 Output Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 23. " PODR07 ,P107 Output Data" "Low,High"
|
|
bitfld.long 0x00 22. " PODR06 ,P106 Output Data" "Low,High"
|
|
bitfld.long 0x00 21. " PODR05 ,P105 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 20. " PODR04 ,P104 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " PODR03 ,P103 Output Data" "Low,High"
|
|
bitfld.long 0x00 18. " PODR02 ,P102 Output Data" "Low,High"
|
|
bitfld.long 0x00 17. " PODR01 ,P101 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PODR00 ,P100 Output Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 13. " PDR13 ,P113 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " PDR12 ,P112 Direction" "Input,Output"
|
|
bitfld.long 0x00 11. " PDR11 ,P111 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDR10 ,P110 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PDR09 ,P109 Direction" "Input,Output"
|
|
bitfld.long 0x00 8. " PDR08 ,P108 Direction" "Input,Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 7. " PDR07 ,P107 Direction" "Input,Output"
|
|
bitfld.long 0x00 6. " PDR06 ,P106 Direction" "Input,Output"
|
|
bitfld.long 0x00 5. " PDR05 ,P105 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 4. " PDR04 ,P104 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PDR03 ,P103 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDR02 ,P102 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDR01 ,P101 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PDR00 ,P100 Direction" "Input,Output"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 29. " EIDR13 ,P113 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " EIDR12 ,P112 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 27. " EIDR11 ,P111 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 26. " EIDR10 ,P110 Event Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EIDR09 ,P109 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 24. " EIDR08 ,P108 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 23. " EIDR07 ,P107 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 22. " EIDR06 ,P106 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 21. " EIDR05 ,P105 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 20. " EIDR04 ,P104 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " EIDR03 ,P103 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 18. " EIDR02 ,P102 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 17. " EIDR01 ,P101 Event Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EIDR00 ,P100 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 13. " PIDR13 ,P113 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " PIDR12 ,P112 Input Data" "Low,High"
|
|
bitfld.long 0x00 11. " PIDR11 ,P111 Input Data" "Low,High"
|
|
bitfld.long 0x00 10. " PIDR10 ,P110 Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 9. " PIDR09 ,P109 Input Data" "Low,High"
|
|
bitfld.long 0x00 8. " PIDR08 ,P108 Input Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 7. " PIDR07 ,P107 Input Data" "Low,High"
|
|
bitfld.long 0x00 6. " PIDR06 ,P106 Input Data" "Low,High"
|
|
bitfld.long 0x00 5. " PIDR05 ,P105 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 4. " PIDR04 ,P104 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " PIDR03 ,P103 Input Data" "Low,High"
|
|
bitfld.long 0x00 2. " PIDR02 ,P102 Input Data" "Low,High"
|
|
bitfld.long 0x00 1. " PIDR01 ,P101 Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PIDR00 ,P100 Input Data" "Low,High"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 29. " PORR13 ,P113 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " PORR12 ,P112 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 27. " PORR11 ,P111 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 26. " PORR10 ,P110 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " PORR09 ,P109 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 24. " PORR08 ,P108 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 23. " PORR07 ,P107 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 22. " PORR06 ,P106 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 21. " PORR05 ,P105 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 20. " PORR04 ,P104 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " PORR03 ,P103 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 18. " PORR02 ,P102 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 17. " PORR01 ,P101 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PORR00 ,P100 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 13. " POSR13 ,P113 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " POSR12 ,P112 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 11. " POSR11 ,P111 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 10. " POSR10 ,P110 Output Set" "Not affected,High output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " POSR09 ,P109 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 8. " POSR08 ,P108 Output Set" "Not affected,High output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 7. " POSR07 ,P107 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 6. " POSR06 ,P106 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 5. " POSR05 ,P105 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 4. " POSR04 ,P104 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " POSR03 ,P103 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 2. " POSR02 ,P102 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 1. " POSR01 ,P101 Output Set" "Not affected,High output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " POSR00 ,P100 Output Set" "Not affected,High output"
|
|
group.long 0x4C++0x03
|
|
line.long 0x00 "PCNTR4,Port Control Register 4"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 29. " EORR13 ,P113 Event Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 28. " EORR12 ,P112 Event Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 27. " EORR11 ,P111 Event Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 26. " EORR10 ,P110 Event Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
bitfld.long 0x00 25. " EORR09 ,P109 Event Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 24. " EORR08 ,P108 Event Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 23. " EORR07 ,P107 Event Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 22. " EORR06 ,P106 Event Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 21. " EORR05 ,P105 Event Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 20. " EORR04 ,P104 Event Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 19. " EORR03 ,P103 Event Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 18. " EORR02 ,P102 Event Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 17. " EORR01 ,P101 Event Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
bitfld.long 0x00 16. " EORR00 ,P100 Event Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 13. " EOSR13 ,P113 Event Output Set" "Not affected,High Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 12. " EOSR12 ,P112 Event Output Set" "Not affected,High Output"
|
|
bitfld.long 0x00 11. " EOSR11 ,P111 Event Output Set" "Not affected,High Output"
|
|
bitfld.long 0x00 10. " EOSR10 ,P110 Event Output Set" "Not affected,High Output"
|
|
textline " "
|
|
bitfld.long 0x00 9. " EOSR09 ,P109 Event Output Set" "Not affected,High Output"
|
|
bitfld.long 0x00 8. " EOSR08 ,P108 Event Output Set" "Not affected,High Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 7. " EOSR07 ,P107 Event Output Set" "Not affected,High Output"
|
|
bitfld.long 0x00 6. " EOSR06 ,P106 Event Output Set" "Not affected,High Output"
|
|
bitfld.long 0x00 5. " EOSR05 ,P105 Event Output Set" "Not affected,High Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 4. " EOSR04 ,P104 Event Output Set" "Not affected,High Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 3. " EOSR03 ,P103 Event Output Set" "Not affected,High Output"
|
|
bitfld.long 0x00 2. " EOSR02 ,P102 Event Output Set" "Not affected,High Output"
|
|
bitfld.long 0x00 1. " EOSR01 ,P101 Event Output Set" "Not affected,High Output"
|
|
textline " "
|
|
bitfld.long 0x00 0. " EOSR00 ,P100 Event Output Set" "Not affected,High Output"
|
|
width 0x0B
|
|
textline ""
|
|
base ad:0x40040840
|
|
width 8.
|
|
group.long 0x00++0x3
|
|
line.long 0x00 "P100PFS,Port 100 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTIO0_A,GTETRGA_A,GTIOC5B_A,RXD0_A/SCL0_A/MISO0_A,SCK1_A,MISOA_A,SCL1_B,KR00,,,,TS26,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "P101PFS,Port 101 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTEE0,GTETRGB_A,GTIOC5A_A,TXD0_A/SDA0_A/MOSI0_A,CTS1_RST1_A/SS1_A,MOSIA_A,SDA1_B,KR01,,,,TS16,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x08++0x3
|
|
line.long 0x00 "P102PFS,Port 102 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTO0,GTOWLO_A,GTIOC2B_A,SCK0_A,,RSPCKA_A,,KR02,,ADTRG0_A,,TS15,,,,CRX0_C,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x0C++0x3
|
|
line.long 0x00 "P103PFS,Port 103 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOWUP_A,GTIOC2A_A,CTS0_RTS0_A/SS0_A,,SSLA0_A,,KR03,,,,TS14,,,,CTX0_C,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "P104PFS,Port 104 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTETRGB_B,,RXD0_C/SCL0_C/MISO0_C,,SSLA1_A,,KR04,,,,TS13,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "P105PFS,Port 105 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTETRGA_C,,,,SSLA2_A,,KR05,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "P106PFS,Port 106 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC0B_B,,,SSLA3_A,,KR06,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "P107PFS,Port 107 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC0A_B,,,,,KR07,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "P108PFS,Port 108 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "SWDIO,,GTOULO_C,GTIOC0B_A,,CTS9_RTS9_B/SS9_B,SSLB0_B,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "P109PFS,Port 109 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOVUP_A,GTIOC1A_A,,TXD9_B/SDA9_B/MOSI9_B,MOSIB_B,,,CLKOUT_B,,,TS10,,,,CTX0_A,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "P110PFS,Port 110 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOVLO_A,GTIOC1B_A,CTS0_RTS0_C/SS0_C,RXD9_B/SCL9_B/MISO9_B,MISOB_B,,,VCOUT,,,TS11,,,,CRX0_A,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "P111PFS,Port 111 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC3A_A,SCK0_C,SCK9_B,RSPCKB_B,,,,,,TS12,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "P112PFS,Port 112 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC3B_A,TXD0_C/SDA0_C/MOSI0_C,,,,,,,,TSCAP_C,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "P113PFS,Port 113 Pin Function Select Register"
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port 2"
|
|
base ad:0x40040040
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
bitfld.long 0x00 31. " PODR15 ,P215 Output Data" "Low,High"
|
|
bitfld.long 0x00 30. " PODR14 ,P214 Output Data" "Low,High"
|
|
bitfld.long 0x00 29. " PODR13 ,P213 Output Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PODR12 ,P212 Output Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 22. " PODR06 ,P206 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 21. " PODR05 ,P205 Output Data" "Low,High"
|
|
bitfld.long 0x00 20. " PODR04 ,P204 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " PODR01 ,P201 Output Data" "Low,High"
|
|
bitfld.long 0x00 16. " PODR00 ,P200 Output Data" "Low,High"
|
|
bitfld.long 0x00 13. " PDR13 ,P213 Direction" "Input,Output"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PDR12 ,P212 Direction" "Input,Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 6. " PDR06 ,P206 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 5. " PDR05 ,P205 Direction" "Input,Output"
|
|
bitfld.long 0x00 4. " PDR04 ,P204 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " PDR01 ,P201 Direction" "Input,Output"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
bitfld.long 0x00 31. " EIDR15 ,P215 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 30. " EIDR14 ,P214 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 29. " EIDR13 ,P213 Event Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EIDR12 ,P212 Event Input Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 22. " EIDR06 ,P206 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 21. " EIDR05 ,P205 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 20. " EIDR04 ,P204 Event Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " EIDR01 ,P201 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 16. " EIDR00 ,P200 Event Input Data" "Low,High"
|
|
bitfld.long 0x00 15. " PIDR15 ,P215 Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 14. " PIDR14 ,P214 Input Data" "Low,High"
|
|
bitfld.long 0x00 13. " PIDR13 ,P213 Input Data" "Low,High"
|
|
bitfld.long 0x00 12. " PIDR12 ,P212 Input Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 6. " PIDR06 ,P206 Input Data" "Low,High"
|
|
bitfld.long 0x00 5. " PIDR05 ,P205 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 4. " PIDR04 ,P204 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " PIDR01 ,P201 Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PIDR00 ,P200 Input Data" "Low,High"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
bitfld.long 0x00 31. " PORR15 ,P215 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 30. " PORR14 ,P214 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 29. " PORR13 ,P213 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " PORR12 ,P212 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 22. " PORR06 ,P206 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 21. " PORR05 ,P205 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 20. " PORR04 ,P204 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " PORR01 ,P201 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 15. " POSR15 ,P215 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 14. " POSR14 ,P214 Output Set" "Not affected,High output"
|
|
textline " "
|
|
bitfld.long 0x00 13. " POSR13 ,P213 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 12. " POSR12 ,P212 Output Set" "Not affected,High output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 6. " POSR06 ,P206 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 5. " POSR05 ,P205 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 4. " POSR04 ,P204 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " POSR01 ,P201 Output Set" "Not affected,High output"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "PCNTR4,Port Control Register 4"
|
|
bitfld.long 0x00 31. " EORR15 ,P215 Event Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 30. " EORR14 ,P214 Event Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 29. " EORR13 ,P213 Event Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
bitfld.long 0x00 28. " EORR12 ,P212 Event Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 22. " EORR06 ,P206 Event Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 21. " EORR05 ,P205 Event Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 20. " EORR04 ,P204 Event Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 17. " EORR01 ,P201 Event Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 16. " EORR00 ,P200 Event Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 15. " EOSR15 ,P215 Event Output Set" "Not affected,High Output"
|
|
textline " "
|
|
bitfld.long 0x00 14. " EOSR14 ,P214 Event Output Set" "Not affected,High Output"
|
|
bitfld.long 0x00 13. " EOSR13 ,P213 Event Output Set" "Not affected,High Output"
|
|
bitfld.long 0x00 12. " EOSR12 ,P212 Event Output Set" "Not affected,High Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 6. " EOSR06 ,P206 Event Output Set" "Not affected,High Output"
|
|
bitfld.long 0x00 5. " EOSR05 ,P205 Event Output Set" "Not affected,High Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 4. " EOSR04 ,P204 Event Output Set" "Not affected,High Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 1. " EOSR01 ,P201 Event Output Set" "Not affected,High Output"
|
|
bitfld.long 0x00 0. " EOSR00 ,P200 Event Output Set" "Not affected,High Output"
|
|
width 0x0B
|
|
textline ""
|
|
base ad:0x40040880
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P200PFS,Port 200 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x04++0x3
|
|
line.long 0x00 "P201PFS,Port 201 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "P204PFS,Port 204 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTIO1,GTIW_A,GTIOC4B_B,SCK0_D,SCK9_A,RSPCKB_A,SCL0_B,,,CACREF_A,,TS00,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x14++0x03
|
|
line.long 0x00 "P205PFS,Port 205 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTO1,GTIV_A,GTIOC4A_B,TXD0_D/SDA0_D/MOSI0_D,CTS9_RTS9_A/SS9_A,SSLB0_A,SCL1_A,,CLKOUT_A,,,TSCAP_A,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
group.long 0x18++0x03
|
|
line.long 0x00 "P206PFS,Port 206 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTIU_A,,RXD0_D/SCL0_D/MISO0_D,,SSLB1_A,SDA1_A,,,,,TS01,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
group.long 0x30++0x03
|
|
line.long 0x00 "P212PFS,Port 212 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTEE1,GTETRGB_D,,,RXD1_A/SCL1_A/MISO1_A,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x34++0x03
|
|
line.long 0x00 "P213PFS,Port 213 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTETRGA_D,,,TXD1_A/SDA1_A/MOSI_A,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x38++0x03
|
|
line.long 0x00 "P214PFS,Port 214 Pin Function Select Register"
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x3C++0x03
|
|
line.long 0x00 "P215PFS,Port 215 Pin Function Select Register"
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port 3"
|
|
base ad:0x40040060
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 20. " PODR04 ,P304 Output Data" "Low,High"
|
|
bitfld.long 0x00 19. " PODR03 ,P303 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 18. " PODR02 ,P302 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 17. " PODR01 ,P301 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PODR00 ,P300 Output Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 4. " PDR04 ,P304 Direction" "Input,Output"
|
|
bitfld.long 0x00 3. " PDR03 ,P303 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 2. " PDR02 ,P302 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 1. " PDR01 ,P301 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " PDR00 ,P300 Direction" "Input,Output"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 4. " PIDR04 ,P304 Input Data" "Low,High"
|
|
bitfld.long 0x00 3. " PIDR03 ,P303 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 2. " PIDR02 ,P302 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 1. " PIDR01 ,P301 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " PIDR00 ,P300 Input Data" "Low,High"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 20. " PORR04 ,P304 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 19. " PORR03 ,P303 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 18. " PORR02 ,P302 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 17. " PORR01 ,P301 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PORR00 ,P300 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 4. " POSR04 ,P304 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 3. " POSR03 ,P303 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 2. " POSR02 ,P302 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 1. " POSR01 ,P301 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " POSR00 ,P300 Output Set" "Not affected,High output"
|
|
width 0x0B
|
|
textline ""
|
|
base ad:0x400408C0
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P300PFS,Port 300 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "SWCLK,,GTOUUP_C,GTIOC0A_A,,,SSLB1_B,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P301PFS,Port 301 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOULO_A,GTIOC4B_A,,,SSLB2_B,,,,,,TS09,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P302PFS,Port 302 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOUUP_A,GTIOC4A_A,,,SSLB3_B,,,,,,TS08,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "P303PFS,Port 303 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC1B_B,,,,,,,,,TS02,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x10++0x03
|
|
line.long 0x00 "P304PFS,Port 304 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC1A_B,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
width 0x0B
|
|
tree.end
|
|
tree "Port 4"
|
|
base ad:0x40040080
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 27. " PODR11 ,P411 Output Data" "Low,High"
|
|
bitfld.long 0x00 26. " PODR10 ,P410 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 25. " PODR09 ,P409 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 24. " PODR08 ,P408 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " PODR07 ,P407 Output Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 19. " PODR03 ,P403 Output Data" "Low,High"
|
|
bitfld.long 0x00 18. " PODR02 ,P402 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 17. " PODR01 ,P401 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PODR00 ,P400 Output Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 11. " PDR11 ,P411 Direction" "Input,Output"
|
|
bitfld.long 0x00 10. " PDR10 ,P410 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 9. " PDR09 ,P409 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 8. " PDR08 ,P408 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " PDR07 ,P407 Direction" "Input,Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 3. " PDR03 ,P403 Direction" "Input,Output"
|
|
bitfld.long 0x00 2. " PDR02 ,P402 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 1. " PDR01 ,P401 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " PDR00 ,P400 Direction" "Input,Output"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 11. " PIDR11 ,P411 Input Data" "Low,High"
|
|
bitfld.long 0x00 10. " PIDR10 ,P410 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 9. " PIDR09 ,P409 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 8. " PIDR08 ,P408 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " PIDR07 ,P407 Input Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 3. " PIDR03 ,P403 Input Data" "Low,High"
|
|
bitfld.long 0x00 2. " PIDR02 ,P402 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 1. " PIDR01 ,P401 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " PIDR00 ,P400 Input Data" "Low,High"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 27. " PORR11 ,P411 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 26. " PORR10 ,P410 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 25. " PORR09 ,P409 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 24. " PORR08 ,P408 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 23. " PORR07 ,P407 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 19. " PORR03 ,P403 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 18. " PORR02 ,P402 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 17. " PORR01 ,P401 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PORR00 ,P400 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 11. " POSR11 ,P411 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 10. " POSR10 ,P410 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 9. " POSR09 ,P409 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
bitfld.long 0x00 8. " POSR08 ,P408 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 7. " POSR07 ,P407 Output Set" "Not affected,High output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 3. " POSR03 ,P403 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 2. " POSR02 ,P402 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
bitfld.long 0x00 1. " POSR01 ,P401 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " POSR00 ,P400 Output Set" "Not affected,High output"
|
|
width 0x0B
|
|
textline ""
|
|
base ad:0x40040900
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P400PFS,Port 400 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTIO1_D,,GTIOC6A_A,SCK0_B,SCK1_B,,SCL0_A,,,CACREF_C,,TS20,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P401PFS,Port 401 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTETRGA_B,GTIOC6B_A,CTS0_RTS0_B/SS0_B,TXD1_B/SDA1_B/MOSI1_B,,SDA0_A,,,,,TS19,,,,CTX0_B,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P402PFS,Port 402 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,,RXD1_B/SCL1_B/MISO1_B,,,,,,,TS18,,,,CRX0_B,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x0C++0x03
|
|
line.long 0x00 "P403PFS,Port 403 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,GTIOC3A_B,,CTS1_RTS1_B/SS1_B,,,,,,,TS17,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
group.long 0x1C++0x03
|
|
line.long 0x00 "P407PFS,Port 407 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,,,CTS0_RTS0_D/SS0_D,,SSLB3_A,SDA0_B,,RTCOUT,ADTRG0_B,,TS03,,,,,,,USB_VBUS,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
textline " "
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")||cpuis("R7FS124773A01CNF")||cpuis("R7FS124763A01CNF")
|
|
group.long 0x20++0x03
|
|
line.long 0x00 "P408PFS,Port 408 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOWLO_B,GTIOC5B_B,,RXD9_A/SCL9_A/MISO9_A,,,,,,,TS04,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
group.long 0x24++0x03
|
|
line.long 0x00 "P409PFS,Port 409 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTOWUP_B,GTIOC5A_B,,TXD9_A/SDA9_A/MOSI9_A,,,,,,,TS05,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
group.long 0x28++0x03
|
|
line.long 0x00 "P410PFS,Port 410 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTOB1,GTOVLO_B,GTIOC6B_B,RXD0_B/SCL0_B/MISO0_B,,MISOA_B,,,,,,TS06,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x2C++0x03
|
|
line.long 0x00 "P411PFS,Port 411 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTOA1,GTOVUP_B,GTIOC6A_B,TXD0_B/SDA0_B/MOSI0_B,,MOSIA_B,,,,,,TS07,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 14. " ISEL ,IRQ Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " EOF ,Event on Falling" "No,Yes"
|
|
textline " "
|
|
bitfld.long 0x00 12. " EOR ,Event on Rising" "No,Yes"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
bitfld.long 0x00 6. " NCODR ,N-Channel Open Drain Control" "CMOS,NMOS"
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
textline " "
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
width 0x0B
|
|
tree.end
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")||cpuis("R7FS124773A01CFL")||cpuis("R7FS124763A01CFL")||cpuis("R7FS124773A01CNE")||cpuis("R7FS124763A01CNE")
|
|
tree "Port 5"
|
|
base ad:0x400400A0
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "PCNTR1,Port Control Register 1"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 18. " PODR02 ,P502 Output Data" "Low,High"
|
|
bitfld.long 0x00 17. " PODR01 ,P501 Output Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PODR00 ,P500 Output Data" "Low,High"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 2. " PDR02 ,P502 Direction" "Input,Output"
|
|
bitfld.long 0x00 1. " PDR01 ,P501 Direction" "Input,Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " PDR00 ,P500 Direction" "Input,Output"
|
|
rgroup.long 0x04++0x03
|
|
line.long 0x00 "PCNTR2,Port Control Register 2"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 2. " PIDR02 ,P502 Input Data" "Low,High"
|
|
bitfld.long 0x00 1. " PIDR01 ,P501 Input Data" "Low,High"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " PIDR00 ,P500 Input Data" "Low,High"
|
|
wgroup.long 0x08++0x03
|
|
line.long 0x00 "PCNTR3,Port Control Register 3"
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 18. " PORR02 ,P502 Output Reset" "Not affected,Low Output"
|
|
bitfld.long 0x00 17. " PORR01 ,P501 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 16. " PORR00 ,P500 Output Reset" "Not affected,Low Output"
|
|
textline " "
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
bitfld.long 0x00 2. " POSR02 ,P502 Output Set" "Not affected,High output"
|
|
bitfld.long 0x00 1. " POSR01 ,P501 Output Set" "Not affected,High output"
|
|
textline " "
|
|
endif
|
|
bitfld.long 0x00 0. " POSR00 ,P500 Output Set" "Not affected,High output"
|
|
width 0x0B
|
|
textline ""
|
|
base ad:0x40040940
|
|
width 8.
|
|
sif cpuis("R7FS124773A01CFM")||cpuis("R7FS124763A01CFM")||cpuis("R7FS124773A01CNB")||cpuis("R7FS124763A01CNB")
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "P500PFS,Port 500 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTOA0,GTIU_B,GTIOC2A_B,,,,,,,,,TS27,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
group.long 0x04++0x03
|
|
line.long 0x00 "P501PFS,Port 501 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,AGTOB0,GTIV_B,GTIOC2B_B,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
endif
|
|
group.long 0x08++0x03
|
|
line.long 0x00 "P502PFS,Port 502 Pin Function Select Register"
|
|
bitfld.long 0x00 24.--28. " PSEL ,Peripheral Select" "Hi-Z,,GTIW_B,GTIOC3B_B,?..."
|
|
bitfld.long 0x00 16. " PMR ,Port Mode Control" "General,Peripherals"
|
|
bitfld.long 0x00 15. " ASEL ,Analog Input Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCR ,Port Drive Capability" "Low,Middle"
|
|
textline " "
|
|
bitfld.long 0x00 4. " PCR ,Pull-up Control" "Pull-up disabled,Pull-up enabled"
|
|
bitfld.long 0x00 2. " PDR ,Port Direction" "Input,Output"
|
|
rbitfld.long 0x00 1. " PIDR ,Port Input Data" "Low,High"
|
|
bitfld.long 0x00 0. " PODR ,Port Output Data" "Low,high"
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
textline ""
|
|
base ad:0x40040D00
|
|
width 6.
|
|
if (((per.b(ad:0x40040D00+0x03))&0x80)==0x80)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x00 7. " B0WI ,PFSWE Bit Write Disable" "No,Yes"
|
|
rbitfld.byte 0x00 6. " PFSWE ,PmnPFS Register Write Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "PWPR,Write-Protect Register"
|
|
bitfld.byte 0x00 7. " B0WI ,PFSWE Bit Write Disable" "No,Yes"
|
|
bitfld.byte 0x00 6. " PFSWE ,PmnPFS Register Write Enable" "Disabled,Enabled"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "KINT (Key Interrupt Function)"
|
|
base ad:0x40008000
|
|
width 7.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "KRCTL,Key Return Control Register"
|
|
bitfld.byte 0x00 7. " KRMD ,Usage of Key Interrupt Flags" "Not used,Used"
|
|
bitfld.byte 0x00 0. " KREG ,Selection of Detection Edge" "Falling edge,Rising edge"
|
|
if (((per.b(ad:0x40008000))&0x80)==0x80)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "KRF,Key Return Flag Register"
|
|
bitfld.byte 0x00 7. " KRF7 ,Key Interrupt Flag 7" "Not detected,Detected"
|
|
bitfld.byte 0x00 6. " KRF6 ,Key Interrupt Flag 6" "Not detected,Detected"
|
|
bitfld.byte 0x00 5. " KRF5 ,Key Interrupt Flag 5" "Not detected,Detected"
|
|
bitfld.byte 0x00 4. " KRF4 ,Key Interrupt Flag 4" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " KRF3 ,Key Interrupt Flag 3" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " KRF2 ,Key Interrupt Flag 2" "Not detected,Detected"
|
|
bitfld.byte 0x00 1. " KRF1 ,Key Interrupt Flag 1" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " KRF0 ,Key Interrupt Flag 0" "Not detected,Detected"
|
|
else
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "KRF,Key Return Flag Register"
|
|
bitfld.byte 0x00 7. " KRF7 ,Key Interrupt Flag 7" "Not detected,?..."
|
|
bitfld.byte 0x00 6. " KRF6 ,Key Interrupt Flag 6" "Not detected,?..."
|
|
bitfld.byte 0x00 5. " KRF5 ,Key Interrupt Flag 5" "Not detected,?..."
|
|
bitfld.byte 0x00 4. " KRF4 ,Key Interrupt Flag 4" "Not detected,?..."
|
|
textline " "
|
|
bitfld.byte 0x00 3. " KRF3 ,Key Interrupt Flag 3" "Not detected,?..."
|
|
bitfld.byte 0x00 2. " KRF2 ,Key Interrupt Flag 2" "Not detected,?..."
|
|
bitfld.byte 0x00 1. " KRF1 ,Key Interrupt Flag 1" "Not detected,?..."
|
|
bitfld.byte 0x00 0. " KRF0 ,Key Interrupt Flag 0" "Not detected,?..."
|
|
endif
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "KRM,Key Return Mode Register"
|
|
bitfld.byte 0x00 7. " KRM7 ,Key Interrupt Mode Control 7" "Not detected,Detected"
|
|
bitfld.byte 0x00 6. " KRM6 ,Key Interrupt Mode Control 6" "Not detected,Detected"
|
|
bitfld.byte 0x00 5. " KRM5 ,Key Interrupt Mode Control 5" "Not detected,Detected"
|
|
bitfld.byte 0x00 4. " KRM4 ,Key Interrupt Mode Control 4" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " KRM3 ,Key Interrupt Mode Control 3" "Not detected,Detected"
|
|
bitfld.byte 0x00 2. " KRM2 ,Key Interrupt Mode Control 2" "Not detected,Detected"
|
|
bitfld.byte 0x00 1. " KRM1 ,Key Interrupt Mode Control 1" "Not detected,Detected"
|
|
bitfld.byte 0x00 0. " KRM0 ,Key Interrupt Mode Control 0" "Not detected,Detected"
|
|
width 0x0B
|
|
tree.end
|
|
tree "POEG (Port Output Enable for GPT)"
|
|
base ad:0x40042000
|
|
width 8.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "POEGGA,POEG Group A Setting Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,Noise Filter Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/128"
|
|
bitfld.long 0x00 29. " NFEN ,Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INV ,GTETRGA Input Reverse" "Not reversed,Reversed"
|
|
rbitfld.long 0x00 16. " ST ,GTETRGA Input Status Flag" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OSTPE ,Oscillation Stop Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IOCE ,Output-disable request from GPT Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PIDE ,Port Input Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSF ,Software Stop Flag" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OSTPF ,Oscillation Stop Detection Flag" "Not generated,Generated"
|
|
bitfld.long 0x00 1. " IOCF ,Output-disable request from GPT Detection Flag" "Not generated,Generated"
|
|
bitfld.long 0x00 0. " PIDF ,Port Input Detection Flag" "Not generated,Generated"
|
|
group.long 0x100++0x03
|
|
line.long 0x00 "POEGGB,POEG Group B Setting Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,Noise Filter Clock Select" "PCLKB,PCLKB/8,PCLKB/32,PCLKB/128"
|
|
bitfld.long 0x00 29. " NFEN ,Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 28. " INV ,GTETRGB Input Reverse" "Not reversed,Reversed"
|
|
rbitfld.long 0x00 16. " ST ,GTETRGB Input Status Flag" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OSTPE ,Oscillation Stop Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " IOCE ,Output-disable request from GPT Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " PIDE ,Port Input Detection Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSF ,Software Stop Flag" "Not generated,Generated"
|
|
textline " "
|
|
bitfld.long 0x00 2. " OSTPF ,Oscillation Stop Detection Flag" "Not generated,Generated"
|
|
bitfld.long 0x00 1. " IOCF ,Output-disable request from GPT Detection Flag" "Not generated,Generated"
|
|
bitfld.long 0x00 0. " PIDF ,Port Input Detection Flag" "Not generated,Generated"
|
|
width 0x0B
|
|
tree.end
|
|
tree "GPT (General PWM Timer)"
|
|
tree "32bit"
|
|
base ad:0x40078000
|
|
width 10.
|
|
group.long (0x00+0x00)++0x03
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "Enabled,Disabled"
|
|
group.long (0x04+0x00)++0x03
|
|
line.long 0x00 "GTSTR,General PWM Timer Software Start Register"
|
|
bitfld.long 0x00 6. " CSTRT6 ,Channel 6 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 5. " CSTRT5 ,Channel 5 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 4. " CSTRT4 ,Channel 4 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 3. " CSTRT3 ,Channel 3 GTCNT Count Start)" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSTRT2 ,Channel 2 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 1. " CSTRT1 ,Channel 1 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 0. " CSTRT0 ,Channel 0 GTCNT Count Start)" "No effect,Start"
|
|
group.long (0x08+0x00)++0x03
|
|
line.long 0x00 "GTSTP,General PWM Timer Software Stop Register"
|
|
bitfld.long 0x00 6. " CSTOP6 ,Channel 6 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 5. " CSTOP5 ,Channel 5 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 4. " CSTOP4 ,Channel 4 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 3. " CSTOP3 ,Channel 3 GTCNT Count Stop)" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSTOP2 ,Channel 2 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 1. " CSTOP1 ,Channel 1 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CSTOP0 ,Channel 0 GTCNT Count Stop)" "No effect,Stop"
|
|
group.long (0x0C+0x00)++0x03
|
|
line.long 0x00 "GTCLR,General PWM Timer Software Clear Register"
|
|
bitfld.long 0x00 6. " CCLR6 ,Channel 6 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CCLR5 ,Channel 5 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CCLR4 ,Channel 4 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CCLR3 ,Channel 3 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CCLR2 ,Channel 2 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CCLR1 ,Channel 1 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CCLR0 ,Channel 0 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
if (((per.w(ad:0x40078000))&0x01)==0x00)
|
|
group.long (0x10+0x00)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
group.long (0x14+0x00)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
group.long (0x18+0x00)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
group.long (0x1C+0x00)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
group.long (0x20+0x00)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long (0x24+0x00)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long (0x28+0x00)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
group.long (0x2C+0x00)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
group.long (0x30+0x00)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
group.long (0x34+0x00)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
group.long (0x38+0x00)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
group.long (0x3c+0x00)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
rbitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
group.long (0x40+0x00)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long (0x48+0x00)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long (0x4C+0x00)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long (0x50+0x00)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long (0x54+0x00)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long (0x5C+0x00)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
group.long (0x58+0x00)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
group.long (0x60+0x00)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
group.long (0x64+0x00)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
group.long (0x68+0x00)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long (0x88+0x00)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
group.long (0x8C+0x00)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
else
|
|
rgroup.long (0x10+0x00)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
rgroup.long (0x14+0x00)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
rgroup.long (0x18+0x00)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
rgroup.long (0x1C+0x00)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
rgroup.long (0x20+0x00)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
rgroup.long (0x24+0x00)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x28+0x00)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x00)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
rgroup.long (0x30+0x00)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
rgroup.long (0x34+0x00)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
rgroup.long (0x38+0x00)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
rgroup.long (0x3c+0x00)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
bitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
bitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
rgroup.long (0x40+0x00)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
rgroup.long (0x48+0x00)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
rgroup.long (0x4C+0x00)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
rgroup.long (0x50+0x00)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
rgroup.long (0x54+0x00)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
rgroup.long (0x5C+0x00)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
rgroup.long (0x58+0x00)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
rgroup.long (0x60+0x00)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
rgroup.long (0x64+0x00)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
rgroup.long (0x68+0x00)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
rgroup.long (0x88+0x00)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
rgroup.long (0x8C+0x00)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "16bit (1)"
|
|
base ad:0x40078000
|
|
width 10.
|
|
group.long (0x00+0x100)++0x03
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "Enabled,Disabled"
|
|
group.long (0x04+0x100)++0x03
|
|
line.long 0x00 "GTSTR,General PWM Timer Software Start Register"
|
|
bitfld.long 0x00 6. " CSTRT6 ,Channel 6 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 5. " CSTRT5 ,Channel 5 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 4. " CSTRT4 ,Channel 4 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 3. " CSTRT3 ,Channel 3 GTCNT Count Start)" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSTRT2 ,Channel 2 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 1. " CSTRT1 ,Channel 1 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 0. " CSTRT0 ,Channel 0 GTCNT Count Start)" "No effect,Start"
|
|
group.long (0x08+0x100)++0x03
|
|
line.long 0x00 "GTSTP,General PWM Timer Software Stop Register"
|
|
bitfld.long 0x00 6. " CSTOP6 ,Channel 6 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 5. " CSTOP5 ,Channel 5 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 4. " CSTOP4 ,Channel 4 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 3. " CSTOP3 ,Channel 3 GTCNT Count Stop)" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSTOP2 ,Channel 2 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 1. " CSTOP1 ,Channel 1 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CSTOP0 ,Channel 0 GTCNT Count Stop)" "No effect,Stop"
|
|
group.long (0x0C+0x100)++0x03
|
|
line.long 0x00 "GTCLR,General PWM Timer Software Clear Register"
|
|
bitfld.long 0x00 6. " CCLR6 ,Channel 6 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CCLR5 ,Channel 5 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CCLR4 ,Channel 4 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CCLR3 ,Channel 3 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CCLR2 ,Channel 2 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CCLR1 ,Channel 1 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CCLR0 ,Channel 0 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
if (((per.w(ad:0x40078000))&0x01)==0x00)
|
|
group.long (0x10+0x100)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
group.long (0x14+0x100)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
group.long (0x18+0x100)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
group.long (0x1C+0x100)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
group.long (0x20+0x100)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long (0x24+0x100)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long (0x28+0x100)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
group.long (0x2C+0x100)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
group.long (0x30+0x100)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
group.long (0x34+0x100)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
group.long (0x38+0x100)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
group.long (0x3c+0x100)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
rbitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
group.long (0x40+0x100)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long (0x48+0x100)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long (0x4C+0x100)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long (0x50+0x100)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long (0x54+0x100)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long (0x5C+0x100)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
group.long (0x58+0x100)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
group.long (0x60+0x100)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
group.long (0x64+0x100)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
group.long (0x68+0x100)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long (0x88+0x100)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
group.long (0x8C+0x100)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
else
|
|
rgroup.long (0x10+0x100)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
rgroup.long (0x14+0x100)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
rgroup.long (0x18+0x100)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
rgroup.long (0x1C+0x100)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
rgroup.long (0x20+0x100)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
rgroup.long (0x24+0x100)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x28+0x100)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x100)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
rgroup.long (0x30+0x100)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
rgroup.long (0x34+0x100)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
rgroup.long (0x38+0x100)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
rgroup.long (0x3c+0x100)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
bitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
bitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
rgroup.long (0x40+0x100)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
rgroup.long (0x48+0x100)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
rgroup.long (0x4C+0x100)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
rgroup.long (0x50+0x100)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
rgroup.long (0x54+0x100)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
rgroup.long (0x5C+0x100)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
rgroup.long (0x58+0x100)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
rgroup.long (0x60+0x100)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
rgroup.long (0x64+0x100)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
rgroup.long (0x68+0x100)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
rgroup.long (0x88+0x100)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
rgroup.long (0x8C+0x100)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "16bit (2)"
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base ad:0x40078000
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width 10.
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group.long (0x00+0x200)++0x03
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line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
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hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
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bitfld.long 0x00 0. " WP ,Register Write Disable" "Enabled,Disabled"
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group.long (0x04+0x200)++0x03
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line.long 0x00 "GTSTR,General PWM Timer Software Start Register"
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bitfld.long 0x00 6. " CSTRT6 ,Channel 6 GTCNT Count Start)" "No effect,Start"
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bitfld.long 0x00 5. " CSTRT5 ,Channel 5 GTCNT Count Start)" "No effect,Start"
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bitfld.long 0x00 4. " CSTRT4 ,Channel 4 GTCNT Count Start)" "No effect,Start"
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bitfld.long 0x00 3. " CSTRT3 ,Channel 3 GTCNT Count Start)" "No effect,Start"
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textline " "
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bitfld.long 0x00 2. " CSTRT2 ,Channel 2 GTCNT Count Start)" "No effect,Start"
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bitfld.long 0x00 1. " CSTRT1 ,Channel 1 GTCNT Count Start)" "No effect,Start"
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bitfld.long 0x00 0. " CSTRT0 ,Channel 0 GTCNT Count Start)" "No effect,Start"
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group.long (0x08+0x200)++0x03
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line.long 0x00 "GTSTP,General PWM Timer Software Stop Register"
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bitfld.long 0x00 6. " CSTOP6 ,Channel 6 GTCNT Count Stop)" "No effect,Stop"
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bitfld.long 0x00 5. " CSTOP5 ,Channel 5 GTCNT Count Stop)" "No effect,Stop"
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bitfld.long 0x00 4. " CSTOP4 ,Channel 4 GTCNT Count Stop)" "No effect,Stop"
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bitfld.long 0x00 3. " CSTOP3 ,Channel 3 GTCNT Count Stop)" "No effect,Stop"
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textline " "
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bitfld.long 0x00 2. " CSTOP2 ,Channel 2 GTCNT Count Stop)" "No effect,Stop"
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bitfld.long 0x00 1. " CSTOP1 ,Channel 1 GTCNT Count Stop)" "No effect,Stop"
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bitfld.long 0x00 0. " CSTOP0 ,Channel 0 GTCNT Count Stop)" "No effect,Stop"
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group.long (0x0C+0x200)++0x03
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line.long 0x00 "GTCLR,General PWM Timer Software Clear Register"
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bitfld.long 0x00 6. " CCLR6 ,Channel 6 GTCNT Counter Value Cleared)" "No effect,Clear"
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bitfld.long 0x00 5. " CCLR5 ,Channel 5 GTCNT Counter Value Cleared)" "No effect,Clear"
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bitfld.long 0x00 4. " CCLR4 ,Channel 4 GTCNT Counter Value Cleared)" "No effect,Clear"
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bitfld.long 0x00 3. " CCLR3 ,Channel 3 GTCNT Counter Value Cleared)" "No effect,Clear"
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textline " "
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bitfld.long 0x00 2. " CCLR2 ,Channel 2 GTCNT Counter Value Cleared)" "No effect,Clear"
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bitfld.long 0x00 1. " CCLR1 ,Channel 1 GTCNT Counter Value Cleared)" "No effect,Clear"
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bitfld.long 0x00 0. " CCLR0 ,Channel 0 GTCNT Counter Value Cleared)" "No effect,Clear"
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if (((per.w(ad:0x40078000))&0x01)==0x00)
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group.long (0x10+0x200)++0x03
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line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
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bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
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bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
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bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
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bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
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bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
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bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
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bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
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bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
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bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
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bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
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bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
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bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
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group.long (0x14+0x200)++0x03
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line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
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bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
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bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
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bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
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bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
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bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
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bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
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bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
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bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
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bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
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bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
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bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
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bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
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group.long (0x18+0x200)++0x03
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line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
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bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
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bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
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bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
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bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
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bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
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bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
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bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
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bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
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bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
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bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
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bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
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bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
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group.long (0x1C+0x200)++0x03
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line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
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bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
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bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
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bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
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bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
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bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
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bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
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bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
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bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
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bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
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bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
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bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
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group.long (0x20+0x200)++0x03
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line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
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bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
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bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
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bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
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bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
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bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
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bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
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bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
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bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
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bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
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bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
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bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
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group.long (0x24+0x200)++0x03
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line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
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bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
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bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
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group.long (0x28+0x200)++0x03
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line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
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bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
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bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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textline " "
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bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
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group.long (0x2C+0x200)++0x03
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line.long 0x00 "GTCR,General PWM Timer Control Register"
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bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
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bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
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bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
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group.long (0x30+0x200)++0x03
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line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
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bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
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bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
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bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
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bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
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textline " "
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bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
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bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
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bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
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group.long (0x34+0x200)++0x03
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line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
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|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
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bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
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|
textline " "
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bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
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bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
group.long (0x38+0x200)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
group.long (0x3c+0x200)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
rbitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
group.long (0x40+0x200)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long (0x48+0x200)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long (0x4C+0x200)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long (0x50+0x200)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long (0x54+0x200)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long (0x5C+0x200)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
group.long (0x58+0x200)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
group.long (0x60+0x200)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
group.long (0x64+0x200)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
group.long (0x68+0x200)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long (0x88+0x200)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
group.long (0x8C+0x200)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
else
|
|
rgroup.long (0x10+0x200)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
rgroup.long (0x14+0x200)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
rgroup.long (0x18+0x200)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
rgroup.long (0x1C+0x200)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
rgroup.long (0x20+0x200)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
rgroup.long (0x24+0x200)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x28+0x200)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x200)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
rgroup.long (0x30+0x200)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
rgroup.long (0x34+0x200)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
rgroup.long (0x38+0x200)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
rgroup.long (0x3c+0x200)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
bitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
bitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
rgroup.long (0x40+0x200)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
rgroup.long (0x48+0x200)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
rgroup.long (0x4C+0x200)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
rgroup.long (0x50+0x200)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
rgroup.long (0x54+0x200)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
rgroup.long (0x5C+0x200)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
rgroup.long (0x58+0x200)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
rgroup.long (0x60+0x200)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
rgroup.long (0x64+0x200)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
rgroup.long (0x68+0x200)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
rgroup.long (0x88+0x200)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
rgroup.long (0x8C+0x200)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "16bit (3)"
|
|
base ad:0x40078000
|
|
width 10.
|
|
group.long (0x00+0x300)++0x03
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "Enabled,Disabled"
|
|
group.long (0x04+0x300)++0x03
|
|
line.long 0x00 "GTSTR,General PWM Timer Software Start Register"
|
|
bitfld.long 0x00 6. " CSTRT6 ,Channel 6 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 5. " CSTRT5 ,Channel 5 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 4. " CSTRT4 ,Channel 4 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 3. " CSTRT3 ,Channel 3 GTCNT Count Start)" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSTRT2 ,Channel 2 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 1. " CSTRT1 ,Channel 1 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 0. " CSTRT0 ,Channel 0 GTCNT Count Start)" "No effect,Start"
|
|
group.long (0x08+0x300)++0x03
|
|
line.long 0x00 "GTSTP,General PWM Timer Software Stop Register"
|
|
bitfld.long 0x00 6. " CSTOP6 ,Channel 6 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 5. " CSTOP5 ,Channel 5 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 4. " CSTOP4 ,Channel 4 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 3. " CSTOP3 ,Channel 3 GTCNT Count Stop)" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSTOP2 ,Channel 2 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 1. " CSTOP1 ,Channel 1 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CSTOP0 ,Channel 0 GTCNT Count Stop)" "No effect,Stop"
|
|
group.long (0x0C+0x300)++0x03
|
|
line.long 0x00 "GTCLR,General PWM Timer Software Clear Register"
|
|
bitfld.long 0x00 6. " CCLR6 ,Channel 6 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CCLR5 ,Channel 5 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CCLR4 ,Channel 4 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CCLR3 ,Channel 3 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CCLR2 ,Channel 2 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CCLR1 ,Channel 1 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CCLR0 ,Channel 0 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
if (((per.w(ad:0x40078000))&0x01)==0x00)
|
|
group.long (0x10+0x300)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
group.long (0x14+0x300)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
group.long (0x18+0x300)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
group.long (0x1C+0x300)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
group.long (0x20+0x300)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long (0x24+0x300)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long (0x28+0x300)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
group.long (0x2C+0x300)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
group.long (0x30+0x300)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
group.long (0x34+0x300)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
group.long (0x38+0x300)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
group.long (0x3c+0x300)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
rbitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
group.long (0x40+0x300)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long (0x48+0x300)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long (0x4C+0x300)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long (0x50+0x300)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long (0x54+0x300)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long (0x5C+0x300)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
group.long (0x58+0x300)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
group.long (0x60+0x300)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
group.long (0x64+0x300)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
group.long (0x68+0x300)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long (0x88+0x300)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
group.long (0x8C+0x300)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
else
|
|
rgroup.long (0x10+0x300)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
rgroup.long (0x14+0x300)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
rgroup.long (0x18+0x300)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
rgroup.long (0x1C+0x300)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
rgroup.long (0x20+0x300)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
rgroup.long (0x24+0x300)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x28+0x300)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x300)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
rgroup.long (0x30+0x300)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
rgroup.long (0x34+0x300)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
rgroup.long (0x38+0x300)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
rgroup.long (0x3c+0x300)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
bitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
bitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
rgroup.long (0x40+0x300)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
rgroup.long (0x48+0x300)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
rgroup.long (0x4C+0x300)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
rgroup.long (0x50+0x300)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
rgroup.long (0x54+0x300)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
rgroup.long (0x5C+0x300)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
rgroup.long (0x58+0x300)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
rgroup.long (0x60+0x300)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
rgroup.long (0x64+0x300)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
rgroup.long (0x68+0x300)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
rgroup.long (0x88+0x300)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
rgroup.long (0x8C+0x300)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "16bit (4)"
|
|
base ad:0x40078000
|
|
width 10.
|
|
group.long (0x00+0x400)++0x03
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "Enabled,Disabled"
|
|
group.long (0x04+0x400)++0x03
|
|
line.long 0x00 "GTSTR,General PWM Timer Software Start Register"
|
|
bitfld.long 0x00 6. " CSTRT6 ,Channel 6 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 5. " CSTRT5 ,Channel 5 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 4. " CSTRT4 ,Channel 4 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 3. " CSTRT3 ,Channel 3 GTCNT Count Start)" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSTRT2 ,Channel 2 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 1. " CSTRT1 ,Channel 1 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 0. " CSTRT0 ,Channel 0 GTCNT Count Start)" "No effect,Start"
|
|
group.long (0x08+0x400)++0x03
|
|
line.long 0x00 "GTSTP,General PWM Timer Software Stop Register"
|
|
bitfld.long 0x00 6. " CSTOP6 ,Channel 6 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 5. " CSTOP5 ,Channel 5 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 4. " CSTOP4 ,Channel 4 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 3. " CSTOP3 ,Channel 3 GTCNT Count Stop)" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSTOP2 ,Channel 2 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 1. " CSTOP1 ,Channel 1 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CSTOP0 ,Channel 0 GTCNT Count Stop)" "No effect,Stop"
|
|
group.long (0x0C+0x400)++0x03
|
|
line.long 0x00 "GTCLR,General PWM Timer Software Clear Register"
|
|
bitfld.long 0x00 6. " CCLR6 ,Channel 6 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CCLR5 ,Channel 5 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CCLR4 ,Channel 4 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CCLR3 ,Channel 3 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CCLR2 ,Channel 2 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CCLR1 ,Channel 1 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CCLR0 ,Channel 0 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
if (((per.w(ad:0x40078000))&0x01)==0x00)
|
|
group.long (0x10+0x400)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
group.long (0x14+0x400)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
group.long (0x18+0x400)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
group.long (0x1C+0x400)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
group.long (0x20+0x400)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long (0x24+0x400)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long (0x28+0x400)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
group.long (0x2C+0x400)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
group.long (0x30+0x400)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
group.long (0x34+0x400)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
group.long (0x38+0x400)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
group.long (0x3c+0x400)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
rbitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
group.long (0x40+0x400)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long (0x48+0x400)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long (0x4C+0x400)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long (0x50+0x400)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long (0x54+0x400)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long (0x5C+0x400)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
group.long (0x58+0x400)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
group.long (0x60+0x400)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
group.long (0x64+0x400)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
group.long (0x68+0x400)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long (0x88+0x400)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
group.long (0x8C+0x400)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
else
|
|
rgroup.long (0x10+0x400)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
rgroup.long (0x14+0x400)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
rgroup.long (0x18+0x400)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
rgroup.long (0x1C+0x400)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
rgroup.long (0x20+0x400)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
rgroup.long (0x24+0x400)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x28+0x400)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x400)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
rgroup.long (0x30+0x400)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
rgroup.long (0x34+0x400)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
rgroup.long (0x38+0x400)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
rgroup.long (0x3c+0x400)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
bitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
bitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
rgroup.long (0x40+0x400)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
rgroup.long (0x48+0x400)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
rgroup.long (0x4C+0x400)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
rgroup.long (0x50+0x400)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
rgroup.long (0x54+0x400)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
rgroup.long (0x5C+0x400)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
rgroup.long (0x58+0x400)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
rgroup.long (0x60+0x400)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
rgroup.long (0x64+0x400)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
rgroup.long (0x68+0x400)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
rgroup.long (0x88+0x400)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
rgroup.long (0x8C+0x400)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
sif !cpuis("R7FS124762A01CLM")&&!cpuis("R7FS124762A01CLM")&&!cpuis("R7FS124773A01CNF")&&!cpuis("R7FS124763A01CNF")
|
|
tree "16bit (5)"
|
|
base ad:0x40078000
|
|
width 10.
|
|
group.long (0x00+0x500)++0x03
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "Enabled,Disabled"
|
|
group.long (0x04+0x500)++0x03
|
|
line.long 0x00 "GTSTR,General PWM Timer Software Start Register"
|
|
bitfld.long 0x00 6. " CSTRT6 ,Channel 6 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 5. " CSTRT5 ,Channel 5 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 4. " CSTRT4 ,Channel 4 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 3. " CSTRT3 ,Channel 3 GTCNT Count Start)" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSTRT2 ,Channel 2 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 1. " CSTRT1 ,Channel 1 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 0. " CSTRT0 ,Channel 0 GTCNT Count Start)" "No effect,Start"
|
|
group.long (0x08+0x500)++0x03
|
|
line.long 0x00 "GTSTP,General PWM Timer Software Stop Register"
|
|
bitfld.long 0x00 6. " CSTOP6 ,Channel 6 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 5. " CSTOP5 ,Channel 5 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 4. " CSTOP4 ,Channel 4 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 3. " CSTOP3 ,Channel 3 GTCNT Count Stop)" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSTOP2 ,Channel 2 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 1. " CSTOP1 ,Channel 1 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CSTOP0 ,Channel 0 GTCNT Count Stop)" "No effect,Stop"
|
|
group.long (0x0C+0x500)++0x03
|
|
line.long 0x00 "GTCLR,General PWM Timer Software Clear Register"
|
|
bitfld.long 0x00 6. " CCLR6 ,Channel 6 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CCLR5 ,Channel 5 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CCLR4 ,Channel 4 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CCLR3 ,Channel 3 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CCLR2 ,Channel 2 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CCLR1 ,Channel 1 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CCLR0 ,Channel 0 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
if (((per.w(ad:0x40078000))&0x01)==0x00)
|
|
group.long (0x10+0x500)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
group.long (0x14+0x500)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
group.long (0x18+0x500)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
group.long (0x1C+0x500)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
group.long (0x20+0x500)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long (0x24+0x500)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long (0x28+0x500)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
group.long (0x2C+0x500)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
group.long (0x30+0x500)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
group.long (0x34+0x500)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
group.long (0x38+0x500)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
group.long (0x3c+0x500)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
rbitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
group.long (0x40+0x500)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long (0x48+0x500)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long (0x4C+0x500)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long (0x50+0x500)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long (0x54+0x500)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long (0x5C+0x500)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
group.long (0x58+0x500)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
group.long (0x60+0x500)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
group.long (0x64+0x500)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
group.long (0x68+0x500)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long (0x88+0x500)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
group.long (0x8C+0x500)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
else
|
|
rgroup.long (0x10+0x500)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
rgroup.long (0x14+0x500)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
rgroup.long (0x18+0x500)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
rgroup.long (0x1C+0x500)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
rgroup.long (0x20+0x500)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
rgroup.long (0x24+0x500)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x28+0x500)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x500)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
rgroup.long (0x30+0x500)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
rgroup.long (0x34+0x500)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
rgroup.long (0x38+0x500)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
rgroup.long (0x3c+0x500)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
bitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
bitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
rgroup.long (0x40+0x500)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
rgroup.long (0x48+0x500)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
rgroup.long (0x4C+0x500)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
rgroup.long (0x50+0x500)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
rgroup.long (0x54+0x500)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
rgroup.long (0x5C+0x500)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
rgroup.long (0x58+0x500)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
rgroup.long (0x60+0x500)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
rgroup.long (0x64+0x500)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
rgroup.long (0x68+0x500)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
rgroup.long (0x88+0x500)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
rgroup.long (0x8C+0x500)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
tree "16bit (6)"
|
|
base ad:0x40078000
|
|
width 10.
|
|
group.long (0x00+0x600)++0x03
|
|
line.long 0x00 "GTWP,General PWM Timer Write-Protection Register"
|
|
hexmask.long.byte 0x00 8.--15. 1. " PRKEY ,GTWP Key Code"
|
|
bitfld.long 0x00 0. " WP ,Register Write Disable" "Enabled,Disabled"
|
|
group.long (0x04+0x600)++0x03
|
|
line.long 0x00 "GTSTR,General PWM Timer Software Start Register"
|
|
bitfld.long 0x00 6. " CSTRT6 ,Channel 6 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 5. " CSTRT5 ,Channel 5 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 4. " CSTRT4 ,Channel 4 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 3. " CSTRT3 ,Channel 3 GTCNT Count Start)" "No effect,Start"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSTRT2 ,Channel 2 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 1. " CSTRT1 ,Channel 1 GTCNT Count Start)" "No effect,Start"
|
|
bitfld.long 0x00 0. " CSTRT0 ,Channel 0 GTCNT Count Start)" "No effect,Start"
|
|
group.long (0x08+0x600)++0x03
|
|
line.long 0x00 "GTSTP,General PWM Timer Software Stop Register"
|
|
bitfld.long 0x00 6. " CSTOP6 ,Channel 6 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 5. " CSTOP5 ,Channel 5 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 4. " CSTOP4 ,Channel 4 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 3. " CSTOP3 ,Channel 3 GTCNT Count Stop)" "No effect,Stop"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CSTOP2 ,Channel 2 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 1. " CSTOP1 ,Channel 1 GTCNT Count Stop)" "No effect,Stop"
|
|
bitfld.long 0x00 0. " CSTOP0 ,Channel 0 GTCNT Count Stop)" "No effect,Stop"
|
|
group.long (0x0C+0x600)++0x03
|
|
line.long 0x00 "GTCLR,General PWM Timer Software Clear Register"
|
|
bitfld.long 0x00 6. " CCLR6 ,Channel 6 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 5. " CCLR5 ,Channel 5 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 4. " CCLR4 ,Channel 4 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 3. " CCLR3 ,Channel 3 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
textline " "
|
|
bitfld.long 0x00 2. " CCLR2 ,Channel 2 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 1. " CCLR1 ,Channel 1 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
bitfld.long 0x00 0. " CCLR0 ,Channel 0 GTCNT Counter Value Cleared)" "No effect,Clear"
|
|
if (((per.w(ad:0x40078000))&0x01)==0x00)
|
|
group.long (0x10+0x600)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
group.long (0x14+0x600)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
group.long (0x18+0x600)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
group.long (0x1C+0x600)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
group.long (0x20+0x600)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
group.long (0x24+0x600)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
group.long (0x28+0x600)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
group.long (0x2C+0x600)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
group.long (0x30+0x600)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
group.long (0x34+0x600)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
group.long (0x38+0x600)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
group.long (0x3c+0x600)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
rbitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
rbitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
rbitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
group.long (0x40+0x600)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
group.long (0x48+0x600)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
group.long (0x4C+0x600)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
group.long (0x50+0x600)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
group.long (0x54+0x600)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
group.long (0x5C+0x600)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
group.long (0x58+0x600)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
group.long (0x60+0x600)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
group.long (0x64+0x600)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
group.long (0x68+0x600)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
group.long (0x88+0x600)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
group.long (0x8C+0x600)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
else
|
|
rgroup.long (0x10+0x600)++0x03
|
|
line.long 0x00 "GTSSR,General PWM Timer Start Source Select Register"
|
|
bitfld.long 0x00 31. " CSTRT ,Software Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " SSELCD ,ELCD Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " SSELCC ,ELCC Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " SSELCB ,ELCB Event Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " SSELCA ,ELCA Event Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " SSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " SSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " SSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " SSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " SSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " SSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " SSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " SSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " SSGTRGBF ,GTETRGB Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " SSGTRGBR ,GTETRGB Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " SSGTRGAF ,GTETRGA Pin Falling Input Source Counter Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " SSGTRGAR ,GTETRGA Pin Rising Input Source Counter Start Enable" "Disabled,Enabled"
|
|
rgroup.long (0x14+0x600)++0x03
|
|
line.long 0x00 "GTPSR,General PWM Timer Stop Source Select Register"
|
|
bitfld.long 0x00 31. " CSTOP ,Software Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " PSELCD ,ELCD Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " PSELCC ,ELCC Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " PSELCB ,ELCB Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " PSELCA ,ELCA Event Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " PSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " PSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " PSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " PSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " PSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " PSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " PSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " PSCARBL ,GTIOCA Pin Rising Input duringGTIOCB Value Low Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " PSGTRGBF ,GTETRGB Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " PSGTRGBR ,GTETRGB Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " PSGTRGAF ,GTETRGA Pin Falling Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " PSGTRGAR ,GTETRGA Pin Rising Input Source Counter Stop Enable" "Disabled,Enabled"
|
|
rgroup.long (0x18+0x600)++0x03
|
|
line.long 0x00 "GTCSR,General PWM Timer Clear Source Select Register"
|
|
bitfld.long 0x00 31. " CCLR ,Software Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " CSELCD ,ELCD Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " CSELCC ,ELCC Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " CSELCB ,ELCB Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " CSELCA ,ELCA Event Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " CSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " CSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " CSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " CSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " CSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " CSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " CSCARBH ,GTIOCA Pin Rising Input during GIOCB Value High Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 8. " CSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " CSGTRGBF ,GTETRGB Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " CSGTRGBR ,GTETRGB Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " CSGTRGAF ,GTETRGA Pin Falling Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CSGTRGAR ,GTETRGA Pin Rising Input Source Counter Clear Enable" "Disabled,Enabled"
|
|
rgroup.long (0x1C+0x600)++0x03
|
|
line.long 0x00 "GTUPSR,General PWM Timer Up Count Source Select Register"
|
|
bitfld.long 0x00 19. " USELCD ,ELCD Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " USELCC ,ELCC Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " USELCB ,ELCB Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " USELCA ,ELCA Event Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " USCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " USCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " USCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " USCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " USCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " USCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " USCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " USCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Up Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " USGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " USGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " USGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " USGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Up Enable" "Disabled,Enabled"
|
|
rgroup.long (0x20+0x600)++0x03
|
|
line.long 0x00 "GTDNSR,General PWM Timer Down Count Source Select Register"
|
|
bitfld.long 0x00 19. " DSELCD ,ELCD Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " DSELCC ,ELCC Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " DSELCB ,ELCB Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " DSELCA ,ELCA Event Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " DSCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " DSCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " DSCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " DSCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " DSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " DSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " DSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " DSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Count Down Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " DSGTRGBF ,GTETRGB Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " DSGTRGBR ,GTETRGB Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " DSGTRGAF ,GTETRGA Pin Falling Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " DSGTRGAR ,GTETRGA Pin Rising Input Source Counter Count Down Enable" "Disabled,Enabled"
|
|
rgroup.long (0x24+0x600)++0x03
|
|
line.long 0x00 "GTICASR,General PWM Timer Input Capture Source Select Register A"
|
|
bitfld.long 0x00 19. " ASELCD ,ELCD Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " ASELCC ,ELCC Event Source GTCCRA Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " ASELCB ,ELCB Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " ASELCA ,ELCA Event Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " ASCBFAH ,GTIOCB Pin Falling Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " ASCBFAL ,GTIOCB Pin Falling Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " ASCBRAH ,GTIOCB Pin Rising Input during GTIOCA Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " ASCBRAL ,GTIOCB Pin Rising Input during GTIOCA Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " ASCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " ASCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " ASCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " ASCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " ASGTRGBF ,GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " ASGTRGBR ,GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " ASGTRGAF ,GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " ASGTRGAR ,GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x28+0x600)++0x03
|
|
line.long 0x00 "GTICBSR,General PWM Timer Input Capture Source Select Register B"
|
|
bitfld.long 0x00 19. " BSELCD ,ELCD Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " BSELCC ,ELCC Event Source GTCCRB Input Capture Enablee" "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " BSELCB ,ELCB Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " BSELCA ,ELCA Event Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " BSCBFAH ,GTIOCB Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " BSCBFAL ,GTIOCB Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " BSCBRAH ,GTIOCB Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " BSCBRAL ,GTIOCB Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 11. " BSCAFBH ,GTIOCA Pin Falling Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " BSCAFBL ,GTIOCA Pin Falling Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " BSCARBH ,GTIOCA Pin Rising Input during GTIOCB Value High Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " BSCARBL ,GTIOCA Pin Rising Input during GTIOCB Value Low Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " BSGTRGBF ,GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " BSGTRGBR ,GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " BSGTRGAF ,GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " BSGTRGAR ,GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable" "Disabled,Enabled"
|
|
rgroup.long (0x2C+0x600)++0x03
|
|
line.long 0x00 "GTCR,General PWM Timer Control Register"
|
|
bitfld.long 0x00 24.--26. " TPCS ,Timer Prescaler Select" "PCKLD,PCKLD/4,PCKLD/16,PCKLD/64,PCKLD/256,PCKLD/1024,?..."
|
|
bitfld.long 0x00 16.--18. " MD ,Mode Select" "Saw-wave PWM,Saw-wave one-shot,,,triangle PWM 1,Triangle PWM 2,Triangle PWM 3,?..."
|
|
bitfld.long 0x00 0. " CST ,Count Start" "Stopped,Performed"
|
|
rgroup.long (0x30+0x600)++0x03
|
|
line.long 0x00 "GTUDDTYC,General PWM Timer Count Direction and Duty Setting Register"
|
|
bitfld.long 0x00 27. " OBDTYR ,GTIOCB Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
bitfld.long 0x00 26. " OBDTYF ,Forcible GTIOCB Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 24.--25. " OBDTY ,GTIOCB Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 19. " OADTYR ,GTIOCA Output Value Selecting after Releasing 0%/100% Duty Setting" "Output value,Masked compare match output"
|
|
textline " "
|
|
bitfld.long 0x00 18. " OADTYF ,Forcible GTIOCA Output Duty Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 16.--17. " OADTY ,GTIOCA Output Duty Setting" "Compare match dependent,Compare match dependent,0%,100%"
|
|
bitfld.long 0x00 1. " UDF ,Forcible Count Direction Setting" "Not forced,Forced"
|
|
bitfld.long 0x00 0. " UD ,Count Direction Setting" "Count down,Count up"
|
|
rgroup.long (0x34+0x600)++0x03
|
|
line.long 0x00 "GTIOR,General PWM Timer I/O Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCSB ,Noise Filter B Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFBEN ,Noise Filter B Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 25.--26. " OBDF ,GTIOCB Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 24. " OBE ,GTIOCB Pin Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 23. " OBHLD ,GTIOCB Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
bitfld.long 0x00 22. " OBDFLT ,GTIOCB Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 16.--20. " GTIOB ,GTIOCB Pin Function Select (Initial-output)_(cycle-end)_(compare-match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
bitfld.long 0x00 14.--15. " NFCSA ,Noise Filter A Sampling Clock Select" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
textline " "
|
|
bitfld.long 0x00 13. " NFAEN ,Noise Filter A Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 9.--10. " OADF ,GTIOCA Pin Disable Value Setting" "Prohibited,Hi-Z,0,1"
|
|
bitfld.long 0x00 8. " OAE ,GTIOCA Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " OAHLD ,GTIOCA Pin Output Setting at the Start/Stop Count" "Register setting,Retained"
|
|
textline " "
|
|
bitfld.long 0x00 6. " OADFLT ,GTIOCA Pin Output Value Setting at the Count Stop" "Low,High"
|
|
bitfld.long 0x00 0.--4. " GTIOA ,GTIOCB Pin Function Select (Initial output)_(Output at cycle-end)_(Compare match)" "Low_retained_retained,Low_retained_low,Low_retained_high,Low_retained_toggled,Low_low_retained,Low_low_low,Low_low_high,Low_low_toggled,Low_high_retained,Low_high_low,Low_high_high,Low_high_toggled,Low_toggled_retained,Low_toggled_low,Low_toggled_high,Low_toggled_toggled,High_retained_retained,High_retained_low,High_retained_high,High_retained_toggled,High_low_retained,High_low_low,High_low_high,High_low_toggled,High_high_retained,High_high_low,High_high_high,High_high_toggled,High_toggled_retained,High_toggled_low,High_toggled_high,High_toggled_toggled"
|
|
rgroup.long (0x38+0x600)++0x03
|
|
line.long 0x00 "GTINTAD,General PWM Timer Interrupt Output Setting Register"
|
|
bitfld.long 0x00 30. " GRPABL ,Same Time Output Level Low Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " GRPABH ,Same Time Output Level High Disable Request Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 24.--25. " GRP ,Output Disable Source Select" "Group A,Group B,?..."
|
|
rgroup.long (0x3c+0x600)++0x03
|
|
line.long 0x00 "GTST,General PWM Timer Status Register"
|
|
bitfld.long 0x00 30. " OABLF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 29. " OABHF ,Same Time Output Level Low Flag" "No,Yes"
|
|
bitfld.long 0x00 24. " ODF ,Output Disable Flag" "No,Yes"
|
|
bitfld.long 0x00 15. " TUCF ,Count Direction Flag" "Downward,Upward"
|
|
textline " "
|
|
bitfld.long 0x00 7. " TCFPU ,Underflow Flag" "No undeflow,Underflow"
|
|
bitfld.long 0x00 6. " TCFPO ,Overflow Flag" "No overflow,Overflow"
|
|
bitfld.long 0x00 3. " TCFD ,Input Compare Match Flag D" "No match,Match"
|
|
bitfld.long 0x00 2. " TCFC ,Input Compare Match Flag C" "No match,Match"
|
|
textline " "
|
|
bitfld.long 0x00 1. " TCFB ,Input Capture/Compare Match Flag B" "No capture/match,Capture/match"
|
|
bitfld.long 0x00 0. " TCFA ,Input Capture/Compare Match Flag A" "No capture/match,Capture/match"
|
|
rgroup.long (0x40+0x600)++0x03
|
|
line.long 0x00 "GTBER,General PWM Timer Buffer Enable Register"
|
|
eventfld.long 0x00 22. " CCRSWT ,GTCCRA and GTCCRB Forcible Buffer Operation" "Not forced,Forced"
|
|
bitfld.long 0x00 20.--21. " PR ,GTPR Buffer Operation" "No operation,Single,?..."
|
|
bitfld.long 0x00 18.--19. " CCRB ,GTCCRB Buffer Operation" "No operation,Single,Double,Double"
|
|
bitfld.long 0x00 16.--17. " CCRA ,GTCCRA Buffer Operation" "No operation,Single,Double,Double"
|
|
textline " "
|
|
bitfld.long 0x00 1. " BD[1] ,GTPR Buffer Operation Disable" "No,Yes"
|
|
bitfld.long 0x00 0. " BD[0] ,GTCCR Buffer Operation Disable" "No,Yes"
|
|
rgroup.long (0x48+0x600)++0x03
|
|
line.long 0x00 "GTCNT,General PWM Timer Counter"
|
|
rgroup.long (0x4C+0x600)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register A"
|
|
rgroup.long (0x50+0x600)++0x03
|
|
line.long 0x00 "GTCCRB,General PWM Timer Compare Capture Register B"
|
|
rgroup.long (0x54+0x600)++0x03
|
|
line.long 0x00 "GTCCRC,General PWM Timer Compare Capture Register C"
|
|
rgroup.long (0x5C+0x600)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register D"
|
|
rgroup.long (0x58+0x600)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register E"
|
|
rgroup.long (0x60+0x600)++0x03
|
|
line.long 0x00 "GTCCRA,General PWM Timer Compare Capture Register F"
|
|
rgroup.long (0x64+0x600)++0x03
|
|
line.long 0x00 "GTPR,General PWM Timer Cycle Setting Register"
|
|
rgroup.long (0x68+0x600)++0x03
|
|
line.long 0x00 "GTPBR,General PWM Timer Cycle Setting Buffer Register"
|
|
rgroup.long (0x88+0x600)++0x03
|
|
line.long 0x00 "GTDTCR,General PWM Timer Dead Time Control Register"
|
|
bitfld.long 0x00 0. " TDE ,Negative-Phase Waveform Setting" "Not using GTDVU,Using GTDVU"
|
|
rgroup.long (0x8C+0x600)++0x03
|
|
line.long 0x00 "GTDVU,General PWM Timer Dead Time Value Register U"
|
|
endif
|
|
width 0x0B
|
|
tree.end
|
|
endif
|
|
textline ""
|
|
base ad:0x40078FF0
|
|
width 7.
|
|
group.long 0x00++0x03
|
|
line.long 0x00 "OPSCR,Output Phase Switching Control Register"
|
|
bitfld.long 0x00 30.--31. " NFCS ,External Input Noise Filter Clock Selection" "PCLKD,PCLKD/4,PCLKD/16,PCLKD/64"
|
|
bitfld.long 0x00 29. " NFEN ,External Input Noise Filter Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " GODF ,Group Output Disable Function" "No effect,Clear"
|
|
bitfld.long 0x00 24. " GRP ,Output Disabled Source Selection" "Group A,Group B"
|
|
textline " "
|
|
rbitfld.long 0x00 21. " ALIGN ,Input Phase Alignment" "PCLKD,PWM"
|
|
bitfld.long 0x00 20. " RV ,Output Phase Rotation Direction Reversal" "U/V/W-phase,Reverse V/W-phase"
|
|
bitfld.long 0x00 19. " INV ,Invert-Phase Output Control" "Active high,Active low"
|
|
bitfld.long 0x00 18. " N ,Negative-Phase Output (N) Control" "Level signal, PWM signal"
|
|
textline " "
|
|
bitfld.long 0x00 17. " P ,Positive-Phase Output (P) Control" "Level signal, PWM signal"
|
|
bitfld.long 0x00 16. " FB ,External Feedback Signal Enable" "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " EN ,Enable-Phase Output Control" "No Output,Output"
|
|
rbitfld.long 0x00 6. " W ,Input W-Phase Monitor" "0,1"
|
|
textline " "
|
|
rbitfld.long 0x00 5. " V ,Input W-Phase Monitor" "0,1"
|
|
rbitfld.long 0x00 4. " U ,Input W-Phase Monitor" "0,1"
|
|
bitfld.long 0x00 2. " WF ,Input Phase Soft Setting" "0,1"
|
|
bitfld.long 0x00 1. " VF ,Input Phase Soft Setting" "0,1"
|
|
textline " "
|
|
bitfld.long 0x00 0. " UF ,Input Phase Soft Setting" "0,1"
|
|
width 0x0B
|
|
tree.end
|
|
tree "AGT (Asynchronous General Purpose Timer)"
|
|
tree "AGT 1"
|
|
base ad:0x40084000
|
|
width 10.
|
|
group.word 0x00++0x05
|
|
line.word 0x00 "AGT,AGT Counter Register"
|
|
line.word 0x02 "AGTCMA,AGT Compare Match A Register"
|
|
line.word 0x04 "AGTCMB,AGT Compare Match B Register"
|
|
group.byte 0x08++0x02
|
|
line.byte 0x00 "AGTCR,AGT Control Register"
|
|
bitfld.byte 0x00 7. " TCMBF ,Compare match B flag" "No match,Match"
|
|
bitfld.byte 0x00 6. " TCMAF ,Compare match A flag" "No match,Match"
|
|
bitfld.byte 0x00 5. " TUNDF ,Underflow flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " TEDGF ,Active edge judgment flag" "Not received,Received"
|
|
bitfld.byte 0x00 2. " TSTOP ,AGT count forced stop" "Write invalid,Forced"
|
|
rbitfld.byte 0x00 1. " TCSTF ,AGT count status flag" "Stopped,Started"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TSTART ,AGT count start" "Stop,Start"
|
|
line.byte 0x01 "AGTMR1,AGT Mode Register 1"
|
|
bitfld.byte 0x01 4.--6. " TCK ,Count source" "PCLKB,PCLKB/8,,PCLKB/2,Divided AGTLCLK,Underflow signal,Divided AGTSCLK,?..."
|
|
bitfld.byte 0x01 3. " TEDGPL ,Edge polarity" "Single-edge,Both-edges"
|
|
bitfld.byte 0x01 0.--2. " TMOD ,Operating mode" "Timer,Pulse output,Event counter,Pulse width measurement,Pulse period measurement,?..."
|
|
line.byte 0x02 "AGTMR2,AGT Mode Register 2"
|
|
bitfld.byte 0x02 7. " LPM ,Low Power Mode" "Normal,Low power"
|
|
bitfld.byte 0x02 0.--2. " CKS ,AGTLCLK/AGTSCLK division" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128"
|
|
if (((per.w(ad:0x40084000+0x09))&0x07)==0x00)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,Specified for AGTEEN,?..."
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTOn output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40084000+0x09))&0x07)==0x01)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,Specified for AGTEEN,?..."
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTOn output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch" "High,Low"
|
|
elif (((per.w(ad:0x40084000+0x09))&0x07)==0x02)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,Specified for AGTEEN,?..."
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTOn output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch" "Rising edge,Falling edge"
|
|
elif (((per.w(ad:0x40084000+0x09))&0x07)==0x03)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,Specified for AGTEEN,?..."
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTOn output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch" "Low-level,High-level"
|
|
elif (((per.w(ad:0x40084000+0x09))&0x07)==0x04)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,Specified for AGTEEN,?..."
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTOn output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch" "Rising to rising,Falling to falling"
|
|
else
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,Specified for AGTEEN,?..."
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTOn output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch" "Low,High"
|
|
endif
|
|
group.byte 0x0D++0x02
|
|
line.byte 0x00 "AGTISR,AGT Event Pin Select Register"
|
|
bitfld.byte 0x00 2. " EEPS ,AGTEEn polarity selection" "Low-level,High-level"
|
|
line.byte 0x01 "AGTCMSR,AGT Compare Match Function Select Register"
|
|
bitfld.byte 0x01 6. " TOPOLB ,AGTOB polarity select" "Low,High"
|
|
bitfld.byte 0x01 5. " TOEB ,AGTOB output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " TCMEB ,Compare match B register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " TOPOLA ,AGTOA polarity select" "Low,High"
|
|
bitfld.byte 0x01 1. " TOEA ,AGTOA output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " TCMEA ,Compare match A register enable" "Disabled,Enabled"
|
|
line.byte 0x02 "AGTIOSEL,AGT Pin Select Register"
|
|
bitfld.byte 0x02 4. " TIES ,AGTIOn Input Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "AGT 2"
|
|
base ad:0x40084100
|
|
width 10.
|
|
group.word 0x00++0x05
|
|
line.word 0x00 "AGT,AGT Counter Register"
|
|
line.word 0x02 "AGTCMA,AGT Compare Match A Register"
|
|
line.word 0x04 "AGTCMB,AGT Compare Match B Register"
|
|
group.byte 0x08++0x02
|
|
line.byte 0x00 "AGTCR,AGT Control Register"
|
|
bitfld.byte 0x00 7. " TCMBF ,Compare match B flag" "No match,Match"
|
|
bitfld.byte 0x00 6. " TCMAF ,Compare match A flag" "No match,Match"
|
|
bitfld.byte 0x00 5. " TUNDF ,Underflow flag" "No underflow,Underflow"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " TEDGF ,Active edge judgment flag" "Not received,Received"
|
|
bitfld.byte 0x00 2. " TSTOP ,AGT count forced stop" "Write invalid,Forced"
|
|
rbitfld.byte 0x00 1. " TCSTF ,AGT count status flag" "Stopped,Started"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TSTART ,AGT count start" "Stop,Start"
|
|
line.byte 0x01 "AGTMR1,AGT Mode Register 1"
|
|
bitfld.byte 0x01 4.--6. " TCK ,Count source" "PCLKB,PCLKB/8,,PCLKB/2,Divided AGTLCLK,Underflow signal,Divided AGTSCLK,?..."
|
|
bitfld.byte 0x01 3. " TEDGPL ,Edge polarity" "Single-edge,Both-edges"
|
|
bitfld.byte 0x01 0.--2. " TMOD ,Operating mode" "Timer,Pulse output,Event counter,Pulse width measurement,Pulse period measurement,?..."
|
|
line.byte 0x02 "AGTMR2,AGT Mode Register 2"
|
|
bitfld.byte 0x02 7. " LPM ,Low Power Mode" "Normal,Low power"
|
|
bitfld.byte 0x02 0.--2. " CKS ,AGTLCLK/AGTSCLK division" "1,1/2,1/4,1/8,1/16,1/32,1/64,1/128"
|
|
if (((per.w(ad:0x40084100+0x09))&0x07)==0x00)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,Specified for AGTEEN,?..."
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTOn output enable" "Disabled,Enabled"
|
|
elif (((per.w(ad:0x40084100+0x09))&0x07)==0x01)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,Specified for AGTEEN,?..."
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTOn output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch" "High,Low"
|
|
elif (((per.w(ad:0x40084100+0x09))&0x07)==0x02)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,Specified for AGTEEN,?..."
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTOn output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch" "Rising edge,Falling edge"
|
|
elif (((per.w(ad:0x40084100+0x09))&0x07)==0x03)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,Specified for AGTEEN,?..."
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTOn output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch" "Low-level,High-level"
|
|
elif (((per.w(ad:0x40084100+0x09))&0x07)==0x04)
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,Specified for AGTEEN,?..."
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTOn output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch" "Rising to rising,Falling to falling"
|
|
else
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "AGTIOC,AGT I/O Control Register"
|
|
bitfld.byte 0x00 6.--7. " TIOGT ,Count control" "Always,Specified for AGTEEN,?..."
|
|
bitfld.byte 0x00 4.--5. " TIPF ,Input filter" "No filter,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 2. " TOE ,AGTOn output enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " TEDGSEL ,I/O polarity switch" "Low,High"
|
|
endif
|
|
group.byte 0x0D++0x02
|
|
line.byte 0x00 "AGTISR,AGT Event Pin Select Register"
|
|
bitfld.byte 0x00 2. " EEPS ,AGTEEn polarity selection" "Low-level,High-level"
|
|
line.byte 0x01 "AGTCMSR,AGT Compare Match Function Select Register"
|
|
bitfld.byte 0x01 6. " TOPOLB ,AGTOB polarity select" "Low,High"
|
|
bitfld.byte 0x01 5. " TOEB ,AGTOB output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " TCMEB ,Compare match B register enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 2. " TOPOLA ,AGTOA polarity select" "Low,High"
|
|
bitfld.byte 0x01 1. " TOEA ,AGTOA output enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 0. " TCMEA ,Compare match A register enable" "Disabled,Enabled"
|
|
line.byte 0x02 "AGTIOSEL,AGT Pin Select Register"
|
|
bitfld.byte 0x02 4. " TIES ,AGTIOn Input Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "RTC (Real Time Clock)"
|
|
base ad:0x40044000
|
|
width 11.
|
|
rgroup.byte 0x00++0x00
|
|
line.byte 0x00 "R64CNT,64-Hz Counter"
|
|
bitfld.byte 0x00 6. " F1HZ ,1Hz" "0,1"
|
|
bitfld.byte 0x00 5. " F2HZ ,1Hz" "0,1"
|
|
bitfld.byte 0x00 4. " F4HZ ,1Hz" "0,1"
|
|
bitfld.byte 0x00 3. " F8HZ ,1Hz" "0,1"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " F16HZ ,1Hz" "0,1"
|
|
bitfld.byte 0x00 1. " F32HZ ,1Hz" "0,1"
|
|
bitfld.byte 0x00 0. " F64HZ ,1Hz" "0,1"
|
|
if (((per.w(ad:0x40044000+0x24))&0x80)==0x0)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "RSECCNT,Second Counter (RSECCNT)/Binary Counter 0 (BCNT0)"
|
|
bitfld.byte 0x00 4.--6. " SEC10 ,10-Second Count" "0,1,2,3,4,5,,"
|
|
bitfld.byte 0x00 0.--3. " SEC1 ,1-Second Count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "RMINCNT,Minute Counter (RMINCNT)/Binary Counter 1 (BCNT1)"
|
|
bitfld.byte 0x00 4.--6. " MIN10 ,10-Minute Count" "0,1,2,3,4,5,,"
|
|
bitfld.byte 0x00 0.--3. " MIN1 ,1-Minute Count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
if (((per.b(ad:0x40044000+0x06))&0x30)<0x20)
|
|
group.byte 0x06++0x0
|
|
line.byte 0x00 "RHRCNT,Hour Counter"
|
|
bitfld.byte 0x00 6. " PM ,AM/PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HOURS ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of hours" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.b(ad:0x40044000+0x06))&0x30)==0x20)
|
|
group.byte 0x06++0x0
|
|
line.byte 0x00 "RHRCNT,Hour Counter"
|
|
bitfld.byte 0x00 6. " PM ,AM/PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HOURS ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of hours" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x06++0x0
|
|
line.byte 0x00 "RHRCNT,Hour Counter"
|
|
bitfld.byte 0x00 6. " PM ,AM/PM" "AM,PM"
|
|
bitfld.byte 0x00 4.--5. " HOURS ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of hours" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "RWKCNT,Day-of-Week Counter (RWKCNT)/Binary Counter 3 (BCNT3)"
|
|
bitfld.byte 0x00 0.--2. " DAYW ,Day-of-Week Counting" "Sunday,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "BCNT0,Binary Counter 0"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "BCNT1,Binary Counter 1"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "BCNT2,Binary Counter 2"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "BCNT3,Binary Counter 3"
|
|
endif
|
|
if (((per.b(ad:0x40044000+0x0C))&0x1F)==(0x04||0x06||0x09||0x11))
|
|
if (((per.b(ad:0x40044000+0x0A))&0x30)<0x30)
|
|
group.byte 0x0A++0x0
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x0A++0x0
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((((per.b(ad:0x40044000+0x0C))&0x1F)==0x01)||(((per.b(ad:0x40044000+0x0C))&0x1F)==0x03)||(((per.b(ad:0x40044000+0x0C))&0x1F)==0x05)||(((per.b(ad:0x40044000+0x0C))&0x1F)==0x07)||(((per.b(ad:0x40044000+0x0C))&0x1F)==0x08)||(((per.b(ad:0x40044000+0x0C))&0x1F)==0x10)||(((per.b(ad:0x40044000+0x0C))&0x1F)==0x12))
|
|
if (((per.b(ad:0x40044000+0x0A))&0x30)<0x30)
|
|
group.byte 0x0A++0x0
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x0A++0x0
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((((per.w(ad:0x40044000+0x0E))&0x0F)!=0x0)||(((per.w(ad:0x40044000+0x0E))&0xF0)!=0x0))
|
|
if ((((per.w(ad:0x40044000+0x0E))&0xF0)==0x00)||(((per.w(ad:0x40044000+0x0E))&0xF0)==0x20)||(((per.w(ad:0x40044000+0x0E))&0xF0)==0x40)||(((per.w(ad:0x40044000+0x0E))&0xF0)==0x60)||(((per.w(ad:0x40044000+0x0E))&0xF0)==0x80))
|
|
if ((((per.w(ad:0x40044000+0x0E))&0x0F)==0x0)||(((per.w(ad:0x40044000+0x0E))&0x0F)==0x4)||(((per.w(ad:0x40044000+0x0E))&0x0F)==0x8))
|
|
group.byte 0x0A++0x0
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x0A++0x0
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,-,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((((per.w(ad:0x40044000+0x0E))&0x0F)==0x2)||(((per.w(ad:0x40044000+0x0E))&0x0F)==0x6))
|
|
group.byte 0x0A++0x0
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x0A++0x0
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,-,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
else
|
|
if ((((per.w(ad:0x40044000+0x0E))&0xF000)==0x0000)||(((per.w(ad:0x40044000+0x0E))&0xF000)==0x2000)||(((per.w(ad:0x40044000+0x0E))&0xF000)==0x4000)||(((per.w(ad:0x40044000+0x0E))&0xF000)==0x6000)||(((per.w(ad:0x40044000+0x0E))&0xF000)==0x8000))
|
|
if ((((per.w(ad:0x40044000+0x0E))&0xF00)==0x0)||(((per.w(ad:0x40044000+0x0E))&0xF00)==0x400)||(((per.w(ad:0x40044000+0x0E))&0x0F00)==0x800))
|
|
group.byte 0x0A++0x0
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x0A++0x0
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,-,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if ((((per.w(ad:0x40044000+0x0E))&0xF00)==0x200)||(((per.w(ad:0x40044000+0x0E))&0xF00)==0x600))
|
|
group.byte 0x0A++0x0
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x0A++0x0
|
|
line.byte 0x00 "RDAYCNT,Day Counter"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,-,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40044000+0x0C))&0x1F)==0x00)
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "RMONCNT,Month Counter"
|
|
bitfld.byte 0x0 4. " MONTHS ,Counting ten's position of months" "-,1"
|
|
bitfld.byte 0x0 0.--3. ",Counting one's position of months" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.b(ad:0x40044000+0x0C))&0x10)<0x10)
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x0 "RMONCNT,Month Counter"
|
|
bitfld.byte 0x0 4. " MONTHS ,Counting ten's position of months" "0,1"
|
|
bitfld.byte 0x0 0.--3. ",Counting one's position of months" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x0C++0x0
|
|
line.byte 0x00 "RMONCNT,Month Counter"
|
|
bitfld.byte 0x00 4. " MONTHS ,Counting ten's position of months" "0,1"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of months" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
textline ""
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "RYRCNT,Year Counter"
|
|
bitfld.word 0x00 4.--7. " YR10 ,10-Year Count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.word 0x00 0.--3. " YR1 ,1-Year Count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
if (((per.w(ad:0x40044000+0x24))&0x80)==0x0)
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "RSECAR,Second Alarm Register (RSECCNT)/Binary Counter 0 (BCNT0)"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Not compared,Compared"
|
|
bitfld.byte 0x00 4.--6. " SEC10 ,10-Second Count" "0,1,2,3,4,5,,"
|
|
bitfld.byte 0x00 0.--3. " SEC1 ,1-Second Count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "RMINCNT,Minute Alarm register (RMINCNT)/Binary Alarm register 1 (BCNT1)"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Not compared,Compared"
|
|
bitfld.byte 0x00 4.--6. " MIN10 ,10-Minute Count" "0,1,2,3,4,5,,"
|
|
bitfld.byte 0x00 0.--3. " MIN1 ,1-Minute Count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
if (((per.b(ad:0x40044000+0x14))&0x30)<0x20)
|
|
group.byte 0x14++0x0
|
|
line.byte 0x00 "RHRAR,Hour Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RHRCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " HOURS ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of hours" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.b(ad:0x40044000+0x14))&0x30)==0x20)
|
|
group.byte 0x14++0x0
|
|
line.byte 0x00 "RHRAR,Hour Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RHRCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " HOURS ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of hours" "0,1,2,3,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x14++0x0
|
|
line.byte 0x00 "RHRAR,Hour Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RHRCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " HOURS ,Counting ten's position of hours" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of hours" "-,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
group.byte 0x16++0x0
|
|
line.byte 0x00 "RWKAR,Day of Week Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RWKCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 0.--2. " WEEKDAY ,Day-of-week counting" "Sunday,Monday,Tuesday,Wednesday,Thursday,Friday,Saturday,-"
|
|
if ((((per.b(ad:0x40044000+0x1A))&0x1F)==0x04)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x06)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x09)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x11))
|
|
if (((per.b(ad:0x40044000+0x18))&0x30)<0x30)
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RDAYCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RDAYCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,-,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
elif ((((per.b(ad:0x40044000+0x1A))&0x1F)==0x01)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x03)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x05)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x07)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x08)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x10)||(((per.b(ad:0x40044000+0x1A))&0x1F)==0x12))
|
|
if (((per.b(ad:0x40044000+0x18))&0x30)<0x30)
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RDAYCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RDAYCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,-,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40044000+0x20))&0x0F)!=0x0)
|
|
if (((per.w(ad:0x40044000+0x20))&0xF0)==(0x00||0x20||0x40||0x60||0x80))&&((((per.w(ad:0x40044000+0x20))&0x0F)==0x0)||(((per.w(ad:0x40044000+0x20))&0x0F)==0x4)||(((per.w(ad:0x40044000+0x20))&0x0F)==0x8))
|
|
;
|
|
;
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RDAYCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.w(ad:0x40044000+0x20))&0xF0)==(0x00||0x20||0x40||0x60||0x80))&&!((((per.w(ad:0x40044000+0x20))&0x0F)==0x0)||(((per.w(ad:0x40044000+0x20))&0x0F)==0x4)||(((per.w(ad:0x40044000+0x20))&0x0F)==0x8))
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RDAYCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,-,-,-,-,-,-,-"
|
|
endif
|
|
elif !(((per.w(ad:0x40044000+0x20))&0xF0)==(0x00||0x20||0x40||0x60||0x80))&&((((per.w(ad:0x40044000+0x20))&0x0F)==0x2)||(((per.w(ad:0x40044000+0x20))&0x0F)==0x6))
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RDAYCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif !(((per.w(ad:0x40044000+0x20))&0xF0)==(0x00||0x20||0x40||0x60||0x80))&&!((((per.w(ad:0x40044000+0x20))&0x0F)==0x2)||(((per.w(ad:0x40044000+0x20))&0x0F)==0x6))
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RDAYCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,-,-,-,-,-,-,-"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x40044000+0x20))&0xF000)==(0x0000||0x2000||0x4000||0x6000||0x8000))&&(((per.w(ad:0x40044000+0x20))&0xF00)==(0x0||0x400||0x800))
|
|
if (((per.w(ad:0x40044000+0x20))&0xF00)==(0x0||0x400||0x800))
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RDAYCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.w(ad:0x40044000+0x20))&0xF000)==(0x0000||0x2000||0x4000||0x6000||0x8000))&&!(((per.w(ad:0x40044000+0x20))&0xF00)==(0x0||0x400||0x800))
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RDAYCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,-,-,-,-,-,-,-"
|
|
elif !(((per.w(ad:0x40044000+0x20))&0xF000)==(0x0000||0x2000||0x4000||0x6000||0x8000))&&((((per.w(ad:0x40044000+0x20))&0xF00)==0x200)||(((per.w(ad:0x40044000+0x20))&0xF00)==0x600))
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RDAYCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x18++0x0
|
|
line.byte 0x00 "RDAYAR,Date Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RDAYCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4.--5. " DAYS ,Counting ten's position of dates" "0,1,2,-"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of dates" "0,1,2,3,4,5,6,7,8,-,-,-,-,-,-,-"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40044000+0x1A))&0x1F)==0x00)
|
|
group.byte 0x1A++0x0
|
|
line.byte 0x00 "RMONAR,Month Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RMONCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4. " MONTHS ,Counting ten's position of months" "-,1"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of months" "-,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
elif (((per.b(ad:0x40044000+0x1A))&0x10)<0x10)
|
|
group.byte 0x1A++0x0
|
|
line.byte 0x00 "RMONAR,Month Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RMONCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4. " MONTHS ,Counting ten's position of months" "0,1"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of months" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
else
|
|
group.byte 0x1A++0x0
|
|
line.byte 0x00 "RMONAR,Month Alarm Register"
|
|
bitfld.byte 0x00 7. " ENB ,Comparison with the RMONCNT value" "Not performed,Performed"
|
|
bitfld.byte 0x00 4. " MONTHS ,Counting ten's position of months" "0,1"
|
|
bitfld.byte 0x00 0.--3. ",Counting one's position of months" "0,1,2,-,-,-,-,-,-,-,-,-,-,-,-,-"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "RYRAR,Year Alarm Register (RYRAR)/Binary Counter 2 Alarm Enable Register(BCNT2AER)"
|
|
bitfld.word 0x00 4.--7. " YR10 ,10-Year Count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
bitfld.word 0x00 0.--3. " YR1 ,1-Year Count" "0,1,2,3,4,5,6,7,8,9,-,-,-,-,-,-"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "RYRAREN,Year Alarm Enable Register"
|
|
bitfld.byte 0x00 7. " ENB ,ENB" "Not compared,Compared"
|
|
else
|
|
group.byte 0x10++0x00
|
|
line.byte 0x00 "BCNT0AR,Binary Counter 0 Alarm Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "BCNT1AR,Binary Counter 1 Alarm Register"
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "BCNT2AR,Binary Counter 2 Alarm Register"
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "BCNT3AR,Binary Counter 3 Alarm Register"
|
|
group.byte 0x18++0x00
|
|
line.byte 0x00 "BCNT0AER,Binary Counter 0 Alarm Enable Register"
|
|
group.byte 0x1A++0x00
|
|
line.byte 0x00 "BCNT1AER,Binary Counter 1 Alarm Enable Register"
|
|
endif
|
|
group.word 0x1C++0x01
|
|
line.word 0x00 "BCNT2AER,Binary Counter 2 Alarm Enable Register"
|
|
hexmask.word.byte 0x00 0.--7. 1. " ENB ,"
|
|
group.byte 0x1E++0x00
|
|
line.byte 0x00 "BCNT3AER,Binary Counter 3 Alarm Enable Register"
|
|
if (((per.w(ad:0x40044000+0x28))&0x01)==0x01)
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "RCR1,RTC Control Register 1"
|
|
bitfld.byte 0x00 4.--7. " PES ,Periodic Interrupt Select" ",,,,,,1/128,1/128,1/64,1/32,1/16,1/8,1/4,1/2,1,2"
|
|
bitfld.byte 0x00 3. " RTCOS ,RTCOUT Output Select" "1Hz,64Hz"
|
|
bitfld.byte 0x00 2. " PIE ,Periodic Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CIE ,Carry Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AIE ,Alarm Interrupt Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x22++0x00
|
|
line.byte 0x00 "RCR1,RTC Control Register 1"
|
|
bitfld.byte 0x00 4.--7. " PES ,Periodic Interrupt Select" ",,,,,,1/256,1/128,1/64,1/32,1/16,1/8,1/4,1/2,1,2"
|
|
bitfld.byte 0x00 3. " RTCOS ,RTCOUT Output Select" "1Hz,64Hz"
|
|
bitfld.byte 0x00 2. " PIE ,Periodic Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " CIE ,Carry Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " AIE ,Alarm Interrupt Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.w(ad:0x40044000+0x28))&0x01)==0x01)
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "RCR2,RTC Control Register 2"
|
|
bitfld.byte 0x00 7. " CNTMD ,Count Mode Select" "Calendar,Binary"
|
|
bitfld.byte 0x00 6. " HR24 , Hours Mode" "12,24"
|
|
bitfld.byte 0x00 3. " RTCOE ,RTCOUT Output Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " ADJ30 ,30-Second Adjustment" "Normal operation,30-sec. adjustment"
|
|
bitfld.byte 0x00 1. " RESET ,RTC Software Reset" "Normal operation,Reset"
|
|
bitfld.byte 0x00 0. " START ," "Stopped,Operating normally"
|
|
else
|
|
group.byte 0x24++0x00
|
|
line.byte 0x00 "RCR2,RTC Control Register 2"
|
|
bitfld.byte 0x00 7. " CNTMD ,Count Mode Select" "Calendar,Binary"
|
|
bitfld.byte 0x00 6. " HR24 , Hours Mode" "12,24"
|
|
bitfld.byte 0x00 5. " AADJP ,Automatic Adjustment Period Select" "1min,10sec"
|
|
bitfld.byte 0x00 4. " AADJE ,Automatic Adjustment Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " RTCOE ,RTCOUT Output Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " ADJ30 ,30-Second Adjustment" "Normal operation,30-sec. adjustment"
|
|
bitfld.byte 0x00 1. " RESET ,RTC Software Reset" "Normal operation,Reset"
|
|
bitfld.byte 0x00 0. " START ," "Stopped,Operating normally"
|
|
endif
|
|
group.byte 0x28++0x00
|
|
line.byte 0x00 "RCR4,RTC Control Register 4"
|
|
bitfld.byte 0x00 0. " RCKSEL ,Count Source Select" "Sub-clock,LOCO"
|
|
group.word 0x2A++0x03
|
|
line.word 0x00 "RFRH,Frequency Register"
|
|
bitfld.word 0x00 0. " RFC16 ," "0,1"
|
|
line.word 0x02 "RFRL,Frequency Register"
|
|
group.byte 0x2E++0x00
|
|
line.byte 0x00 "RADJ,Time Error Adjustment Register"
|
|
bitfld.byte 0x00 6.--7. " PMADJ ,Plus-Minus" "Not performed,Addition to prescaler,Substraction from prescaler,"
|
|
bitfld.byte 0x00 0.--5. " ADJ ,Adjustment Value" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
width 0x0B
|
|
tree.end
|
|
tree "WDT (Watchdog Timer)"
|
|
base ad:0x40044200
|
|
width 10.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "WDTRR,WDT Refresh Register"
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "WDTCR,WDT Control Register"
|
|
bitfld.word 0x00 12.--13. " RPSS ,Window Start Position Selection" "25%,50%,75%,100%"
|
|
bitfld.word 0x00 8.--9. " RPES ,Window End Position Selection" "75%,50%,25%,0%"
|
|
bitfld.word 0x00 4.--7. " CKS ,Clock Division Ratio Selection" ",PCLK/4,,,PCLK/64,,PCLK/512,PCLK/2048,PCLK/8192,,,,,,,PCLK/128"
|
|
textline " "
|
|
bitfld.word 0x00 0.--1. " TOPS ,Timeout Period Selection" "1024,4096,8192,16384"
|
|
line.word 0x02 "WDTSR,WDT Status Register"
|
|
bitfld.word 0x02 15. " REFEF ,Refresh Error Flag" "No refresh,Refresh"
|
|
bitfld.word 0x02 14. " UNDFF ,Underflow Flag" "No underflow,Underflow"
|
|
hexmask.word 0x02 0.--13. 1. " CNTVAL ,Down-Counter Value"
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "WDTRCR,WDT Reset Control Register"
|
|
bitfld.byte 0x00 7. " RSTIRQS ,Reset Interrupt Request Selection" "Interrupt,Reset"
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "WDTCSTPR,WDT Count Stop Control Register"
|
|
bitfld.byte 0x00 7. " SLCSTP ,Sleep-Mode Count Stop Control" "Disabled,Stopped"
|
|
width 0x0B
|
|
tree.end
|
|
tree "IWDT (Independent Watchdog Timer)"
|
|
base ad:0x40044400
|
|
width 8.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "WDTRR,WDT Refresh Register"
|
|
group.word 0x02++0x01
|
|
line.word 0x00 "WDTSR,WDT Status Register"
|
|
bitfld.word 0x00 15. " REFEF ,Refresh Error Flag" "No error,Error"
|
|
bitfld.word 0x00 14. " UNDFF ,Underflow Flag" "No underflow,Underflow"
|
|
hexmask.word 0x00 0.--13. 1. " CNTVAL ,Down-Counter Value"
|
|
width 0x0B
|
|
tree.end
|
|
tree "USBFS (USB 2.0 Full-Speed Module)"
|
|
base ad:0x40090000
|
|
width 12.
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "SYSCFG,System Configuration Control Register"
|
|
bitfld.word 0x00 10. " SCKE ,USB Clock Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CNEN ,CNEN Single End Receiver Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " DPRPU ,D+ Line Resistor Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DMRPU ,D- Line Resistor Control" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " USBE ,USBFS Operation Enable" "Disabled,Enabled"
|
|
if (((per.w(ad:0x40090000+0x08))&0x03)==0x01)
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "SYSSTS0,System Configuration Status Register 0"
|
|
bitfld.word 0x00 0.--1. " LNST ,USB Data Line Status Monitor" "SE0,K-state,J-state,SE1"
|
|
elif (((per.w(ad:0x40090000+0x08))&0x03)==0x02)
|
|
rgroup.word 0x04++0x01
|
|
line.word 0x00 "SYSSTS0,System Configuration Status Register 0"
|
|
bitfld.word 0x00 0.--1. " LNST ,USB Data Line Status Monitor" "SE0,J-state,K-state,SE1"
|
|
else
|
|
hgroup.word 0x04++0x01
|
|
hide.word 0x00 "SYSSTS0,System Configuration Status Register 0"
|
|
endif
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "DVSTCTR0,Device State Control Register 0"
|
|
bitfld.word 0x00 8. " WKUP ,Wakeup Output" "No,Yes"
|
|
rbitfld.word 0x00 0.--2. " RHST ,USB Bus Reset Status" "Not determined,Low-speed,Full-speed,?..."
|
|
if (((per.w(ad:0x40090000+0x20))&0x400)==0x400)
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "CFIFO,CFIFO Port Register"
|
|
else
|
|
group.byte 0x14++0x00
|
|
line.byte 0x00 "CFIFO,CFIFO Port Register"
|
|
endif
|
|
group.word 0x20++0x03
|
|
line.word 0x00 "CFIFOSEL,CFIFO Port Select Register"
|
|
bitfld.word 0x00 15. " RCNT ,Read Count Mode" "Cleared,Decremented"
|
|
bitfld.word 0x00 14. " REW ,Buffer Pointer Rewind" "Not rewound,Rewound"
|
|
bitfld.word 0x00 10. " MBW ,CFIFO Port Access Bit Width" "8 bit,16 bit"
|
|
textline " "
|
|
bitfld.word 0x00 8. " BIGEND ,CFIFO Port Endian Control" "Little endian,Big endian"
|
|
bitfld.word 0x00 5. " ISEL ,CFIFO Port Access Direction When DCP is Selected" "Read,Write"
|
|
bitfld.word 0x00 0.--3. " CURPIPE ,CFIFO Port Access Pipe Specification" "DCP,,,,Pipe 4,Pipe 5,Pipe 6,Pipe 7,?..."
|
|
line.word 0x02 "CFIFOCTR,CFIFO Port Control Register"
|
|
bitfld.word 0x02 15. " BVAL ,Buffer Memory Valid Flag" "Invalid,Writing ended"
|
|
bitfld.word 0x02 14. " BCLR ,CPU Buffer Clear" "No effect,Clear"
|
|
rbitfld.word 0x02 13. " FRDY ,FIFO Port Ready" "Not ready,Ready"
|
|
textline " "
|
|
hexmask.word 0x02 0.--9. 1. " DTLN ,Receive Data Length"
|
|
group.word 0x30++0x01
|
|
line.word 0x00 "INTENB0,Interrupt Enable Register 0"
|
|
bitfld.word 0x00 15. " VBSE ,VBUS Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " RSME ,Resume Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " SOFE ,Frame Number Update Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DVSE ,Device State Transition Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CTRE ,Control Transfer Stage Transition Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " BEMPE ,Buffer Empty Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " NRDYE ,Buffer Not Ready Response Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " BRDYE ,Buffer Ready Interrupt Enable" "Disabled,Enabled"
|
|
group.word 0x36++0x07
|
|
line.word 0x00 "BRDYENB,BRDY Interrupt Enable Register"
|
|
bitfld.word 0x00 7. " PIPE7BRDYE ,BRDY Interrupt Enable for PIPE7" "Disabled,Enabled"
|
|
bitfld.word 0x00 6. " PIPE6BRDYE ,BRDY Interrupt Enable for PIPE6" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " PIPE5BRDYE ,BRDY Interrupt Enable for PIPE5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 4. " PIPE4BRDYE ,BRDY Interrupt Enable for PIPE4" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " PIPE0BRDYE ,BRDY Interrupt Enable for PIPE0" "Disabled,Enabled"
|
|
line.word 0x02 "NRDYENB,NRDY Interrupt Enable Register"
|
|
bitfld.word 0x02 7. " PIPE7NRDYE ,NRDY Interrupt Enable for PIPE7" "Disabled,Enabled"
|
|
bitfld.word 0x02 6. " PIPE6NRDYE ,NRDY Interrupt Enable for PIPE6" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " PIPE5NRDYE ,NRDY Interrupt Enable for PIPE5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 4. " PIPE4NRDYE ,NRDY Interrupt Enable for PIPE4" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " PIPE0NRDYE ,NRDY Interrupt Enable for PIPE0" "Disabled,Enabled"
|
|
line.word 0x04 "BEMPENB,BEMP Interrupt Enable Register"
|
|
bitfld.word 0x04 7. " PIPE7BEMPE ,BEMP Interrupt Enable for PIPE7" "Disabled,Enabled"
|
|
bitfld.word 0x04 6. " PIPE6BEMPE ,BEMP Interrupt Enable for PIPE6" "Disabled,Enabled"
|
|
bitfld.word 0x04 5. " PIPE5BEMPE ,BEMP Interrupt Enable for PIPE5" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x04 4. " PIPE4BEMPE ,BEMP Interrupt Enable for PIPE4" "Disabled,Enabled"
|
|
bitfld.word 0x04 0. " PIPE0BEMPE ,BEMP Interrupt Enable for PIPE0" "Disabled,Enabled"
|
|
line.word 0x06 "SOFCFG,SOF Output Configuration Register"
|
|
bitfld.word 0x06 6. " BRDYM ,BRDY Interrupt Status Clear Timing" "Software clears,USB clears"
|
|
rbitfld.word 0x06 4. " EDGESTS ,Edge Interrupt Output Status Monitor" ",Edge processing"
|
|
group.word 0x40++0x01
|
|
line.word 0x00 "INTSTS0,Interrupt Status Register 0"
|
|
bitfld.word 0x00 15. " VBINT ,VBUS Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 14. " RESM ,Resume Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 13. " SOFR ,Frame Number Refresh Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 12. " DVST ,Device State Transition Interrupt Status" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 11. " CTRT ,Control Transfer StageTransition Interrupt Status" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 10. " BEMP ,Buffer Empty Interrupt Status" "No interrupt,Interrupt"
|
|
textline " "
|
|
rbitfld.word 0x00 9. " NRDY ,Buffer Not Ready Interrupt Status" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 8. " BRDY ,VBUS Interrupt Status" "No interrupt,Interrupt"
|
|
rbitfld.word 0x00 7. " VBSTS ,VBUS Input Status" "Low,High"
|
|
textline " "
|
|
rbitfld.word 0x00 4.--6. " DVSQ ,Device State" "Powered,Default,Adress,Configured,Suspended,Suspended,Suspended,Suspended"
|
|
bitfld.word 0x00 3. " VBINT ,VBUS Interrupt Status" "Not received,Received"
|
|
bitfld.word 0x00 0.--2. " CTSQ ,Control Transfer Stage" "Idle/Setup,Read data,Read status,Write data,Write status,Write(no data) status,Error,?..."
|
|
group.word 0x46++0x05
|
|
line.word 0x00 "BRDYSTS,BRDY Interrupt Status Register"
|
|
bitfld.word 0x00 7. " PIPE7BRDY ,BRDY Interrupt Status for PIPE7" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 6. " PIPE6BRDY ,BRDY Interrupt Status for PIPE6" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 5. " PIPE5BRDY ,BRDY Interrupt Status for PIPE5" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x00 4. " PIPE4BRDY ,BRDY Interrupt Status for PIPE4" "No interrupt,Interrupt"
|
|
bitfld.word 0x00 0. " PIPE0BRDY ,BRDY Interrupt Status for PIPE0" "No interrupt,Interrupt"
|
|
line.word 0x02 "NRDYSTS,NRDY Interrupt Status Register"
|
|
bitfld.word 0x02 7. " PIPE7NRDY ,NRDY Interrupt Status for PIPE7" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 6. " PIPE7NRDY ,NRDY Interrupt Status for PIPE6" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 5. " PIPE7NRDY ,NRDY Interrupt Status for PIPE5" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x02 4. " PIPE7NRDY ,NRDY Interrupt Status for PIPE4" "No interrupt,Interrupt"
|
|
bitfld.word 0x02 0. " PIPE7NRDY ,NRDY Interrupt Status for PIPE0" "No interrupt,Interrupt"
|
|
line.word 0x04 "BEMPSTS,BEMP Interrupt Status Register"
|
|
bitfld.word 0x04 7. " PIPE7BEMP ,BEMP Interrupt Status for PIPE7" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 6. " PIPE6BEMP ,BEMP Interrupt Status for PIPE6" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 5. " PIPE5BEMP ,BEMP Interrupt Status for PIPE5" "No interrupt,Interrupt"
|
|
textline " "
|
|
bitfld.word 0x04 4. " PIPE4BEMP ,BEMP Interrupt Status for PIPE4" "No interrupt,Interrupt"
|
|
bitfld.word 0x04 0. " PIPE0BEMP ,BEMP Interrupt Status for PIPE0" "No interrupt,Interrupt"
|
|
group.word 0x4C++0x01
|
|
line.word 0x00 "FRMNUM,Frame Number Register"
|
|
hexmask.word 0x00 0.--10. 1. " FRNM ,Frame Number"
|
|
group.word 0x54++0x0D
|
|
line.word 0x00 "USBREQ,USB Request Type Register"
|
|
hexmask.word.byte 0x00 8.--15. 1. " BREQUEST ,Request"
|
|
hexmask.word.byte 0x00 0.--7. 1. " BMREQUESTTYPE ,Request Type"
|
|
line.word 0x02 "USBVAL,USB Request Value Register"
|
|
line.word 0x04 "USBINDX,USB Request Index Register"
|
|
line.word 0x06 "USBLENG,USB Request Length Register"
|
|
line.word 0x08 "DCPCFG,DCP Configuration Register"
|
|
bitfld.word 0x08 7. " SHTNAK ,Pipe Disabled at End of Transfer" "Continued,Disabled"
|
|
line.word 0x0A "DCPCFG,DCP Configuration Register"
|
|
hexmask.word.byte 0x0A 0.--6. 1. " MXPS ,Maximum Packet Size"
|
|
line.word 0x0C "DCPCTR,DCP Control Register"
|
|
rbitfld.word 0x0C 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
bitfld.word 0x0C 8. " SQCLR ,Sequence Toggle Bit Clear" "Invalid,Data0"
|
|
bitfld.word 0x0C 7. " SQSET ,Sequence Toggle Bit Set" "Invalid,Data1"
|
|
textline " "
|
|
rbitfld.word 0x0C 6. " SQMON ,Sequence Toggle Bit Monitor" "DATA0,DATA1"
|
|
rbitfld.word 0x0C 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
bitfld.word 0x0C 2. " CCPL ,Control Transfer End Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x0C 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
group.word 0x64++0x01
|
|
line.word 0x00 "PIPESEL,Pipe Window Select Register"
|
|
bitfld.word 0x00 0.--3. " PIPESEL ,Pipe Window Select" "None,,,,PIPE4,PIPE5,PIPE6,PIPE7,?..."
|
|
if (((per.b(ad:0x40090000+0x64))&0x0F)==(0x04||0x05))
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "PIPECFG,Pipe Configuration Register"
|
|
bitfld.word 0x00 14.--15. " TYPE ,Transfer Type" "Pipe not used,Bulk,,?..."
|
|
bitfld.word 0x00 10. " BFRE ,BRDY Interrupt Operation Specification" "Upon transmitting,Upon completion"
|
|
bitfld.word 0x00 9. " DBLB ,Double Buffer Mode" "Single,Double"
|
|
textline " "
|
|
bitfld.word 0x00 7. " SHTNAK ,Pipe Disabled at End of Transfer" "Continued,Disabled"
|
|
bitfld.word 0x00 4. " DIR ,Transfer Direction" "Receiving,Transmitting"
|
|
bitfld.word 0x00 0.--3. " EPNUM ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
elif (((per.b(ad:0x40090000+0x64))&0x0F)==(0x06||0x07))
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "PIPECFG,Pipe Configuration Register"
|
|
bitfld.word 0x00 14.--15. " TYPE ,Transfer Type" "Pipe not used,,Interrupt,?..."
|
|
bitfld.word 0x00 10. " BFRE ,BRDY Interrupt Operation Specification" "Upon transmitting,Upon completion"
|
|
bitfld.word 0x00 9. " DBLB ,Double Buffer Mode" "Single,Double"
|
|
textline " "
|
|
bitfld.word 0x00 7. " SHTNAK ,Pipe Disabled at End of Transfer" "Continued,Disabled"
|
|
bitfld.word 0x00 4. " DIR ,Transfer Direction" "Receiving,Transmitting"
|
|
bitfld.word 0x00 0.--3. " EPNUM ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
else
|
|
group.word 0x68++0x01
|
|
line.word 0x00 "PIPECFG,Pipe Configuration Register"
|
|
bitfld.word 0x00 10. " BFRE ,BRDY Interrupt Operation Specification" "Upon transmitting,Upon completion"
|
|
bitfld.word 0x00 9. " DBLB ,Double Buffer Mode" "Single,Double"
|
|
textline " "
|
|
bitfld.word 0x00 7. " SHTNAK ,Pipe Disabled at End of Transfer" "Continued,Disabled"
|
|
bitfld.word 0x00 4. " DIR ,Transfer Direction" "Receiving,Transmitting"
|
|
bitfld.word 0x00 0.--3. " EPNUM ,Endpoint Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
endif
|
|
group.word 0x6C++0x01
|
|
line.word 0x00 "PIPEMAXP,Pipe Maximum Packet Size Register"
|
|
hexmask.word 0x00 0.--8. 1. " MXPS ,Maximum Packet Size"
|
|
group.word 0x76++0x07
|
|
line.word 0x00 "PIPE4CTR,PIPE4 Control Registers"
|
|
rbitfld.word 0x00 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
rbitfld.word 0x00 14. " INBUFM ,Transmit Buffer Monitor" "No data,Data"
|
|
bitfld.word 0x00 10. " ATREPM ,Auto Response Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " SQCLR ,Sequence Toggle Bit Clear" "Disabled,DATA0"
|
|
bitfld.word 0x00 7. " SQSET ,Sequence Toggle Bit Set" "Disabled,DATA1"
|
|
textline " "
|
|
rbitfld.word 0x00 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x00 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
bitfld.word 0x00 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
line.word 0x02 "PIPE5CTR,PIPE5 Control Registers"
|
|
rbitfld.word 0x02 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
rbitfld.word 0x02 14. " INBUFM ,Transmit Buffer Monitor" "No data,Data"
|
|
bitfld.word 0x02 10. " ATREPM ,Auto Response Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " SQCLR ,Sequence Toggle Bit Clear" "Disabled,DATA0"
|
|
bitfld.word 0x02 7. " SQSET ,Sequence Toggle Bit Set" "Disabled,DATA1"
|
|
textline " "
|
|
rbitfld.word 0x02 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x02 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
bitfld.word 0x02 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
line.word 0x04 "PIPE6CTR,PIPE6 Control Registers"
|
|
rbitfld.word 0x04 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
bitfld.word 0x04 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
bitfld.word 0x04 8. " SQCLR ,Sequence Toggle Bit Clear" "Disabled,DATA0"
|
|
textline " "
|
|
bitfld.word 0x04 7. " SQSET ,Sequence Toggle Bit Set" "Disabled,DATA1"
|
|
rbitfld.word 0x04 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x04 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x04 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
line.word 0x06 "PIPE7CTR,PIPE7 Control Registers"
|
|
rbitfld.word 0x06 15. " BSTS ,Buffer Status" "Disabled,Enabled"
|
|
bitfld.word 0x06 9. " ACLRM ,Auto Buffer Clear Mode" "Disabled,Enabled"
|
|
bitfld.word 0x06 8. " SQCLR ,Sequence Toggle Bit Clear" "Disabled,DATA0"
|
|
textline " "
|
|
bitfld.word 0x06 7. " SQSET ,Sequence Toggle Bit Set" "Disabled,DATA1"
|
|
rbitfld.word 0x06 6. " SQMON ,Sequence Toggle Bit Confirmation" "DATA0,DATA1"
|
|
rbitfld.word 0x06 5. " PBUSY ,Pipe Busy" "Not busy,Busy"
|
|
textline " "
|
|
bitfld.word 0x06 0.--1. " PID ,Response PID" "NAK,BUF,STALL,STALL"
|
|
group.word 0x9C++0x01
|
|
line.word 0x00 "PIPE4TRE,PIPE4 Transaction Counter Enable Register"
|
|
bitfld.word 0x00 9. " TRENB ,Transaction Counter Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TRCLR ,Transaction Counter Clear" "No effect,Clear"
|
|
group.word 0xA0++0x01
|
|
line.word 0x00 "PIPE5TRE,PIPE5 Transaction Counter Enable Register"
|
|
bitfld.word 0x00 9. " TRENB ,Transaction Counter Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " TRCLR ,Transaction Counter Clear" "No effect,Clear"
|
|
group.word 0x9E++0x01
|
|
line.word 0x00 "PIPE4TRN,PIPE4 Transaction Counter Register"
|
|
group.word 0xA2++0x01
|
|
line.word 0x00 "PIPE5TRN,PIPE5 Transaction Counter Register"
|
|
group.word 0xCC++0x01
|
|
line.word 0x00 "USBMC,USB Module Control Register"
|
|
bitfld.word 0x00 7. " VDCEN ,USB Regulator On/Off Control" "Off,On"
|
|
bitfld.word 0x00 0. " VDDUSBE ,USB Reference Power Supply Circuit On/Off Control" "Off,On"
|
|
group.word 0xB0++0x01
|
|
line.word 0x00 "USBBCCTRL0,BC Control Register 0"
|
|
rbitfld.word 0x00 9. " PDDETSTS0 ,D+ Pin 0.6 V Input Detection Status" "Not detected,Dected"
|
|
rbitfld.word 0x00 8. " CHGDETSTS0 ,D- Pin 0.6 V Input Detection Status" "Not detected,Dected"
|
|
bitfld.word 0x00 7. " BATCHGE0 ,BC (Battery Charger) Function Ch0 General Enable Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 5. " VDMSRCE0 ,D- Pin VDMSRC (0.6 V) Output Control" "Stop,0.6V"
|
|
bitfld.word 0x00 4. " IDPSINKE0 ,D+ Pin 0.6 V Input Detection (Comparator and Sink) Control" "Off,On"
|
|
bitfld.word 0x00 3. " VDPSRCE0 ,D+ Pin VDPSRC (0.6 V) Output Control" "Stop,0.6V"
|
|
textline " "
|
|
bitfld.word 0x00 2. " IDMSINKE0 ,D- Pin 0.6 V Input Detection (Comparator and Sink) Control" "Off,On"
|
|
bitfld.word 0x00 1. " IDPSRCE0 ,D+ Pin IDPSRC Output Control" "Stop,10uA"
|
|
bitfld.word 0x00 0. " RPDME0 ,D- Pin Pull-Down Control" "Off,On"
|
|
group.word 0xC4++0x01
|
|
line.word 0x00 "UCKSEL,USB Clock Selection Register"
|
|
bitfld.word 0x00 0. " UCKSELC ,USB Clock Selection" "HOCO not selected,Hoco selected"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI (Serial Communications Interface)"
|
|
tree "SCI 0"
|
|
base ad:0x40070000
|
|
width 10.
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "RDR,Receive Data Register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RDRHL,Receive 9-bit Data Register"
|
|
rgroup.word 0x10++0x01
|
|
line.word 0x00 "FRDRHL,Receive FIFO Data Register H, L, HL"
|
|
bitfld.word 0x00 14. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.word 0x00 13. " ORER ,Overrun Error Flag" "No error,Error"
|
|
bitfld.word 0x00 12. " FER ,Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.word 0x00 11. " PER ,Parity Error Flag" "No error,Error"
|
|
bitfld.word 0x00 10. " DR ,Receive Data Ready Flag" "Not ready,Ready"
|
|
bitfld.word 0x00 9. " MPB ,Multi-Processor Bit Flag" "Data,ID"
|
|
textline " "
|
|
hexmask.word 0x00 0.--8. 1. " RDAT ,Serial Receive Data"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "TDR,Transmit Data Register"
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "TDRHL,Transmit 9-Bit Data Register"
|
|
wgroup.word 0x0E++0x01
|
|
line.word 0x00 "FTDRHL,Transmit FIFO Data Register H, L, HL"
|
|
bitfld.word 0x00 9. " MPBT ,Multi-Processor Transfer Bit Flag" "Data,ID"
|
|
hexmask.word 0x00 0.--8. 1. " TDAT ,Serial Transmit Data"
|
|
if (((per.b(ad:0x40070000+0x06))&0x01)==0x00)
|
|
if (((per.b(ad:0x40070000))&0x80)==0x80)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register for Non-Smart Card Interface mode"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/IIC,Synchronous/SPI"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
else
|
|
if (((per.b(ad:0x40070000))&0x20)==0x20)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register for Non-Smart Card Interface mode"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/IIC,Synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length (In combination with SCMR.CHR1)" "9/8 bit,9/7 bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register for Non-Smart Card Interface mode"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/IIC,Synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length (In combination with SCMR.CHR1)" "9/8 bit,9/7 bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070000))&0x20)==0x20)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register for Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " GM ,GSM mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse (In combination with SCMR.BCP2)" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register for Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " GM ,GSM mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse (In combination with SCMR.BCP2)" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070000+0x06))&0x01)==0x00)
|
|
if (((per.b(ad:0x40070000))&0x80)==0x80)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register for Non-Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Internal,Internal,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register for Non-Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "On chip,On chip,External,External"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070000))&0x80)==0x80)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register for Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Low,Output,High,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register for Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Disabled,Output,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070000+0x06))&0x01)==0x00)&&(((per.b(ad:0x40070000+0x14))&0x01)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Ongoing,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,Id"
|
|
elif (((per.b(ad:0x40070000+0x06))&0x01)==0x00)&&(((per.b(ad:0x40070000+0x14))&0x01)==0x01)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_FIFO,Serial Status Register for Non-Smart Card Interface and FIFO Mode"
|
|
bitfld.byte 0x00 7. " TDFE ,Transmit FIFO Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDF ,Receive FIFO Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Ongoing,Completed"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " DR ,Receive Data Ready Flag" "Not ready,Ready"
|
|
elif (((per.b(ad:0x40070000+0x06))&0x01)==0x01)&&(((per.b(ad:0x40070000+0x14))&0x01)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_SMCI,Serial Status Register for Non-Smart Card"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ERS ,Error Signal Status Flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Ongoing,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,Id"
|
|
else
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "SSR,Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode"
|
|
endif
|
|
if (((per.b(ad:0x40070000))&0x80)==0x80)&&(((per.b(ad:0x40070000+0x02))&0x02)!=0x02)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction 2" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9/9 bit,8/7 bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction 2" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MDRR,Modulation Duty Register"
|
|
if (((per.b(ad:0x40070000))&0x80)==0x80)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous Mode Base Clock Select" "16 cycles,8 cycles"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40070000))&0x80)==0x00)&&(((per.b(ad:0x40070000+0x02))&0x02)==0x00)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling edge"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate GeneratorDouble-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous Mode Base Clock Select" "16 cycles,8 cycles"
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "BGDM+ABCS,6 cycles"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling edge"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous Mode Base Clock Select" "16 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40070000))&0x80)==0x80)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",Not divided,/2,/4,/8,?..."
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "Not divided,?..."
|
|
endif
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No delay,1 cycle,1-2 cycles,2-3 cycles,3-4 cycles,4-5 cycles,,,,,,,,,,,,,,,,,,,,,,,,,29-30 cycles,30-31 cycles"
|
|
bitfld.byte 0x00 0. " IICM ,Simple IIC Mode Select" "0,1"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
bitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
bitfld.byte 0x00 0. " IICINTM ,IIC Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
group.byte 0x0B++0x02
|
|
line.byte 0x00 "SIMR3,I2C Mode Register 3"
|
|
bitfld.byte 0x00 6.--7. " IICSCLS ,SCL Output Select" "Serial clock,Start/Restart/Stop,Low SCLn,HI-z SCLn"
|
|
bitfld.byte 0x00 4.--5. " IICSDAS ,SDA Output Select" "Serial Data,Start/Restart/Stop,Low SDAn,HI-z SDAn"
|
|
bitfld.byte 0x00 3. " IICSTIF ,Issuing of Start, Restart, or Stop Condition Completed Flag" "Generated,Completed"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " IICSTPREQ ,Stop Condition Generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 1. " IICRSTAREQ ,Restart Condition Generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " IICSTAREQ ,Start Condition Generation" "Not generated,Generated"
|
|
line.byte 0x01 "SISR,I2C Status Register"
|
|
bitfld.byte 0x01 0. " IICACKR ,ACK Reception Data Flag" "ACK,NACK"
|
|
line.byte 0x02 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x02 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
bitfld.byte 0x02 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x02 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x02 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
bitfld.byte 0x02 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
if (((per.b(ad:0x40070000+0x14))&0x01)==0x01)&&(((per.b(ad:0x40070000))&0x80)==0x80)
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "RXI,ERI"
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
elif (((per.b(ad:0x40070000+0x14))&0x01)==0x01)&&(((per.b(ad:0x40070000))&0x80)==0x00)
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "RXI,ERI"
|
|
bitfld.word 0x00 2. " TFRST ,Transmit FIFO Data Register Reset" "No reset,Reset"
|
|
bitfld.word 0x00 1. " RFRST ,Receive FIFO Data Register Reset" "No reset,Reset"
|
|
textline " "
|
|
bitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
elif (((per.b(ad:0x40070000+0x14))&0x01)==0x00)&&(((per.b(ad:0x40070000))&0x80)==0x80)
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "RXI,ERI"
|
|
else
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "FCR,FIFO Control Register"
|
|
bitfld.word 0x00 12.--15. " RSTRG ,RTS Output Active Trigger Number Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 8.--11. " RTRG ,Receive FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
bitfld.word 0x00 4.--7. " TTRG ,Transmit FIFO Data Trigger Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
textline " "
|
|
bitfld.word 0x00 3. " DRES ,Receive Data Ready Error Select Bit" "RXI,ERI"
|
|
bitfld.word 0x00 0. " FM ,FIFO Mode Select" "Non-FIFO,FIFO"
|
|
endif
|
|
if (((per.b(ad:0x40070000+0x14))&0x01)==0x01)&&(((per.b(ad:0x40070000))&0x80)==0x80)
|
|
rgroup.word 0x16++0x01
|
|
line.word 0x00 "FDR,FIFO Data Count Register"
|
|
bitfld.word 0x00 8.--12. " T ,Receive FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0.--4. " R ,Transmit FIFO Data Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
else
|
|
hgroup.word 0x16++0x01
|
|
hide.word 0x00 "FDR,FIFO Data Count Register"
|
|
endif
|
|
if (((per.b(ad:0x40070000+0x14))&0x01)==0x01)&&(((per.b(ad:0x40070000))&0x80)==0x80)
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 8.--12. " PNUM ,Parity Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 2.--6. " FNUM ,Framing Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 0. " ORER ,Overrun Error Flag" "No overrun,Overrun"
|
|
else
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "LSR,Line Status Register"
|
|
bitfld.word 0x00 8.--12. " PNUM ,Parity Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
bitfld.word 0x00 2.--6. " FNUM ,Framing Error Count" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
endif
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "CDR,Compare Match Data Register"
|
|
hexmask.word 0x00 0.--8. 1. " CMPD ,Compare Match Data"
|
|
if (((per.b(ad:0x40070000))&0x80)==0x80)
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.byte 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
else
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.byte 0x00 7. " DCME ,Data Compare Match Enable" "Disabled,Enable"
|
|
bitfld.byte 0x00 6. " IDSEL ,ID Frame Select" "Always compare,When MPB=1"
|
|
bitfld.byte 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
endif
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SPTR,Serial Port Register"
|
|
bitfld.byte 0x00 2. " SPB2IO ,Serial Port Break I/O (Selects whether the value of SPB2DT is output to TXD pin)" "No,Yes"
|
|
bitfld.byte 0x00 1. " SPB2DT ,Serial Port Break Data Select" "Low,High"
|
|
rbitfld.byte 0x00 0. " RXDMON ,Serial Input Data Monitor" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI 1"
|
|
base ad:0x40070020
|
|
width 10.
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "RDR,Receive Data Register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RDRHL,Receive 9-bit Data Register"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "TDR,Transmit Data Register"
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "TDRHL,Transmit 9-Bit Data Register"
|
|
if (((per.b(ad:0x40070020+0x06))&0x01)==0x00)
|
|
if (((per.b(ad:0x40070020))&0x80)==0x80)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register for Non-Smart Card Interface mode"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/IIC,Synchronous/SPI"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
else
|
|
if (((per.b(ad:0x40070020))&0x20)==0x20)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register for Non-Smart Card Interface mode"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/IIC,Synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length (In combination with SCMR.CHR1)" "9/8 bit,9/7 bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register for Non-Smart Card Interface mode"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/IIC,Synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length (In combination with SCMR.CHR1)" "9/8 bit,9/7 bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070020))&0x20)==0x20)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register for Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " GM ,GSM mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse (In combination with SCMR.BCP2)" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register for Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " GM ,GSM mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse (In combination with SCMR.BCP2)" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070020+0x06))&0x01)==0x00)
|
|
if (((per.b(ad:0x40070020))&0x80)==0x80)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register for Non-Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Internal,Internal,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register for Non-Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "On chip,On chip,External,External"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070020))&0x80)==0x80)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register for Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Low,Output,High,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register for Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Disabled,Output,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070020+0x06))&0x01)==0x00)&&(((per.b(ad:0x40070020+0x14))&0x01)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Ongoing,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,Id"
|
|
elif (((per.b(ad:0x40070020+0x06))&0x01)==0x00)&&(((per.b(ad:0x40070020+0x14))&0x01)==0x01)
|
|
elif (((per.b(ad:0x40070020+0x06))&0x01)==0x01)&&(((per.b(ad:0x40070020+0x14))&0x01)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_SMCI,Serial Status Register for Non-Smart Card"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ERS ,Error Signal Status Flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Ongoing,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,Id"
|
|
else
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "SSR,Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode"
|
|
endif
|
|
if (((per.b(ad:0x40070020))&0x80)==0x80)&&(((per.b(ad:0x40070020+0x02))&0x02)!=0x02)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction 2" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9/9 bit,8/7 bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction 2" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MDRR,Modulation Duty Register"
|
|
if (((per.b(ad:0x40070020))&0x80)==0x80)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous Mode Base Clock Select" "16 cycles,8 cycles"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40070020))&0x80)==0x00)&&(((per.b(ad:0x40070020+0x02))&0x02)==0x00)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling edge"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate GeneratorDouble-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous Mode Base Clock Select" "16 cycles,8 cycles"
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "BGDM+ABCS,6 cycles"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling edge"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous Mode Base Clock Select" "16 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40070020))&0x80)==0x80)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",Not divided,/2,/4,/8,?..."
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "Not divided,?..."
|
|
endif
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No delay,1 cycle,1-2 cycles,2-3 cycles,3-4 cycles,4-5 cycles,,,,,,,,,,,,,,,,,,,,,,,,,29-30 cycles,30-31 cycles"
|
|
bitfld.byte 0x00 0. " IICM ,Simple IIC Mode Select" "0,1"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
bitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
bitfld.byte 0x00 0. " IICINTM ,IIC Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
group.byte 0x0B++0x02
|
|
line.byte 0x00 "SIMR3,I2C Mode Register 3"
|
|
bitfld.byte 0x00 6.--7. " IICSCLS ,SCL Output Select" "Serial clock,Start/Restart/Stop,Low SCLn,HI-z SCLn"
|
|
bitfld.byte 0x00 4.--5. " IICSDAS ,SDA Output Select" "Serial Data,Start/Restart/Stop,Low SDAn,HI-z SDAn"
|
|
bitfld.byte 0x00 3. " IICSTIF ,Issuing of Start, Restart, or Stop Condition Completed Flag" "Generated,Completed"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " IICSTPREQ ,Stop Condition Generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 1. " IICRSTAREQ ,Restart Condition Generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " IICSTAREQ ,Start Condition Generation" "Not generated,Generated"
|
|
line.byte 0x01 "SISR,I2C Status Register"
|
|
bitfld.byte 0x01 0. " IICACKR ,ACK Reception Data Flag" "ACK,NACK"
|
|
line.byte 0x02 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x02 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
bitfld.byte 0x02 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x02 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x02 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
bitfld.byte 0x02 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "CDR,Compare Match Data Register"
|
|
hexmask.word 0x00 0.--8. 1. " CMPD ,Compare Match Data"
|
|
if (((per.b(ad:0x40070020))&0x80)==0x80)
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.byte 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
else
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.byte 0x00 7. " DCME ,Data Compare Match Enable" "Disabled,Enable"
|
|
bitfld.byte 0x00 6. " IDSEL ,ID Frame Select" "Always compare,When MPB=1"
|
|
bitfld.byte 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
endif
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SPTR,Serial Port Register"
|
|
bitfld.byte 0x00 2. " SPB2IO ,Serial Port Break I/O (Selects whether the value of SPB2DT is output to TXD pin)" "No,Yes"
|
|
bitfld.byte 0x00 1. " SPB2DT ,Serial Port Break Data Select" "Low,High"
|
|
rbitfld.byte 0x00 0. " RXDMON ,Serial Input Data Monitor" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SCI 9"
|
|
base ad:0x40070120
|
|
width 10.
|
|
group.byte 0x05++0x00
|
|
line.byte 0x00 "RDR,Receive Data Register"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "RDRHL,Receive 9-bit Data Register"
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "TDR,Transmit Data Register"
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "TDRHL,Transmit 9-Bit Data Register"
|
|
if (((per.b(ad:0x40070120+0x06))&0x01)==0x00)
|
|
if (((per.b(ad:0x40070120))&0x80)==0x80)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register for Non-Smart Card Interface mode"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/IIC,Synchronous/SPI"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
else
|
|
if (((per.b(ad:0x40070120))&0x20)==0x20)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register for Non-Smart Card Interface mode"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/IIC,Synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length (In combination with SCMR.CHR1)" "9/8 bit,9/7 bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR,Serial Mode Register for Non-Smart Card Interface mode"
|
|
bitfld.byte 0x00 7. " CM ,Communication Mode" "Asynchronous/IIC,Synchronous/SPI"
|
|
bitfld.byte 0x00 6. " CHR ,Character Length (In combination with SCMR.CHR1)" "9/8 bit,9/7 bit"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " STOP ,Stop Bit Length" "1 bit,2 bits"
|
|
bitfld.byte 0x00 2. " MP ,Multi-Processor Mode" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
endif
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070120))&0x20)==0x20)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register for Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " GM ,GSM mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " PM ,Parity Mode" "Even,Odd"
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse (In combination with SCMR.BCP2)" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "SMR_SMCI,Serial Mode Register for Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " GM ,GSM mode" "Normal,GSM"
|
|
bitfld.byte 0x00 6. " BLK ,Block Transfer Mode" "No,Yes"
|
|
bitfld.byte 0x00 5. " PE ,Parity Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2.--3. " BCP ,Base Clock Pulse (In combination with SCMR.BCP2)" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " CKS ,Clock Select" "PCLKB,PCLKB/4,PCLKB/16,PCLKB/64"
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070120+0x06))&0x01)==0x00)
|
|
if (((per.b(ad:0x40070120))&0x80)==0x80)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register for Non-Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Internal,Internal,External,External"
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR,Serial Control Register for Non-Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "On chip,On chip,External,External"
|
|
endif
|
|
else
|
|
if (((per.b(ad:0x40070120))&0x80)==0x80)
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register for Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Low,Output,High,?..."
|
|
else
|
|
group.byte 0x02++0x00
|
|
line.byte 0x00 "SCR_SMCI,Serial Control Register for Smart Card Interface Mode"
|
|
bitfld.byte 0x00 7. " TIE ,Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " RIE ,Receive Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " TE ,Transmit Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RE ,Receive Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " MPIE ,Multi-Processor Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " TEIE ,Transmit End Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " CKE ,Clock Enable" "Disabled,Output,?..."
|
|
endif
|
|
endif
|
|
if (((per.b(ad:0x40070120+0x06))&0x01)==0x00)&&(((per.b(ad:0x40070120+0x14))&0x01)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR,Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " FER ,Framing Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Ongoing,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,Id"
|
|
elif (((per.b(ad:0x40070120+0x06))&0x01)==0x00)&&(((per.b(ad:0x40070120+0x14))&0x01)==0x01)
|
|
elif (((per.b(ad:0x40070120+0x06))&0x01)==0x01)&&(((per.b(ad:0x40070120+0x14))&0x01)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SSR_SMCI,Serial Status Register for Non-Smart Card"
|
|
bitfld.byte 0x00 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x00 6. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
bitfld.byte 0x00 5. " ORER ,Overrun Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ERS ,Error Signal Status Flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " PER ,Parity Error Flag" "No error,Error"
|
|
rbitfld.byte 0x00 2. " TEND ,Transmit End Flag" "Ongoing,Completed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " MPB ,Multi-Processor" "Data,ID"
|
|
bitfld.byte 0x00 0. " MPBT ,Multi-Processor Bit Transfer" "Data,Id"
|
|
else
|
|
hgroup.byte 0x04++0x00
|
|
hide.byte 0x00 "SSR,Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode"
|
|
endif
|
|
if (((per.b(ad:0x40070120))&0x80)==0x80)&&(((per.b(ad:0x40070120+0x02))&0x02)!=0x02)
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction 2" "LSB,MSB"
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
else
|
|
group.byte 0x06++0x00
|
|
line.byte 0x00 "SCMR,Smart Card Mode Register"
|
|
bitfld.byte 0x00 7. " BCP2 ,Base Clock Pulse 2" "0,1"
|
|
bitfld.byte 0x00 4. " CHR1 ,Character Length 1" "9/9 bit,8/7 bit"
|
|
bitfld.byte 0x00 3. " SDIR ,Transmitted/Received Data Transfer Direction 2" "LSB,MSB"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " SINV ,Transmitted/Received Data Invert" "Not inverted,Inverted"
|
|
bitfld.byte 0x00 0. " SMIF ,Smart Card Interface Mode Select" "Non-smart,Smart"
|
|
endif
|
|
group.byte 0x01++0x00
|
|
line.byte 0x00 "BRR,Bit Rate Register"
|
|
group.byte 0x12++0x00
|
|
line.byte 0x00 "MDRR,Modulation Duty Register"
|
|
if (((per.b(ad:0x40070120))&0x80)==0x80)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous Mode Base Clock Select" "16 cycles,8 cycles"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40070120))&0x80)==0x00)&&(((per.b(ad:0x40070120+0x02))&0x02)==0x00)
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling edge"
|
|
bitfld.byte 0x00 6. " BGDM ,Baud Rate GeneratorDouble-Speed Mode Select" "Normal,Doubled"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous Mode Base Clock Select" "16 cycles,8 cycles"
|
|
bitfld.byte 0x00 3. " ABCSE ,Asynchronous Mode Extended Base Clock Select 1" "BGDM+ABCS,6 cycles"
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x07++0x00
|
|
line.byte 0x00 "SEMR,Serial Extended Mode Register"
|
|
bitfld.byte 0x00 7. " RXDESEL ,Asynchronous Start Bit Edge Detection Select" "Low level,Falling edge"
|
|
bitfld.byte 0x00 5. " NFEN ,Digital Noise Filter Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " ABCS ,Asynchronous Mode Base Clock Select" "16 cycles,8 cycles"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " BRME ,Bit Rate Modulation Enable" "Disabled,Enabled"
|
|
endif
|
|
if (((per.b(ad:0x40070120))&0x80)==0x80)
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" ",Not divided,/2,/4,/8,?..."
|
|
else
|
|
group.byte 0x08++0x00
|
|
line.byte 0x00 "SNFR,Noise Filter Setting Register"
|
|
bitfld.byte 0x00 0.--2. " NFCS ,Noise Filter Clock Select" "Not divided,?..."
|
|
endif
|
|
group.byte 0x09++0x00
|
|
line.byte 0x00 "SIMR1,I2C Mode Register 1"
|
|
bitfld.byte 0x00 3.--7. " IICDL ,SDA Delay Output Select" "No delay,1 cycle,1-2 cycles,2-3 cycles,3-4 cycles,4-5 cycles,,,,,,,,,,,,,,,,,,,,,,,,,29-30 cycles,30-31 cycles"
|
|
bitfld.byte 0x00 0. " IICM ,Simple IIC Mode Select" "0,1"
|
|
group.byte 0x0A++0x00
|
|
line.byte 0x00 "SIMR2,I2C Mode Register 2"
|
|
bitfld.byte 0x00 5. " IICACKT ,ACK Transmission Data" "ACK,NACK"
|
|
bitfld.byte 0x00 1. " IICCSC ,Clock Synchronization" "No synchronization,Synchronization"
|
|
bitfld.byte 0x00 0. " IICINTM ,IIC Interrupt Mode Select" "ACK/NACK,Reception and transmission"
|
|
group.byte 0x0B++0x02
|
|
line.byte 0x00 "SIMR3,I2C Mode Register 3"
|
|
bitfld.byte 0x00 6.--7. " IICSCLS ,SCL Output Select" "Serial clock,Start/Restart/Stop,Low SCLn,HI-z SCLn"
|
|
bitfld.byte 0x00 4.--5. " IICSDAS ,SDA Output Select" "Serial Data,Start/Restart/Stop,Low SDAn,HI-z SDAn"
|
|
bitfld.byte 0x00 3. " IICSTIF ,Issuing of Start, Restart, or Stop Condition Completed Flag" "Generated,Completed"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " IICSTPREQ ,Stop Condition Generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 1. " IICRSTAREQ ,Restart Condition Generation" "Not generated,Generated"
|
|
bitfld.byte 0x00 0. " IICSTAREQ ,Start Condition Generation" "Not generated,Generated"
|
|
line.byte 0x01 "SISR,I2C Status Register"
|
|
bitfld.byte 0x01 0. " IICACKR ,ACK Reception Data Flag" "ACK,NACK"
|
|
line.byte 0x02 "SPMR,SPI Mode Register"
|
|
bitfld.byte 0x02 7. " CKPH ,Clock Phase Select" "Not delayed,Delayed"
|
|
bitfld.byte 0x02 6. " CKPOL ,Clock Polarity Select" "Not inverted,Inverted"
|
|
bitfld.byte 0x02 4. " MFF ,Mode Fault Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x02 2. " MSS ,Master Slave Select" "Master,Slave"
|
|
bitfld.byte 0x02 1. " CTSE ,CTS Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " SSE ,SSn Pin Function Enable" "Disabled,Enabled"
|
|
group.word 0x1A++0x01
|
|
line.word 0x00 "CDR,Compare Match Data Register"
|
|
hexmask.word 0x00 0.--8. 1. " CMPD ,Compare Match Data"
|
|
if (((per.b(ad:0x40070120))&0x80)==0x80)
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.byte 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
else
|
|
group.byte 0x13++0x00
|
|
line.byte 0x00 "DCCR,Data Compare Match Control Register"
|
|
bitfld.byte 0x00 7. " DCME ,Data Compare Match Enable" "Disabled,Enable"
|
|
bitfld.byte 0x00 6. " IDSEL ,ID Frame Select" "Always compare,When MPB=1"
|
|
bitfld.byte 0x00 4. " DFER ,Data Compare Match Framing Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " DPER ,Data Compare Match Parity Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 0. " DCMF ,Data Compare Match Flag" "Not matched,Matched"
|
|
endif
|
|
group.byte 0x1C++0x00
|
|
line.byte 0x00 "SPTR,Serial Port Register"
|
|
bitfld.byte 0x00 2. " SPB2IO ,Serial Port Break I/O (Selects whether the value of SPB2DT is output to TXD pin)" "No,Yes"
|
|
bitfld.byte 0x00 1. " SPB2DT ,Serial Port Break Data Select" "Low,High"
|
|
rbitfld.byte 0x00 0. " RXDMON ,Serial Input Data Monitor" "Low,High"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "IIC (I2C Bus Interface)"
|
|
tree "IIC 0"
|
|
base ad:0x40053000
|
|
width 7.
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "ICCR1,I2C Bus Control Register 1"
|
|
bitfld.byte 0x00 7. " ICE ,IIC bus Interface Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICRST ,IIC bus Interface Internal Reset" "Realesed,Initiated"
|
|
bitfld.byte 0x00 5. " CLO ,Extra SCL Clock Cycle Output" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " SOWP ,SCLO/SDAO Write Protect" "Not protected,Protected"
|
|
bitfld.byte 0x00 3. " SCLO ,SCL Output Control/Monitor" "Drove,Realesed"
|
|
bitfld.byte 0x00 2. " SDAO ,SDA Output Control/Monitor" "Drove,Realesed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " SCLI ,SCL Line Monitor" "Low,High"
|
|
rbitfld.byte 0x00 0. " SDAI ,SDA Line Monitor" "Low,High"
|
|
line.byte 0x01 "ICCR2,I2C Bus Control Register 2"
|
|
bitfld.byte 0x01 7. " BBSY ,Bus Busy Detection Flag" "Not busy,Busy"
|
|
bitfld.byte 0x01 6. " MST ,Master/Slave Mode" "Slave,Master"
|
|
bitfld.byte 0x01 5. " TRS ,Transmit/Receive Mode" "Receive,Transmit"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " SP ,Stop Condition Issuance Request" "No issue,Issue"
|
|
bitfld.byte 0x01 2. " RS ,Restart Condition Issuance Request" "Nossue,Issue"
|
|
bitfld.byte 0x01 1. " ST ,Start Condition Issuance Request" "No issue,Issue"
|
|
line.byte 0x02 "ICMR1,I2C Bus Mode Register 1"
|
|
bitfld.byte 0x02 7. " MTWP ,MST/TRS Write Protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 4.--6. " CKS ,Internal Reference Clock Select" "PCLKB,PCLKB/2,PCLKB/4,PCLKB/8,PCLKB/16,PCLKB/32,PCLKB/64,PCLKB/128"
|
|
bitfld.byte 0x02 3. " BCWP ,BC Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.byte 0x02 0.--2. " BC ,Bit Counter" "9 bits,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
if (((per.b(ad:0x40053000+0x03))&0x80)==0x80)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "ICMR2,I2C Bus Mode Register 2"
|
|
bitfld.byte 0x00 7. " DLCS ,SDA Output Delay Clock Source Select" "Clock,Clock/2"
|
|
bitfld.byte 0x00 4.--6. " SDDL ,SDA Output Delay Counter" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.byte 0x00 2. " TMOH ,Timeout H Count Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TMOL ,Timeout L Count Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TMOS ,Timeout Detection Time Select" "Long,Short"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "ICMR2,I2C Bus Mode Register 2"
|
|
bitfld.byte 0x00 7. " DLCS ,SDA Output Delay Clock Source Select" "Clock,Clock/2"
|
|
bitfld.byte 0x00 4.--6. " SDDL ,SDA Output Delay Counter" "No delay,1/2 cycles,3/4 cycles,5/6 cycles,7/8 cycles,9/10 cycles,11/12 cycles,13/14 cycles"
|
|
bitfld.byte 0x00 2. " TMOH ,Timeout H Count Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TMOL ,Timeout L Count Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TMOS ,Timeout Detection Time Select" "Long,Short"
|
|
endif
|
|
group.byte 0x04++0x05
|
|
line.byte 0x00 "ICMR3,I2C Bus Mode Register 3"
|
|
bitfld.byte 0x00 7. " SMBS ,SMBus/IIC bus Select" "I2C,SMB"
|
|
bitfld.byte 0x00 6. " WAIT ,WAIT" "No wait,Wait"
|
|
bitfld.byte 0x00 5. " RDRFS ,RDRF Flag Set Timing Select" "9 cycle,8 cycle"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ACKWP ,ACKBT Write Protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " ACKBT ,Transmit Acknowledge" "ACK,NACK"
|
|
rbitfld.byte 0x00 2. " ACKBR ,Receive Acknowledge" "ACK,NACK"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " NF ,Noise Filter Stage Select" "1,2,3,4"
|
|
line.byte 0x01 "ICFER,I2C Bus Function Enable Register"
|
|
bitfld.byte 0x01 6. " SCLE ,SCL Synchronous Circuit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " NFE ,Digital Noise Filter Circuit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " NACKE ,NACK Reception Transfer Suspension Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " SALE ,Slave Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " NALE ,NACK Transmission Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " MALE ,Master Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " TMOE ,Timeout Function Enable" "Disabled,Enabled"
|
|
line.byte 0x02 "ICSER,I2C Bus Status Enable Register"
|
|
bitfld.byte 0x02 7. " HOAE ,Host Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " DIDE ,Device-ID Address Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 3. " GCAE ,General Call Address Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 2. " SAR2E ,Slave Address Register 2 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " SAR1E ,Slave Address Register 1 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " SAR0E ,Slave Address Register 0 Enable" "Disabled,Enabled"
|
|
line.byte 0x03 "ICIER,I2C Bus Interrupt Enable Register"
|
|
bitfld.byte 0x03 7. " TIE ,Transmit Data Empty Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TEIE ,Transmit End Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receive Data Full Interrupt Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " NAKIE ,NACK Reception Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " SPIE ,Stop Condition Detection Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " STIE ,Start Condition Detection Interrupt Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " ALIE ,Arbitration-Lost Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " TMOIE ,Timeout Interrupt Request Enable" "Disabled,Enabled"
|
|
line.byte 0x04 "ICSR1,I2C Bus Status Register 1"
|
|
bitfld.byte 0x04 7. " HOA ,Host Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 5. " DID ,Device-ID Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 3. " GCA ,General Call Address Detection Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x04 2. " AAS2 ,Slave Address 2 Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 1. " AAS1 ,Slave Address 1 Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 0. " AAS0 ,Slave Address 0 Detection Flag" "Not detected,Detected"
|
|
line.byte 0x05 "ICSR2,I2C Bus Status Register 2"
|
|
rbitfld.byte 0x05 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x05 6. " TEND ,Transmit End Flag" "Ongoing,Completed"
|
|
bitfld.byte 0x05 5. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
textline " "
|
|
bitfld.byte 0x05 4. " NACKF ,NACK Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x05 3. " STOP ,Stop Condition Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x05 2. " START ,Start Condition Detection Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x05 1. " AL ,Arbitration-Lost Flag" "Not lost,Lost"
|
|
bitfld.byte 0x05 0. " TMOF ,Timeout Detection Flag" "Not detected,Detected"
|
|
if (((per.b(ad:0x40053000))&0x40)==0x40)
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "ICWUR,I2C Bus Wakeup Unit Register"
|
|
bitfld.byte 0x00 7. " WUE ,Wakeup Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " WUIE ,Wakeup Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " WUF ,Wakeup Event Occurrence Flag" "Not occured,Occured"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUACK ,ACK bit for Wakeup Mode" "Command recovery,EEP response"
|
|
bitfld.byte 0x00 0. " WUAFA ,Wakeup Analog Filter Additional Selection" "Not added,Added"
|
|
else
|
|
group.byte 0x16++0x00
|
|
line.byte 0x00 "ICWUR,I2C Bus Wakeup Unit Register"
|
|
bitfld.byte 0x00 7. " WUE ,Wakeup Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " WUIE ,Wakeup Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " WUF ,Wakeup Event Occurrence Flag" "Not occured,Occured"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " WUACK ,ACK bit for Wakeup Mode" "Wakeup 1,Wakeup 2"
|
|
bitfld.byte 0x00 0. " WUAFA ,Wakeup Analog Filter Additional Selection" "Not added,Added"
|
|
endif
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "SARL0,Slave Address Register L0"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "SARL1,Slave Address Register L1"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "SARL2,Slave Address Register L2"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "SARU0,Slave Address Register U0"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7 bit,10 bit"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "SARU1,Slave Address Register U1"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7 bit,10 bit"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "SARU2,Slave Address Register U2"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7 bit,10 bit"
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "ICBRL,I2C Bus Bit Rate Low-Level Register"
|
|
bitfld.byte 0x00 0.--4. " BRL ,Bit Rate Low-Level Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "ICBRH,I2C Bus Bit Rate High-Level Register"
|
|
bitfld.byte 0x01 0.--4. " BRH ,Bit Rate High-Level Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x02 "ICDRT,I2C Bus Transmit Data Register"
|
|
line.byte 0x03 "ICDRR,I2C Bus Receive Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "IIC 1"
|
|
base ad:0x40053100
|
|
width 7.
|
|
group.byte 0x00++0x02
|
|
line.byte 0x00 "ICCR1,I2C Bus Control Register 1"
|
|
bitfld.byte 0x00 7. " ICE ,IIC bus Interface Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " IICRST ,IIC bus Interface Internal Reset" "Realesed,Initiated"
|
|
bitfld.byte 0x00 5. " CLO ,Extra SCL Clock Cycle Output" "No,Yes"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " SOWP ,SCLO/SDAO Write Protect" "Not protected,Protected"
|
|
bitfld.byte 0x00 3. " SCLO ,SCL Output Control/Monitor" "Drove,Realesed"
|
|
bitfld.byte 0x00 2. " SDAO ,SDA Output Control/Monitor" "Drove,Realesed"
|
|
textline " "
|
|
rbitfld.byte 0x00 1. " SCLI ,SCL Line Monitor" "Low,High"
|
|
rbitfld.byte 0x00 0. " SDAI ,SDA Line Monitor" "Low,High"
|
|
line.byte 0x01 "ICCR2,I2C Bus Control Register 2"
|
|
bitfld.byte 0x01 7. " BBSY ,Bus Busy Detection Flag" "Not busy,Busy"
|
|
bitfld.byte 0x01 6. " MST ,Master/Slave Mode" "Slave,Master"
|
|
bitfld.byte 0x01 5. " TRS ,Transmit/Receive Mode" "Receive,Transmit"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " SP ,Stop Condition Issuance Request" "No issue,Issue"
|
|
bitfld.byte 0x01 2. " RS ,Restart Condition Issuance Request" "Nossue,Issue"
|
|
bitfld.byte 0x01 1. " ST ,Start Condition Issuance Request" "No issue,Issue"
|
|
line.byte 0x02 "ICMR1,I2C Bus Mode Register 1"
|
|
bitfld.byte 0x02 7. " MTWP ,MST/TRS Write Protect" "Protected,Not protected"
|
|
bitfld.byte 0x02 4.--6. " CKS ,Internal Reference Clock Select" "PCLKB,PCLKB/2,PCLKB/4,PCLKB/8,PCLKB/16,PCLKB/32,PCLKB/64,PCLKB/128"
|
|
bitfld.byte 0x02 3. " BCWP ,BC Write Protect" "Not protected,Protected"
|
|
textline " "
|
|
bitfld.byte 0x02 0.--2. " BC ,Bit Counter" "9 bits,2 bits,3 bits,4 bits,5 bits,6 bits,7 bits,8 bits"
|
|
if (((per.b(ad:0x40053100+0x03))&0x80)==0x80)
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "ICMR2,I2C Bus Mode Register 2"
|
|
bitfld.byte 0x00 7. " DLCS ,SDA Output Delay Clock Source Select" "Clock,Clock/2"
|
|
bitfld.byte 0x00 4.--6. " SDDL ,SDA Output Delay Counter" "No delay,1 cycle,2 cycles,3 cycles,4 cycles,5 cycles,6 cycles,7 cycles"
|
|
bitfld.byte 0x00 2. " TMOH ,Timeout H Count Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TMOL ,Timeout L Count Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TMOS ,Timeout Detection Time Select" "Long,Short"
|
|
else
|
|
group.byte 0x03++0x00
|
|
line.byte 0x00 "ICMR2,I2C Bus Mode Register 2"
|
|
bitfld.byte 0x00 7. " DLCS ,SDA Output Delay Clock Source Select" "Clock,Clock/2"
|
|
bitfld.byte 0x00 4.--6. " SDDL ,SDA Output Delay Counter" "No delay,1/2 cycles,3/4 cycles,5/6 cycles,7/8 cycles,9/10 cycles,11/12 cycles,13/14 cycles"
|
|
bitfld.byte 0x00 2. " TMOH ,Timeout H Count Control" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " TMOL ,Timeout L Count Control" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " TMOS ,Timeout Detection Time Select" "Long,Short"
|
|
endif
|
|
group.byte 0x04++0x05
|
|
line.byte 0x00 "ICMR3,I2C Bus Mode Register 3"
|
|
bitfld.byte 0x00 7. " SMBS ,SMBus/IIC bus Select" "I2C,SMB"
|
|
bitfld.byte 0x00 6. " WAIT ,WAIT" "No wait,Wait"
|
|
bitfld.byte 0x00 5. " RDRFS ,RDRF Flag Set Timing Select" "9 cycle,8 cycle"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " ACKWP ,ACKBT Write Protect" "Protected,Not protected"
|
|
bitfld.byte 0x00 3. " ACKBT ,Transmit Acknowledge" "ACK,NACK"
|
|
rbitfld.byte 0x00 2. " ACKBR ,Receive Acknowledge" "ACK,NACK"
|
|
textline " "
|
|
bitfld.byte 0x00 0.--1. " NF ,Noise Filter Stage Select" "1,2,3,4"
|
|
line.byte 0x01 "ICFER,I2C Bus Function Enable Register"
|
|
bitfld.byte 0x01 6. " SCLE ,SCL Synchronous Circuit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 5. " NFE ,Digital Noise Filter Circuit Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 4. " NACKE ,NACK Reception Transfer Suspension Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " SALE ,Slave Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " NALE ,NACK Transmission Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 1. " MALE ,Master Arbitration-Lost Detection Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x01 0. " TMOE ,Timeout Function Enable" "Disabled,Enabled"
|
|
line.byte 0x02 "ICSER,I2C Bus Status Enable Register"
|
|
bitfld.byte 0x02 7. " HOAE ,Host Address Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 5. " DIDE ,Device-ID Address Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 3. " GCAE ,General Call Address Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x02 2. " SAR2E ,Slave Address Register 2 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 1. " SAR1E ,Slave Address Register 1 Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 0. " SAR0E ,Slave Address Register 0 Enable" "Disabled,Enabled"
|
|
line.byte 0x03 "ICIER,I2C Bus Interrupt Enable Register"
|
|
bitfld.byte 0x03 7. " TIE ,Transmit Data Empty Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 6. " TEIE ,Transmit End Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 5. " RIE ,Receive Data Full Interrupt Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 4. " NAKIE ,NACK Reception Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 3. " SPIE ,Stop Condition Detection Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 2. " STIE ,Start Condition Detection Interrupt Request Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x03 1. " ALIE ,Arbitration-Lost Interrupt Request Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x03 0. " TMOIE ,Timeout Interrupt Request Enable" "Disabled,Enabled"
|
|
line.byte 0x04 "ICSR1,I2C Bus Status Register 1"
|
|
bitfld.byte 0x04 7. " HOA ,Host Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 5. " DID ,Device-ID Address Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 3. " GCA ,General Call Address Detection Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x04 2. " AAS2 ,Slave Address 2 Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 1. " AAS1 ,Slave Address 1 Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x04 0. " AAS0 ,Slave Address 0 Detection Flag" "Not detected,Detected"
|
|
line.byte 0x05 "ICSR2,I2C Bus Status Register 2"
|
|
rbitfld.byte 0x05 7. " TDRE ,Transmit Data Empty Flag" "Not empty,Empty"
|
|
bitfld.byte 0x05 6. " TEND ,Transmit End Flag" "Ongoing,Completed"
|
|
bitfld.byte 0x05 5. " RDRF ,Receive Data Full Flag" "Not full,Full"
|
|
textline " "
|
|
bitfld.byte 0x05 4. " NACKF ,NACK Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x05 3. " STOP ,Stop Condition Detection Flag" "Not detected,Detected"
|
|
bitfld.byte 0x05 2. " START ,Start Condition Detection Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x05 1. " AL ,Arbitration-Lost Flag" "Not lost,Lost"
|
|
bitfld.byte 0x05 0. " TMOF ,Timeout Detection Flag" "Not detected,Detected"
|
|
group.byte 0xA++0x00
|
|
line.byte 0x00 "SARL0,Slave Address Register L0"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xC++0x00
|
|
line.byte 0x00 "SARL1,Slave Address Register L1"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xE++0x00
|
|
line.byte 0x00 "SARL2,Slave Address Register L2"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " SVA0 ,10-Bit Address LSB" "0,1"
|
|
group.byte 0xB++0x00
|
|
line.byte 0x00 "SARU0,Slave Address Register U0"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7 bit,10 bit"
|
|
group.byte 0xD++0x00
|
|
line.byte 0x00 "SARU1,Slave Address Register U1"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7 bit,10 bit"
|
|
group.byte 0xF++0x00
|
|
line.byte 0x00 "SARU2,Slave Address Register U2"
|
|
hexmask.byte 0x00 1.--7. 1. " SVA ,7-Bit Address/10-Bit Address Lower Bits"
|
|
bitfld.byte 0x00 0. " FS ,7-Bit/10-Bit Address Format Select" "7 bit,10 bit"
|
|
group.byte 0x10++0x03
|
|
line.byte 0x00 "ICBRL,I2C Bus Bit Rate Low-Level Register"
|
|
bitfld.byte 0x00 0.--4. " BRL ,Bit Rate Low-Level Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x01 "ICBRH,I2C Bus Bit Rate High-Level Register"
|
|
bitfld.byte 0x01 0.--4. " BRH ,Bit Rate High-Level Period" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
line.byte 0x02 "ICDRT,I2C Bus Transmit Data Register"
|
|
line.byte 0x03 "ICDRR,I2C Bus Receive Data Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "CAN (Controller Area Network)"
|
|
base ad:0x40050000
|
|
width 11.
|
|
group.word 0x840++0x01
|
|
line.word 0x00 "CTLR,Control Register"
|
|
bitfld.word 0x00 13. " RBOC ,Forced Return from Bus-Off" "Not forced,Forced"
|
|
bitfld.word 0x00 11.--12. " BOM ,Bus-Off Recovery Mode" "Normal,Automatic on entry,Automatic on end,During recovery"
|
|
bitfld.word 0x00 10. " SLPM ,CAN Sleep Mode" "Exit,Enter"
|
|
bitfld.word 0x00 8.--9. " CANM ,CAN Mode Operation Select" "Operation,Reset,Halt,Reset(forced)"
|
|
textline " "
|
|
bitfld.word 0x00 8.--9. " TSPS ,Time Stamp Prescaler Select" "1 bit,2 bit,4 bit,8 bit"
|
|
bitfld.word 0x00 5. " TSRC ,Time Stamp Counter Reset Command" "No reset,Reset"
|
|
bitfld.word 0x00 4. " TPM ,Transmission Priority Mode Select" "ID,Mailbox"
|
|
eventfld.word 0x00 3. " MLM ,Message Lost Mode Select" "Overwrite,Overrun"
|
|
textline " "
|
|
bitfld.word 0x00 1.--2. " IDFM ,ID Format Mode Select" "Standard,Extended,Mixed,?..."
|
|
bitfld.word 0x00 0. " MBM ,CAN Mailbox Mode Select" "Normal,FIFO"
|
|
group.long 0x844++0x03
|
|
line.long 0x00 "BCR,Bit Configuration Register"
|
|
bitfld.long 0x00 28.--31. " TSEG1 ,Time Segment 1 Control" ",,,4 Tq,5 Tq,6 Tq,7 Tq,8 Tq,9 Tq,10 Tq,11 Tq,12 Tq,13 Tq,14 Tq,15 Tq,16 Tq"
|
|
hexmask.long.word 0x00 16.--25. 1. " BRP ,Baud Rate Prescaler Select"
|
|
bitfld.long 0x00 12.--13. " SJW ,Synchronization Jump Width Control" "1 Tq,2 Tq,3 Tq,4 Tq"
|
|
bitfld.long 0x00 8.--10. " TSEG2 ,Time Segment 2 Control" ",2 Tq,3 Tq,4 Tq,5 Tq,6 Tq,7 Tq,8 Tq"
|
|
textline " "
|
|
bitfld.long 0x00 0. " CCLKS ,CAN Clock Source Selection" ",CANMCLK"
|
|
group.long 0x400++0x03
|
|
line.long 0x00 "MKR0,Mask Register 0"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x404++0x03
|
|
line.long 0x00 "MKR1,Mask Register 1"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x408++0x03
|
|
line.long 0x00 "MKR2,Mask Register 2"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x40C++0x03
|
|
line.long 0x00 "MKR3,Mask Register 3"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x410++0x03
|
|
line.long 0x00 "MKR4,Mask Register 4"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x414++0x03
|
|
line.long 0x00 "MKR5,Mask Register 5"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x418++0x03
|
|
line.long 0x00 "MKR6,Mask Register 6"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x41C++0x03
|
|
line.long 0x00 "MKR7,Mask Register 7"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.long 0x420++0x0B
|
|
line.long 0x00 "FIDCR0,FIFO Received ID Compare Register 0"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
line.long 0x04 "FIDCR1,FIFO Received ID Compare Register 1"
|
|
bitfld.long 0x04 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x04 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x04 18.--28. 1. " SID ,Standard Id bits"
|
|
hexmask.long.tbyte 0x04 0.--17. 1. " EID ,Extended Id bits"
|
|
line.long 0x08 "MKIVLR,Mask Invalid Register"
|
|
bitfld.long 0x08 31. " MB31 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 30. " MB30 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 29. " MB29 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 28. " MB28 ,Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x08 27. " MB27 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 26. " MB26 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 25. " MB25 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 24. " MB24 ,Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x08 23. " MB23 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 22. " MB22 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 21. " MB21 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 20. " MB20 ,Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x08 19. " MB19 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 18. " MB18 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 17. " MB17 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 16. " MB16 ,Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x08 15. " MB15 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 14. " MB14 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 13. " MB13 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 12. " MB12 ,Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x08 11. " MB11 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 10. " MB10 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 9. " MB9 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 8. " MB8 ,Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x08 7. " MB7 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 6. " MB6 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 5. " MB5 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 4. " MB4 ,Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
bitfld.long 0x08 3. " MB3 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 2. " MB2 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 1. " MB1 ,Mask Invalid" "Valid,Invalid"
|
|
bitfld.long 0x08 0. " MB0 ,Mask Invalid" "Valid,Invalid"
|
|
textline " "
|
|
group.long 0x200++0x03
|
|
line.long 0x00 "MB0_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x200+0x04)++0x01
|
|
line.word 0x00 "MB0_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x200+0x06)++0x07
|
|
line.byte 0x00 "MB0_D0,DATA0"
|
|
line.byte 0x01 "MB0_D1,DATA1"
|
|
line.byte 0x02 "MB0_D2,DATA2"
|
|
line.byte 0x03 "MB0_D3,DATA3"
|
|
line.byte 0x04 "MB0_D4,DATA4"
|
|
line.byte 0x05 "MB0_D5,DATA5"
|
|
line.byte 0x06 "MB0_D6,DATA6"
|
|
line.byte 0x07 "MB0_D7,DATA7"
|
|
group.word (0x200+0x0E)++0x01
|
|
line.word 0x00 "MB0_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x210++0x03
|
|
line.long 0x00 "MB1_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x210+0x04)++0x01
|
|
line.word 0x00 "MB1_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x210+0x06)++0x07
|
|
line.byte 0x00 "MB1_D0,DATA0"
|
|
line.byte 0x01 "MB1_D1,DATA1"
|
|
line.byte 0x02 "MB1_D2,DATA2"
|
|
line.byte 0x03 "MB1_D3,DATA3"
|
|
line.byte 0x04 "MB1_D4,DATA4"
|
|
line.byte 0x05 "MB1_D5,DATA5"
|
|
line.byte 0x06 "MB1_D6,DATA6"
|
|
line.byte 0x07 "MB1_D7,DATA7"
|
|
group.word (0x210+0x0E)++0x01
|
|
line.word 0x00 "MB1_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x220++0x03
|
|
line.long 0x00 "MB2_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x220+0x04)++0x01
|
|
line.word 0x00 "MB2_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x220+0x06)++0x07
|
|
line.byte 0x00 "MB2_D0,DATA0"
|
|
line.byte 0x01 "MB2_D1,DATA1"
|
|
line.byte 0x02 "MB2_D2,DATA2"
|
|
line.byte 0x03 "MB2_D3,DATA3"
|
|
line.byte 0x04 "MB2_D4,DATA4"
|
|
line.byte 0x05 "MB2_D5,DATA5"
|
|
line.byte 0x06 "MB2_D6,DATA6"
|
|
line.byte 0x07 "MB2_D7,DATA7"
|
|
group.word (0x220+0x0E)++0x01
|
|
line.word 0x00 "MB2_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x230++0x03
|
|
line.long 0x00 "MB3_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x230+0x04)++0x01
|
|
line.word 0x00 "MB3_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x230+0x06)++0x07
|
|
line.byte 0x00 "MB3_D0,DATA0"
|
|
line.byte 0x01 "MB3_D1,DATA1"
|
|
line.byte 0x02 "MB3_D2,DATA2"
|
|
line.byte 0x03 "MB3_D3,DATA3"
|
|
line.byte 0x04 "MB3_D4,DATA4"
|
|
line.byte 0x05 "MB3_D5,DATA5"
|
|
line.byte 0x06 "MB3_D6,DATA6"
|
|
line.byte 0x07 "MB3_D7,DATA7"
|
|
group.word (0x230+0x0E)++0x01
|
|
line.word 0x00 "MB3_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x240++0x03
|
|
line.long 0x00 "MB4_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x240+0x04)++0x01
|
|
line.word 0x00 "MB4_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x240+0x06)++0x07
|
|
line.byte 0x00 "MB4_D0,DATA0"
|
|
line.byte 0x01 "MB4_D1,DATA1"
|
|
line.byte 0x02 "MB4_D2,DATA2"
|
|
line.byte 0x03 "MB4_D3,DATA3"
|
|
line.byte 0x04 "MB4_D4,DATA4"
|
|
line.byte 0x05 "MB4_D5,DATA5"
|
|
line.byte 0x06 "MB4_D6,DATA6"
|
|
line.byte 0x07 "MB4_D7,DATA7"
|
|
group.word (0x240+0x0E)++0x01
|
|
line.word 0x00 "MB4_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x250++0x03
|
|
line.long 0x00 "MB5_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x250+0x04)++0x01
|
|
line.word 0x00 "MB5_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x250+0x06)++0x07
|
|
line.byte 0x00 "MB5_D0,DATA0"
|
|
line.byte 0x01 "MB5_D1,DATA1"
|
|
line.byte 0x02 "MB5_D2,DATA2"
|
|
line.byte 0x03 "MB5_D3,DATA3"
|
|
line.byte 0x04 "MB5_D4,DATA4"
|
|
line.byte 0x05 "MB5_D5,DATA5"
|
|
line.byte 0x06 "MB5_D6,DATA6"
|
|
line.byte 0x07 "MB5_D7,DATA7"
|
|
group.word (0x250+0x0E)++0x01
|
|
line.word 0x00 "MB5_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x260++0x03
|
|
line.long 0x00 "MB6_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x260+0x04)++0x01
|
|
line.word 0x00 "MB6_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x260+0x06)++0x07
|
|
line.byte 0x00 "MB6_D0,DATA0"
|
|
line.byte 0x01 "MB6_D1,DATA1"
|
|
line.byte 0x02 "MB6_D2,DATA2"
|
|
line.byte 0x03 "MB6_D3,DATA3"
|
|
line.byte 0x04 "MB6_D4,DATA4"
|
|
line.byte 0x05 "MB6_D5,DATA5"
|
|
line.byte 0x06 "MB6_D6,DATA6"
|
|
line.byte 0x07 "MB6_D7,DATA7"
|
|
group.word (0x260+0x0E)++0x01
|
|
line.word 0x00 "MB6_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x270++0x03
|
|
line.long 0x00 "MB7_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x270+0x04)++0x01
|
|
line.word 0x00 "MB7_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x270+0x06)++0x07
|
|
line.byte 0x00 "MB7_D0,DATA0"
|
|
line.byte 0x01 "MB7_D1,DATA1"
|
|
line.byte 0x02 "MB7_D2,DATA2"
|
|
line.byte 0x03 "MB7_D3,DATA3"
|
|
line.byte 0x04 "MB7_D4,DATA4"
|
|
line.byte 0x05 "MB7_D5,DATA5"
|
|
line.byte 0x06 "MB7_D6,DATA6"
|
|
line.byte 0x07 "MB7_D7,DATA7"
|
|
group.word (0x270+0x0E)++0x01
|
|
line.word 0x00 "MB7_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x280++0x03
|
|
line.long 0x00 "MB8_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x280+0x04)++0x01
|
|
line.word 0x00 "MB8_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x280+0x06)++0x07
|
|
line.byte 0x00 "MB8_D0,DATA0"
|
|
line.byte 0x01 "MB8_D1,DATA1"
|
|
line.byte 0x02 "MB8_D2,DATA2"
|
|
line.byte 0x03 "MB8_D3,DATA3"
|
|
line.byte 0x04 "MB8_D4,DATA4"
|
|
line.byte 0x05 "MB8_D5,DATA5"
|
|
line.byte 0x06 "MB8_D6,DATA6"
|
|
line.byte 0x07 "MB8_D7,DATA7"
|
|
group.word (0x280+0x0E)++0x01
|
|
line.word 0x00 "MB8_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x290++0x03
|
|
line.long 0x00 "MB9_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x290+0x04)++0x01
|
|
line.word 0x00 "MB9_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x290+0x06)++0x07
|
|
line.byte 0x00 "MB9_D0,DATA0"
|
|
line.byte 0x01 "MB9_D1,DATA1"
|
|
line.byte 0x02 "MB9_D2,DATA2"
|
|
line.byte 0x03 "MB9_D3,DATA3"
|
|
line.byte 0x04 "MB9_D4,DATA4"
|
|
line.byte 0x05 "MB9_D5,DATA5"
|
|
line.byte 0x06 "MB9_D6,DATA6"
|
|
line.byte 0x07 "MB9_D7,DATA7"
|
|
group.word (0x290+0x0E)++0x01
|
|
line.word 0x00 "MB9_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2A0++0x03
|
|
line.long 0x00 "MB10_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2A0+0x04)++0x01
|
|
line.word 0x00 "MB10_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x2A0+0x06)++0x07
|
|
line.byte 0x00 "MB10_D0,DATA0"
|
|
line.byte 0x01 "MB10_D1,DATA1"
|
|
line.byte 0x02 "MB10_D2,DATA2"
|
|
line.byte 0x03 "MB10_D3,DATA3"
|
|
line.byte 0x04 "MB10_D4,DATA4"
|
|
line.byte 0x05 "MB10_D5,DATA5"
|
|
line.byte 0x06 "MB10_D6,DATA6"
|
|
line.byte 0x07 "MB10_D7,DATA7"
|
|
group.word (0x2A0+0x0E)++0x01
|
|
line.word 0x00 "MB10_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2B0++0x03
|
|
line.long 0x00 "MB11_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2B0+0x04)++0x01
|
|
line.word 0x00 "MB11_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x2B0+0x06)++0x07
|
|
line.byte 0x00 "MB11_D0,DATA0"
|
|
line.byte 0x01 "MB11_D1,DATA1"
|
|
line.byte 0x02 "MB11_D2,DATA2"
|
|
line.byte 0x03 "MB11_D3,DATA3"
|
|
line.byte 0x04 "MB11_D4,DATA4"
|
|
line.byte 0x05 "MB11_D5,DATA5"
|
|
line.byte 0x06 "MB11_D6,DATA6"
|
|
line.byte 0x07 "MB11_D7,DATA7"
|
|
group.word (0x2B0+0x0E)++0x01
|
|
line.word 0x00 "MB11_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2C0++0x03
|
|
line.long 0x00 "MB12_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2C0+0x04)++0x01
|
|
line.word 0x00 "MB12_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x2C0+0x06)++0x07
|
|
line.byte 0x00 "MB12_D0,DATA0"
|
|
line.byte 0x01 "MB12_D1,DATA1"
|
|
line.byte 0x02 "MB12_D2,DATA2"
|
|
line.byte 0x03 "MB12_D3,DATA3"
|
|
line.byte 0x04 "MB12_D4,DATA4"
|
|
line.byte 0x05 "MB12_D5,DATA5"
|
|
line.byte 0x06 "MB12_D6,DATA6"
|
|
line.byte 0x07 "MB12_D7,DATA7"
|
|
group.word (0x2C0+0x0E)++0x01
|
|
line.word 0x00 "MB12_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2D0++0x03
|
|
line.long 0x00 "MB13_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2D0+0x04)++0x01
|
|
line.word 0x00 "MB13_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x2D0+0x06)++0x07
|
|
line.byte 0x00 "MB13_D0,DATA0"
|
|
line.byte 0x01 "MB13_D1,DATA1"
|
|
line.byte 0x02 "MB13_D2,DATA2"
|
|
line.byte 0x03 "MB13_D3,DATA3"
|
|
line.byte 0x04 "MB13_D4,DATA4"
|
|
line.byte 0x05 "MB13_D5,DATA5"
|
|
line.byte 0x06 "MB13_D6,DATA6"
|
|
line.byte 0x07 "MB13_D7,DATA7"
|
|
group.word (0x2D0+0x0E)++0x01
|
|
line.word 0x00 "MB13_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2E0++0x03
|
|
line.long 0x00 "MB14_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2E0+0x04)++0x01
|
|
line.word 0x00 "MB14_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x2E0+0x06)++0x07
|
|
line.byte 0x00 "MB14_D0,DATA0"
|
|
line.byte 0x01 "MB14_D1,DATA1"
|
|
line.byte 0x02 "MB14_D2,DATA2"
|
|
line.byte 0x03 "MB14_D3,DATA3"
|
|
line.byte 0x04 "MB14_D4,DATA4"
|
|
line.byte 0x05 "MB14_D5,DATA5"
|
|
line.byte 0x06 "MB14_D6,DATA6"
|
|
line.byte 0x07 "MB14_D7,DATA7"
|
|
group.word (0x2E0+0x0E)++0x01
|
|
line.word 0x00 "MB14_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x2F0++0x03
|
|
line.long 0x00 "MB15_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x2F0+0x04)++0x01
|
|
line.word 0x00 "MB15_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x2F0+0x06)++0x07
|
|
line.byte 0x00 "MB15_D0,DATA0"
|
|
line.byte 0x01 "MB15_D1,DATA1"
|
|
line.byte 0x02 "MB15_D2,DATA2"
|
|
line.byte 0x03 "MB15_D3,DATA3"
|
|
line.byte 0x04 "MB15_D4,DATA4"
|
|
line.byte 0x05 "MB15_D5,DATA5"
|
|
line.byte 0x06 "MB15_D6,DATA6"
|
|
line.byte 0x07 "MB15_D7,DATA7"
|
|
group.word (0x2F0+0x0E)++0x01
|
|
line.word 0x00 "MB15_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x300++0x03
|
|
line.long 0x00 "MB16_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x300+0x04)++0x01
|
|
line.word 0x00 "MB16_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x300+0x06)++0x07
|
|
line.byte 0x00 "MB16_D0,DATA0"
|
|
line.byte 0x01 "MB16_D1,DATA1"
|
|
line.byte 0x02 "MB16_D2,DATA2"
|
|
line.byte 0x03 "MB16_D3,DATA3"
|
|
line.byte 0x04 "MB16_D4,DATA4"
|
|
line.byte 0x05 "MB16_D5,DATA5"
|
|
line.byte 0x06 "MB16_D6,DATA6"
|
|
line.byte 0x07 "MB16_D7,DATA7"
|
|
group.word (0x300+0x0E)++0x01
|
|
line.word 0x00 "MB16_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x310++0x03
|
|
line.long 0x00 "MB17_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x310+0x04)++0x01
|
|
line.word 0x00 "MB17_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x310+0x06)++0x07
|
|
line.byte 0x00 "MB17_D0,DATA0"
|
|
line.byte 0x01 "MB17_D1,DATA1"
|
|
line.byte 0x02 "MB17_D2,DATA2"
|
|
line.byte 0x03 "MB17_D3,DATA3"
|
|
line.byte 0x04 "MB17_D4,DATA4"
|
|
line.byte 0x05 "MB17_D5,DATA5"
|
|
line.byte 0x06 "MB17_D6,DATA6"
|
|
line.byte 0x07 "MB17_D7,DATA7"
|
|
group.word (0x310+0x0E)++0x01
|
|
line.word 0x00 "MB17_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x320++0x03
|
|
line.long 0x00 "MB18_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x320+0x04)++0x01
|
|
line.word 0x00 "MB18_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x320+0x06)++0x07
|
|
line.byte 0x00 "MB18_D0,DATA0"
|
|
line.byte 0x01 "MB18_D1,DATA1"
|
|
line.byte 0x02 "MB18_D2,DATA2"
|
|
line.byte 0x03 "MB18_D3,DATA3"
|
|
line.byte 0x04 "MB18_D4,DATA4"
|
|
line.byte 0x05 "MB18_D5,DATA5"
|
|
line.byte 0x06 "MB18_D6,DATA6"
|
|
line.byte 0x07 "MB18_D7,DATA7"
|
|
group.word (0x320+0x0E)++0x01
|
|
line.word 0x00 "MB18_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x330++0x03
|
|
line.long 0x00 "MB19_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x330+0x04)++0x01
|
|
line.word 0x00 "MB19_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x330+0x06)++0x07
|
|
line.byte 0x00 "MB19_D0,DATA0"
|
|
line.byte 0x01 "MB19_D1,DATA1"
|
|
line.byte 0x02 "MB19_D2,DATA2"
|
|
line.byte 0x03 "MB19_D3,DATA3"
|
|
line.byte 0x04 "MB19_D4,DATA4"
|
|
line.byte 0x05 "MB19_D5,DATA5"
|
|
line.byte 0x06 "MB19_D6,DATA6"
|
|
line.byte 0x07 "MB19_D7,DATA7"
|
|
group.word (0x330+0x0E)++0x01
|
|
line.word 0x00 "MB19_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x340++0x03
|
|
line.long 0x00 "MB20_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x340+0x04)++0x01
|
|
line.word 0x00 "MB20_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x340+0x06)++0x07
|
|
line.byte 0x00 "MB20_D0,DATA0"
|
|
line.byte 0x01 "MB20_D1,DATA1"
|
|
line.byte 0x02 "MB20_D2,DATA2"
|
|
line.byte 0x03 "MB20_D3,DATA3"
|
|
line.byte 0x04 "MB20_D4,DATA4"
|
|
line.byte 0x05 "MB20_D5,DATA5"
|
|
line.byte 0x06 "MB20_D6,DATA6"
|
|
line.byte 0x07 "MB20_D7,DATA7"
|
|
group.word (0x340+0x0E)++0x01
|
|
line.word 0x00 "MB20_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x350++0x03
|
|
line.long 0x00 "MB21_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x350+0x04)++0x01
|
|
line.word 0x00 "MB21_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x350+0x06)++0x07
|
|
line.byte 0x00 "MB21_D0,DATA0"
|
|
line.byte 0x01 "MB21_D1,DATA1"
|
|
line.byte 0x02 "MB21_D2,DATA2"
|
|
line.byte 0x03 "MB21_D3,DATA3"
|
|
line.byte 0x04 "MB21_D4,DATA4"
|
|
line.byte 0x05 "MB21_D5,DATA5"
|
|
line.byte 0x06 "MB21_D6,DATA6"
|
|
line.byte 0x07 "MB21_D7,DATA7"
|
|
group.word (0x350+0x0E)++0x01
|
|
line.word 0x00 "MB21_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x360++0x03
|
|
line.long 0x00 "MB22_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x360+0x04)++0x01
|
|
line.word 0x00 "MB22_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x360+0x06)++0x07
|
|
line.byte 0x00 "MB22_D0,DATA0"
|
|
line.byte 0x01 "MB22_D1,DATA1"
|
|
line.byte 0x02 "MB22_D2,DATA2"
|
|
line.byte 0x03 "MB22_D3,DATA3"
|
|
line.byte 0x04 "MB22_D4,DATA4"
|
|
line.byte 0x05 "MB22_D5,DATA5"
|
|
line.byte 0x06 "MB22_D6,DATA6"
|
|
line.byte 0x07 "MB22_D7,DATA7"
|
|
group.word (0x360+0x0E)++0x01
|
|
line.word 0x00 "MB22_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x370++0x03
|
|
line.long 0x00 "MB23_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x370+0x04)++0x01
|
|
line.word 0x00 "MB23_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x370+0x06)++0x07
|
|
line.byte 0x00 "MB23_D0,DATA0"
|
|
line.byte 0x01 "MB23_D1,DATA1"
|
|
line.byte 0x02 "MB23_D2,DATA2"
|
|
line.byte 0x03 "MB23_D3,DATA3"
|
|
line.byte 0x04 "MB23_D4,DATA4"
|
|
line.byte 0x05 "MB23_D5,DATA5"
|
|
line.byte 0x06 "MB23_D6,DATA6"
|
|
line.byte 0x07 "MB23_D7,DATA7"
|
|
group.word (0x370+0x0E)++0x01
|
|
line.word 0x00 "MB23_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x380++0x03
|
|
line.long 0x00 "MB24_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x380+0x04)++0x01
|
|
line.word 0x00 "MB24_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x380+0x06)++0x07
|
|
line.byte 0x00 "MB24_D0,DATA0"
|
|
line.byte 0x01 "MB24_D1,DATA1"
|
|
line.byte 0x02 "MB24_D2,DATA2"
|
|
line.byte 0x03 "MB24_D3,DATA3"
|
|
line.byte 0x04 "MB24_D4,DATA4"
|
|
line.byte 0x05 "MB24_D5,DATA5"
|
|
line.byte 0x06 "MB24_D6,DATA6"
|
|
line.byte 0x07 "MB24_D7,DATA7"
|
|
group.word (0x380+0x0E)++0x01
|
|
line.word 0x00 "MB24_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x390++0x03
|
|
line.long 0x00 "MB25_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x390+0x04)++0x01
|
|
line.word 0x00 "MB25_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x390+0x06)++0x07
|
|
line.byte 0x00 "MB25_D0,DATA0"
|
|
line.byte 0x01 "MB25_D1,DATA1"
|
|
line.byte 0x02 "MB25_D2,DATA2"
|
|
line.byte 0x03 "MB25_D3,DATA3"
|
|
line.byte 0x04 "MB25_D4,DATA4"
|
|
line.byte 0x05 "MB25_D5,DATA5"
|
|
line.byte 0x06 "MB25_D6,DATA6"
|
|
line.byte 0x07 "MB25_D7,DATA7"
|
|
group.word (0x390+0x0E)++0x01
|
|
line.word 0x00 "MB25_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x3A0++0x03
|
|
line.long 0x00 "MB26_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x3A0+0x04)++0x01
|
|
line.word 0x00 "MB26_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x3A0+0x06)++0x07
|
|
line.byte 0x00 "MB26_D0,DATA0"
|
|
line.byte 0x01 "MB26_D1,DATA1"
|
|
line.byte 0x02 "MB26_D2,DATA2"
|
|
line.byte 0x03 "MB26_D3,DATA3"
|
|
line.byte 0x04 "MB26_D4,DATA4"
|
|
line.byte 0x05 "MB26_D5,DATA5"
|
|
line.byte 0x06 "MB26_D6,DATA6"
|
|
line.byte 0x07 "MB26_D7,DATA7"
|
|
group.word (0x3A0+0x0E)++0x01
|
|
line.word 0x00 "MB26_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x3B0++0x03
|
|
line.long 0x00 "MB27_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x3B0+0x04)++0x01
|
|
line.word 0x00 "MB27_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x3B0+0x06)++0x07
|
|
line.byte 0x00 "MB27_D0,DATA0"
|
|
line.byte 0x01 "MB27_D1,DATA1"
|
|
line.byte 0x02 "MB27_D2,DATA2"
|
|
line.byte 0x03 "MB27_D3,DATA3"
|
|
line.byte 0x04 "MB27_D4,DATA4"
|
|
line.byte 0x05 "MB27_D5,DATA5"
|
|
line.byte 0x06 "MB27_D6,DATA6"
|
|
line.byte 0x07 "MB27_D7,DATA7"
|
|
group.word (0x3B0+0x0E)++0x01
|
|
line.word 0x00 "MB27_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x3C0++0x03
|
|
line.long 0x00 "MB28_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x3C0+0x04)++0x01
|
|
line.word 0x00 "MB28_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x3C0+0x06)++0x07
|
|
line.byte 0x00 "MB28_D0,DATA0"
|
|
line.byte 0x01 "MB28_D1,DATA1"
|
|
line.byte 0x02 "MB28_D2,DATA2"
|
|
line.byte 0x03 "MB28_D3,DATA3"
|
|
line.byte 0x04 "MB28_D4,DATA4"
|
|
line.byte 0x05 "MB28_D5,DATA5"
|
|
line.byte 0x06 "MB28_D6,DATA6"
|
|
line.byte 0x07 "MB28_D7,DATA7"
|
|
group.word (0x3C0+0x0E)++0x01
|
|
line.word 0x00 "MB28_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x3D0++0x03
|
|
line.long 0x00 "MB29_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x3D0+0x04)++0x01
|
|
line.word 0x00 "MB29_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x3D0+0x06)++0x07
|
|
line.byte 0x00 "MB29_D0,DATA0"
|
|
line.byte 0x01 "MB29_D1,DATA1"
|
|
line.byte 0x02 "MB29_D2,DATA2"
|
|
line.byte 0x03 "MB29_D3,DATA3"
|
|
line.byte 0x04 "MB29_D4,DATA4"
|
|
line.byte 0x05 "MB29_D5,DATA5"
|
|
line.byte 0x06 "MB29_D6,DATA6"
|
|
line.byte 0x07 "MB29_D7,DATA7"
|
|
group.word (0x3D0+0x0E)++0x01
|
|
line.word 0x00 "MB29_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x3E0++0x03
|
|
line.long 0x00 "MB30_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x3E0+0x04)++0x01
|
|
line.word 0x00 "MB30_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x3E0+0x06)++0x07
|
|
line.byte 0x00 "MB30_D0,DATA0"
|
|
line.byte 0x01 "MB30_D1,DATA1"
|
|
line.byte 0x02 "MB30_D2,DATA2"
|
|
line.byte 0x03 "MB30_D3,DATA3"
|
|
line.byte 0x04 "MB30_D4,DATA4"
|
|
line.byte 0x05 "MB30_D5,DATA5"
|
|
line.byte 0x06 "MB30_D6,DATA6"
|
|
line.byte 0x07 "MB30_D7,DATA7"
|
|
group.word (0x3E0+0x0E)++0x01
|
|
line.word 0x00 "MB30_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
group.long 0x3F0++0x03
|
|
line.long 0x00 "MB31_ID,Mailbox ID"
|
|
bitfld.long 0x00 31. " IDE ,ID Extension" "Standard,Extended"
|
|
bitfld.long 0x00 30. " RTR ,Remote Transmission Request" "Data,Remote"
|
|
hexmask.long.word 0x00 18.--28. 1. " SID ,Standard ID"
|
|
hexmask.long.tbyte 0x00 0.--17. 1. " EID ,Extended ID"
|
|
group.word (0x3F0+0x04)++0x01
|
|
line.word 0x00 "MB31_DL,Mailbox Data Length"
|
|
bitfld.word 0x00 0.--3. " DLC ,Data Length Code" "0 bytes,1 byte,2 bytes,3 bytes,4 bytes,5 bytes,6 bytes,7 bytes,8 bytes,?..."
|
|
group.byte (0x3F0+0x06)++0x07
|
|
line.byte 0x00 "MB31_D0,DATA0"
|
|
line.byte 0x01 "MB31_D1,DATA1"
|
|
line.byte 0x02 "MB31_D2,DATA2"
|
|
line.byte 0x03 "MB31_D3,DATA3"
|
|
line.byte 0x04 "MB31_D4,DATA4"
|
|
line.byte 0x05 "MB31_D5,DATA5"
|
|
line.byte 0x06 "MB31_D6,DATA6"
|
|
line.byte 0x07 "MB31_D7,DATA7"
|
|
group.word (0x3F0+0x0E)++0x01
|
|
line.word 0x00 "MB31_TS,Time Stamps"
|
|
hexmask.word.byte 0x00 8.--15. 1. " TSH ,Time Stamp Higher Byte"
|
|
hexmask.word.byte 0x00 0.--7. 1. " TSL ,Time Stamp Lower Byte"
|
|
textline " "
|
|
if (((per.w(ad:0x40050000+0x840))&0x01)==0x01)
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "MIER,Mailbox Interrupt Enable Register"
|
|
bitfld.long 0x00 31. " MB31 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 30. " MB30 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 29. " MB29 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 28. " MB28 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 27. " MB27 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 26. " MB26 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 25. " MB25 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 24. " MB24 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " MB23 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 22. " MB22 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 21. " MB21 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MB20 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 19. " MB19 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 18. " MB18 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MB17 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 16. " MB16 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 15. " MB15 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MB14 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 13. " MB13 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 12. " MB12 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MB11 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 10. " MB10 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 9. " MB9 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MB8 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 7. " MB7 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 6. " MB6 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MB5 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 4. " MB4 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 3. " MB3 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MB2 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 1. " MB1 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 0. " MB0 ,Interrupt Enable " "Disabled,Enabled"
|
|
else
|
|
group.long 0x42C++0x03
|
|
line.long 0x00 "MIER_FIFO,Mailbox Interrupt Enable Register for FIFO Mailbox Mode"
|
|
bitfld.long 0x00 29. " MB29 ,Interrupt Enable " "Completed,Buffer warning"
|
|
bitfld.long 0x00 28. " MB28 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 25. " MB25 ,Interrupt Enable " "Completed,Emptied"
|
|
textline " "
|
|
bitfld.long 0x00 24. " MB24 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 23. " MB23 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 22. " MB22 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 21. " MB21 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 20. " MB20 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 19. " MB19 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 18. " MB18 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 17. " MB17 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 16. " MB16 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 15. " MB15 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 14. " MB14 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 13. " MB13 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 12. " MB12 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 11. " MB11 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 10. " MB10 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 9. " MB9 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 8. " MB8 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 7. " MB7 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 6. " MB6 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 5. " MB5 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 4. " MB4 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 3. " MB3 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 2. " MB2 ,Interrupt Enable " "Disabled,Enabled"
|
|
bitfld.long 0x00 1. " MB1 ,Interrupt Enable " "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.long 0x00 0. " MB0 ,Interrupt Enable " "Disabled,Enabled"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x820))&0xC0)==0x80)
|
|
group.byte 0x820++0x00
|
|
line.byte 0x00 "MCTL_TX0,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x820))&0xC0)==0x40)
|
|
group.byte 0x820++0x00
|
|
line.byte 0x00 "MCTL_TX0,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x820++0x00
|
|
line.byte 0x00 "MCTL_TX0,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x821))&0xC0)==0x80)
|
|
group.byte 0x821++0x00
|
|
line.byte 0x00 "MCTL_TX1,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x821))&0xC0)==0x40)
|
|
group.byte 0x821++0x00
|
|
line.byte 0x00 "MCTL_TX1,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x821++0x00
|
|
line.byte 0x00 "MCTL_TX1,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x822))&0xC0)==0x80)
|
|
group.byte 0x822++0x00
|
|
line.byte 0x00 "MCTL_TX2,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x822))&0xC0)==0x40)
|
|
group.byte 0x822++0x00
|
|
line.byte 0x00 "MCTL_TX2,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x822++0x00
|
|
line.byte 0x00 "MCTL_TX2,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x823))&0xC0)==0x80)
|
|
group.byte 0x823++0x00
|
|
line.byte 0x00 "MCTL_TX3,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x823))&0xC0)==0x40)
|
|
group.byte 0x823++0x00
|
|
line.byte 0x00 "MCTL_TX3,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x823++0x00
|
|
line.byte 0x00 "MCTL_TX3,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x824))&0xC0)==0x80)
|
|
group.byte 0x824++0x00
|
|
line.byte 0x00 "MCTL_TX4,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x824))&0xC0)==0x40)
|
|
group.byte 0x824++0x00
|
|
line.byte 0x00 "MCTL_TX4,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x824++0x00
|
|
line.byte 0x00 "MCTL_TX4,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x825))&0xC0)==0x80)
|
|
group.byte 0x825++0x00
|
|
line.byte 0x00 "MCTL_TX5,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x825))&0xC0)==0x40)
|
|
group.byte 0x825++0x00
|
|
line.byte 0x00 "MCTL_TX5,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x825++0x00
|
|
line.byte 0x00 "MCTL_TX5,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x826))&0xC0)==0x80)
|
|
group.byte 0x826++0x00
|
|
line.byte 0x00 "MCTL_TX6,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x826))&0xC0)==0x40)
|
|
group.byte 0x826++0x00
|
|
line.byte 0x00 "MCTL_TX6,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x826++0x00
|
|
line.byte 0x00 "MCTL_TX6,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x827))&0xC0)==0x80)
|
|
group.byte 0x827++0x00
|
|
line.byte 0x00 "MCTL_TX7,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x827))&0xC0)==0x40)
|
|
group.byte 0x827++0x00
|
|
line.byte 0x00 "MCTL_TX7,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x827++0x00
|
|
line.byte 0x00 "MCTL_TX7,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x828))&0xC0)==0x80)
|
|
group.byte 0x828++0x00
|
|
line.byte 0x00 "MCTL_TX8,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x828))&0xC0)==0x40)
|
|
group.byte 0x828++0x00
|
|
line.byte 0x00 "MCTL_TX8,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x828++0x00
|
|
line.byte 0x00 "MCTL_TX8,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x829))&0xC0)==0x80)
|
|
group.byte 0x829++0x00
|
|
line.byte 0x00 "MCTL_TX9,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x829))&0xC0)==0x40)
|
|
group.byte 0x829++0x00
|
|
line.byte 0x00 "MCTL_TX9,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x829++0x00
|
|
line.byte 0x00 "MCTL_TX9,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x82A))&0xC0)==0x80)
|
|
group.byte 0x82A++0x00
|
|
line.byte 0x00 "MCTL_TX10,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x82A))&0xC0)==0x40)
|
|
group.byte 0x82A++0x00
|
|
line.byte 0x00 "MCTL_TX10,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x82A++0x00
|
|
line.byte 0x00 "MCTL_TX10,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x82B))&0xC0)==0x80)
|
|
group.byte 0x82B++0x00
|
|
line.byte 0x00 "MCTL_TX11,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x82B))&0xC0)==0x40)
|
|
group.byte 0x82B++0x00
|
|
line.byte 0x00 "MCTL_TX11,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x82B++0x00
|
|
line.byte 0x00 "MCTL_TX11,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x82C))&0xC0)==0x80)
|
|
group.byte 0x82C++0x00
|
|
line.byte 0x00 "MCTL_TX12,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x82C))&0xC0)==0x40)
|
|
group.byte 0x82C++0x00
|
|
line.byte 0x00 "MCTL_TX12,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x82C++0x00
|
|
line.byte 0x00 "MCTL_TX12,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x82D))&0xC0)==0x80)
|
|
group.byte 0x82D++0x00
|
|
line.byte 0x00 "MCTL_TX13,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x82D))&0xC0)==0x40)
|
|
group.byte 0x82D++0x00
|
|
line.byte 0x00 "MCTL_TX13,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x82D++0x00
|
|
line.byte 0x00 "MCTL_TX13,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x82E))&0xC0)==0x80)
|
|
group.byte 0x82E++0x00
|
|
line.byte 0x00 "MCTL_TX14,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x82E))&0xC0)==0x40)
|
|
group.byte 0x82E++0x00
|
|
line.byte 0x00 "MCTL_TX14,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x82E++0x00
|
|
line.byte 0x00 "MCTL_TX14,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x82F))&0xC0)==0x80)
|
|
group.byte 0x82F++0x00
|
|
line.byte 0x00 "MCTL_TX15,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x82F))&0xC0)==0x40)
|
|
group.byte 0x82F++0x00
|
|
line.byte 0x00 "MCTL_TX15,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x82F++0x00
|
|
line.byte 0x00 "MCTL_TX15,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x830))&0xC0)==0x80)
|
|
group.byte 0x830++0x00
|
|
line.byte 0x00 "MCTL_TX16,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x830))&0xC0)==0x40)
|
|
group.byte 0x830++0x00
|
|
line.byte 0x00 "MCTL_TX16,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x830++0x00
|
|
line.byte 0x00 "MCTL_TX16,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x831))&0xC0)==0x80)
|
|
group.byte 0x831++0x00
|
|
line.byte 0x00 "MCTL_TX17,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x831))&0xC0)==0x40)
|
|
group.byte 0x831++0x00
|
|
line.byte 0x00 "MCTL_TX17,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x831++0x00
|
|
line.byte 0x00 "MCTL_TX17,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x832))&0xC0)==0x80)
|
|
group.byte 0x832++0x00
|
|
line.byte 0x00 "MCTL_TX18,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x832))&0xC0)==0x40)
|
|
group.byte 0x832++0x00
|
|
line.byte 0x00 "MCTL_TX18,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x832++0x00
|
|
line.byte 0x00 "MCTL_TX18,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x833))&0xC0)==0x80)
|
|
group.byte 0x833++0x00
|
|
line.byte 0x00 "MCTL_TX19,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x833))&0xC0)==0x40)
|
|
group.byte 0x833++0x00
|
|
line.byte 0x00 "MCTL_TX19,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x833++0x00
|
|
line.byte 0x00 "MCTL_TX19,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x834))&0xC0)==0x80)
|
|
group.byte 0x834++0x00
|
|
line.byte 0x00 "MCTL_TX20,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x834))&0xC0)==0x40)
|
|
group.byte 0x834++0x00
|
|
line.byte 0x00 "MCTL_TX20,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x834++0x00
|
|
line.byte 0x00 "MCTL_TX20,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x835))&0xC0)==0x80)
|
|
group.byte 0x835++0x00
|
|
line.byte 0x00 "MCTL_TX21,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x835))&0xC0)==0x40)
|
|
group.byte 0x835++0x00
|
|
line.byte 0x00 "MCTL_TX21,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x835++0x00
|
|
line.byte 0x00 "MCTL_TX21,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x836))&0xC0)==0x80)
|
|
group.byte 0x836++0x00
|
|
line.byte 0x00 "MCTL_TX22,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x836))&0xC0)==0x40)
|
|
group.byte 0x836++0x00
|
|
line.byte 0x00 "MCTL_TX22,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x836++0x00
|
|
line.byte 0x00 "MCTL_TX22,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x837))&0xC0)==0x80)
|
|
group.byte 0x837++0x00
|
|
line.byte 0x00 "MCTL_TX23,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x837))&0xC0)==0x40)
|
|
group.byte 0x837++0x00
|
|
line.byte 0x00 "MCTL_TX23,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x837++0x00
|
|
line.byte 0x00 "MCTL_TX23,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x838))&0xC0)==0x80)
|
|
group.byte 0x838++0x00
|
|
line.byte 0x00 "MCTL_TX24,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x838))&0xC0)==0x40)
|
|
group.byte 0x838++0x00
|
|
line.byte 0x00 "MCTL_TX24,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x838++0x00
|
|
line.byte 0x00 "MCTL_TX24,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x839))&0xC0)==0x80)
|
|
group.byte 0x839++0x00
|
|
line.byte 0x00 "MCTL_TX25,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x839))&0xC0)==0x40)
|
|
group.byte 0x839++0x00
|
|
line.byte 0x00 "MCTL_TX25,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x839++0x00
|
|
line.byte 0x00 "MCTL_TX25,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x83A))&0xC0)==0x80)
|
|
group.byte 0x83A++0x00
|
|
line.byte 0x00 "MCTL_TX26,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x83A))&0xC0)==0x40)
|
|
group.byte 0x83A++0x00
|
|
line.byte 0x00 "MCTL_TX26,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x83A++0x00
|
|
line.byte 0x00 "MCTL_TX26,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x83B))&0xC0)==0x80)
|
|
group.byte 0x83B++0x00
|
|
line.byte 0x00 "MCTL_TX27,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x83B))&0xC0)==0x40)
|
|
group.byte 0x83B++0x00
|
|
line.byte 0x00 "MCTL_TX27,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x83B++0x00
|
|
line.byte 0x00 "MCTL_TX27,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x83C))&0xC0)==0x80)
|
|
group.byte 0x83C++0x00
|
|
line.byte 0x00 "MCTL_TX28,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x83C))&0xC0)==0x40)
|
|
group.byte 0x83C++0x00
|
|
line.byte 0x00 "MCTL_TX28,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x83C++0x00
|
|
line.byte 0x00 "MCTL_TX28,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x83D))&0xC0)==0x80)
|
|
group.byte 0x83D++0x00
|
|
line.byte 0x00 "MCTL_TX29,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x83D))&0xC0)==0x40)
|
|
group.byte 0x83D++0x00
|
|
line.byte 0x00 "MCTL_TX29,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x83D++0x00
|
|
line.byte 0x00 "MCTL_TX29,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x83E))&0xC0)==0x80)
|
|
group.byte 0x83E++0x00
|
|
line.byte 0x00 "MCTL_TX30,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x83E))&0xC0)==0x40)
|
|
group.byte 0x83E++0x00
|
|
line.byte 0x00 "MCTL_TX30,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x83E++0x00
|
|
line.byte 0x00 "MCTL_TX30,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
if (((per.w(ad:0x40050000+0x83F))&0xC0)==0x80)
|
|
group.byte 0x83F++0x00
|
|
line.byte 0x00 "MCTL_TX31,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " TRMABT ,Transmission Abort Complete Flag" "Not Occurred,Occurred"
|
|
rbitfld.byte 0x00 1. " TRMACTIVE ,Transmission-in-Progress Status Flag" "Not Occurred,Occurred"
|
|
bitfld.byte 0x00 0. " SENTDATA ,Transmission Complete Flag" "Not complete,Completed"
|
|
elif (((per.w(ad:0x40050000+0x83F))&0xC0)==0x40)
|
|
group.byte 0x83F++0x00
|
|
line.byte 0x00 "MCTL_TX31,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
bitfld.byte 0x00 4. " ONESHOT ,One-Shot Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " MSGLOST ,Message Lost Flag" "Not Overwritten/Overrun,Overwritten/Overrun"
|
|
rbitfld.byte 0x00 1. " INVALDATA ,Reception-in-Progress Status Flag" "Valid,being updated"
|
|
bitfld.byte 0x00 0. " NEWDATA ,Reception Complete Flag" "No data,New message"
|
|
else
|
|
group.byte 0x83F++0x00
|
|
line.byte 0x00 "MCTL_TX31,Message Control Register for Transmit"
|
|
bitfld.byte 0x00 7. " TRMREQ ,Transmit Mailbox Request" "No transmission,Transmission"
|
|
bitfld.byte 0x00 6. " RECREQ ,Receive Mailbox Request" "No reception,Reception"
|
|
endif
|
|
textline " "
|
|
group.byte 0x848++0x03
|
|
line.byte 0x00 "RFCR,Receive FIFO Control Register"
|
|
rbitfld.byte 0x00 7. " RFEST ,Receive FIFO Empty Status Flag" "Not empty,Empty"
|
|
rbitfld.byte 0x00 6. " RFWST ,Receive FIFO Buffer Warning Status Flag" "No warning,Warning"
|
|
rbitfld.byte 0x00 5. " RFFST ,Receive FIFO Full Status Flag" "Not full,Full"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " RFMLF ,Receive FIFO Message Lost Flag" "Not lost,Lost"
|
|
rbitfld.byte 0x00 1.--3. " RFUST ,Receive FIFO Unread Message Number Status" "None,1,2,3,4,?..."
|
|
bitfld.byte 0x00 0. " RFE ,Receive FIFO Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "RFPCR,Receive FIFO Pointer Control Register"
|
|
line.byte 0x02 "TFCR,Transmit FIFO Control Register"
|
|
rbitfld.byte 0x02 7. " TFEST ,Transmit FIFO Empty Status" "Not empty,Empty"
|
|
rbitfld.byte 0x02 6. " TFFST ,Transmit FIFO Full Status" "Not full,Full"
|
|
rbitfld.byte 0x02 1.--3. " TFUST ,Transmit FIFO Unsent Message Number Status" "None,1,2,3,4,?..."
|
|
textline " "
|
|
bitfld.byte 0x02 0. " TFE ,Transmit FIFO Enable" "Disabled,Enabled"
|
|
line.byte 0x03 "TFPCR,Transmit FIFO Pointer Control Register"
|
|
rgroup.word 0x842++0x01
|
|
line.word 0x00 "STR,Status Register"
|
|
bitfld.word 0x00 14. " RECST ,Receive Status Flag" "Idle/transmission in progress,Reception in progress"
|
|
bitfld.word 0x00 13. " TRMST ,Transmit Status Flag" "Idle/reception in progress,Transmission n progress/bus-off"
|
|
bitfld.word 0x00 12. " BOST ,Bus-Off Status Flag" "No bus-off,Bus-off"
|
|
textline " "
|
|
bitfld.word 0x00 11. " EPST ,Error-Passive Status Flagg" "No error-passive state,Error-passive state"
|
|
bitfld.word 0x00 11. " SLPST ,CAN Sleep Status Flag" "No sleep mode,Sleep mode"
|
|
bitfld.word 0x00 9. " HLTST ,CAN Halt Status Flag" "No halt mode,Halt mode"
|
|
textline " "
|
|
bitfld.word 0x00 8. " RSTST ,CAN Reset Status Flag" "No reset mode,Reset mode"
|
|
bitfld.word 0x00 7. " EST ,Error Status Flag" "No error,Error"
|
|
bitfld.word 0x00 6. " TABST ,Transmission Abort Status Flag" "No mailbox,Mailbox/es"
|
|
textline " "
|
|
bitfld.word 0x00 5. " FMLST ,FIFO Mailbox Message Lost Status Flag" "Not lost,Lost"
|
|
bitfld.word 0x00 4. " NMLST ,Normal Mailbox Message Lost Status Flag" "No mailbox,Mailbox/es"
|
|
bitfld.word 0x00 3. " TFST ,Transmit FIFO Status Flag" "Full,Not full"
|
|
textline " "
|
|
bitfld.word 0x00 2. " RFST ,Receive FIFO Status Flag" "Empty,Not empty"
|
|
bitfld.word 0x00 1. " SDST ,SENTDATA Status Flag" "No mailbox,Mailbox/es"
|
|
bitfld.word 0x00 0. " NDST ,NEWDATA Status Flag" "No mailbox,Mailbox/es"
|
|
group.byte 0x853++0x00
|
|
line.byte 0x00 "MSMR,Mailbox Search Mode Register"
|
|
bitfld.byte 0x00 0.--1. " MBSM ,Mailbox Search Mode Select" "Receive mailbox,Transmit mailbox,Message lost mode,Channel"
|
|
rgroup.byte 0x852++0x00
|
|
line.byte 0x00 "MSSR,Mailbox Search Status Register"
|
|
bitfld.byte 0x00 7. " SEST ,Search Result Status" "Found,Not found"
|
|
bitfld.byte 0x00 0.--4. " MBNST ,Search Result Mailbox Number Status" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.byte 0x851++0x00
|
|
line.byte 0x00 "CSSR,Channel Search Support Register"
|
|
group.word 0x856++0x01
|
|
line.word 0x00 "AFSR,Acceptance Filter Support Register"
|
|
group.byte 0x84C++0x03
|
|
line.byte 0x00 "EIER,Error Interrupt Enable Register"
|
|
bitfld.byte 0x00 7. " BLIE ,Bus Lock Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " OLIE ,Overload Frame Transmit Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " ORIE ,Overrun Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " BORIE ,Bus-Off Recovery Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 3. " BOEIE ,Bus-Off Entry Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 2. " EPIE ,EPIE Error-Passive Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " EWIE ,Error-Warning Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " BEIE ,Bus Error Interrupt Enable" "Disabled,Enabled"
|
|
line.byte 0x01 "EIFR,Error Interrupt Factor Judge Register"
|
|
bitfld.byte 0x01 7. " BLIF ,Bus Lock Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 6. " OLIF ,Overload Frame Transmission Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 5. " ORIF ,Receive Overrun Detect Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x01 4. " BORIF ,Bus-Off Recovery Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 3. " BOEIF ,Bus-Off Entry Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 2. " EPIF ,Error-Passive Detect Flag" "Not detected,Detected"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " EWIF ,Error-Warning Detect Flag" "Not detected,Detected"
|
|
bitfld.byte 0x01 0. " BEIF ,Bus Error Detect Flag" "Not detected,Detected"
|
|
line.byte 0x02 "RECR,Receive Error Count Register"
|
|
line.byte 0x03 "TECR,Transmit Error Count Register"
|
|
group.byte 0x850++0x00
|
|
line.byte 0x00 "ECSR,Error Code Store Register"
|
|
bitfld.byte 0x00 7. " EDPM ,Error Display Mode Select" "Output first detected,Output accumulated"
|
|
bitfld.byte 0x00 6. " ADEF ,ACK Delimiter Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 5. " BE0F ,Bit Error (dominant) Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 4. " BE1F ,Bit Error (recessive) Flag" "No error,Error"
|
|
bitfld.byte 0x00 3. " CEF ,CRC Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 2. " AEF ,ACK Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x00 1. " FEF ,Form Error Flag" "No error,Error"
|
|
bitfld.byte 0x00 0. " SEF ,Stuff Error Flag" "No error,Error"
|
|
group.word 0x854++0x01
|
|
line.word 0x00 "TSR,Time Stamp Register"
|
|
group.byte 0x858++0x00
|
|
line.byte 0x00 "TCR,Test Control Register"
|
|
bitfld.byte 0x00 1.--2. " TSTM ,CAN Test Mode Select" "Not CAN,Listen-only,Self-test 0,Self-test 1"
|
|
bitfld.byte 0x00 0. " TSTE ,CAN Test Mode Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI (Serial Peripheral Interface)"
|
|
tree "SPI 0"
|
|
base ad:0x40072000
|
|
width 9.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "SPCR,SPI Control Register"
|
|
bitfld.byte 0x00 7. " SPRIE ,SPI Receive Buffer Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,Transmit Buffer Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SPEIE ,SPI Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MSTR ,SPI Master/Slave Mode Select" "Slave,Master"
|
|
bitfld.byte 0x00 2. " MODFEN ,Mode Fault Error Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TXMD ,Communications Operating Mode Select" "Full-duplex,Transmit-only"
|
|
bitfld.byte 0x00 0. " SPMS ,SPI Mode Select" "SPI,Clock-synchronous"
|
|
line.byte 0x01 "SSLP,SPI Slave Select Polarity Register"
|
|
bitfld.byte 0x01 3. " SSL3P ,SSL3 Signal Polarity Setting" "Active low,Active high"
|
|
bitfld.byte 0x01 2. " SSL2P ,SSL2 Signal Polarity Setting" "Active low,Active high"
|
|
bitfld.byte 0x01 1. " SSL1P ,SSL1 Signal Polarity Setting" "Active low,Active high"
|
|
bitfld.byte 0x01 0. " SSL0P ,SSL0 Signal Polarity Setting" "Active low,Active high"
|
|
line.byte 0x02 "SPPCR,SPI Pin Control Register"
|
|
bitfld.byte 0x02 5. " MOIFE ,MOSI Idle Value Fixing Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 4. " MOIFV ,MOSI Idle Fixed Value" "Low,High"
|
|
bitfld.byte 0x02 1. " SPLP2 ,SPI Loopback 2" "Normal,Loopback"
|
|
bitfld.byte 0x02 0. " SPLP ,SPI Loopback " "Normal,Loopback"
|
|
line.byte 0x03 "SPSR,SPI Status Register"
|
|
bitfld.byte 0x03 7. " SPRF ,SPI Receive Buffer Full Flag" "Not full,Full"
|
|
bitfld.byte 0x03 5. " SPTEF ,SPI Transmit Buffer Empty" "Not empty,Empty"
|
|
bitfld.byte 0x03 4. " UDRF ,Underrun Error Flag" "Mode fault error,Underrun error"
|
|
bitfld.byte 0x03 3. " PERF ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x03 2. " MODF ,Mode Fault Error Flag" "No error,Error"
|
|
rbitfld.byte 0x03 1. " IDLNF ,SPI Idle Flag" "Idle,Busy"
|
|
bitfld.byte 0x03 0. " OVRF ,Overrun Error Flag" "No error,Error"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPDR_HA,SPI Data Register"
|
|
group.byte 0xA++0x05
|
|
line.byte 0x00 "SPBR,SPI Bit Rate Register"
|
|
line.byte 0x01 "SPDCR,SPI Data Control Register"
|
|
bitfld.byte 0x01 4. " SPRDTD ,SPI Receive/Transmit Data Select" "Recive,Transmit"
|
|
line.byte 0x02 "SPCKD,SPI Clock Delay Register"
|
|
bitfld.byte 0x02 0.--2. " SCKDL ,RSPCK Delay Setting" "1,2,3,4,5,6,7,8"
|
|
line.byte 0x03 "SSLND,SPI Slave Select Negation Delay Register"
|
|
bitfld.byte 0x03 0.--2. " SLNDL ,SSL Negation Delay Setting" "1,2,3,4,5,6,7,8"
|
|
line.byte 0x04 "SPND,SPI Next-Access Delay Register"
|
|
bitfld.byte 0x04 0.--2. " SPNDL ,SPI Next-Access Delay Setting" "1 RSPCK+2PCLKB,2 RSPCK+2PCLKB,3 RSPCK+2PCLKB,4 RSPCK+2PCLKB,5 RSPCK+2PCLKB,6 RSPCK+2PCLKB,7 RSPCK+2PCLKB,8 RSPCK+2PCLKB"
|
|
line.byte 0x05 "SPCR2,SPI Control Register 2"
|
|
bitfld.byte 0x05 4. " SCKASE ,RSPCK Auto-Stop Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 3. " PTE ,Parity Self-Testing" "Disabled,Enabled"
|
|
bitfld.byte 0x05 2. " SPIIE ,SPI Idle Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 1. " SPOE ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x05 0. " SPPE ,Parity Enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPCMD0,SPI Command Registers 0"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK+2PCLKB,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" ",,,,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Idle low,Idle high"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting (on leading edge/ on trailing edge)" "Sampling/data change,Data change/sampling"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SPI 1"
|
|
base ad:0x40072100
|
|
width 9.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "SPCR,SPI Control Register"
|
|
bitfld.byte 0x00 7. " SPRIE ,SPI Receive Buffer Full Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 6. " SPE ,SPI Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 5. " SPTIE ,Transmit Buffer Empty Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " SPEIE ,SPI Error Interrupt Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " MSTR ,SPI Master/Slave Mode Select" "Slave,Master"
|
|
bitfld.byte 0x00 2. " MODFEN ,Mode Fault Error Detection Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " TXMD ,Communications Operating Mode Select" "Full-duplex,Transmit-only"
|
|
bitfld.byte 0x00 0. " SPMS ,SPI Mode Select" "SPI,Clock-synchronous"
|
|
line.byte 0x01 "SSLP,SPI Slave Select Polarity Register"
|
|
bitfld.byte 0x01 3. " SSL3P ,SSL3 Signal Polarity Setting" "Active low,Active high"
|
|
bitfld.byte 0x01 2. " SSL2P ,SSL2 Signal Polarity Setting" "Active low,Active high"
|
|
bitfld.byte 0x01 1. " SSL1P ,SSL1 Signal Polarity Setting" "Active low,Active high"
|
|
bitfld.byte 0x01 0. " SSL0P ,SSL0 Signal Polarity Setting" "Active low,Active high"
|
|
line.byte 0x02 "SPPCR,SPI Pin Control Register"
|
|
bitfld.byte 0x02 5. " MOIFE ,MOSI Idle Value Fixing Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x02 4. " MOIFV ,MOSI Idle Fixed Value" "Low,High"
|
|
bitfld.byte 0x02 1. " SPLP2 ,SPI Loopback 2" "Normal,Loopback"
|
|
bitfld.byte 0x02 0. " SPLP ,SPI Loopback " "Normal,Loopback"
|
|
line.byte 0x03 "SPSR,SPI Status Register"
|
|
bitfld.byte 0x03 7. " SPRF ,SPI Receive Buffer Full Flag" "Not full,Full"
|
|
bitfld.byte 0x03 5. " SPTEF ,SPI Transmit Buffer Empty" "Not empty,Empty"
|
|
bitfld.byte 0x03 4. " UDRF ,Underrun Error Flag" "Mode fault error,Underrun error"
|
|
bitfld.byte 0x03 3. " PERF ,Parity Error Flag" "No error,Error"
|
|
textline " "
|
|
bitfld.byte 0x03 2. " MODF ,Mode Fault Error Flag" "No error,Error"
|
|
rbitfld.byte 0x03 1. " IDLNF ,SPI Idle Flag" "Idle,Busy"
|
|
bitfld.byte 0x03 0. " OVRF ,Overrun Error Flag" "No error,Error"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "SPDR_HA,SPI Data Register"
|
|
group.byte 0xA++0x05
|
|
line.byte 0x00 "SPBR,SPI Bit Rate Register"
|
|
line.byte 0x01 "SPDCR,SPI Data Control Register"
|
|
bitfld.byte 0x01 4. " SPRDTD ,SPI Receive/Transmit Data Select" "Recive,Transmit"
|
|
line.byte 0x02 "SPCKD,SPI Clock Delay Register"
|
|
bitfld.byte 0x02 0.--2. " SCKDL ,RSPCK Delay Setting" "1,2,3,4,5,6,7,8"
|
|
line.byte 0x03 "SSLND,SPI Slave Select Negation Delay Register"
|
|
bitfld.byte 0x03 0.--2. " SLNDL ,SSL Negation Delay Setting" "1,2,3,4,5,6,7,8"
|
|
line.byte 0x04 "SPND,SPI Next-Access Delay Register"
|
|
bitfld.byte 0x04 0.--2. " SPNDL ,SPI Next-Access Delay Setting" "1 RSPCK+2PCLKB,2 RSPCK+2PCLKB,3 RSPCK+2PCLKB,4 RSPCK+2PCLKB,5 RSPCK+2PCLKB,6 RSPCK+2PCLKB,7 RSPCK+2PCLKB,8 RSPCK+2PCLKB"
|
|
line.byte 0x05 "SPCR2,SPI Control Register 2"
|
|
bitfld.byte 0x05 4. " SCKASE ,RSPCK Auto-Stop Function Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 3. " PTE ,Parity Self-Testing" "Disabled,Enabled"
|
|
bitfld.byte 0x05 2. " SPIIE ,SPI Idle Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x05 1. " SPOE ,Parity Mode" "Even,Odd"
|
|
textline " "
|
|
bitfld.byte 0x05 0. " SPPE ,Parity Enable" "Disabled,Enabled"
|
|
group.word 0x10++0x01
|
|
line.word 0x00 "SPCMD0,SPI Command Registers 0"
|
|
bitfld.word 0x00 15. " SCKDEN ,RSPCK Delay Setting Enable" "1 RSPCK,SPCKD"
|
|
bitfld.word 0x00 14. " SLNDEN ,SSL Negation Delay Setting Enable" "1 RSPCK,SSLND"
|
|
bitfld.word 0x00 13. " SPNDEN ,SPI Next-Access Delay Enable" "1 RSPCK+2PCLKB,SPND"
|
|
bitfld.word 0x00 12. " LSBF ,SPI LSB First" "MSB,LSB"
|
|
textline " "
|
|
bitfld.word 0x00 8.--11. " SPB ,SPI Data Length Setting" ",,,,8 bits,8 bits,8 bits,8 bits,9 bits,10 bits,11 bits,12 bits,13 bits,14 bits,15 bits,16 bits"
|
|
bitfld.word 0x00 4.--6. " SSLA ,SSL Signal Assertion Setting" "SSL0,SSL1,SSL2,SSL3,?..."
|
|
bitfld.word 0x00 2.--3. " BRDV ,Bit Rate Division Setting" "/1,/2,/4,/8"
|
|
bitfld.word 0x00 1. " CPOL ,RSPCK Polarity Setting" "Idle low,Idle high"
|
|
textline " "
|
|
bitfld.word 0x00 0. " CPHA ,RSPCK Phase Setting (on leading edge/ on trailing edge)" "Sampling/data change,Data change/sampling"
|
|
width 0x0B
|
|
tree.end
|
|
tree.end
|
|
tree "CRC (Cyclic Redundancy Check Calculator)"
|
|
base ad:0x40074000
|
|
width 14.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "CRCCR0,CRC Control Register 0"
|
|
bitfld.byte 0x00 7. " DORCLR ,CRCDOR* Register Clear" "No effect,Clear"
|
|
bitfld.byte 0x00 6. " LMS ,CRC Calculation Switching" "LSB,MSB"
|
|
bitfld.byte 0x00 0.--2. " GPS ,CRC Generating Polynomial Switching" "No calculation,8-bit CRC,16-bit CRC-16,16-bit CRC-CCITT,32-bit CRC-32,32-bit CRC-32C,No calculation,No calculation"
|
|
line.byte 0x01 "CRCCR1,CRC Control Register 1"
|
|
bitfld.byte 0x01 7. " CRCSWR ,Snoop-On-Write/Read Switch" "On-read,On-write"
|
|
bitfld.byte 0x01 6. " CRCSEN ,Snoop Enable" "Disabled,Enabled"
|
|
group.long 0x04++0x07
|
|
line.long 0x00 "CRCDIR/BY,CRC Data Input Register"
|
|
line.long 0x04 "CRCDIR/HA/BY,CRC Data Output Register"
|
|
group.word 0x0C++0x01
|
|
line.word 0x00 "CRCSAR,Snoop Address Register"
|
|
hexmask.word 0x00 0.--13. 1. " CRCSA ,Register Snoop Address"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ADC14 (14-Bit A/D Converter)"
|
|
base ad:0x4005C000
|
|
width 13.
|
|
if (((per.b(ad:0x4005C000+0x0C))&0x07)==0x00)
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x8000)==0x0000)
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x06)==0x06)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Register 0"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Register 1"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Register 2"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Register 3"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Register 4"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Register 5"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Register 6"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Register 7"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Register 8"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Register 9"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Register 10"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Register 16"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Register 17"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Register 18"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Register 19"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Register 20"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Register 21"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Register 22"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14bit converted value"
|
|
else
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Register 0"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Register 1"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Register 2"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Register 3"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Register 4"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Register 5"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Register 6"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Register 7"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Register 8"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Register 9"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Register 10"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Register 16"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Register 17"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Register 18"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Register 19"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Register 20"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Register 21"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Register 22"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x06)==0x06)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Register 0"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Register 1"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Register 2"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Register 3"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Register 4"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Register 5"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Register 6"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Register 7"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Register 8"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Register 9"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Register 10"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Register 16"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Register 17"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Register 18"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Register 19"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Register 20"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Register 21"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Register 22"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14bit converted value"
|
|
else
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Register 0"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Register 1"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Register 2"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Register 3"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Register 4"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Register 5"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Register 6"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Register 7"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Register 8"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Register 9"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Register 10"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Register 16"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Register 17"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Register 18"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Register 19"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Register 20"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Register 21"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Register 22"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12bit converted value"
|
|
endif
|
|
endif
|
|
elif (((per.b(ad:0x4005C000+0x0C))&0x07)==0x05)
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x06)==0x06)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Register 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Register 1"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Register 2"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Register 3"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Register 4"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Register 5"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Register 6"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Register 7"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Register 8"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Register 9"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Register 10"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Register 16"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Register 17"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Register 18"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Register 19"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Register 20"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Register 21"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Register 22"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
else
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Register 0"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Register 1"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Register 2"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Register 3"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Register 4"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Register 5"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Register 6"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Register 7"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Register 8"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Register 9"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Register 10"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Register 16"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Register 17"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Register 18"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Register 19"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Register 20"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Register 21"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Register 22"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12bit converted value"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x8000)==0x0)
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x06)==0x06)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Register 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Register 1"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Register 2"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Register 3"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Register 4"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Register 5"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Register 6"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Register 7"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Register 8"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Register 9"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Register 10"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Register 16"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Register 17"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Register 18"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Register 19"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Register 20"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Register 21"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Register 22"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
else
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Register 0"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Register 1"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Register 2"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Register 3"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Register 4"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Register 5"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Register 6"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Register 7"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Register 8"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Register 9"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Register 10"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Register 16"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Register 17"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Register 18"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Register 19"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Register 20"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Register 21"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Register 22"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,12bit converted value"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x06)==0x06)
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Register 0"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Register 1"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Register 2"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Register 3"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Register 4"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Register 5"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Register 6"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Register 7"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Register 8"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Register 9"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Register 10"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Register 16"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Register 17"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Register 18"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Register 19"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Register 20"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Register 21"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Register 22"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
else
|
|
rgroup.word 0x20++0x01
|
|
line.word 0x00 "ADDR0,A/D Data Register 0"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x22++0x01
|
|
line.word 0x00 "ADDR1,A/D Data Register 1"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x24++0x01
|
|
line.word 0x00 "ADDR2,A/D Data Register 2"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x26++0x01
|
|
line.word 0x00 "ADDR3,A/D Data Register 3"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x28++0x01
|
|
line.word 0x00 "ADDR4,A/D Data Register 4"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2A++0x01
|
|
line.word 0x00 "ADDR5,A/D Data Register 5"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2C++0x01
|
|
line.word 0x00 "ADDR6,A/D Data Register 6"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x2E++0x01
|
|
line.word 0x00 "ADDR7,A/D Data Register 7"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x30++0x01
|
|
line.word 0x00 "ADDR8,A/D Data Register 8"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x32++0x01
|
|
line.word 0x00 "ADDR9,A/D Data Register 9"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x34++0x01
|
|
line.word 0x00 "ADDR10,A/D Data Register 10"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x40++0x01
|
|
line.word 0x00 "ADDR16,A/D Data Register 16"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x42++0x01
|
|
line.word 0x00 "ADDR17,A/D Data Register 17"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x44++0x01
|
|
line.word 0x00 "ADDR18,A/D Data Register 18"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x46++0x01
|
|
line.word 0x00 "ADDR19,A/D Data Register 19"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x48++0x01
|
|
line.word 0x00 "ADDR20,A/D Data Register 20"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x4A++0x01
|
|
line.word 0x00 "ADDR21,A/D Data Register 21"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x4C++0x01
|
|
line.word 0x00 "ADDR22,A/D Data Register 22"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x18++0x01
|
|
line.word 0x00 "ADDBLDR,A/D Data Duplexing Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x84++0x01
|
|
line.word 0x00 "ADDBLDRA,A/D Data Duplexing Register A"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x86++0x01
|
|
line.word 0x00 "ADDBLDRB,A/D Data Duplexing Register B"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x1A++0x01
|
|
line.word 0x00 "ADTSDR,A/D Temperature Sensor Data Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
rgroup.word 0x1C++0x01
|
|
line.word 0x00 "ADOCDR,A/D Internal Reference Voltage Data Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,12bit converted value"
|
|
endif
|
|
endif
|
|
endif
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x8000)==0x0)
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x06)==0x06)
|
|
rgroup.word 0x1E++0x01
|
|
line.word 0x00 "ADRD,A/D Self-Diagnosis Data Register"
|
|
bitfld.word 0x00 14.--15. " DIAGST ,Self-Diagnosis Status" "Not executed,0 volts,Voltage/2,Volatage"
|
|
hexmask.word 0x00 0.--13. 1. " AD ,14-bit converted value"
|
|
else
|
|
rgroup.word 0x1E++0x01
|
|
line.word 0x00 "ADRD,A/D Self-Diagnosis Data Register"
|
|
bitfld.word 0x00 14.--15. " DIAGST ,Self-Diagnosis Status" "Not executed,0 volts,Voltage/2,Volatage"
|
|
hexmask.word 0x00 0.--11. 1. " AD ,12-bit converted value"
|
|
endif
|
|
else
|
|
if (((per.w(ad:0x4005C000+0x0E))&0x06)==0x06)
|
|
rgroup.word 0x1E++0x01
|
|
line.word 0x00 "ADRD,A/D Self-Diagnosis Data Register"
|
|
hexmask.word 0x00 2.--15. 1. " AD ,14-bit converted value"
|
|
bitfld.word 0x00 0.--1. " DIAGST ,Self-Diagnosis Status" "Not executed,0 volts,Voltage/2,Volatage"
|
|
else
|
|
rgroup.word 0x1E++0x01
|
|
line.word 0x00 "ADRD,A/D Self-Diagnosis Data Register"
|
|
hexmask.word 0x00 4.--15. 1. " AD ,12-bit converted value"
|
|
bitfld.word 0x00 0.--1. " DIAGST ,Self-Diagnosis Status" "Not executed,0 volts,Voltage/2,Volatage"
|
|
endif
|
|
endif
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "ADCSR,A/D Control Register"
|
|
bitfld.word 0x00 15. " ADST ,A/D Conversion Start" "Stop,Start"
|
|
bitfld.word 0x00 13.--14. " ADCS ,Scan Mode Select" "Single,group,Continous,?..."
|
|
bitfld.word 0x00 10. " ASHSC ,A/D Conversion Mode Select" "High-speed,Low-power"
|
|
bitfld.word 0x00 9. " TRGE ,Trigger Start Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 8. " EXTRG ,Trigger Select" "Synchronous,Asynchronous"
|
|
bitfld.word 0x00 7. " DBLE ,Double Trigger Mode Select" "Deselected,Selected"
|
|
bitfld.word 0x00 6. " GBADIE ,Group B Scan End Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--4. " DBLANS ,Double Trigger Channel Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
group.word 0x04++0x01
|
|
line.word 0x00 "ADANSA0,A/D Channel Select Register A0"
|
|
bitfld.word 0x00 10. " ANSA10 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 9. " ANSA09 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 8. " ANSA08 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 7. " ANSA07 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ANSA06 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 5. " ANSA05 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 4. " ANSA04 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 3. " ANSA03 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ANSA02 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 1. " ANSA01 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 0. " ANSA00 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
group.word 0x06++0x01
|
|
line.word 0x00 "ADANSA1,A/D Channel Select Register A1"
|
|
bitfld.word 0x00 6. " ANSA22 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 5. " ANSA21 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 4. " ANSA20 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 3. " ANSA19 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ANSA18 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 1. " ANSA17 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
bitfld.word 0x00 0. " ANSA16 ,A/D Conversion Channels Select " "Not selected,Selected"
|
|
group.word 0x14++0x01
|
|
line.word 0x00 "ADANSB0,A/D Channel Select Register B0"
|
|
bitfld.word 0x00 10. " ANSB10 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 9. " ANSB09 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 8. " ANSB08 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 7. " ANSB07 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ANSB06 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 5. " ANSB05 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 4. " ANSB04 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 3. " ANSB03 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ANSB02 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 1. " ANSB01 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 0. " ANSB00 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
group.word 0x16++0x01
|
|
line.word 0x00 "ADANSB1,A/D Channel Select Register B1"
|
|
bitfld.word 0x00 6. " ANSB22 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 5. " ANSB21 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 4. " ANSB20 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 3. " ANSB19 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ANSB18 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 1. " ANSB17 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 0. " ANSB16 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
group.word 0x08++0x01
|
|
line.word 0x00 "ADADS0,A/D-Converted Value Addition/Average Channel Select Register 0"
|
|
bitfld.word 0x00 10. " ADS10 ,A/D Conversion Channels Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 9. " ADS09 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 8. " ADS08 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 7. " ADS07 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 6. " ADS06 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 5. " ADS05 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 4. " ADS04 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 3. " ADS03 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ADS02 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 1. " ADS01 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 0. " ADS00 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
group.word 0x0A++0x01
|
|
line.word 0x00 "ADADS1,A/D-Converted Value Addition/Average Channel Select Register 1"
|
|
bitfld.word 0x00 6. " ADS22 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 5. " ADS21 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 4. " ADS20 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 3. " ADS19 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
textline " "
|
|
bitfld.word 0x00 2. " ADS18 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 1. " ADS17 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
bitfld.word 0x00 0. " ADS16 ,A/D-Converted Value Addition/ Average Channel Select" "Not Selected,Selected"
|
|
group.byte 0x0C++0x00
|
|
line.byte 0x00 "ADADC,A/D-Converted Value Addition/Average Count Select Register"
|
|
bitfld.byte 0x00 7. " AVE ,Average Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0.--2. " ADC ,Count Select" "1-time(normal),2-time,3-time,4-time,16-time,?..."
|
|
group.word 0x0E++0x01
|
|
line.word 0x00 "ADCER,A/D Control Extended Register"
|
|
bitfld.word 0x00 15. " ADRFMT ,A/D Data Register Format Select" "Flush-right,Flush-left"
|
|
bitfld.word 0x00 11. " DIAGM ,Self-Diagnosis Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 10. " DIAGLD ,Self-Diagnosis Mode Select" "Rotation,Fixed"
|
|
bitfld.word 0x00 8.--9. " DIAGVAL ,Self-Diagnosis Conversion Voltage Select" ",0 volts,Voltage/2,Voltage"
|
|
textline " "
|
|
bitfld.word 0x00 5. " ACE ,A/D Data Register Automatic Clearing Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 1.--2. " ADPRC ,A/D Conversion Accuracy Specify" "12 bit,,,14 bit"
|
|
group.word 0x10++0x03
|
|
line.word 0x00 "ADSTRGR,A/D Conversion Start Trigger Select Register"
|
|
bitfld.word 0x00 8.--13. " TRSA ,A/D Conversion Start Trigger Select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
bitfld.word 0x00 0.--5. " TRSB ,A/D Conversion Start Trigger Select for Group B" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
line.word 0x02 "ADEXICR,A/D Conversion Extended Input Control Register"
|
|
bitfld.word 0x02 9. " OCSA ,Internal Reference Voltage A/D Conversion Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 8. " TSSA ,Temperature Sensor Output A/D Conversion Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " OCSAD ,Internal Reference Voltage A/DConverted Value Addition/Average Mode Select" "Not selected,Selected"
|
|
bitfld.word 0x02 0. " TSSAD ,Temperature Sensor Output A/DConverted Value Addition/Average Mode Select" "Not selected,Selected"
|
|
group.byte 0xE0++0x00
|
|
line.byte 0x00 "ADSSTR00,A/D Sampling State Register 0"
|
|
group.byte 0xE1++0x00
|
|
line.byte 0x00 "ADSSTR01,A/D Sampling State Register 1"
|
|
group.byte 0xE2++0x00
|
|
line.byte 0x00 "ADSSTR02,A/D Sampling State Register 2"
|
|
group.byte 0xE3++0x00
|
|
line.byte 0x00 "ADSSTR03,A/D Sampling State Register 3"
|
|
group.byte 0xE4++0x00
|
|
line.byte 0x00 "ADSSTR04,A/D Sampling State Register 4"
|
|
group.byte 0xE5++0x00
|
|
line.byte 0x00 "ADSSTR05,A/D Sampling State Register 5"
|
|
group.byte 0xE6++0x00
|
|
line.byte 0x00 "ADSSTR06,A/D Sampling State Register 6"
|
|
group.byte 0xE7++0x00
|
|
line.byte 0x00 "ADSSTR07,A/D Sampling State Register 7"
|
|
group.byte 0xE8++0x00
|
|
line.byte 0x00 "ADSSTR08,A/D Sampling State Register 8"
|
|
group.byte 0xE9++0x00
|
|
line.byte 0x00 "ADSSTR09,A/D Sampling State Register 9"
|
|
group.byte 0xEA++0x00
|
|
line.byte 0x00 "ADSSTR10,A/D Sampling State Register 10"
|
|
group.byte 0xDD++0x02
|
|
line.byte 0x00 "ADSSTRL,A/D Sampling State Register L"
|
|
line.byte 0x01 "ADSSTRT,A/D Sampling State Register T"
|
|
line.byte 0x01 "ADSSTRO,A/D Sampling State Register O"
|
|
group.byte 0x7A++0x00
|
|
line.byte 0x00 "ADDISCR,A/D Disconnection Detection Control Register"
|
|
bitfld.byte 0x00 0.--4. " ADNDIS ,Disconnection Detection Assist Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31"
|
|
if (((per.w(ad:0x4005C000+0x80))&0x01)==0x01)
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "ADGSPCR,A/D Group Scan Priority Control Register"
|
|
bitfld.word 0x00 15. " GBRP ,Group B Single Scan Continuous Start" "Not activated,Activated"
|
|
bitfld.word 0x00 1. " GBRSCN ,Group B Restart Setting" "No restart,Restart"
|
|
bitfld.word 0x00 0. " PGS ,Group A Priority Control Setting" "No priority,Priority"
|
|
else
|
|
group.word 0x80++0x01
|
|
line.word 0x00 "ADGSPCR,A/D Group Scan Priority Control Register"
|
|
bitfld.word 0x00 0. " PGS ,Group A Priority Control Setting" "No priority,Priority"
|
|
endif
|
|
if (((per.w(ad:0x4005C000+0x90))&0xA00)==0xA00)
|
|
group.word 0x90++0x01
|
|
line.word 0x00 "ADCMPCR,A/D Compare Function Control Register"
|
|
bitfld.word 0x00 15. " CMPAIE ,Compare A Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " WCMPE ,Window Function Setting" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CMPBIE ,Compare B Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CMPAE ,Compare Window A Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CMPBE ,Compare Window B Operation Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 0.--1. " CMPAB ,Window A/B Composite Conditions Setting" "OR,EXOR,AND,?..."
|
|
else
|
|
group.word 0x90++0x01
|
|
line.word 0x00 "ADCMPCR,A/D Compare Function Control Register"
|
|
bitfld.word 0x00 15. " CMPAIE ,Compare A Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 14. " WCMPE ,Window Function Setting" "Disabled,Enabled"
|
|
bitfld.word 0x00 13. " CMPBIE ,Compare B Interrupt Enable" "Disabled,Enabled"
|
|
bitfld.word 0x00 11. " CMPAE ,Compare Window A Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 9. " CMPBE ,Compare Window B Operation Enable" "Disabled,Enabled"
|
|
endif
|
|
group.word 0x94++0x03
|
|
line.word 0x00 "ADCMPANSR0,A/D Compare Function Window A Channel Select Register 0"
|
|
bitfld.word 0x00 10. " CMPCHA10 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 9. " CMPCHA09 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 8. " CMPCHA08 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 7. " CMPCHA07 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CMPCHA06 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 5. " CMPCHA05 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 4. " CMPCHA04 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 3. " CMPCHA03 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CMPCHA02 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 1. " CMPCHA01 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x00 0. " CMPCHA00 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
line.word 0x02 "ADCMPANSR1,A/D Compare Function Window A Channel Select Register 1"
|
|
bitfld.word 0x02 6. " CMPCHA22 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 5. " CMPCHA21 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 4. " CMPCHA20 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 3. " CMPCHA19 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
textline " "
|
|
bitfld.word 0x02 2. " CMPCHA18 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 1. " CMPCHA17 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
bitfld.word 0x02 0. " CMPCHA16 ,Compare Window A Channel Select" "Disabled,Enabled"
|
|
group.byte 0x92++0x00
|
|
line.byte 0x00 "ADCMPANSER,A/D Compare Function Window A Extended Input Select Register"
|
|
bitfld.byte 0x00 1. " CMPOCA ,Internal Reference Voltage Compare Select" "Excluded,Included"
|
|
bitfld.byte 0x00 0. " CMPTSA ,Temperature Sensor Output Compare Select" "Excluded,Included"
|
|
if (((per.l(ad:0x4005C000+0x90))&0x4000)==0x00)
|
|
group.word 0x98++0x01
|
|
line.word 0x00 "ADCMPLR0,A/D Compare Function Window A Comparison Condition Setting Register 0"
|
|
bitfld.word 0x00 10. " CMPLCHA10 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 9. " CMPLCHA09 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 8. " CMPLCHA08 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 7. " CMPLCHA07 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CMPLCHA06 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 5. " CMPLCHA05 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 4. " CMPLCHA04 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 3. " CMPLCHA03 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CMPLCHA02 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 1. " CMPLCHA01 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 0. " CMPLCHA00 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
else
|
|
group.word 0x98++0x01
|
|
line.word 0x00 "ADCMPLR0,A/D Compare Function Window A Comparison Condition Setting Register 0"
|
|
bitfld.word 0x00 10. " CMPLCHA10 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 9. " CMPLCHA09 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 8. " CMPLCHA08 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 7. " CMPLCHA07 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CMPLCHA06 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 5. " CMPLCHA05 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 4. " CMPLCHA04 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 3. " CMPLCHA03 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CMPLCHA02 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 1. " CMPLCHA01 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 0. " CMPLCHA00 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
endif
|
|
if (((per.l(ad:0x4005C000+0x90))&0x4000)==0x00)
|
|
group.word 0x9A++0x01
|
|
line.word 0x00 "ADCMPLR1,A/D Compare Function Window A Comparison Condition Setting Register 1"
|
|
bitfld.word 0x00 6. " CMPLCHA22 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 5. " CMPLCHA21 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 4. " CMPLCHA20 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 3. " CMPLCHA19 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CMPLCHA18 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 1. " CMPLCHA17 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.word 0x00 0. " CMPLCHA16 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
else
|
|
group.word 0x9A++0x01
|
|
line.word 0x00 "ADCMPLR1,A/D Compare Function Window A Comparison Condition Setting Register 1"
|
|
bitfld.word 0x00 6. " CMPLCHA22 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 5. " CMPLCHA21 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 4. " CMPLCHA20 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 3. " CMPLCHA19 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CMPLCHA18 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 1. " CMPLCHA17 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.word 0x00 0. " CMPLCHA16 ,Compare Window A Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
endif
|
|
if (((per.l(ad:0x4005C000+0x90))&0x4000)==0x00)
|
|
group.byte 0x93++0x00
|
|
line.byte 0x00 "ADCMPLER,A/D Compare Function Window A Extended Input Comparison Condition Setting Register"
|
|
bitfld.byte 0x00 1. " CMPLOCA ,Compare Window A Internal Reference Voltage Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
bitfld.byte 0x00 0. " CMPLTSA ,Compare Window A Temperature Sensor Output Comparison Condition Select" "ADCMPDR0>A/D,ADCMPDR0<A/D"
|
|
else
|
|
group.byte 0x93++0x00
|
|
line.byte 0x00 "ADCMPLER,A/D Compare Function Window A Extended Input Comparison Condition Setting Register"
|
|
bitfld.byte 0x00 1. " CMPLOCA ,Compare Window A Internal Reference Voltage Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
bitfld.byte 0x00 0. " CMPLTSA ,Compare Window A Temperature Sensor Output Comparison Condition Select" "ADCMPDR0>A/D OR ADCMPDR1<A/D,ADCMPDR0<A/D<ADCMPDR1"
|
|
endif
|
|
group.word 0x9C++0x03
|
|
line.word 0x00 "ADCMPDR0,A/D Compare Function Window A Lower-Side Level Setting Register"
|
|
line.word 0x02 "ADCMPDR1,A/D Compare Function Window A Upper-Side Level Setting Register"
|
|
group.word 0xA8++0x03
|
|
line.word 0x00 "ADWINLLB,A/D Compare Function Window B Lower-Side Level Setting Register"
|
|
line.word 0x02 "ADWINULB,A/D Compare Function Window B Upper-Side Level Setting Register"
|
|
group.word 0xA0++0x03
|
|
line.word 0x00 "ADCMPSR0,A/D Compare Function Window A Channel Status Register 0"
|
|
bitfld.word 0x00 10. " CMPSTCHA10 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x00 9. " CMPSTCHA9 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x00 8. " CMPSTCHA8 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x00 7. " CMPSTCHA7 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
textline " "
|
|
bitfld.word 0x00 6. " CMPSTCHA6 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x00 5. " CMPSTCHA5 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x00 4. " CMPSTCHA4 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x00 3. " CMPSTCHA3 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
textline " "
|
|
bitfld.word 0x00 2. " CMPSTCHA2 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x00 1. " CMPSTCHA1 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x00 0. " CMPSTCHA0 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
line.word 0x02 "ADCMPSR1,A/D Compare Function Window A Channel Status Register1"
|
|
bitfld.word 0x02 6. " CMPSTCHA22 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x02 5. " CMPSTCHA21 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x02 4. " CMPSTCHA20 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x02 3. " CMPSTCHA19 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
textline " "
|
|
bitfld.word 0x02 2. " CMPSTCHA18 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x02 1. " CMPSTCHA17 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
bitfld.word 0x02 0. " CMPSTCHA16 ,Compare Window A Flag" "Conditions not met,Conditions met"
|
|
group.byte 0xA4++0x00
|
|
line.byte 0x00 "ADCMPSER,A/D Compare Function Window A Extended Input Channel Status Register"
|
|
bitfld.byte 0x00 1. " CMPSTOCA ,Compare Window A Internal Reference Voltage Compare Flag" "Conditions not met,Conditions met"
|
|
bitfld.byte 0x00 0. " ADCMPSER ,Compare Window A Temperature Sensor Output Compare Flag" "Conditions not met,Conditions met"
|
|
if (((per.l(ad:0x4005C000+0x90))&0x4000)==0x00)
|
|
group.byte 0xA6++0x00
|
|
line.byte 0x00 "ADCMPBNSR,A/D Compare Function Window B Channel Select Register"
|
|
bitfld.byte 0x00 7. " CMPLB ,Compare Window B Comparison Condition Setting" "CMPLLB>A/D,CMPLLB<A/D"
|
|
bitfld.byte 0x00 0.--5. " CMPCHB ,Compare Window B Channel Select" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,,,,,,AN016,AN017,AN018,AN019,AN020,AN021,AN022,,,,,,,,,,Temperature sensor,Internal reference voltage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Do not select"
|
|
else
|
|
group.byte 0xA6++0x00
|
|
line.byte 0x00 "ADCMPBNSR,A/D Compare Function Window B Channel Select Register"
|
|
bitfld.byte 0x00 7. " CMPLB ,Compare Window B Comparison Condition Setting" "CMPLLB>A/D OR CMPULB<A/D,CMPLLB<A/D<CMPULB"
|
|
bitfld.byte 0x00 0.--5. " CMPCHB ,Compare Window B Channel Select" "AN000,AN001,AN002,AN003,AN004,AN005,AN006,AN007,AN008,AN009,AN010,,,,,,AN016,AN017,AN018,AN019,AN020,AN021,AN022,,,,,,,,,,Temperature sensor,Internal reference voltage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Do not select"
|
|
endif
|
|
group.byte 0xAC++0x00
|
|
line.byte 0x00 "ADCMPBSR,A/D Compare Function Window B Status Register"
|
|
bitfld.byte 0x00 0. " CMPSTB ,Compare Window B Flag" "Conditions not met,Conditions met"
|
|
rgroup.byte 0x8C++0x00
|
|
line.byte 0x00 "ADWINMON,A/D Compare Function Window A/B Status Monitor Register"
|
|
bitfld.byte 0x00 5. " MONCMPB ,Comparison Result Monitor B" "Conditions not met,Conditions met"
|
|
bitfld.byte 0x00 4. " MONCMPA ,Comparison Result Monitor A" "Conditions not met,Conditions met"
|
|
bitfld.byte 0x00 0. " MONCOMB ,Combination Result Monitor" "Conditions not met,Conditions met"
|
|
group.byte 0x8A++0x00
|
|
line.byte 0x00 "ADHVREFCNT,A/D High-Potential/Low-Potential Reference Voltage Control Register"
|
|
bitfld.byte 0x00 7. " ADSLP ,Sleep" "Normal,Standby"
|
|
bitfld.byte 0x00 4. " LVSEL ,Low-Potential Reference Voltage Select" "AVSS0,VREFL0"
|
|
bitfld.byte 0x00 0.--1. " HVSEL ,High-Potential Reference Voltage Select" "AVCC0,VREFH0,Internal,Node discharge"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DAC12 (12-Bit D/A Converter)"
|
|
base ad:0x4005E000
|
|
width 10.
|
|
if (((per.w(ad:0x4005E000+0x05))&0x80)==0x80)
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DADR0,D/A Data Register 0"
|
|
hexmask.word 0x00 4.--15. 1. " DADR0 ,D/A Data Register 0"
|
|
else
|
|
group.word 0x00++0x01
|
|
line.word 0x00 "DADR0,D/A Data Register 0"
|
|
hexmask.word 0x00 0.--11. 1. " DADR0 ,D/A Data Register 0"
|
|
endif
|
|
group.byte 0x04++0x03
|
|
line.byte 0x00 "DACR ,D/A Control Register"
|
|
bitfld.byte 0x00 6. " DAOE0 ,D/A Output Enable 0" "Disabled,Enabled"
|
|
line.byte 0x01 "DADPR,DADR0 Format Select Register"
|
|
bitfld.byte 0x01 7. " DPSEL ,DADR0 Format Select" "Right-justified,Left-justified"
|
|
line.byte 0x02 "DAADSCR,D/A A/D Synchronous Start Control Register"
|
|
bitfld.byte 0x02 7. " DAADST ,D/A A/D Synchronous Conversion" "Not synchronized,Synchronized"
|
|
line.byte 0x03 "DAVREFCR,D/A VREF Control Register"
|
|
bitfld.byte 0x03 0. " REF ,D/A Reference Voltage Select" "None,AVCC0/AVSS0"
|
|
width 0x0B
|
|
tree.end
|
|
tree "TSN (Temperature Sensor)"
|
|
base ad:0x407EC228
|
|
width 8.
|
|
group.byte 0x00++0x01
|
|
line.byte 0x00 "TSCDRH,Temperature Sensor Calibration Data Register H"
|
|
line.byte 0x01 "TSCDRL,Temperature Sensor Calibration Data Register L"
|
|
width 0x0B
|
|
tree.end
|
|
tree "ACMPLP (Low-Power Analog Comparator)"
|
|
base ad:0x40085E00
|
|
width 9.
|
|
if (((per.b(ad:0x40085E00))&0x22)==0x00)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "COMPMDR,ACMPLP Mode Setting Register"
|
|
rbitfld.byte 0x00 7. " C1MON ,ACMPLP1 Monitor Flag" "CMPIN1<CMPREF1/CMPIN1<VREF/ACMPLP1 off,CMPIN1>CMPREF1/CMPIN1>VREF"
|
|
bitfld.byte 0x00 6. " C1VRF ,ACMPLP1 Reference Voltage Selection" "CMPREF1,Vref"
|
|
bitfld.byte 0x00 5. " C1WDE ,ACMPLP1 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " C1ENB ,ACMPLP1 Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " C0MON ,ACMPLP0 Monitor Flag" "CMPIN0<CMPREF0/CMPIN0<VREF/ACMPLP0 off,CMPIN0>CMPREF0/CMPIN0>VREF"
|
|
bitfld.byte 0x00 2. " C0VRF ,ACMPLP0 Reference Voltage Selection" "CMPREF0,Vref"
|
|
bitfld.byte 0x00 1. " C0WDE ,ACMPLP0 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " C0ENB ,ACMPLP1 Monitor Flag" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40085E00))&0x22)==0x02)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "COMPMDR,ACMPLP Mode Setting Register"
|
|
rbitfld.byte 0x00 7. " C1MON ,ACMPLP1 Monitor Flag" "CMPIN1<CMPREF1/CMPIN1<VREF/ACMPLP1 off,CMPIN1>CMPREF1/CMPIN1>VREF"
|
|
bitfld.byte 0x00 6. " C1VRF ,ACMPLP1 Reference Voltage Selection" "CMPREF1,Vref"
|
|
bitfld.byte 0x00 5. " C1WDE ,ACMPLP1 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " C1ENB ,ACMPLP1 Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " C0MON ,ACMPLP0 Monitor Flag" "CMPIN0<VRFL/CMPIN0>VRFH/ACMPLP0 off,VRFL<CMPIN0<VRFH"
|
|
bitfld.byte 0x00 2. " C0VRF ,ACMPLP0 Reference Voltage Selection" "CMPREF0,Vref"
|
|
bitfld.byte 0x00 1. " C0WDE ,ACMPLP0 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " C0ENB ,ACMPLP1 Monitor Flag" "Disabled,Enabled"
|
|
elif (((per.b(ad:0x40085E00))&0x22)==0x20)
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "COMPMDR,ACMPLP Mode Setting Register"
|
|
rbitfld.byte 0x00 7. " C1MON ,ACMPLP1 Monitor Flag" "CMPIN1>CMPREF1/CMPIN1>VREF/ACMPLP1 off,VRFL<CMPIN1<VRFH"
|
|
bitfld.byte 0x00 6. " C1VRF ,ACMPLP1 Reference Voltage Selection" "CMPREF1,Vref"
|
|
bitfld.byte 0x00 5. " C1WDE ,ACMPLP1 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " C1ENB ,ACMPLP1 Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " C0MON ,ACMPLP0 Monitor Flag" "CMPIN0<CMPREF0/CMPIN0<VREF/ACMPLP0 off,CMPIN0>CMPREF0/CMPIN0>VREF"
|
|
bitfld.byte 0x00 2. " C0VRF ,ACMPLP0 Reference Voltage Selection" "CMPREF0,Vref"
|
|
bitfld.byte 0x00 1. " C0WDE ,ACMPLP0 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " C0ENB ,ACMPLP1 Monitor Flag" "Disabled,Enabled"
|
|
else
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "COMPMDR,ACMPLP Mode Setting Register"
|
|
rbitfld.byte 0x00 7. " C1MON ,ACMPLP1 Monitor Flag" "CMPIN1>CMPREF1/CMPIN1>VREF/ACMPLP1 off,VRFL<CMPIN1<VRFH"
|
|
bitfld.byte 0x00 6. " C1VRF ,ACMPLP1 Reference Voltage Selection" "CMPREF1,Vref"
|
|
bitfld.byte 0x00 5. " C1WDE ,ACMPLP1 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 4. " C1ENB ,ACMPLP1 Operation Enable" "Disabled,Enabled"
|
|
textline " "
|
|
rbitfld.byte 0x00 3. " C0MON ,ACMPLP0 Monitor Flag" "CMPIN0<VRFL/CMPIN0>VRFH/ACMPLP0 off,VRFL<CMPIN0<VRFH"
|
|
bitfld.byte 0x00 2. " C0VRF ,ACMPLP0 Reference Voltage Selection" "CMPREF0,Vref"
|
|
bitfld.byte 0x00 1. " C0WDE ,ACMPLP0 Window Function Mode Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 0. " C0ENB ,ACMPLP1 Monitor Flag" "Disabled,Enabled"
|
|
endif
|
|
group.byte 0x01++0x01
|
|
line.byte 0x00 "COMPFIR,ACMPLP Filter Control Register"
|
|
bitfld.byte 0x00 7. " C1EDG ,ACMPLP1 Edge Detection Selection" "One edge,Both edges"
|
|
bitfld.byte 0x00 6. " C1EPO ,ACMPLP1 Edge Polarity Switching" "Rising edge,Falling edge"
|
|
bitfld.byte 0x00 4.--5. " C1FCK ,ACMPLP1 Filter Select" "Bypass,PCLKB,PCLKB/8,PCLKB/32"
|
|
bitfld.byte 0x00 3. " C0EDG ,ACMPLP0 Edge Detection Selection" "One edge,Both edges"
|
|
textline " "
|
|
bitfld.byte 0x00 2. " C0EPO ,ACMPLP0 Edge Polarity Switching" "Rising edge,Falling edge"
|
|
bitfld.byte 0x00 0.--1. " C0FCK ,ACMPLP0 Filter Select" "Bypass,PCLKB,PCLKB/8,PCLKB/32"
|
|
line.byte 0x01 "COMPOCR,ACMPLP Output Control Register"
|
|
bitfld.byte 0x01 7. " SPDMD ,ACMPLP0/ACMPLP1 Speed Selection" "Low speed,High speed"
|
|
bitfld.byte 0x01 6. " C1OP ,ACMPLP1 VCOUT Output Polarity Selection" "Not inverted,Inverted"
|
|
bitfld.byte 0x01 5. " C1OE ,ACMPLP1 VCOUT Pin Output Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x01 2. " C0OP ,ACMPLP0 VCOUT Output Polarity Selection" "Not inverted,Inverted"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " C0OE ,ACMPLP0 VCOUT Pin Output Enable" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
tree "CTSU (Capacitive Touch Sensing Unit)"
|
|
base ad:0x40081000
|
|
width 12.
|
|
group.byte 0x00++0x03
|
|
line.byte 0x00 "CTSUCR0,CTSU Control Register 0"
|
|
bitfld.byte 0x00 4. " CTSUINIT ,CTSU Control Block Initialization" "No effect,Initialize"
|
|
bitfld.byte 0x00 2. " CTSUSNZ ,CTSU Wait State Power-Saving Enable" "Disabled,Enabled"
|
|
bitfld.byte 0x00 1. " CTSUCAP ,CTSU Measurement Operation Start Trigger Select" "Software,External"
|
|
bitfld.byte 0x00 0. " CTSUSTRT ,CTSU Measurement Operation Start" "Stopped,Started"
|
|
line.byte 0x01 "CTSUCR1,CTSU Control Register 1"
|
|
bitfld.byte 0x01 6.--7. " CTSUMD ,CTSU Measurement Mode Select" "Single scan,Multi scan,,Full scan"
|
|
bitfld.byte 0x01 4.--5. " CTSUCLK ,CTSU Operating Clock Select" "PCLKB,PCLKB/2,PCLKB/4,?..."
|
|
bitfld.byte 0x01 3. " CTSUATUNE1 ,CTSU Power Supply Capacity Adjustment" "Normal,High"
|
|
bitfld.byte 0x01 2. " CTSUATUNE0 ,CTSU Power Supply Operating Mode Setting" "Normal,Low voltage"
|
|
textline " "
|
|
bitfld.byte 0x01 1. " CTSUCSW ,CTSU LPF Capacitance Charging Control" "Off,On"
|
|
bitfld.byte 0x01 0. " CTSUPON ,CTSU Power Supply Enable" "Off,On"
|
|
line.byte 0x02 "CTSUSDPRS,CTSU Synchronous Noise Reduction Setting Register"
|
|
bitfld.byte 0x02 6. " CTSUSOFF ,CTSU High-Pass Noise Reduction Function Off Setting" "On,Off"
|
|
bitfld.byte 0x02 4.--5. " CTSUPRMODE ,CTSU Base Period and Pulse Count Setting" "510,126,62,?..."
|
|
bitfld.byte 0x02 0.--3. " CTSUPRRATIO ,CTSU Measurement Time and Pulse Count Adjustment" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15"
|
|
line.byte 0x03 "CTSUSST,CTSU Sensor Stabilization Wait Control Register"
|
|
if (((per.b(ad:0x40081000+0x01))&0xC0)==0x00)
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "CTSUMCH0,CTSU Measurement Channel 0"
|
|
bitfld.byte 0x00 0.--5. " CTSUMCH0 ,CTSU Measurement Channel 0" "TS0,TS1,TS2,TS3,TS4,TS5,TS6,TS7,TS8,TS9,TS10,TS11,TS12,TS13,TS14,TS15,TS16,TS17,TS18,TS19,TS20,TS21,TS22,TS23,TS24,TS25,TS26,TS27,TS28,TS29,TS30,TS31,?..."
|
|
else
|
|
rgroup.byte 0x04++0x00
|
|
line.byte 0x00 "CTSUMCH0,CTSU Measurement Channel 0"
|
|
bitfld.byte 0x00 0.--5. " CTSUMCH0 ,CTSU Measurement Channel 0" "TS0,TS1,TS2,TS3,TS4,TS5,TS6,TS7,TS8,TS9,TS10,TS11,TS12,TS13,TS14,TS15,TS16,TS17,TS18,TS19,TS20,TS21,TS22,TS23,TS24,TS25,TS26,TS27,TS28,TS29,TS30,TS31,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Measurement is being stopped"
|
|
endif
|
|
rgroup.byte 0x05++0x00
|
|
line.byte 0x00 "CTSUMCH1,CTSU Measurement Channel 1"
|
|
bitfld.byte 0x00 0.--5. " CTSUMCH1 ,CTSU Measurement Channel 0" "TS0,TS1,TS2,TS3,TS4,TS5,TS6,TS7,TS8,TS9,TS10,TS11,TS12,TS13,TS14,TS15,TS16,TS17,TS18,TS19,TS20,TS21,TS22,TS23,TS24,TS25,TS26,TS27,TS28,TS29,TS30,TS31,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,Measurement is being stopped"
|
|
group.byte 0x06++0x03
|
|
line.byte 0x00 "CTSUCHAC0,CTSU Channel Enable Control Register 0"
|
|
bitfld.byte 0x00 7. " CTSUCHAC0[7] ,CTSU Channel Enable Control 0" "Not measured,Measured"
|
|
bitfld.byte 0x00 6. " CTSUCHAC0[6] ,CTSU Channel Enable Control 0" "Not measured,Measured"
|
|
bitfld.byte 0x00 5. " CTSUCHAC0[5] ,CTSU Channel Enable Control 0" "Not measured,Measured"
|
|
bitfld.byte 0x00 4. " CTSUCHAC0[4] ,CTSU Channel Enable Control 0" "Not measured,Measured"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CTSUCHAC0[3] ,CTSU Channel Enable Control 0" "Not measured,Measured"
|
|
bitfld.byte 0x00 2. " CTSUCHAC0[2] ,CTSU Channel Enable Control 0" "Not measured,Measured"
|
|
bitfld.byte 0x00 1. " CTSUCHAC0[1] ,CTSU Channel Enable Control 0" "Not measured,Measured"
|
|
bitfld.byte 0x00 0. " CTSUCHAC0[0] ,CTSU Channel Enable Control 0" "Not measured,Measured"
|
|
line.byte 0x01 "CTSUCHAC1,CTSU Channel Enable Control Register 1"
|
|
bitfld.byte 0x01 7. " CTSUCHAC1[7] ,CTSU Channel Enable Control 1" "Not measured,Measured"
|
|
bitfld.byte 0x01 6. " CTSUCHAC1[6] ,CTSU Channel Enable Control 1" "Not measured,Measured"
|
|
bitfld.byte 0x01 5. " CTSUCHAC1[5] ,CTSU Channel Enable Control 1" "Not measured,Measured"
|
|
bitfld.byte 0x01 4. " CTSUCHAC1[4] ,CTSU Channel Enable Control 1" "Not measured,Measured"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " CTSUCHAC1[3] ,CTSU Channel Enable Control 1" "Not measured,Measured"
|
|
bitfld.byte 0x01 2. " CTSUCHAC1[2] ,CTSU Channel Enable Control 1" "Not measured,Measured"
|
|
bitfld.byte 0x01 1. " CTSUCHAC1[1] ,CTSU Channel Enable Control 1" "Not measured,Measured"
|
|
bitfld.byte 0x01 0. " CTSUCHAC1[0] ,CTSU Channel Enable Control 1" "Not measured,Measured"
|
|
line.byte 0x02 "CTSUCHAC2,CTSU Channel Enable Control Register 2"
|
|
bitfld.byte 0x02 7. " CTSUCHAC2[7] ,CTSU Channel Enable Control 2" "Not measured,Measured"
|
|
bitfld.byte 0x02 6. " CTSUCHAC2[6] ,CTSU Channel Enable Control 2" "Not measured,Measured"
|
|
bitfld.byte 0x02 5. " CTSUCHAC2[5] ,CTSU Channel Enable Control 2" "Not measured,Measured"
|
|
bitfld.byte 0x02 4. " CTSUCHAC2[4] ,CTSU Channel Enable Control 2" "Not measured,Measured"
|
|
textline " "
|
|
bitfld.byte 0x02 3. " CTSUCHAC2[3] ,CTSU Channel Enable Control 2" "Not measured,Measured"
|
|
bitfld.byte 0x02 2. " CTSUCHAC2[2] ,CTSU Channel Enable Control 2" "Not measured,Measured"
|
|
bitfld.byte 0x02 1. " CTSUCHAC2[1] ,CTSU Channel Enable Control 2" "Not measured,Measured"
|
|
bitfld.byte 0x02 0. " CTSUCHAC2[0] ,CTSU Channel Enable Control 2" "Not measured,Measured"
|
|
line.byte 0x03 "CTSUCHAC3,CTSU Channel Enable Control Register 3"
|
|
bitfld.byte 0x03 7. " CTSUCHAC3[7] ,CTSU Channel Enable Control 3" "Not measured,Measured"
|
|
bitfld.byte 0x03 6. " CTSUCHAC3[6] ,CTSU Channel Enable Control 3" "Not measured,Measured"
|
|
bitfld.byte 0x03 4. " CTSUCHAC3[5] ,CTSU Channel Enable Control 3" "Not measured,Measured"
|
|
bitfld.byte 0x03 3. " CTSUCHAC3[3] ,CTSU Channel Enable Control 3" "Not measured,Measured"
|
|
textline " "
|
|
bitfld.byte 0x03 2. " CTSUCHAC3[2] ,CTSU Channel Enable Control 3" "Not measured,Measured"
|
|
bitfld.byte 0x03 1. " CTSUCHAC3[1] ,CTSU Channel Enable Control 3" "Not measured,Measured"
|
|
bitfld.byte 0x03 0. " CTSUCHAC3[0] ,CTSU Channel Enable Control 3" "Not measured,Measured"
|
|
group.byte 0x0B++0x03
|
|
line.byte 0x00 "CTSUCHTRC0,CTSU Channel Transmit/Receive Control Register 0"
|
|
bitfld.byte 0x00 7. " CTSUCHTRC0[7] ,CTSU Channel Transmit Receive Control 0" "Reception,Transmission"
|
|
bitfld.byte 0x00 6. " CTSUCHTRC0[6] ,CTSU Channel Transmit Receive Control 0" "Reception,Transmission"
|
|
bitfld.byte 0x00 5. " CTSUCHTRC0[5] ,CTSU Channel Transmit Receive Control 0" "Reception,Transmission"
|
|
bitfld.byte 0x00 4. " CTSUCHTRC0[4] ,CTSU Channel Transmit Receive Control 0" "Reception,Transmission"
|
|
textline " "
|
|
bitfld.byte 0x00 3. " CTSUCHTRC0[3] ,CTSU Channel Transmit Receive Control 0" "Reception,Transmission"
|
|
bitfld.byte 0x00 2. " CTSUCHTRC0[2] ,CTSU Channel Transmit Receive Control 0" "Reception,Transmission"
|
|
bitfld.byte 0x00 1. " CTSUCHTRC0[1] ,CTSU Channel Transmit Receive Control 0" "Reception,Transmission"
|
|
bitfld.byte 0x00 0. " CTSUCHTRC0[0] ,CTSU Channel Transmit Receive Control 0" "Reception,Transmission"
|
|
line.byte 0x01 "CTSUCHTRC1,CTSU Channel Transmit/Receive Control Register 1"
|
|
bitfld.byte 0x01 7. " CTSUCHTRC1[7] ,CTSU Channel Transmit Receive Control 1" "Reception,Transmission"
|
|
bitfld.byte 0x01 6. " CTSUCHTRC1[6] ,CTSU Channel Transmit Receive Control 1" "Reception,Transmission"
|
|
bitfld.byte 0x01 5. " CTSUCHTRC1[5] ,CTSU Channel Transmit Receive Control 1" "Reception,Transmission"
|
|
bitfld.byte 0x01 4. " CTSUCHTRC1[4] ,CTSU Channel Transmit Receive Control 1" "Reception,Transmission"
|
|
textline " "
|
|
bitfld.byte 0x01 3. " CTSUCHTRC1[3] ,CTSU Channel Transmit Receive Control 1" "Reception,Transmission"
|
|
bitfld.byte 0x01 2. " CTSUCHTRC1[2] ,CTSU Channel Transmit Receive Control 1" "Reception,Transmission"
|
|
bitfld.byte 0x01 1. " CTSUCHTRC1[1] ,CTSU Channel Transmit Receive Control 1" "Reception,Transmission"
|
|
bitfld.byte 0x01 0. " CTSUCHTRC1[0] ,CTSU Channel Transmit Receive Control 1" "Reception,Transmission"
|
|
line.byte 0x02 "CTSUCHTRC2,CTSU Channel Transmit/Receive Control Register 2"
|
|
bitfld.byte 0x02 7. " CTSUCHTRC2[7] ,CTSU Channel Transmit Receive Control 2" "Reception,Transmission"
|
|
bitfld.byte 0x02 6. " CTSUCHTRC2[6] ,CTSU Channel Transmit Receive Control 2" "Reception,Transmission"
|
|
bitfld.byte 0x02 5. " CTSUCHTRC2[5] ,CTSU Channel Transmit Receive Control 2" "Reception,Transmission"
|
|
bitfld.byte 0x02 4. " CTSUCHTRC2[4] ,CTSU Channel Transmit Receive Control 2" "Reception,Transmission"
|
|
textline " "
|
|
bitfld.byte 0x02 3. " CTSUCHTRC2[3] ,CTSU Channel Transmit Receive Control 2" "Reception,Transmission"
|
|
bitfld.byte 0x02 2. " CTSUCHTRC2[2] ,CTSU Channel Transmit Receive Control 2" "Reception,Transmission"
|
|
bitfld.byte 0x02 1. " CTSUCHTRC2[1] ,CTSU Channel Transmit Receive Control 2" "Reception,Transmission"
|
|
bitfld.byte 0x02 0. " CTSUCHTRC2[0] ,CTSU Channel Transmit Receive Control 2" "Reception,Transmission"
|
|
line.byte 0x03 "CTSUCHTRC3,CTSU Channel Transmit/Receive Control Register 3"
|
|
bitfld.byte 0x03 7. " CTSUCHTRC3[7] ,CTSU Channel Transmit Receive Control 3" "Reception,Transmission"
|
|
bitfld.byte 0x03 6. " CTSUCHTRC3[6] ,CTSU Channel Transmit Receive Control 3" "Reception,Transmission"
|
|
bitfld.byte 0x03 4. " CTSUCHTRC3[4] ,CTSU Channel Transmit Receive Control 3" "Reception,Transmission"
|
|
bitfld.byte 0x03 3. " CTSUCHTRC3[3] ,CTSU Channel Transmit Receive Control 3" "Reception,Transmission"
|
|
textline " "
|
|
bitfld.byte 0x03 2. " CTSUCHTRC3[2] ,CTSU Channel Transmit Receive Control 3" "Reception,Transmission"
|
|
bitfld.byte 0x03 1. " CTSUCHTRC3[1] ,CTSU Channel Transmit Receive Control 3" "Reception,Transmission"
|
|
bitfld.byte 0x03 0. " CTSUCHTRC3[0] ,CTSU Channel Transmit Receive Control 3" "Reception,Transmission"
|
|
group.byte 0x10++0x01
|
|
line.byte 0x00 "CTSUDCLKC,CTSU High-Pass Noise Reduction Control Register"
|
|
bitfld.byte 0x00 4.--5. " CTSUSSCNT ,CTSU Diffusion Clock Mode Control" "0,1,2,3"
|
|
bitfld.byte 0x00 0.--1. " CTSUSSMOD ,CTSU Diffusion Clock Mode Select" "0,1,2,3"
|
|
line.byte 0x01 "CTSUST,CTSU Status Register"
|
|
rbitfld.byte 0x01 7. " CTSUPS ,CTSU Mutual Capacitance Status Flag" "First,Second"
|
|
bitfld.byte 0x01 6. " CTSUROVF ,CTSU Reference Counter Overflow Flag" "No overflow,Overflow"
|
|
bitfld.byte 0x01 5. " CTSUSOVF ,CTSU Sensor Counter Overflow Flag" "No overflow,Overflow"
|
|
rbitfld.byte 0x01 4. " CTSUDTSR ,CTSUDTSR CTSU Data Transfer Status Flag" "Read,Not read"
|
|
textline " "
|
|
rbitfld.byte 0x01 0.--2. " CTSUSTC ,CTSU Measurement Status Counter" "Status 0,Status 1,Status 2,Status 3,Status 4,Status 5,?..."
|
|
group.word 0x12++0x03
|
|
line.word 0x00 "CTSUSSC,CTSU High-Pass Noise Reduction Spectrum Diffusion Control Register"
|
|
bitfld.word 0x00 8.--11. " CTSUSSDIV ,CTSU Spectrum Diffusion Frequency Division Setting" "4<fb,2<fb<4,1.33<fb<2,1<fb<1.33,0.8<fb<1,0.67<fb<0.8,0.57<fb<0.67,0.5<fb<0.57,0.44<fb<0.5,0.4<fb<0.44,0.36<fb<0.4,0.33<fb<0.36,0.31<fb<0.33,0.29<fb<0.31,0.27<fb<0.29,fb<0.27"
|
|
line.word 0x02 "CTSUSO0,CTSU Sensor Offset Register 0"
|
|
bitfld.word 0x02 10.--15. " CTSUSNUM ,CTSU Measurement Count Setting" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63"
|
|
hexmask.word 0x02 0.--9. 1. " CTSUSO ,CTSU Sensor Offset Adjustment"
|
|
group.word 0x16++0x01
|
|
line.word 0x00 "CTSUSO1,CTSU Sensor Offset Register 1"
|
|
bitfld.word 0x00 13.--14. " CTSUICOG ,CTSU ICO Gain Adjustment" "100%,66%,50%,40%"
|
|
bitfld.word 0x00 8.--12. " CTSUSDPA ,CTSU Base Clock Setting" "/2,/4,/6,/8,/10,/12,/14,/16,/18,/20,/22,/24,/26,/28,/30,/32,/34,/36,/38,/40,/42,/44,/46,/48,/50,/52,/54,/56,/58,/60,/62,/64"
|
|
hexmask.word.byte 0x00 0.--7. 1. " CTSURICOA ,CTSU Reference ICO Current Adjustment"
|
|
rgroup.word 0x18++0x05
|
|
line.word 0x00 "CTSUSC,CTSU Sensor Counter"
|
|
line.word 0x02 "CTSURC,CTSU Reference Counter"
|
|
line.word 0x04 "CTSUERRS,CTSU Error Status Register"
|
|
bitfld.word 0x04 15. " CTSUICOMP ,TSCAP Voltage Error Monitor" "Normal,Abnormal"
|
|
width 0x0B
|
|
tree.end
|
|
tree "DOC (Data Operation Circuit)"
|
|
base ad:0x40054100
|
|
width 7.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "DOCR,DOC Control Register"
|
|
bitfld.byte 0x00 6. " DOPCFCL ,DOPCF Clear" "Save,Clear"
|
|
rbitfld.byte 0x00 5. " DOPCF ,Data Operation Circuit Flag" "0,1"
|
|
bitfld.byte 0x00 2. " DCSEL ,Detection Condition Select" "Mismatched,Matched"
|
|
bitfld.byte 0x00 0.--1. " OMS ,Operating Mode Select" "Comparison,Addition,Subtraction,?..."
|
|
group.word 0x02++0x03
|
|
line.word 0x00 "DODIR,DOC Data Input Register"
|
|
line.word 0x02 "DODSR,DOC Data Setting Register"
|
|
width 0x0B
|
|
tree.end
|
|
tree "SRAM (Static Random Access Memory)"
|
|
base ad:0x40002000
|
|
width 10.
|
|
group.byte 0x00++0x00
|
|
line.byte 0x00 "PARIOAD,SRAM Parity Error Operation After Detection Register"
|
|
bitfld.byte 0x00 0. " OAD ,Operation After Detection" "Rest,Non-maskable interrupt"
|
|
group.byte 0x04++0x00
|
|
line.byte 0x00 "SRAMPRCR,SRAM Protection Register"
|
|
hexmask.byte 0x00 1.--7. 1. " KW ,Write Key Code"
|
|
bitfld.byte 0x00 0. " SRAMPRCR ,Register Write Control" "Disabled,Enabled"
|
|
width 0x0B
|
|
tree.end
|
|
textline ""
|